EVAL-SSM2335Z [ADI]
Filterless, High Efficiency, Mono 3 W Class-D Audio Amplifier; 无滤波器，高效率，单声道3瓦D类音频放大器
| 型号： | EVAL-SSM2335Z |
| 厂家： | 
ADI |
| 描述： | Filterless, High Efficiency, Mono 3 W Class-D Audio Amplifier |
| 文件： | 总16页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Filterless, High Efficiency,
Mono 3 W Class-D Audio Amplifier
SSM2335
The SSM2335 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The modu-
lation continues to provide high efficiency even at low output
power. It operates with 93% efficiency at 1.4 W into 8 Ω or 85%
efficiency at 3 W into 3 Ω from a 5.0 V supply and has an SNR
of >96 dB. Spread-spectrum pulse density modulation is used
to provide lower EMI-radiated emissions compared with other
Class-D architectures.
FEATURES
Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Class-D amplifiers
from Analog Devices, Inc.
3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion (THD + N)
93% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
>96 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Default fixed 18 dB or user-adjustable gain setting
The SSM2335 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying
SD
a logic low to the
pin.
The device also includes pop-and-click suppression circuitry.
This suppression circuitry minimizes voltage glitches at the
output during turn-on and turn-off, reducing audible noise
on activation and deactivation.
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
The fully differential input of the SSM2335 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the input dc common-mode voltage
is approximately VDD/2.
The default gain of the SSM2335 is 18 dB, but users can reduce the
gain by using a pair of external resistors (see the Gain section).
GENERAL DESCRIPTION
The SSM2335 is specified over the industrial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.5 mm ×
1.5 mm wafer level chip scale package (WLCSP).
The SSM2335 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 3 W of continuous output power
with <1% THD + N driving a 3 Ω load from a 5.0 V supply.
FUNCTIONAL BLOCK DIAGRAM
0.1µF
10µF
VBATT
2.5V TO 5.5V
VDD
SSM2335
160kΩ
47nF*
20kΩ
20kΩ
IN+
IN–
OUT–
OUT+
AUDIO IN+
AUDIO IN–
MODULATOR
FET
DRIVER
(Σ-Δ)
47nF*
160kΩ
SD
INTERNAL
OSCILLATOR
POP-AND-CLICK
SUPPRESSION
BIAS
SHUTDOWN
GND
*INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V /2.
DD
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
SSM2335
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Application Circuits ......................................................... 11
Theory of Operation ...................................................................... 12
Overview ..................................................................................... 12
Gain.............................................................................................. 12
Pop-and-Click Suppression ...................................................... 12
Output Modulation Description .............................................. 12
Layout .......................................................................................... 13
Input Capacitor Selection.......................................................... 13
Power Supply Decoupling ......................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
SSM2335
SPECIFICATIONS
VDD = 5.0 V, TA = 25°C, RL = 8 Ω +33 μH, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments1
Min
Typ
Max
Unit
DEVICE CHARACTERISTICS
Output Power
PO
f = 1 kHz, 20 kHz BW
RL = 8 Ω, THD = 1%, VDD = 5.0 V
RL = 8 Ω, THD = 1%, VDD = 3.6 V
RL = 8 Ω, THD = 10%, VDD = 5.0 V
RL = 8 Ω, THD = 10%, VDD = 3.6 V
RL = 4 Ω, THD = 1%, VDD = 5.0 V
RL = 4 Ω, THD = 1%, VDD = 3.6 V
RL = 4 Ω, THD = 10%, VDD = 5.0 V
RL = 4 Ω, THD = 10%, VDD = 3.6 V
RL = 3 Ω, THD = 1%, VDD = 5.0 V
RL = 3 Ω, THD = 1%, VDD = 3.6 V
RL = 3 Ω, THD = 10%, VDD = 5.0 V
RL = 3 Ω, THD = 10%, VDD = 3.6 V
PO = 1.4 W, 8 Ω, VDD = 5.0 V
1.48
0.75
1.84
0.94
2.72
1.38
3.402
1.72
3.432
1.72
4.282
2.14
93
W
W
W
W
W
W
W
W
W
W
W
W
%
Efficiency
η
Total Harmonic Distortion + Noise
THD + N
PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V
PO = 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V
0.01
0.01
%
%
Input Common-Mode Voltage Range VCM
1.0
VDD − 1.0
V
Common-Mode Rejection Ratio
Average Switching Frequency
Differential Output Offset Voltage
POWER SUPPLY
CMRRGSM
fSW
VOOS
VCM = 2.5 V 100 mV at 217 Hz, output referred
Gain = 18 dB
60
300
2.0
dB
kHz
mV
Supply Voltage Range
Power Supply Rejection Ratio
VDD
Guaranteed from PSRR test
2.5
60
5.5
V
dB
dB
mA
mA
mA
mA
mA
mA
nA
PSRRDC
PSRRGSM
ISY
VDD = 2.5 V to 5.0 V, dc input floating
VRIPPLE = 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 μF
VIN = 0 V, no load, VDD = 5.0 V
VIN = 0 V, no load, VDD = 3.6 V
VIN = 0 V, no load, VDD = 2.5 V
VIN = 0 V, load = 8 Ω + 33 μH, VDD = 5.0 V
VIN = 0 V, load = 8 Ω + 33 μH, VDD = 3.6 V
VIN = 0 V, load = 8 Ω + 33 μH, VDD = 2.5 V
85
65
Supply Current
3.2
2.8
2.4
3.3
2.9
2.4
20
Shutdown Current
ISD
SD
= GND
GAIN CONTROL
Closed-Loop Gain
Differential Input Impedance
Gain
ZIN
18
20
dB
kΩ
SD
= VDD
SHUTDOWN CONTROL
Input Voltage High
Input Voltage Low
Turn-On Time
VIH
VIL
tWU
tSD
ISY ≥ 1 mA
ISY ≤ 300 nA
1.2
0.5
7
V
V
ms
μs
kΩ
SD
SD
SD
rising edge from GND to VDD
falling edge from VDD to GND
= GND
Turn-Off Time
5
Output Impedance
ZOUT
>100
NOISE PERFORMANCE
Output Voltage Noise
en
VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are
ac-grounded, gain = 18 dB, A-weighted
PO = 1.4 W, RL = 8 Ω
44
96
μV rms
dB
Signal-to-Noise Ratio
SNR
1 Although the SSM2335 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations.
2 This value represents measured performance; packaging limitations must not be exceeded.
Rev. 0 | Page 3 of 16
SSM2335
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 2.
Parameter
Rating
Supply Voltage
Input Voltage
6 V
VDD
VDD
3 W
Table 3. Thermal Resistance
Package Type
PCB θJA
1S0P 162 39
2S0P 76 21
θJB
Unit
°C/W
°C/W
Common-Mode Input Voltage
Continuous Output Power
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
ESD Susceptibility
9-Ball, 1.5 mm × 1.5 mm WLCSP
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
ESD CAUTION
2.5 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 16
SSM2335
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
CORNER
1
2
3
A
B
C
SSM2335
TOP VIEW
BALL SIDE DOWN
(Not to Scale)
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1A
1B
IN+
VDD
Noninverting Input.
Power Supply.
1C
IN−
Inverting Input.
2A
GND
Ground.
2B
2C
PVDD
SD
Power Supply.
Shutdown Input. Active low digital input.
Inverting Output.
Ground.
3A
3B
OUT−
GND
3C
OUT+
Noninverting Output.
Rev. 0 | Page 5 of 16
SSM2335
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
10
R = 8Ω, 33µH
R
= 8Ω, 33µH
L
L
V
= 2.5V
DD
GAIN = 18dB
GAIN = 18dB
fIN = 1kHz
V
= 5V
DD
10
V
= 3.6V
DD
1
1
0.5W
1W
0.1
0.1
V
= 5V
DD
0.01
0.001
0.01
0.001
0.25W
0.0001
0.001
0.01
0.1
1
10
10
100
1k
10k
100k
OUTPUT POWER (W)
FREQUENCY (Hz)
Figure 3. THD + N vs. Output Power into 8 Ω + 33 μH, Gain = 18 dB
Figure 6. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω + 33 μH, Gain = 18 dB
100
100
R = 4Ω, 33µH
GAIN = 18dB
fIN = 1kHz
R
= 4Ω, 33µH
L
L
V
= 2.5V
DD
GAIN = 18dB
= 5V
V
DD
10
1
10
1
V
= 3.6V
DD
0.1
0.1
2W
0.5W
1W
0.01
0.001
0.01
0.001
V
= 5V
DD
0.0001
0.001
0.01
0.1
1
10
10
100
1k
10k
100k
OUTPUT POWER (W)
FREQUENCY (Hz)
Figure 7. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω + 33 μH, Gain = 18 dB
Figure 4. THD + N vs. Output Power into 4 Ω + 33 μH, Gain = 18 dB
100
100
R
= 3Ω, 33µH
R
= 3Ω, 33µH
L
L
V
= 2.5V
DD
GAIN = 18dB
fIN = 1kHz
GAIN = 18dB
V
= 5V
DD
10
1
10
1
V
= 3.6V
DD
3W
0.1
0.1
1.5W
V
= 5V
0.01
0.001
DD
0.01
0.001
0.75W
0.0001
0.001
0.01
0.1
1
10
10
100
1k
FREQUENCY (Hz)
10k
100k
OUTPUT POWER (W)
Figure 5. THD + N vs. Output Power into 3 Ω + 33 μH, Gain = 18 dB
Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 3 Ω + 33 μH, Gain = 18 dB
Rev. 0 | Page 6 of 16
SSM2335
100
10
100
10
R
= 8Ω, 33µH
R
= 8Ω, 33µH
L
L
GAIN = 18dB
GAIN = 18dB
V
= 3.6V
V
= 2.5V
DD
DD
1
1
0.1
0.1
0.25W
0.5W
0.125W
0.0625W
0.01
0.001
0.01
0.125W
100k
0.25W
100k
0.001
10
100
1k
10k
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω + 33 μH, Gain = 18 dB
Figure 12. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω + 33 μH, Gain = 18 dB
100
100
R
= 4Ω, 33µH
R
= 4Ω, 33µH
L
L
GAIN = 18dB
GAIN = 18dB
V
= 3.6V
V
= 2.5V
DD
DD
10
1
10
1
0.1
0.1
0.5W
1W
0.5W
0.125W
0.25W
0.01
0.001
0.01
0.25W
0.001
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω + 33 μH, Gain = 18 dB
Figure 13. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω + 33 μH, Gain = 18 dB
100
100
R
= 3Ω, 33µH
R
= 3Ω, 33µH
L
L
GAIN = 18dB
GAIN = 18dB
V
= 2.5V
V
= 3.6V
DD
DD
10
1
10
1
1.5W
0.75W
0.1
0.1
0.375W
0.188W
0.75W
0.01
0.001
0.01
0.375W
0.001
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 3 Ω + 33 μH, Gain = 18 dB
Figure 14. THD + N vs. Frequency, VDD = 2.5 V, RL = 3 Ω + 33 μH, Gain = 18 dB
Rev. 0 | Page 7 of 16
SSM2335
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
R
= 3Ω, 33µH
L
GAIN = 18dB
f = 1kHz
R
= 4Ω, 33µH
L
R
= 8Ω, 33µH
L
10%
R
= 3Ω, 33µH
L
1%
NO LOAD
2.2
2.5
2.5
3.0
3.5
4.0
4.5
5.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 18. Maximum Output Power vs. Supply Voltage, RL = 3 Ω + 33 μH,
Gain = 18 dB
Figure 15. Supply Current vs. Supply Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
V
= 2.5V
R
= 8Ω, 33µH
DD
L
GAIN = 18dB
f = 1kHz
90
80
70
60
50
40
30
20
10
0
V
= 5V
DD
V
= 3.6V
DD
10%
1%
R
= 8Ω, 33µH
L
2.5
3.0
3.5
4.0
4.5
5.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
Figure 16. Maximum Output Power vs. Supply Voltage, RL = 8 Ω + 33 μH,
Gain = 18 dB
Figure 19. Efficiency vs. Output Power into 8 Ω + 33 μH
4.0
100
90
80
70
60
50
40
30
20
10
0
R
= 4Ω, 33µH
L
GAIN = 18dB
f = 1kHz
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
DD
V
= 3.6V
DD
V
= 2.5V
DD
10%
1%
R
= 4Ω, 33µH
L
2.5
3.0
3.5
4.0
4.5
5.0
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
Figure 17. Maximum Output Power vs. Supply Voltage, RL = 4 Ω + 33 μH,
Gain = 18 dB
Figure 20. Efficiency vs. Output Power into 4 Ω + 33 μH
Rev. 0 | Page 8 of 16
SSM2335
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
0.12
0.10
0.08
0.06
0.04
0.02
0
R
V
= 8Ω, 33µH
R
V
= 4Ω, 33µH
L
L
= 5V
= 3.6V
DD
DD
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
0.3
0.6
0.9
1.2
1.5
1.8
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 21. Power Dissipation vs. Output Power into 8 Ω + 33 μH, VDD = 5 V
Figure 24. Power Dissipation vs. Output Power into 4 Ω + 33 μH, VDD = 3.6 V
450
0.30
R
= 8Ω, 33µH
R
= 4Ω, 33µH
L
L
V = 5.0V
DD
V
= 5V
DD
400
350
300
250
200
150
100
50
0.25
0.20
0.15
0.10
0.05
0
V
= 3.6V
DD
V
= 2.5V
DD
0
0
0.2
0.4
0.6
0.8
1.0 1.2
1.4
1.6
1.8
2.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 22. Power Dissipation vs. Output Power into 4 Ω + 33 μH, VDD = 5 V
Figure 25. Supply Current vs. Output Power into 8 Ω + 33 μH
800
700
600
500
400
300
200
100
0
0.08
R
= 4Ω, 33µH
R
= 8Ω, 33µH
= 3.6V
L
L
V
DD
V
= 5.0V
DD
0.06
0.04
0.02
0
V
= 3.6V
DD
V
= 2.5V
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 23. Power Dissipation vs. Output Power into 8 Ω + 33 μH, VDD = 3.6 V
Figure 26. Supply Current vs. Output Power into 4 Ω + 33 μH
Rev. 0 | Page 9 of 16
SSM2335
6
5
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
SD INPUT
OUTPUT
4
3
2
1
0
–1
–2
–100
10
100
1k
10k
100k
–2
0
2
4
6
8
10
12
14
16
18
TIME (ms)
FREQUENCY (Hz)
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 29. Turn-On Response
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
7
6
OUTPUT
5
4
3
2
1
0
SD INPUT
–1
–2
–100
10
100
1k
10k
100k
–90
–70
–50
–30
–10
10
30
50
70
90
FREQUENCY (Hz)
TIME (µs)
Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Figure 30. Turn-Off Response
Rev. 0 | Page 10 of 16
SSM2335
TYPICAL APPLICATION CIRCUITS
EXTERNAL GAIN SETTINGS = 160kΩ/(20kΩ + R
)
EXT
0.1µF
10µF
VBATT
2.5V TO 5.5V
VDD
SSM2335
160kΩ
47nF*
47nF*
R
R
20kΩ
EXT
IN+
OUT–
OUT+
AUDIO IN+
AUDIO IN–
MODULATOR
FET
DRIVER
20kΩ
(Σ-Δ)
EXT
IN–
160kΩ
SD
INTERNAL
OSCILLATOR
POP-AND-CLICK
SUPPRESSION
BIAS
SHUTDOWN
GND
*INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V /2.
DD
Figure 31. Differential Input Configuration, User-Adjustable Gain
EXTERNAL GAIN SETTINGS = 160kΩ/(20kΩ + R
)
EXT
0.1µF
10µF
VBATT
2.5V TO 5.5V
VDD
SSM2335
160kΩ
47nF
R
R
20kΩ
20kΩ
EXT
IN+
IN–
OUT–
OUT+
AUDIO IN+
MODULATOR
FET
DRIVER
(Σ-Δ)
EXT
47nF
160kΩ
SD
INTERNAL
OSCILLATOR
POP-AND-CLICK
SUPPRESSION
BIAS
SHUTDOWN
GND
Figure 32. Single-Ended Input Configuration, User-Adjustable Gain
Rev. 0 | Page 11 of 16
SSM2335
THEORY OF OPERATION
OVERVIEW
OUTPUT MODULATION DESCRIPTION
The SSM2335 uses three-level, Σ-Δ output modulation. Each
output can swing from GND to VDD and vice versa. Ideally, when
no input signal is present, the output differential voltage is 0 V
because there is no need to generate a pulse. In a real-world
situation, there are always noise sources present.
The SSM2335 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external component
count, conserving board space and, thus, reducing systems cost.
The SSM2335 does not require an output filter but, instead, relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the square wave output. Most Class-D amplifiers
use some variation of pulse-width modulation (PWM), but the
SSM2335 uses Σ-Δ modulation to determine the switching
pattern of the output devices, resulting in a number of important
benefits. Σ-Δ modulators do not produce a sharp peak with many
harmonics in the AM frequency band, as pulse-width modulators
often do. Σ-Δ modulation provides the benefits of reducing the
amplitude of spectral components at high frequencies, that is,
reducing EMI emission that might otherwise be radiated by
speakers and long cable traces. The SSM2335 does not require
external EMI filtering for twisted speaker cable lengths shorter
than 10 cm. Due to the inherent spread-spectrum nature of Σ-Δ
modulation, the need for oscillator synchronization is eliminated
for designs incorporating multiple SSM2335 amplifiers.
Due to this constant presence of noise, a differential pulse is
generated, when required, in response to this stimulus. A small
amount of current flows into the inductive load when the differ-
ential pulse is generated.
Most of the time, however, output differential voltage is 0 V, due
to the Analog Devices patent pending, three-level, Σ-Δ output
modulation. This feature ensures that the current flowing through
the inductive load is small.
When the user wants to send an input signal, an output pulse is
generated to follow the input voltage. The differential pulse
density is increased by raising the input signal level. Figure 33
depicts three-level, Σ-Δ output modulation with and without
input stimulus.
OUTPUT = 0V
+5V
OUT+
0V
The SSM2335 also offers protection circuits for overcurrent and
temperature protection.
+5V
OUT–
0V
+5V
GAIN
VOUT
0V
–5V
The SSM2335 has a default gain of 18 dB that can be reduced by
using a pair of external resistors with a value calculated as follows:
OUTPUT > 0V
+5V
OUT+
OUT–
VOUT
0V
External Gain Settings = 160 kΩ/(20 kΩ + REXT
)
+5V
0V
POP-AND-CLICK SUPPRESSION
+5V
Voltage transients at the output of audio amplifiers can occur
when shutdown is activated or deactivated. Voltage transients
as low as 10 mV can be heard as an audio pop in the speaker.
Clicks and pops can also be classified as undesirable audible
transients generated by the amplifier system and, therefore, as
not coming from the system input signal. Such transients may
be generated when the amplifier system changes its operating
mode. For example, the following may be sources of audible
transients: system power-up and power-down, mute and unmute,
input source change, and sample rate change. The SSM2335 has
a pop-and-click suppression architecture that reduces these out-
put transients, resulting in noiseless activation and deactivation.
0V
OUTPUT < 0V
+5V
OUT+
OUT–
VOUT
0V
+5V
0V
0V
–5V
Figure 33. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
Rev. 0 | Page 12 of 16
SSM2335
LAYOUT
INPUT CAPACITOR SELECTION
As output power continues to increase, care must be taken to
lay out PCB traces and wires properly among the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Ensure that track widths are at least 200 mil for every inch of
track length for lowest DCR, and use 1 oz or 2 oz of copper PCB
traces to further reduce IR drops and inductance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs to
minimize losses due to parasitic trace resistance.
The SSM2335 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors
are required if the input signal is not biased within this recom-
mended input dc common-mode voltage range, if high-pass
filtering is needed, or if a single-ended source is used. If high-
pass filtering is needed at the input, the input capacitor and the
input resistor of the SSM2335 form a high-pass filter whose
corner frequency is determined by the following equation:
fC = 1/(2π × RIN × CIN)
The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the dc PSRR performance.
Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load, as well as the PCB traces to
the supply pins, should be as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. Although the actual switching frequency can range
from 10 kHz to 100 kHz, these spikes can contain frequency
components that extend into the hundreds of megahertz. The
power supply input needs to be decoupled with a good quality,
low ESL, low ESR capacitor, with a minimum value of 4.7 μF.
This capacitor bypasses low frequency noises to the ground
plane. For high frequency transient noises, use a 0.1 μF capacitor
as close as possible to the VDD pin of the device. Placing the
decoupling capacitor as close as possible to the SSM2335 helps
to maintain efficient performance.
In addition, good PCB layout isolates critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
If the system has separate analog and digital ground and power
planes, the analog ground plane should be directly beneath the
analog power plane, and, similarly, the digital ground plane should
be directly beneath the digital power plane. There should be no
overlap between analog and digital ground planes or between
analog and digital power planes.
Rev. 0 | Page 13 of 16
SSM2335
OUTLINE DIMENSIONS
0.655
0.600
0.545
1.490
1.460 SQ
1.430
A1 BALL
CORNER
SEATING
PLANE
3
2
1
A
B
C
0.350
0.320
0.290
0.50
BALL PITCH
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
0.385
0.360
0.335
0.270
0.240
0.210
Figure 34. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
SSM2335CBZ-R21
SSM2335CBZ-REEL1
SSM2335CBZ-REEL71
EVAL-SSM2335Z1
Temperature Range
Package Description
Package Option
CB-9-2
CB-9-2
Branding
Y1L
Y1L
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
9-Ball Wafer Level Chip Scale Package [WLCSP]
9-Ball Wafer Level Chip Scale Package [WLCSP]
9-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
CB-9-2
Y1L
1 Z = RoHS Compliant Part.
Rev. 0 | Page 14 of 16
SSM2335
NOTES
Rev. 0 | Page 15 of 16
SSM2335
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07551-0-10/08(0)
Rev. 0 | Page 16 of 16
相关型号：
EVAL-SSM2377Z
Filterless, High Efficiency, Mono 2.5 W Class-D Audio Amplifier Pop-and-click suppression
ADI
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