EVAL-AD7665CB [ADI]
16-Bit, 570 kSPS CMOS ADC; 16位570 kSPS的CMOS ADC
| 型号： | EVAL-AD7665CB |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 570 kSPS CMOS ADC |
| 文件： | 总24页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
16-Bit, 570 kSPS CMOS ADC
AD7665*
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Throughput:
AVDD AGND REF REFGND
DVDD DGND
570 kSPS (Warp Mode)
500 kSPS (Normal Mode)
4R
4R
2R
R
IND(4R)
INC(4R)
INB(2R)
INA(R)
AD7665
OVDD
OGND
INL: ꢀ2.5 LSB Max (ꢀ0.0038% of Full Scale)
16-Bit Resolution with No Missing Codes
S/(N+D): 90 dB Typ @ 180 kHz
THD: –100 dB Typ @ 180 kHz
Analog Input Voltage Ranges:
Bipolar: ꢀ10 V, ꢀ5 V, ꢀ2.5 V
Unipolar: 0 V to 10 V, 0 V to 5 V, 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
SERIAL
PORT
SWITCHED
CAP DAC
SER/PAR
BUSY
INGND
PARALLEL
INTERFACE
16
DATA[15:0]
CS
CLOCK
PD
RESET
RD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
OB/2C
Parallel (8/16 Bits) and Serial 5 V/3 V Interface
Single 5 V Supply Operation
Power Dissipation
BYTESWAP
WARP IMPULSE
CNVST
64 mW Typical
15 ꢁW @ 100 SPS
Power-Down Mode: 7 ꢁW Max
Package: 48-Lead Quad Flatpack (LQFP)
Pin-to-Pin Compatible Upgrade of the AD7664/AD7663
APPLICATIONS
Data Acquisition
Communication
Instrumentation
Spectrum Analysis
Medical Instruments
Process Control
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7665 is a 16-bit, 570 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. It contains a high-speed 16-bit sampling ADC, a resistor
input scaler which allows various input ranges, an internal con-
version clock, error correction circuits, and both serial and
parallel system interface ports.
1. Fast Throughput
The AD7665 is a very high speed (570 kSPS in Warp mode
and 500 kSPS in Normal mode), charge redistribution,
16-bit SAR ADC.
2. Single Supply Operation
The AD7665 operates from a single 5 V supply, dissipates
only 64 mW typical, even lower when a reduced throughput
is used with the reduced power mode (Impulse) and a power-
down mode.
The AD7665 is hardware factory-calibrated and is comprehen-
sively tested to ensure such ac parameters as signal-to-noise ratio
(SNR) and total harmonic distortion (THD), in addition to the
more traditional dc parameters of gain, offset, and linearity.
3. Superior INL
It features a very high sampling rate mode (Warp) and, for
asynchronous conversion rate applications, a fast mode (Nor-
mal) and, for low power applications, a reduced power mode
(Impulse) where the power is scaled with the throughput. It is
fabricated using Analog Devices’ high-performance, 0.6 micron
CMOS process and is available in a 48-lead LQFP with opera-
tion specified from –40°C to +85°C.
The AD7665 has a maximum integral nonlinearity of 2.5 LSB
with no missing 16-bit code.
4. Serial or Parallel Interface
Versatile parallel (8 or 16 bits) or 2-wire serial interface
arrangement compatible with both 3 V or 5 V logic.
*Patent pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
(–40ꢂC to +85ꢂC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
AD7665–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
Common-Mode Input Voltage
Analog Input CMRR
Input Impedance
V
IND – VINGND
4 REF, 0 V to 4 REF, 2 REF (See Table I)
VINGND
fIN = 180 kHz
–0.1
+0.5
V
dB
62
See Table I
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Time Between Conversions
Complete Cycle
Throughput Rate
In Warp Mode
In Warp Mode
In Warp Mode
In Normal Mode
In Normal Mode
In Impulse Mode
In Impulse Mode
1.75
570
1
µs
1
kSPS
ms
2
µs
0
0
500
2.25
444
kSPS
µs
Complete Cycle
Throughput Rate
kSPS
DC ACCURACY
Integral Linearity Error
No Missing Codes
–2.5
16
+2.5
LSB1
Bits
Transition Noise
0.7
LSB
LSB
Bipolar Zero Error2, TMIN to TMAX
5 V Range, Normal or
Impulse Modes
–25
+25
Other Range or Mode
–0.06
–0.25
–0.18
–0.38
+0.06
+0.25
+0.18
+0.38
% of FSR
% of FSR
% of FSR
% of FSR
LSB
Bipolar Full-Scale Error2, TMIN to TMAX
Unipolar Zero Error2, TMIN to TMAX
Unipolar Full-Scale Error2, TMIN to TMAX
Power Supply Sensitivity
AVDD = 5 V 5%
9.5
AC ACCURACY
Signal-to-Noise
fIN = 10 kHz
fIN = 180 kHz
89
90
90
dB3
dB
Spurious Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
f
IN = 180 kHz
100
–100
90
dB
dB
dB
dB
fIN = 180 kHz
fIN = 10 kHz
fIN = 180 kHz, –60 dB Input
88.5
30
–3 dB Input Bandwidth
3.6
MHz
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
2
5
ns
ps rms
µs
Transient Response
Full-Scale Step
1
REFERENCE
External Reference Voltage Range
External Reference Current Drain
2.3
2.5
114
2.7
V
µA
570 kSPS Throughput
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.0
–1
+0.8
DVDD + 0.3
+1
+1
V
V
µA
µA
IIH
–1
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Parallel or Serial 16-Bit
Conversion Results Available Immediately
after Completed Conversion
0.4
OVDD – 0.6
VOL
VOH
ISINK = 1.6 mA
ISOURCE = –570 µA
V
V
POWER SUPPLIES
Specified Performance
AVDD
4.75
4.75
2.7
5
5
5.25
5.25
5.25
V
V
V
DVDD
OVDD
Operating Current4
AVDD
570 kSPS Throughput
14
4.5
20
mA
mA
µA
DVDD5
OVDD5
–2–
REV. 0
AD7665
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES (Continued)
Power Dissipation5, 6
444 kSPS Throughput7
100 SPS Throughput7
570 kSPS Throughput4
64
15
93
74
mW
µW
mW
µW
107
7
In Power-Down Mode8
TEMPERATURE RANGE9
Specified Performance
TMIN to TMAX
–40
+85
°C
NOTES
1LSB means Least Significant Bit. With the 5 V input range, one LSB is 152.588 µV.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.
4In warp mode.
5Tested in parallel reading mode.
6Tested with the 0 V to 5 V range and VIN – VINGND = 0 V. See Power Dissipation section.
7In impulse mode.
8With OVDD below DVDD + 0.3 V and all digital inputs forced to OVDD or OGND respectively.
9Contact factory for extended temperature range.
Specifications subject to change without notice.
Table I. Analog Input Configuration
Input Voltage
Input
Range
IND (4R)
INC (4R)
INB (2R)
INA (R)
Impedance1
4 REF
2 REF
REF
0 V to 4 REF
0 V to 2 REF
0 V to REF
VIN
VIN
VIN
VIN
VIN
VIN
INGND
VIN
VIN
VIN
VIN
INGND
INGND
VIN
INGND
VIN
REF
REF
REF
INGND
INGND
VIN
5.85 kΩ
3.41 kΩ
2.56 kΩ
3.41 kΩ
2.56 kΩ
Note 2
VIN
VIN
NOTES
1Typical analog input impedance.
2For this range the input is high impedance.
(–40ꢂC to +85ꢂC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
Time Between Conversions
t1
t2
5
ns
µs
1.75/2/2.25
Note 1
30
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in Master Serial Read after
Convert Mode (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
t3
t4
ns
0.75/1/1.25 µs
t5
t6
t7
t8
t9
2
ns
ns
10
0.75/1/1.25 µs
1
10
µs
ns
RESET Pulsewidth
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
t10
0.75/1/1.25 µs
t11
t12
t13
20
5
ns
40
15
ns
ns
Refer to Figures 17 and 18 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay (Read During Convert)
t14
t15
t16
t17
10
10
10
ns
ns
ns
ns
25/275/525
(Warp Mode/Normal Mode/Impulse Mode)
–3–
REV. 0
AD7665
TIMING SPECIFICATIONS (Continued)
Symbol
Min
Typ
Max
Unit
SYNC Asserted to SCLK First Edge Delay3
Internal SCLK Period3
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
4
ns
ns
ns
ns
ns
ns
25
15
9.5
4.5
2
40
Internal SCLK HIGH3
Internal SCLK LOW3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SCLK Last Edge to SYNC Delay3
CS HIGH to SYNC HI-Z
3
10
10
10
ns
ns
ns
µs
µs
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read After Convert3
CNVST LOW to SYNC Asserted Delay
Master Serial Read after Convert
SYNC Deasserted to BUSY LOW Delay
See Table II
0.75/1/1.25
t30
25
ns
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
t31
t32
t33
t34
t35
t36
t37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
16
External SCLK HIGH
External SCLK LOW
NOTES
1In warp mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3In serial master read during convert mode. See Table II.
Specifications subject to change without notice.
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
0
0
0
1
1
0
1
1
Unit
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY HIGH Width Maximum (Warp)
BUSY HIGH Width Maximum (Normal)
BUSY HIGH Width Maximum (Impulse)
t18
t19
t19
t20
t21
t22
t23
t24
t28
t28
t28
4
20
50
70
25
24
22
4
60
2
2.25
2.5
20
20
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
25
40
15
9.5
4.5
2
100
140
50
49
22
30
140
3
3.25
3.5
200
280
100
99
22
90
300
5.25
5.5
5.75
3
1.5
1.75
2
–4–
REV. 0
AD7665
PIN CONFIGURATION
48-Lead LQFP
(ST-48)
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
C
60pF
L
1
48
47 46 45 44 43 42 41 40 39 38 37
I
500ꢁA
OH
1
2
3
4
5
6
7
AGND
AVDD
36
35
34
33
32
31
30
29
AGND
CNVST
PD
PIN 1
NOTE:
1
IDENTIFIER
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
NC
BYTESWAP
C
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
RESET
CS
L
OB/2C
WARP
AD7665
TOP VIEW
RD
Figure 1. Load Circuit for Digital Interface Timing, SDOUT,
SYNC, SCLK Outputs, CL = 10 pF
IMPULSE
SER/PAR
D0
DGND
BUSY
D15
(Not to Scale)
8
9
28
27
26
25
10
11
D1
D14
D2/DIVSCLK[0]
2V
D13
D3/DIVSCLK[1] 12
0.8V
D12
tDELAY
tDELAY
13 14
15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
2V
2V
0.8V
0.8V
Figure 2. Voltage Reference Levels for Timing
ABSOLUTE MAXIMUM RATINGS1
Analog Inputs
Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . 700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
IND2, INC2, INB2 . . . . . . . . . . . . . . . . . . . –11 V to +30 V
INA, REF, INGND, REFGND
. . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . 0.3 V
Supply Voltages
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2See Analog Input section.
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . .
7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Digital Inputs . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
3Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θJC = 30°C/W.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD7665AST
–40°C to +85°C
–40°C to +85°C
Quad Flatpack (LQFP)
Quad Flatpack (LQFP)
Evaluation Board
ST-48
ST-48
AD7665ASTRL
EVAL-AD7665CB1
EVAL-CONTROL BRD22
Controller Board
NOTES
1This board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
2This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7665 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
AD7665
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Type
Description
1
2
AGND
AVDD
NC
P
P
Analog Power Ground Pin.
Input Analog Power Pin. Nominally 5 V.
No Connect.
Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB
is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on
D[7:0].
3, 44–48
4
BYTESWAP
5
6
OB/2C
DI
DI
Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted, resulting in a two’s complement output
from its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the
maximum throughput is achievable, and a minimum conversion rate must be applied in order
to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.
WARP
7
IMPULSE
SER/PAR
DI
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In
this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
8
DI
9, 10
11, 12
DATA[0:1]
DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs
are in high impedance.
DATA[2:3] or DI/O
DIVSCLK[0:1]
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the serial
master read after convert mode. These inputs, part of the serial port, are used to slow down, if
desired, the internal serial clock that clocks the data output. In the other serial modes, these
inputs are not used.
13
DATA[4]
DI/O
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
or EXT/INT
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock, called respectively, master and slave mode.
With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set
to a logic HIGH, output data is synchronized to an external clock signal connected to the
SCLK input and the external clock is gated by CS.
14
15
DATA[5]
or INVSYNC
DI/O
DI/O
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
DATA[6]
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
or INVSCLK
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK sig-
nal. It is active in both master and slave mode.
16
DATA[7]
DI/O
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN
When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data
input or a read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the con-
version results from two or more ADCs onto a single SDOUT line. The digital data level
on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the
read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is
HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW,
the data can be output on SDOUT only when the conversion is complete.
17
18
OGND
OVDD
P
P
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
19
20
DVDD
DGND
P
P
Digital Power. Nominally at 5 V.
Digital Power Ground.
–6–
REV. 0
AD7665
Pin
No.
Mnemonic
Type
Description
21
DATA[8]
DO
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT
When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7665
provides the conversion result, MSB first, from its internal shift register. The DATA format is
determined by the logic level of OB/2C. In serial mode, when EXT/INT is LOW, SDOUT is
valid on both edges of SCLK.
In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next
rising edge.
22
23
DATA[9]
or SCLK
DI/O
DO
When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
DATA[10]
or SYNC
When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH
while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High,
SYNC is driven LOW and remains LOW while SDOUT output is valid.
24
DATA[11]
DO
When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
or RDERROR
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as
an incomplete read error flag. In slave mode, when a data read is started and not complete when
the following conversion is complete, the current data is lost and RDERROR is pulsed high.
25–28
29
DATA[12:15] DO
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these out-
puts are in high impedance.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data ready clock signal.
BUSY
DO
30
31
DGND
RD
P
DI
Must Be Tied to Digital Ground.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus
is enabled.
32
33
34
35
CS
DI
DI
DI
DI
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled. CS is also used to gate the external serial clock.
Reset Input. When set to a logic HIGH, reset the AD7665. Current conversion, if any, is aborted. If
not used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited after the current one is completed.
Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state
and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if CNVST
is held low when the acquisition phase (t8) is complete, the internal sample/hold is put into
the hold state and a conversion is immediately started.
RESET
PD
CNVST
36
37
38
39
40, 41,
42, 43
AGND
REF
REFGND
INGND
INA, INB,
INC, IND
P
Must Be Tied to Analog Ground.
Reference Input Voltage.
Reference Input Analog Ground.
Analog Input Ground.
AI
AI
AI
AI
Analog Inputs. Refer to Table I for input range configuration.
NOTES
AI = Analog Input.
DI = Digital Input.
DI/O = Bidirectional Digital.
DO = Digital Output.
P = Power.
REV. 0
–7–
AD7665
EFFECTIVE NUMBER OF BITS (ENOB)
A measurement of the resolution with a sine wave input. It is
related to S/(N+D) by the following formula:
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each code to the true straight line.
ENOB = (S/[N+D]dB – 1.76)/6.02)
and is expressed in bits.
TOTAL HARMONIC DISTORTION (THD)
The rms sum of the first five harmonic components to the rms
value of a full-scale input signal and is expressed in decibels.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It is
often specified in terms of resolution for which no missing codes
are guaranteed.
SIGNAL-TO-NOISE RATIO (SNR)
The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre-
quency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
FULL-SCALE ERROR
The last transition (from 011 . . . 10 to 011 . . . 11 in two’s
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.499886 V for the 2.5 V range).
The full-scale error is the deviation of the actual level of the last
transition from the ideal level.
SIGNAL TO (NOISE + DISTORTION) RATIO (S/[N+D])
The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre-
quency, including harmonics but excluding dc. The value for
S/(N+D) is expressed in decibels.
BIPOLAR ZERO ERROR
The difference between the ideal midscale input voltage (0 V) and
the actual voltage producing the midscale output code.
APERTURE DELAY
A measure of the acquisition performance and is measured from
the falling edge of the CNVST input to when the input signal is
held for a conversion.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. The unipolar zero error is the
deviation of the actual transition from that point.
TRANSIENT RESPONSE
The time required for the AD7665 to achieve its rated accuracy
after a full-scale step function is applied to its input.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
–8–
REV. 0
Typical Performance Characteristics–AD7665
80
70
60
50
40
30
20
10
0
–3.0 –2.7 –2.7 –2.1 –1.8 –1.5 –1.2 –0.9 –0.6 –0.3
NEGATIVE INL – LSB
TPC 4. Typical Negative INL Distribution (446 Units)
TPC 1. Integral Nonlinearity vs. Code
8000
7337
7204
7000
6000
5000
4000
3000
2000
932
870
1000
0
0
0
19
22
0
0
7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8005
CODE IN HEXA
TPC 2. Differential Nonlinearity vs. Code
TPC 5. Histogram of 16,384 Conversions of a DC Input at
the Code Transition
10000
70
60
50
40
30
20
10
0
9468
9000
8000
7000
6000
5000
4000
3310
3259
3000
2000
1000
0
214
131
0
0
1
1
0
0
7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006
CODE IN HEXA
0
0.3
0.6 0.9
1.2
1.5
1.8
2.1 2.4
2.7
POSITIVE INL – LSB
TPC 3. Typical Positive INL Distribution (446 Units)
TPC 6. Histogram of 16,384 Conversions of a DC Input at
the Code Center
REV. 0
–9–
AD7665
–0
–98
96
93
90
87
84
4096 POINT FFT
FS = 571kHz
IN
SNR = 90.1 dB
SINAD = 89.7dB
THD = –100.1dB
SFDR = 102.3dB
–20
f
= 45kHz, –0.5dB
–40
–60
–100
–102
–104
THD
–80
–100
–120
–140
–160
SNR
–180
0
57
114
171
228
285
–55
–35
–15
5
25
45
65
85
105 125
FREQUENCY – kHz
TEMPERATURE – ꢂC
TPC 7. FFT Plot
TPC 10. SNR, THD vs. Temperature
110
105
100
95
–60
–65
100
95
90
85
80
75
16.0
SFDR
15.5
15.0
14.5
14.0
13.5
13.0
–70
–75
SNR
SINAD
–80
90
–85
85
–90
80
2ND HARMONIC
–95
75
–100
–105
–110
–115
THD
ENOB
70
65
3RD HARMONIC
60
1000
70
1
1
10
100
10
100
1000
FREQUENCY – kHz
FREQUENCY – kHz
TPC 11. THD, Harmonics, and SFDR vs. Frequency
TPC 8. SNR, S/(N+D), and ENOB vs. Frequency
–60
–70
–80
–90
92
90
88
86
–100
2ND HARMONIC
–110
THD
–120
–130
3RD HARMONIC
–140
–150
–60
–50
–40
–30
–20
–10
0
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT LEVEL – dB
INPUT LEVEL – dB
TPC 12. THD, Harmonics vs. Input Level
TPC 9. SNR vs. Input Level
–10–
REV. 0
AD7665
50
40
30
20
10
0
1000
900
800
700
600
500
400
300
200
100
0
DVDD
OVDD
AVDD
0
50
100
– pF
150
200
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE – ꢂC
C
L
TPC 13. Typical Delay vs. Load Capacitance CL
TPC 15. Power-Down Operating Currents vs. Temperature
100000
AVDD, WARP/NORMAL
10000
DVDD, WARP/NORMAL
1000
100
AVDD, IMPULSE
10
1
DVDD, IMPULSE
0.1
OVDD, ALL MODES
0.01
0.001
1
10
100
1000
10000
100000
1000000
SAMPLING RATE – SPS
TPC 14. Operating Currents vs. Sample Rate
REV. 0
–11–
AD7665
4R
4R
2R
IND
INC
INB
INA
REF
REFGND
SWITCHES
CONTROL
SW
MSB
LSB
SW
A
32,768C 16,384C
4C
C
C
2C
R
BUSY
CONTROL
LOGIC
COMP
OUTPUT
CODE
INGND
65,536C
B
CNVST
Figure 3. ADC Simplified Schematic
CIRCUIT INFORMATION
control logic toggles these switches, starting with the MSB first,
in order to bring the comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings BUSY output low.
The AD7665 is a fast, low-power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7665 features different
modes to optimize performances according to the applications.
In Warp mode, the AD7665 is capable of converting 570,000
samples per second (570 kSPS).
Modes of Operation
The AD7665 features three modes of operations, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
The AD7665 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The Warp mode allows the fastest conversion rate up to 570 kSPS.
However, in this mode, and this mode only, the full specified accu-
racy is guaranteed only when the time between conversion does
not exceed 1 ms. If the time between two consecutive conversions
is longer than 1 ms, for instance, after power-up, the first conver-
sion result should be ignored. This mode makes the AD7665
ideal for applications where both high accuracy and fast sample
rate are required.
It is specified to operate with both bipolar and unipolar input
ranges by changing the connection of its input resistive scaler.
The AD7665 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package that combines space savings and flexible
configurations as either serial or parallel interface. The AD7665
is a pin-to-pin-compatible upgrade of the AD7663 and AD7664.
The normal mode is the fastest mode (500 kSPS) without any
limitation about the time between conversions. This mode makes
the AD7665 ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.
CONVERTER OPERATION
The AD7665 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The input analog signal is,
first, scaled down and level-shifted by the internal input resistive
scaler which allows both unipolar ranges (0 V to 2.5 V, 0 V to
5 V, and 0 to 10 V) and bipolar ranges ( 2.5 V, 5 V, and 10 V).
The output voltage range of the resistive scaler is always 0 V to
2.5 V. The capacitive DAC consists of an array of 16 binary
weighted capacitors and an additional “LSB” capacitor. The
comparator’s negative input is connected to a “dummy” capaci-
tor of the same value as the capacitive DAC array.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput
in this mode is 444 kSPS. When operating at 100 SPS, for ex-
ample, it typically consumes only 15 µW. This feature makes the
AD7665 ideal for battery-powered applications.
Transfer Functions
Using the OB/2C digital input, the AD7665 offers two output
codings: straight binary and two’s complement. The ideal transfer
characteristic for the AD7665 is shown in Figure 4 and Table III.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SWA. All independent switches are connected to the output
of the resistive scaler. Thus, the capacitor array is used as a
sampling capacitor and acquires the analog signal. Similarly, the
“dummy” capacitor acquires the analog signal on INGND input.
111...111
111...110
111...101
When the acquisition phase is complete, and the CNVST input
goes or is low, a conversion phase is initiated. When the conversion
phase begins, SWA and SWB are opened first. The capacitor array
and the “dummy” capacitor are then disconnected from the inputs
and connected to the REFGND input. Therefore, the differen-
tial voltage between the output of the resistive scaler and INGND
captured at the end of the acquisition phase is applied to the
comparator inputs, causing the comparator to become unbalanced.
000...010
000...001
000...000
–FS
–FS + 1 LSB
+FS – 1 LSB
+FS – 1.5 LSB
ANALOG INPUT
By switching each element of the capacitor array between
REFGND or REF, the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536). The
–FS + 0.5 LSB
Figure 4. ADC Ideal Transfer Function
–12–
REV. 0
AD7665
Table III. Output Codes and Ideal Input Voltages
Analog Input
Digital Output Code
(Hexa)
Straight Two’s
Binary Complement
Description
Full-Scale Range
Least Significant Bit 305.2 µV
FSR – 1 LSB
10 V
5 V
152.6 µV
2.5 V
76.3 µV
0 V to 10 V 0 V to 5 V
152.6 µV 76.3 µV
0 V to 2.5 V
38.15 µV
9.999695 V 4.999847 V 2.499924 V 9.999847 V 4.999924 V 2.499962 V FFFF1
7FFF1
0001
0000
Midscale + 1 LSB 305.2 µV
152.6 µV
76.3 µV
5.000153 V 2.570076 V 1.257038 V 8001
5 V 2.5 V 1.25 V 8000
4.999847 V 2.499924 V 1.249962 V 7FFF
Midscale
0 V
0 V
0 V
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
–305.2 µV
–152.6 µV
–76.3 µV
FFFF
8001
–9.999695 V –4.999847 V –2.499924 V 152.6 µV
76.3 µV
38.15 µV
0 V
0001
–10 V
–5 V
–2.5 V
0 V
0 V
00002
80002
NOTES
1This is also the code for an overrange analog input.
2This is also the code for an underrange analog input.
DVDD
100ꢃ
ANALOG
SUPPLY
DIGITAL SUPPLY
(3.3V OR 5V)
NOTE 7
+
(5V)
+
+
100nF
10ꢁF
10ꢁF
100nF
10ꢁF
100nF
ADR421
AVDD AGND
DGND
DVDD
OVDD
OGND
SERIAL
PORT
REF
2.5V REF
NOTE 1
SCLK
SDOUT
BUSY
1Mꢃ
+
C
50kꢃ
REF
NOTE 2
100nF
REFGND
NOTE 3
50ꢃ
ꢁC/ꢁP/DSP
D
CNVST
AD7665
U2
+
INA
NOTE 8
DVDD
10ꢁF
+
100nF
AD8031
NOTE 4
OB/2C
SER/PAR
50ꢃ
WARP
CLOCK
15ꢃ
IMPULSE
CS
U1
+
NOTE 5
IND
ANALOG
INPUT
(ꢀ10V)
2.7nF
AD8021
NOTE
6
RD
C
C
BYTESWAP
RESET
PD
INGND
INB
INC
NOTES :
1. SEE VOLTAGE REFERENCE INPUT CHAPTER.
2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C
IS 47ꢁF. SEE SECTION VOLTAGE REFERENCE INPUT SECTION.
REF
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4. FOR BIPOLAR RANGE ONLY. SEE SCALER REFERENCE INPUT SECTION.
5. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
6. WITH 0 TO 2.5V RANGE ONLY. SEE ANALOG INPUTS SECTION.
7. OPTION. SEE POWER SUPPLY SECTION.
8. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION.
Figure 5. Typical Connection Diagram ( 10 V Range Shown)
REV. 0
–13–
AD7665
TYPICAL CONNECTION DIAGRAM
signals common to both inputs are rejected as shown in Figure 7,
which represents the typical CMRR over frequency. For instance,
by using INGND to sense a remote signal ground, difference of
ground potentials between the sensor and the local ADC ground
are eliminated.
Figure 5 shows a typical connection diagram for the AD7665.
Different circuitry shown on this diagram is optional and is
discussed below.
Analog Inputs
The AD7665 is specified to operate with six full-scale analog
input ranges. Connections required for each of the four ana-
log inputs, IND, INC, INB, INA, and the resulting full-scale
ranges, are shown in Table I. The typical input impedance
for each analog input range is also shown.
75
70
65
60
55
50
45
40
35
Figure 6 shows a simplified analog input section of the AD7665.
The four resistors connected to the four analog inputs form a
resistive scaler which scales-down and shifts the analog input
range to a common input range of 0 V to 2.5 V at the input of
the switched capacitive ADC.
AVDD
4R
IND
1
10
100
1000
10000
4R
FREQUENCY – kHz
INC
R1
C
2R
R
Figure 7. Analog Input CMRR vs. Frequency
INB
INA
S
During the acquisition phase for ac signals, the AD7665 behaves
like a one-pole RC filter consisting of the equivalent resistance
of the resistive scaler R/2 in series with R1 and CS. The resistor
R1 is typically 100 Ω and is a lumped component made up of
some serial resistor and the on-resistance of the switches.
The capacitor CS is typically 60 pF and is mainly the ADC
sampling capacitor. This one-pole filter with a typical –3 dB
cutoff frequency of 3.6 MHz reduces undesirable aliasing effects
and limits the noise coming from the inputs.
R = 1.28kꢃ
AGND
Figure 6. Simplified Analog Input
By connecting the four inputs INA, INB, INC, IND to the input
signal itself, the ground, or a 2.5 V reference, other analog input
ranges can be obtained.
Except when using the 0 V to 2.5 V analog input voltage range,
the AD7665 has to be driven by a very low impedance source to
avoid gain errors. That can be done by using a driver amplifier
whose choice is eased by the primarily resistive analog input
circuitry of the AD7665.
The diodes shown in Figure 6 provide ESD protection for the
four analog inputs. The inputs INB, INC, IND, have a high
voltage protection (–11 V to +30 V) to allow wide input voltage
range. Care must be taken to ensure that the analog input signal
never exceeds the absolute ratings on these inputs including
INA (0 V to 5 V). This will cause these diodes to become forward-
biased and start conducting current. These diodes can handle a
forward-biased current of 120 mA maximum. For instance, when
using the 0 V to 2.5 V input range, these conditions could eventu-
ally occur on the input INA when the input buffer’s (U1) supplies
are different from AVDD. In such case, an input buffer with a
short-circuit current limitation can be used to protect the part.
When using the 0 V to 2.5 V analog input voltage range, the
input impedance of the AD7665 is very high so the AD7665 can
be driven directly by a low impedance source without gain error.
That allows, as shown in Figure 5, putting an external one-
pole RC filter between the output of the amplifier output and
the ADC analog inputs to even further improve the noise
filtering done by the AD7665 analog input circuit. However, the
source impedance has to be kept low because it affects the ac
performances, especially the total harmonic distortion (THD).
The maximum source impedance depends on the amount of
total THD that can be tolerated. The THD degradation is a
function of the source impedance and the maximum input
frequency as shown in Figure 8.
This analog input structure allows the sampling of the differen-
tial signal between the output of the resistive scaler and INGND.
Unlike other converters, the INGND input is sampled at the
same time as the inputs. By using this differential input, small
–14–
REV. 0
AD7665
–70
–80
•
The driver needs to have a THD performance suitable to
that of the AD7665. TPC 8 gives the THD versus frequency
that the driver should preferably exceed.
The AD8021 meets these requirements and is usually appropri-
ate for almost all applications. The AD8021 needs an external
compensation capacitor of 10 pF. This capacitor should have
good linearity as an NPO ceramic or mica type.
R = 100ꢃ
R = 50ꢃ
–90
The AD8022 could also be used where dual version is needed
and gain of 1 is used.
R = 11ꢃ
–100
–110
The AD829 is another alternative where high-frequency (above
100 kHz) performance is not required. In gain of 1, it requires
an 82 pF compensation capacitor.
0
100
1000
The AD8610 is another option where low bias current is needed
in low frequency applications.
FREQUENCY – kHz
Figure 8. THD vs. Analog Input Frequency and Input
Resistance (0 V to 2.5 V Only)
Voltage Reference Input
The AD7665 uses an external 2.5 V voltage reference. The
voltage reference input REF of the AD7665 has a dynamic
input impedance. Therefore, it should be driven by a low
impedance source with an efficient decoupling between REF
and REFGND inputs. This decoupling depends on the choice
of the voltage reference, but usually consists of a low ESR tanta-
lum capacitor connected to the REF and REFGND inputs with
minimum parasitic inductance. 47 µF is an appropriate value for
the tantalum capacitor when used with one of the recommended
reference voltages:
Driver Amplifier Choice
Although the AD7665 is easy to drive, the driver amplifier needs
to meet at least the following requirements:
•
The driver amplifier and the AD7665 analog input circuit
must be able, together, to settle for a full-scale step the capaci-
tor array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, the settling at 0.1% to 0.01% is more commonly speci-
fied. It could significantly differ from the settling time at
16-bit level and it should therefore be verified prior to the
driver selection. The tiny op amp AD8021, which combines
ultralow noise and a high-gain bandwidth, meets this settling
time requirement even when used with a high gain up to 13.
– The low-noise, low-temperature drift ADR421 and AD780
voltage references.
– The low-power ADR291 voltage reference.
– The low-cost AD1582 voltage reference.
•
The noise generated by the driver amplifier needs to be kept
as low as possible in order to preserve the SNR and transi-
tion noise performance of the AD7665. The noise coming
from the driver is first scaled down by the resistive scaler
according to the analog input voltage range used, and is then
filtered by the AD7665 analog input circuit one-pole, low-
pass filter made by (R/2 + R1) and CS. The SNR degradation
due to the amplifier is:
For applications using multiple AD7665s, it is more effective to
buffer the reference voltage with a low-noise, very stable op amp
such as the AD8031.
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference which directly affects the full-scale
accuracy if this parameter matters. For instance, a 15 ppm/°C
tempco of the reference changes the full scale by 1 LSB/°C.
Scaler Reference Input (Bipolar Input Ranges)
When using the AD7665 with bipolar input ranges, the connec-
tion diagram in Figure 5 shows a reference buffer amplifier.
This buffer amplifier is required to isolate the REFIN pin from
the signal dependent current in the AIN pin. A high-speed op
amp such as the AD8031 can be used with a single 5 V power
supply without degrading the performance of the AD7665. The
buffer must have good settling characteristics and provide low
total noise within the input bandwidth of the AD7665.
28
SNRLOSS = 20 log
2
π
2
2.5 N eN
1000 FSR
784 + f–3 dB
where
f–3 dB is the –3 dB input bandwidth of the AD7665 (3.6 MHz)
or the cut-off frequency of the input filter if any used
(0 V to 2.5 V range).
Power Supply
The AD7665 uses three sets of power supply pins: an analog
5 V supply AVDD, a digital 5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.7 V and
5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply as shown in Figure 5. The AD7665 is inde-
pendent of power supply sequencing and thus free from supply
voltage induced latchup. Additionally, it is very insensitive to
power supply variations over a wide frequency range as shown
in Figure 9.
N
is the noise factor of the amplifier (1 if in buffer
configuration).
eN
is the equivalent input noise voltage of the op amp
in nV/(Hz)1/2
.
FSR is the full-scale span (i.e., 5 V for 2.5 V range).
For instance, when using the 0 V to 2.5 V range, a driver like
the AD8021, with an equivalent input noise of 2 nV/√Hz and
configured as a buffer, thus with a noise gain of 1, the SNR
degrades by only 0.12 dB.
REV. 0
–15–
AD7665
75
70
65
60
55
50
45
40
aborted, even by the power-down input PD, until the conver-
sion is complete. The CNVST signal operates independently of
CS and RD signals.
t2
t1
CNVST
BUSY
t4
t3
t6
35
1
t5
10
100
1000
FREQUENCY – kHz
MODE
ACQUIRE
CONVERT
t7
ACQUIRE
t8
CONVERT
Figure 9. PSRR vs. Frequency
POWER DISSIPATION
Figure 11. Basic Conversion Timing
In impulse mode, the AD7665 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows a significant power saving when the conversion rate is
reduced as shown in Figure 10. This feature makes the AD7665
ideal for very low-power battery applications.
In impulse mode, conversions can be automatically initiated. If
CNVST is held low when BUSY is low, the AD7665 controls
the acquisition phase and then automatically initiates a new
conversion. By keeping CNVST low, the AD7665 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up, CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7665 could sometimes
run slightly faster then the guaranteed limits in the impulse
mode of 444 kSPS. This feature does not exist in warp or nor-
mal modes.
This does not take into account the power, if any, dissipated by
the input resistive scaler which depends on the input voltage
range used and the analog input voltage even in power-down
mode. There is no power dissipated when the 0 V to 2.5 V is
used or when both the analog input voltage is 0 V and a unipolar
range, 0 to 5 V or 0 to 10 V, is used.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing. It is a good thing to shield
the CNVST trace with ground and also to add a low value serial
resistor (i.e., 50 V) termination close to the output of the com-
ponent which drives this line.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
For applications where the SNR is critical, CNVST signal should
have a very low jitter. Some solutions to achieve that is to use a
dedicated oscillator for CNVST generation, or at least to clock
it with a high-frequency low-jitter clock as shown in Figure 5.
100000
WARP/NORMAL
10000
1000
100
t9
RESET
10
BUSY
DATA
1
IMPULSE
10
0.1
1
100
1000
10000
100000 1000000
SAMPLING RATE – SPS
t8
Figure 10. Power Dissipation vs. Sample Rate
CNVST
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7665 is controlled by the signal CNVST which
initiates conversion. Once initiated, it cannot be restarted or
Figure 12. RESET Timing
–16–
REV. 0
AD7665
CS = 0
DIGITAL INTERFACE
t1
The AD7665 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7665 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7665
to the host system interface digital supply. Finally, by using the
OB/2C input pin, both two’s complement or straight binary
coding can be used.
CNVST,
RD
BUSY
t4
t3
The two signals CS and RD control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7665 in
multicircuits applications and is held low in a single AD7665
design. RD is generally used to enable the conversion result on
the data bus.
DATA
BUS
PREVIOUS
CONVERSION
t12
t13
Figure 15. Slave Parallel Data Timing for Reading (Read
During Convert)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 16, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16 data bits
can be read in 2 bytes on either D[15:8] or D[7:0].
CS = RD = 0
t1
CNVST
t10
BUSY
t4
t3
t11
CS
RD
DATA
PREVIOUS CONVERSION DATA
NEW DATA
BUS
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
BYTE
PARALLEL INTERFACE
The AD7665 is configured to use the parallel interface when the
SER/PAR is held low. The data can be read either after each
conversion, which is during the next acquisition phase, or dur-
ing the following conversion as shown, respectively, in Figure 14
and Figure 15. When the data is read during the conversion,
however, it is recommended that it be read only during the first
half of the conversion phase. That avoids any potential feed-
through between voltage transients on the digital interface and
the most critical analog conversion circuitry.
HI-Z
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
PINS D[15:8]
PINS D[7:0]
t12
t12
t13
HI-Z
Figure 16. 8-Bit Parallel Interface
SERIAL INTERFACE
The AD7665 is configured to use the serial interface when the
SER/PAR is held high. The AD7665 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on SCLK pin. The output data is
valid on both the rising and falling edge of the data clock.
CS
RD
MASTER SERIAL INTERFACE
Internal Clock
The AD7665 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. It also
generates a SYNC signal to indicate to the host when the serial
data is valid. The serial clock SCLK and the SYNC signal can
be inverted if desired. Depending on RDC/SDIN input, the
data can be read after each conversion or during conversion.
Figure 17 and Figure 18 show the detailed timing diagrams of
these two modes.
BUSY
DATA
BUS
CURRENT
CONVERSION
t12
t13
Usually, because the AD7665 is used with a fast throughput, the
mode master, read during conversion is the most recommended
serial mode when it can be used.
Figure 14. Slave Parallel Data Timing for Reading (Read
After Convert)
REV. 0
–17–
AD7665
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
CS, RD
t3
CNVST
BUSY
t28
t30
t29
t25
SYNC
t14
t18
t19
t24
t20
t21
t26
1
2
3
14
15
16
SCLK
t15
t27
SDOUT
D2
D1
D0
D15
D14
t23
X
t16
t22
Figure 17. Master Serial Data Timing for Reading (Read After Convert)
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
EXT/INT = 0
CS, RD
CNVST
BUSY
t1
t3
t17
t25
SYNC
t14
t19
t20 t21
t24
t26
t15
SCLK
1
2
3
14
15
16
t18
t27
SDOUT
X
D15
D14
t23
D2
D1
D0
t16
t22
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
–18–
REV. 0
AD7665
EXT/INT = 1
INVSCLK = 0
RD = 0
CS
BUSY
t35
t36 t37
SCLK
1
2
3
14
15
16
17
18
t31
t32
X
D15
t34
D14
D13
X13
D1
X1
X15
Y15
X14
Y14
SDOUT
D0
X0
t16
SDIN
X15
X14
t33
Figure 19. Slave Serial Data Timing for Reading (Read After Convert)
In read-during-conversion mode, the serial clock and data toggle
at appropriate instants which minimizes potential feedthrough
between digital activity and the critical conversion decisions.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients on
the digital interface during the conversion process.
In read-after-conversion mode, it should be noted that, unlike in
other modes, the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase which
results in a longer BUSY width.
Another advantage is to be able to read the data at any speed up
to 40 MHz which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7665 provides a “daisy chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing compo-
nent count and wiring connections when desired as, for instance,
in isolated multiconverter applications.
SLAVE SERIAL INTERFACE
External Clock
The AD7665 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read the
data. The external serial clock is gated by CS and the data are
output when both CS and RD are low. Thus, depending on CS,
the data can be read after each conversion or during the follow-
ing conversion. The external clock can be either a continuous or
discontinuous clock. A discontinuous clock can be either nor-
mally high or normally low when inactive. Figure 19 and Figure
21 show the detailed timing diagrams of these methods.
An example of the concatenation of two devices is shown in Fig-
ure 20. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift out
the data on SDOUT. Hence, the MSB of the “upstream” con-
verter just follows the LSB of the “downstream” converter on
the next SCLK cycle.
BUSY
OUT
While the AD7665 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is par-
ticularly important during the second half of the conversion
phase because the AD7665 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is recom-
mended that when an external clock is being provided, it is a
discontinuous clock that is toggling only when BUSY is low or,
more importantly, that is does not transition during the latter
half of BUSY high.
BUSY
BUSY
AD7665
#2
(UPSTREAM)
AD7665
#1
(DOWNSTREAM)
DATA
OUT
RDC/SDIN
SDOUT
RDC/SDIN
SDOUT
CNVST
CS
CNVST
CS
SCLK
SCLK
External Discontinuous Clock Data Read After Conversion
Though the maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both CS and
RD are low. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both rising and falling edge of the clock.
SCLK IN
CS IN
CNVST IN
Figure 20. Two AD7665s in a Daisy-Chain Configuration
REV. 0
–19–
AD7665
INVSCLK = 0
EXT/INT = 1
RD = 0
CS, RD
CNVST
BUSY
t3
t35
t36 t37
SCLK
1
2
3
14
15
16
t31
t32
X
D15
D14
D13
D1
D0
SDOUT
t16
Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
External Clock Data Read During Conversion
if necessary, could be initiated in response to the end-of-conver-
sion signal (BUSY going low) using an interrupt line of the
microcontroller. The Serial Peripheral Interface (SPI) on the
MC68HC11 is configured for master mode (MSTR) = 1, Clock
Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and SPI
interrupt enable (SPIE) = 1 by writing to the SPI Control Regis-
ter (SPCR). The IRQ is configured for edge-sensitive-only
operation (IRQE = 1 in OPTION register).
Figure 21 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses and is valid on both rising and
falling edge of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no “daisy chain” fea-
ture in this mode and RDC/SDIN input should always be tied
either high or low.
DVDD
AD7665*
MC68HC11*
SER/PAR
To reduce performance degradation due to digital activity, a fast
discontinuous clock of, at least 25 MHz, when impulse mode is
used, 40 MHz when normal or warp mode is used, is recom-
mended to ensure that all the bits are read during the first half
of the conversion phase. It is also possible to begin to read the
data after conversion and continue to read the last bits even after
a new conversion has been initiated. That allows the use of a slower
clock speed like 10 MHz in impulse mode, 12 MHz in normal
mode and 15 MHz in warp mode.
EXT/INT
CS
RD
IRQ
BUSY
SDOUT
SCLK
MISO/SDI
SCK
INVSCLK
CNVST
I/O PORT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Interfacing the AD7665 to SPI Interface
MICROPROCESSOR INTERFACING
ADSP-21065L in Master Serial Interface
The AD7665 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal process-
ing applications interfacing to a digital signal processor. The
AD7665 is designed to interface either with a parallel 8-bit or
16-bit wide interface or with a general purpose serial port or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7665 to prevent digital noise from coupling
into the ADC. The following sections illustrate the use of the
AD7665 with an SPI equipped microcontroller, the ADSP-
21065L and ADSP-218x signal processors.
As shown in Figure 23, the AD7665 can be interfaced to the
ADSP-21065L using the serial interface in master mode without
any glue logic required. This mode combines the advantages
of reducing the wire connections and the ability to read the
data during or after conversion maximum speed transfer
(DIVSCLK[0:1] both low).
The AD7665 is configured for the internal clock mode (EXT/
INT low) and acts, therefore, as the master device. The convert
command can be generated by either an external low jitter oscil-
lator or, as shown, by a FLAG output of the ADSP-21065L or
by a frame output TFS of one serial port of the ADSP-21065L
which can be used like a timer. The serial port on the ADSP-
21065L is configured for external clock (IRFS = 0), rising edge
active (CKRE = 1), external late framed sync signals (IRFS = 0,
LAFS = 1, RFSR = 1) and active high (LRFS = 0). The serial
port of the ADSP-21065L is configured by writing to its receive
control register (SRCTL)—see ADSP-2106x SHARC User’s
Manual. Because the serial port within the ADSP-21065L will
SPI Interface (MC68HC11)
Figure 22 shows an interface diagram between the AD7665 and
an SPI-equipped microcontroller like the MC68HC11. To
accommodate the slower speed of the microcontroller, the
AD7665 acts as a slave device and data must be read after con-
version. This mode also allows the “daisy chain” feature. The
convert command could be initiated in response to an internal
timer interrupt. The reading of output data, one byte at a time,
–20–
REV. 0
AD7665
be seeing a discontinuous clock, an initial word reading has to
be done after the ADSP-21065L has been reset to ensure that
the serial port is properly synchronized to this clock during each
following data read operation.
The power supply lines to the AD7665 should use as large a trace
as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the supplies impedance presented to the
AD7665 and reduce the magnitude of the supply spikes. Decoupling
ceramic capacitors, typically 100 nF, should be placed on each
power supplies pins AVDD, DVDD and OVDD close to, and
ideally right up against these pins and their corresponding
ground pins. Additionally, low ESR 10 µF capacitors should be
located in the vicinity of the ADC to further reduce low fre-
quency ripple.
DVDD
AD7665*
ADSP-21065L*
SHARC
SER/PAR
RDC/SDIN
RD
EXT/INT
CS
RFS
SYNC
SDOUT
SCLK
DR
The DVDD supply of the AD7665 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, it is recom-
mended if no separate supply available, to connect the DVDD
digital supply to the analog supply AVDD through an RC filter
as shown in Figure 5, and connect the system supply to the
interface digital supply OVDD and the remaining digital cir-
cuitry. When DVDD is powered from the system supply, it is
useful to insert a bead to further reduce high-frequency spikes.
INVSYNC
INVSCLK
RCLK
CNVST
FLAG OR TFS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Interfacing to the ADSP-21065L Using the
Serial Master Mode
APPLICATION HINTS
Layout
The AD7665 has very good immunity to noise on the power
supplies as can be seen in Figure 9. However, care should still
be taken with regard to grounding layout.
The AD7665 has five different ground pins; INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the
analog input signal. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground plane
depending on the configuration. OGND is connected to the
digital system ground.
The printed circuit board that houses the AD7665 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7665, or, at least, as close as possible to the
AD7665. If the AD7665 is in a system where multiple devices
require analog-to-digital ground connections, the connection
should still be made at one point only, a star ground point,
which should be established as close as possible to the AD7665.
The layout of the decoupling of the reference voltage is impor-
tant. The decoupling capacitor should be close to the ADC and
connected with short and large traces to minimize parasitic
inductances.
It is recommended to avoid running digital lines under the de-
vice as these will couple noise onto the die. The analog ground
plane should be allowed to run under the AD7665 to avoid
noise coupling. Fast switching signals like CNVST or clocks
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and should never run near analog
signal paths. Crossover of digital and analog signals should be
avoided. Traces on different but close layers of the board should
run at right angles to each other. This will reduce the effect of
feedthrough through the board.
Evaluating the AD7665 Performance
A recommended layout for the AD7665 is outlined in the evalu-
ation board for the AD7665. The evaluation board package
includes a fully assembled and tested evaluation board, docu-
mentation, and software for controlling the board from a PC
via the Eval-Control Board.
REV. 0
–21–
AD7665
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Quad Flatpack (LQFP)
(ST-48)
0.067 (1.70)
0.362 (9.19)
0.059 (1.50)
0.354 (9.00) SQ
0.346 (8.79)
0.055 (1.40)
0.039 (1.00)
REF
0.028 (0.7)
0.020 (0.5)
0.012 (0.3)
36
25
37
24
SEATING
PLANE
0.280 (7.1)
0.276 (7.0) SQ
0.272 (6.9)
TOP VIEW
(PINS DOWN)
0.006 (0.15)
0.004 (0.10)
0.002 (0.05)
48
13
12
0ꢂ
MIN
1
0.010 (0.26)
0.007 (0.18)
0.006 (0.15)
0.007 (0.177)
0.005 (0.127)
0.004 (0.107)
0.023 (0.58)
0.020 (0.50)
0.017 (0.42)
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
7ꢂ
3.5ꢂ
0ꢂ
–22–
REV. 0
–23–
–24–
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