EVAL-AD7324CB [ADI]
4-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC; 4通道，软件可选的真双极性输入， 12位加符号位ADC
| 型号： | EVAL-AD7324CB |
| 厂家： | 
ADI |
| 描述： | 4-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC |
| 文件： | 总36页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-Channel, Software-Selectable, True
Bipolar Input, 12-Bit Plus Sign ADC
AD7324
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
REFIN/OUT
V
12-bit plus sign SAR ADC
DD
CC
True bipolar input ranges
AD7324
Software-selectable input ranges
10 V, 5 V, 2.5 V, 0 V to +10 V
1 MSPS throughput rate
2.5V
VREF
V
V
V
V
0
1
2
3
IN
IN
IN
IN
13-BIT
I/P
MUX
SUCCESSIVE
APPROXIMATION
ADC
T/H
Four analog input channels with channel sequencer
Single-ended, true differential, and pseudo differential
analog input capability
High analog input impedance
Low power: 21 mW
Full power signal bandwidth: 22 MHz
Internal 2.5 V reference
DOUT
SCLK
CS
CONTROL LOGIC
AND REGISTERS
CHANNEL
SEQUENCER
DIN
High speed serial interface
Power-down modes
V
DRIVE
16-lead TSSOP package
iCMOS™ process technology
AGND
V
DGND
SS
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD73241 is a 4-channel, 12-bit plus sign, successive
approximation ADC designed on the iCMOS (industrial
CMOS) process. iCMOS is a process combining high voltage
silicon with submicron CMOS and complementary bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 33 ꢁ operation in a footprint
that no previous generation of high voltage parts could achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can accept bipolar input signals while providing
increased performance, dramatically reduced power
1. The AD7324 can accept true bipolar analog input signals,
±1ꢀ ꢁ, ±± ꢁ, ±2.± ꢁ, and ꢀ ꢁ to +1ꢀ ꢁ unipolar signals.
2. The four analog inputs can be configured as four single-
ended inputs, two true differential input pairs, two pseudo
differential inputs, or three pseudo differential inputs.
3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-
compatible interface.
4. Low power, 3ꢀ mW maximum, at 1 MSPS throughput rate.
consumption, and reduced package size.
±. Channel sequencer.
The AD7324 can accept true bipolar analog input signals. The
AD7324 has four software-selectable input ranges, ±1ꢀ ꢁ, ±± ꢁ,
±2.± ꢁ, and ꢀ ꢁ to +1ꢀ ꢁ. Each analog input channel can be
independently programmed to one of the four input ranges.
The analog input channels on the AD7324 can be programmed
to be single-ended, true differential, or pseudo differential.
Table 1. Similar Products Selection Table
Device
Number Rate
Throughput
Number of
Channels
Number of bits
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
AD7329
AD7328
AD7327
AD7323
AD7322
AD7321
250 kSPS
8
8
8
4
2
2
1000 kSPS
500 kSPS
500 kSPS
1000 kSPS
500 kSPS
The ADC contains a 2.± ꢁ internal reference. The AD7324 also
allows for external reference operation. If a 3 ꢁ reference is
applied to the REFIN/OUT pin, the AD7324 can accept a true
bipolar ±12 ꢁ analog input. Minimum ±12 ꢁ ꢁDD and ꢁSS
supplies are required for the ±12 ꢁ input range. The ADC has a
high speed serial interface that can operate at throughput rates
up to 1 MSPS.
1 Protected by U.S. Patent No. 6,731,232.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2005 Analog Devices, Inc. All rights reserved.
AD7324
TABLE OF CONTENTS
Features .............................................................................................. 1
Control Register ......................................................................... 23
Sequence Register....................................................................... 2±
Range Register ............................................................................ 2±
Sequencer Operation ..................................................................... 26
Reference ..................................................................................... 28
ꢁDRIꢁE ............................................................................................ 28
Modes of Operation ....................................................................... 29
Normal Mode.............................................................................. 29
Full Shutdown Mode.................................................................. 29
Autoshutdown Mode ................................................................. 3ꢀ
Autostandby Mode..................................................................... 3ꢀ
Power vs. Throughput Rate....................................................... 31
Serial Interface ................................................................................ 32
Microprocessor Interfacing........................................................... 33
AD7324 to ADSP-218x.............................................................. 33
AD7324 to ADSP-BF±3x........................................................... 33
Application Hints ........................................................................... 34
Layout and Grounding .............................................................. 34
Outline Dimensions....................................................................... 3±
Ordering Guide .......................................................................... 3±
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 1ꢀ
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 16
Circuit Information.................................................................... 16
Converter Operation.................................................................. 16
Analog Input Structure.............................................................. 17
Typical Connection Diagram ................................................... 19
Analog Input ............................................................................... 19
Driver Amplifier Choice............................................................ 21
Registers........................................................................................... 22
Addressing Registers.................................................................. 22
REVISION HISTORY
12/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD7324
SPECIFICATIONS
Unless otherwise noted, ꢁDD = 12 ꢁ to 16.± ꢁ, ꢁSS = −12 ꢁ to −16.± ꢁ, ꢁCC = 4.7± ꢁ to ±.2± ꢁ, ꢁDRIꢁE = 2.7 ꢁ to ±.2± ꢁ, ꢁREF = 2.± ꢁ to 3.ꢀ ꢁ
internal/external, fSCLK = 2ꢀ MHz, fS = 1 MSPS, TA = TMAX to TMIN with ꢁCC < 4.7± ꢁ, all specifications are typical.
Table 2.
B Version
Typ
Parameter1
Min
Max
Unit
Test Conditions/Comments
FIN = 50 kHz sine wave
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)2
76
72.5
75
dB
dB
dB
Differential mode
Single-ended/pseudo differential mode
Differential mode; 2.5 V and 5 V ranges
Signal-to-Noise + Distortion
(SINAD)2
76
dB
dB
Differential mode; 0 V to 10 V and 10 V ranges
Single-ended/pseudo differential mode; 2.5 V and
5 V ranges
72
72.5
−82
−80
dB
Single-ended/pseudo differential mode; 0 V to +10 V
and 10 V ranges
Differential mode; 2.5 V and 5 V ranges
Differential mode; 0 V to +10 V and 10 V ranges
Single-ended/pseudo differential mode; 2.5 V and
5 V ranges
Single-ended/pseudo differential mode; 0 V to +10 V
and 10 V ranges
Differential mode; 2.5 V and 5 V ranges
Total Harmonic Distortion (THD)2
−80
−77
dB
dB
dB
dB
dB
Peak Harmonic or Spurious Noise
(SFDR)2
−80
−78
−82
−79
dB
dB
Differential mode; 0 V to +10 V and 10 V ranges
Single-ended/pseudo differential mode; 2.5 V and 5 V
ranges
Single-ended/pseudo differential mode; 0 V to +10 V
and 10 V ranges
dB
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
fa = 50 kHz, fb = 30 kHz
−88
−90
7
50
−79
dB
dB
ns
ps
dB
Aperture Delay3
Aperture Jitter3
Common-Mode Rejection Ratio
Up to 100 kHz ripple frequency; see Figure 17
(CMRR)2
Channel-to-Channel Isolation2
Full Power Bandwidth
−72
22
5
dB
MHz
MHz
FIN on unselected channels up to 100 kHz; see Figure 14
At 3 dB
At 0.1 dB
Rev. 0 | Page 3 of 36
AD7324
B Version
Typ
Parameter1
DC ACCURACY4
Min
Max
Unit
Test Conditions/Comments
All dc accuracy specifications are typical for 0 V to
10 V mode.
Resolution
No Missing Codes
13
12-bit
Bits
Bits
Differential mode
plus sign
11-bit
Bits
Single-ended/pseudo differential mode
plus sign
Integral Nonlinearity2
1.1
1
LSB
LSB
LSB
Differential mode
Single-ended/pseudo differential mode
Single-ended/pseudo differential mode
(LSB = FSR/8192)
−0.7/+1.2
−0.7/+1
Differential Nonlinearity2
−0.9/+1.5 LSB
Differential mode; guaranteed no missing codes to
13 bits
Single-ended mode; guaranteed no missing codes to
12 bits
Single-ended/psuedo differential mode
(LSB = FSR/8192)
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
0.9
LSB
LSB
Offset Error2, 5
−4/+9
−7/+10
0.6
0.5
8
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Offset Error Match2, 5
Gain Error2, 5
14
Gain Error Match2, 5
0.5
0.5
4
Positive Full-Scale Error2, 6
Positive Full-Scale Error Match2, 6
Bipolar Zero Error2, 6
7
0.5
0.5
8.5
7.5
0.5
0.5
4
6
0.5
0.5
Bipolar Zero Error Match2, 6
Negative Full-Scale Error2, 6
Negative Full-Scale Error Match2, 6
Single-ended/pseudo differential mode
Differential mode
Rev. 0 | Page 4 of 36
AD7324
B Version
Typ
Parameter1
Min
Max
Unit
Test Conditions/Comments
ANALOG INPUT
Input Voltage Ranges
Reference = 2.5 V; see Table 6
(Programmed via Range
Register)
10
V
VDD = 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V
5
2.5
0 to 10
V
V
V
VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V
VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V
VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V
Pseudo Differential VIN(−)
Input Range
VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 40 and
Figure 41
3.5
6
5
V
V
V
V
nA
nA
pF
pF
pF
pF
Reference = 2.5 V; range = 10 V
Reference = 2.5 V; range = 5 V
Reference = 2.5 V; range = 2.5 V
Reference = 2.5 V; range = 0 V to +10 V
VIN = VDD or VSS
Per channel, VIN = VDD or VSS
When in track, 10 V range
When in track, 5 V and 0 V to +10 V ranges
When in track, 2.5 V range
When in hold, all ranges
+3/−5
DC Leakage Current
Input Capacitance3
80
3
13.5
16.5
21.5
3
REFERENCE INPUT/OUTPUT
Input Voltage Range
Input DC Leakage Current
Input Capacitance
2.5
3
1
V
μA
pF
V
10
2.5
Reference Output Voltage
Reference Output Voltage Error
@ 25°C
Reference Output Voltage
TMIN to TMAX
Reference Temperature
Coefficient
5
10
25
mV
mV
ppm/°C
3
7
ppm/°C
Ω
Reference Output Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
2.4
V
V
V
μA
pF
0.8
0.4
1
VCC = 4.75 V to 5.25 V
VCC = 2.7 to 3.6 V
VIN = 0 V or VDRIVE
Input Current, IIN
3
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
VDRIVE
0.2 V
−
V
ISOURCE = 200 μA
ISINK = 200 μA
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output
Capacitance3
0.4
1
V
μA
pF
5
Output Coding
Straight natural binary
Twos complement
Coding bit set to 1 in control register
Coding bit set to 0 in control register
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition
Time2, 3
800
305
ns
ns
16 SCLK cycles with SCLK = 20 MHz
Full-scale step input; see the Terminology section
Throughput Rate
1
770
MSPS
kSPS
See the Serial Interface section; VCC = 4.75 V to 5.25 V
VCC < 4.75 V
Rev. 0 | Page 5 of 36
AD7324
B Version
Typ
Parameter1
Min
Max
Unit
Test Conditions/Comments
Digital inputs = 0 V or VDRIVE
See Table 6
POWER REQUIREMENTS
VDD
VSS
VCC
12
16.5
−16.5
5.25
5.25
V
V
V
V
−12
2.7
2.7
See Table 6
See Table 6; typical specifications for VCC < 4.75 V
VDRIVE
Normal Mode (Static)
0.9
mA
VDD/VSS = 16.5 V, VCC/VDRIVE = 5.25 V
Normal Mode (Operational)
IDD
ISS
ICC and IDRIVE
Autostandby Mode (Dynamic)
IDD
ISS
ICC and IDRIVE
Autoshutdown Mode (Static)
IDD
ISS
ICC and IDRIVE
Full Shutdown Mode
IDD
fSAMPLE = 1 MSPS
VDD = 16.5 V
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
FSAMPLE = 250 kSPS
VDD = 16.5 V
360
410
3.2
μA
μA
mA
200
210
1.3
μA
μA
mA
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
SCLK on or off
VDD = 16.5 V
1
1
1
μA
μA
μA
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
SCLK on or off
VDD = 16.5 V
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
1
1
1
μA
μA
μA
ISS
ICC and IDRIVE
POWER DISSIPATION
Normal Mode (Operational)
30
mW
mW
μW
VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V
VDD = 12 V, VSS = −12 V, VCC = 5 V
VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V
21
Full Shutdown Mode
38.25
1 Temperature range is −40°C to +85°C.
2 See the Terminology section.
3 Sample tested during initial release to ensure compliance.
4 For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless
otherwise noted.
5 Unipolar 0 V to 10 V range with straight binary output coding.
6 Bipolar range with twos complement output coding.
Rev. 0 | Page 6 of 36
AD7324
TIMING SPECIFICATIONS
ꢁDD = 12 ꢁ to 16.± ꢁ, ꢁSS = −12 ꢁ to −16.± ꢁ, ꢁCC = 2.7 ꢁ to ±.2± ꢁ, ꢁDRIꢁE = 2.7 ꢁ to ±.2±, ꢁREF = 2.± ꢁ to 3.ꢀ ꢁ Internal/External,
TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted.1
Table 3.
Limit at TMIN, TMAX
Description
VDRIVE ≤ VCC
Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit
fSCLK
50
14
16 × tSCLK
75
50
20
16 × tSCLK
60
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
μs max
μs typ
tCONVERT
tQUIET
t1
tSCLK = 1/fSCLK
CS
Minimum time between end of serial read and next falling edge of
CS
Minimum pulse width
12
5
2
t2
25
20
CS
to SCLK setup time; bipolar input ranges ( 10 V, 5 V, 2.5 V)
Unipolar input range (0 V to 10 V)
CS
45
26
35
14
t3
t4
t5
t6
t7
t8
Delay from
until DOUT three-state disabled
57
0.4 × tSCLK
0.4 × tSCLK
13
40
10
4
43
0.4 × tSCLK
0.4 × tSCLK
8
22
9
4
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power up from autostandby
t9
t10
tPOWER-UP
2
2
750
500
25
750
500
25
Power up from full shutdown/autoshutdown mode, internal reference
Power up from full shutdown/autoshutdown mode, external reference
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2 When using VCC = 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to
50:50.
t1
CS
tCONVERT
t2
t6
1
2
3
4
5
13
14
t5
15
16
SCLK
DOUT
2 IDENTIFICATION BITS
t3
t7
t8
t4
tQUIET
ADD1
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
ZERO
THREE-STATE
t10
t9
DON’T
CARE
REG
SEL1
REG
SEL2
WRITE
MSB
LSB
DIN
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 7 of 36
AD7324
ABSOLUTE MAXIMUM RATINGS
TA = 2±°C, unless otherwise noted
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to AGND, DGND
VSS to AGND, DGND
VDD to VCC
VCC to AGND, DGND
VDRIVE to AGND, DGND
AGND to DGND
Analog Input Voltage to AGND1
Digital Input Voltage to DGND
Digital Output Voltage to GND
REFIN to AGND
Input Current to Any Pin
Except Supplies2
−0.3 V to +16.5 V
+0.3 V to −16.5 V
VCC − 0.3 V to 16.5 V
−0.3 V to +7 V
−0.3 V to + 7 V
−0.3 V to +0.3 V
VSS −0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VCC + 0.3 V
10 mA
Operating Temperature Range
Storage Temperature Range
Junction Temperature
TSSOP Package
−40°C to +85°C
−65°C to +150°C
150°C
θJA Thermal Impedance
θJC Thermal Impedance
Pb-Free Temperature, Soldering
Reflow
150.4°C/W
27.6°C/W
260(0)°C
2.5 kV
ESD
1 If the analog inputs are being driven from alternative VDD and VSS supply
circuitry, Schottky diodes should be placed in series with the AD7324’s VDD
and VSS supplies.
2 Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 36
AD7324
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CS
SCLK
DGND
DOUT
DIN
DGND
AD7324
TOP VIEW
(Not to Scale)
AGND
V
V
V
V
V
DRIVE
CC
REFIN/OUT
V
SS
DD
V
V
0
2
IN
IN
IN
1
3
IN
Figure 3. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7324 and frames the serial data transfer.
2
DIN
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the
register on the falling edge of SCLK (see the Reference section).
3, 15
DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7324. The DGND and AGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
4
5
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7324. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
REFIN/OUT Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the
AD7324. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor
should be placed on the reference pin. Alternatively, the internal reference can be disabled and an
external reference applied to this input. On power-up, the external reference mode is the default
condition (see the Reference section).
6
VSS
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
7, 8, 10, 9
VIN0 to VIN3 Analog Input 0 to Analog Input 3. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the Channel Address Bit ADD1
and ADD0 in the control register. The inputs can be configured as four single-ended inputs, two true
differential input pairs, two pseudo differential inputs, or three pseudo differential inputs. The config-
uration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and Bit Mode 0, in
the control register. The input range on each input channel is controlled by programming the range
register. Input ranges of 10 V, 5 V, 2.5 V, and 0 V to +10 V can be selected on each analog input
channel when a +2.5 V reference voltage is used (see the Reference section).
11
12
VDD
VCC
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7324.
This supply should be decoupled to AGND. Specifications apply from VCC = 4.75 V to 5.25 V.
13
14
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VCC
but it should not exceed VCC by more than 0.3 V.
,
DOUT
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The
data stream consists of a leading ZERO bit, two channel identification bits, the sign bit, and 12 bits of
conversion data. The data is provided MSB first (see the Serial Interface section).
16
SCLK
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the
AD7324. This clock is also used as the clock source for the conversion process.
Rev. 0 | Page 9 of 36
AD7324
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0
V
= V
DRIVE
= 5V INT/EXT 2.5V REFERENCE
±10V RANGE
CC
= 25°C
4096 POINT FFT
T
A
V
V
= V = 5V
CC
DRIVE
V
, V = ±15V
+INL = +0.55LSB
–INL = –0.68LSB
–20
–40
DD SS
, V = ±15V
DD SS
0.6
T
= 25°C
A
INT/EXT 2.5V REFERENCE
±10V RANGE
0.4
F
= 50kHz
IN
0.2
SNR = 77.30dB
SINAD = 76.85dB
THD = –86.96dB
SFDR = –88.22dB
–60
0
–80
–0.2
–0.4
–0.6
–0.8
–1.0
–100
–120
–140
0
1024
2048
3072
3584
CODE
4096
5120
6144
7168
8192
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
512 1536
2560
4608
5632
6656
7680
Figure 7. Typical INL True Differential Mode
Figure 4. FFT True Differential Mode
1.0
0.8
0
–20
4096 POINT FFT
V
V
= V = 5V
CC
DRIVE
0.6
, V = ±15V
DD SS
T
= 25°C
A
INT/EXT 2.5V REFERENCE
±10V RANGE
0.4
–40
F
= 50kHz
0.2
IN
SNR = 74.67dB
SINAD = 74.03dB
THD = –82.68dB
SFDR = –85.40dB
–60
0
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–100
–120
–140
V
CC
= V
DRIVE
= 5V
±10V RANGE
+DNL = +0.79LSB
–DNL = –0.38LSB
T
= 25°C
A
V
, V = ±15V
DD SS
INT/EXT 2.5V REFERENCE
0
1024
2048
3072
3584
CODE
4096
5120
6144
7168
8192
512 1536
2560
4608
5632
6656
7680
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
Figure 8. Typical DNL Single-Ended Mode
Figure 5. FFT Single-Ended Mode
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
V
= V = 5V
DRIVE
CC
= 25°C
V
= V = 5V
DRIVE
CC
= 25°C
T
A
T
A
V
, V = ±15V
DD SS
V
, V = ±15V
DD SS
INT/EXT 2.5V REFERENCE
±10V RANGE
+INL = +0.87LSB
–INL = –0.49LSB
INT/EXT 2.5V REFERENCE
±10V RANGE
+DNL = +0.72LSB
–DNL = –0.22LSB
0
1024
2048
3072
3584
CODE
4096
5120
6144
7168
8192
0
1024
2048
3072
3584
CODE
4096
5120
6144
7168
8192
512 1536
2560
4608
5632
6656
7680
512
1536 2560
4608
5632
6656
7680
Figure 6. Typical DNL True Differential Mode
Figure 9. Typical INL Single-Ended Mode
Rev. 0 | Page 10 of 36
AD7324
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
80
75
70
65
60
55
50
V
V
= 5V
CC
±5V DIFF
±10V DIFF
/V = ±12V
DD SS
T
f
= 25°C
= 1MSPS
A
±2.5V DIFF
S
±10V SE
0V TO +10V DIFF
0V TO +10V SE
0V TO +10V SE
±5V SE
±2.5V SE
±5V SE
±10V DIFF
±10V SE
±5V DIFF
0V TO +10V DIFF
±2.5V DIFF
±2.5V SE
V
= 3V
CC
V
/V = ±12V
DD SS
T
= 25°C
A
f
= 1MSPS
S
10
100
1000
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
ANALOG INPUT FREQUENCY (kHz)
Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 5 V VCC
Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and
Differential Mode (Diff) at 3 V VCC
–50
–55
–50
V
V
= 3V
CC
/V = ±12V
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
DD SS
T
f
= 25°C
= 1MSPS
A
S
V
= 3V
–60
–65
–70
–75
–80
–85
–90
–95
CC
±10V SE
V
= 5V
CC
0V TO +10V DIFF
±5V SE
0V TO +10V SE
±10V DIFF
±2.5V SE
±5V DIFF
V
/V = ±12V
DD SS
SINGLE-ENDED MODE
= 1MSPS
f
S
T
= 25°C
A
50kHz ON SELECTED CHANNEL
±2.5V DIFF
0
100
200
300
400
500
600
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
FREQUENCY OF INPUT NOISE (kHz)
Figure 14. Channel-to-Channel Isolation
Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 3 V VCC
80
10k
9469
V
V
= 5V
CC
±10V DIFF
±5V DIFF
9k
8k
7k
6k
5k
4k
3k
2k
1k
0
/V = ±12V
DD SS
RANGE = ±10V
10k SAMPLES
75
70
65
60
55
50
±2.5V DIFF
T
= 25°C
A
±2.5V SE
±5V SE
0V TO +10V SE
±10V SE
0V TO +10V DIFF
V
V
= 5V
CC
/V = ±12V
DD SS
T
= 25°C
= 1MSPS
A
f
228
–1
303
1
S
0
0
2
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
–2
0
CODE
Figure 12. SINAD vs. Analog Input Frequency for Single-Ended (SE) and
Differential Mode (Diff) at 5 V VCC
Figure 15. Histogram of Codes, True Differential Mode
Rev. 0 | Page 11 of 36
AD7324
2.0
1.5
8k
7k
6k
5k
4k
3k
2k
1k
0
7600
V
V
= 5V
CC
/V = ±12V
DD SS
RANGE = ±10V
10k SAMPLES
INL = 500kSPS
INL = 500kSPS
INL = 750kSPS
1.0
T
= 25°C
A
0.5
INL = 1MSPS
0
INL = 750kSPS
–0.5
–1.0
–1.5
–2.0
±5V RANGE
= V
1201
–1
1165
1
INL = 1MSPS
V
= 5V
DRIVE
CC
INTERNAL REFERENCE
SINGLE-ENDED MODE
0
23
–2
11
2
0
3
5
7
9
11
13
15
17
19
–3
0
±V /V SUPPLY VOLTAGE (V)
DD SS
CODE
Figure 16. Histogram of Codes, Single-Ended Mode
Figure 19. INL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–50
100mV p-p SINE WAVE ON EACH SUPPLY
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
NO DECOUPLING
SINGLE-ENDED MODE
f
= 1MSPS
S
V
= 5V
CC
V
V
= 3V
CC
DD
V
= 5V
CC
= 12V
V
= 3V
CC
DIFFERENTIAL MODE
V
= –12V
SS
F
= 50kHz
IN
V
/V = ±12V
DD SS
f
= 1MSPS
S
T
= 25°C
A
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
RIPPLE FREQUENCY (kHz)
SUPPLY RIPPLE FREQUENCY (kHz)
Figure 17. CMRR vs. Common-Mode Ripple Frequency
Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
2.0
1.5
–50
V
V
= V = 5V
DRIVE
CC
DNL = 750kSPS
/V = ±12V
DD SS
–55
–60
–65
–70
–75
–80
–85
–90
–95
T
= 25°C
A
DNL = 500kSPS
INTERNAL REFERENCE
RANGE = ±10V AND ±2.5V
R
= 100Ω, ±10V RANGE
IN
1.0
R
= 50Ω,
IN
±10V RANGE
R
= 2000Ω, ±10V RANGE
IN
0.5
DNL = 1MSPS
R
= 4700Ω,
IN
±2.5V RANGE
R
= 1000Ω, ±10V RANGE
IN
DNL = 1MSPS
0
R
= 2000Ω,
IN
±2.5V RANGE
–0.5
–1.0
–1.5
–2.0
R
= 1000Ω,
IN
±2.5V RANGE
DNL = 750kSPS
DNL = 500kSPS
R
= 100Ω,
IN
±2.5V RANGE
±5V RANGE
= V
INTERNAL REFERENCE
V
= 5V
DRIVE
CC
R
= 50Ω,
IN
±2.5V RANGE
SINGLE-ENDED MODE
10
100
ANALOG INPUT FREQUENCY (kHz)
1000
5
7
9
11
13
15
17
19
±V /V SUPPLY VOLTAGE (V)
DD SS
Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,
True Differential Mode
Figure 18. DNL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS
Rev. 0 | Page 12 of 36
AD7324
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
V
V
= V = 5V
DRIVE
CC
/V = ±12V
DD SS
T
= 25°C
A
INTERNAL REFERENCE
RANGE = ±10V AND ±2.5V
R
= 100Ω,
IN
±10V RANGE
R
= 2000Ω, ±10V RANGE
IN
R
= 50Ω,
IN
±10V RANGE
R
= 1000Ω, ±10V RANGE
IN
R
= 2000Ω,
IN
±2.5V RANGE
R
= 1000Ω,
IN
±2.5V RANGE
R
= 100Ω,
IN
±2.5V RANGE
R
= 50Ω,
IN
±2.5V RANGE
10
100
INPUT FREQUENCY (kHz)
1000
Figure 22. THD vs. Analog Input Frequency for Various
Source Impedances, Single-Ended Mode
Rev. 0 | Page 13 of 36
AD7324
TERMINOLOGY
Differential Nonlinearity
Negative Full-Scale Error
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
This applies when using twos complement output coding and
any of the bipolar analog input ranges. This is the deviation of
the first code transition (1ꢀ … ꢀꢀꢀ) to (1ꢀ … ꢀꢀ1) from the ideal
(that is, −4 × ꢁREF + 1 LSB, −2 × ꢁREF + 1 LSB, −ꢁREF + 1 LSB)
after adjusting for the bipolar zero code error.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (a point 1 LSB
below the first code transition) and full scale (a point 1 LSB
above the last code transition).
Negative Full-Scale Error Match
This is the difference in negative full-scale error between any
two input channels.
Offset Code Error
Track-and-Hold Acquisition Time
This applies to straight binary output coding. It is the deviation
of the first code transition (ꢀꢀ ... ꢀꢀꢀ) to (ꢀꢀ ... ꢀꢀ1) from the
ideal, that is, AGND + 1 LSB.
The track-and-hold amplifier returns into track mode after the
14th SCLK rising edge. Track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±1/2 LSB, after the end of a conversion.
For the ±2.±ꢁ range, the specified acquisition time is the time
required for the track-and-hold amplifier to settle to within ±1 LSB.
Offset Error Match
This is the difference in offset error between any two input
channels.
Signal to (Noise + Distortion) Ratio
Gain Error
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digi-
tization process. The more levels, the smaller the quantization
noise. Theoretically, the signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by
This applies to straight binary output coding. It is the deviation
of the last code transition (111 ... 11ꢀ) to (111 ... 111) from the
ideal (that is, 4 × ꢁREF − 1 LSB, 2 × ꢁREF − 1 LSB, ꢁREF − 1 LSB)
after adjusting for the offset error.
Gain Error Match
This is the difference in gain error between any two input
channels.
Signal to (Noise + Distortion) = (6.ꢀ2 N + 1.76) dB
Bipolar Zero Code Error
This applies when using twos complement output coding and a
bipolar analog input. It is the deviation of the midscale
transition (all 1s to all ꢀs) from the ideal input voltage, that is,
AGND − 1 LSB.
For a 13-bit converter, this is 8ꢀ.ꢀ2 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7324, it is defined as
Bipolar Zero Code Error Match
This refers to the difference in bipolar zero code error between
any two input channels.
2
2
2
2
2
V2 +V3 +V4 +V± +V6
THD (dB) = 2ꢀ log
V1
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Positive Full-Scale Error
This applies when using twos complement output coding and
any of the bipolar analog input ranges. It is the deviation of the
last code transition (ꢀ11 … 11ꢀ) to (ꢀ11 … 111) from the ideal
(4 × ꢁREF − 1 LSB, 2 × ꢁREF − 1 LSB, ꢁREF − 1 LSB) after
adjusting for the bipolar zero code error.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, the
largest harmonic could be a noise peak.
Positive Full-Scale Error Match
This is the difference in positive full-scale error between any
two input channels.
Rev. 0 | Page 14 of 36
AD7324
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
per the THD specification, where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of
the sum of the fundamentals expressed in decibels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between any two channels. It is measured by applying a full-scale,
1ꢀꢀ kHz sine wave signal to all unselected input channels and
determining the degree to which the signal attenuates in the
selected channel with a ±ꢀ kHz signal. Figure 14 shows the worst-
case across all eight channels for the AD7324. The analog input
range is programmed to be the same on all channels.
PSR (Power Supply Rejection)
ꢁariations in power supply affect the full-scale transition but
not the linearity of the converter. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value (see the
Typical Performance Characteristics section).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = ꢀ, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to ꢀ. For example,
the second-order terms include (fa + fb) and (fa − fb), whereas
the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb),
and (fa − 2fb).
CMRR (Common-Mode Rejection Ratio)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 1ꢀꢀ mꢁ sine wave
applied to the common-mode voltage of the ꢁIN+ and ꢁIN−
frequency, fS, as
The AD7324 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, whereas the third-order
CMRR (dB) = 1ꢀ log (Pf/PfS)
where Pf is the power at frequency f in the ADC output, and PfS
is the power at frequency fS in the ADC output (see Figure 17).
Rev. 0 | Page 15 of 36
AD7324
THEORY OF OPERATION
The analog inputs can be configured as four single-ended
inputs, two true differential input pairs, two pseudo differential
inputs, or three pseudo differential inputs. Selection can be
made by programming the mode bits, Mode ꢀ and Mode 1, in
the control register.
CIRCUIT INFORMATION
The AD7324 is a fast, 4-channel, 12-bit plus sign, bipolar input,
serial A/D converter. The AD7324 can accept bipolar input ranges
that include ±1ꢀ ꢁ, ±± ꢁ, and ±2.± ꢁ; it can also accept a ꢀ ꢁ to
+1ꢀ ꢁ unipolar input range. A different analog input range can
be programmed on each analog input channel via the on-chip
registers. The AD7324 has a high speed serial interface that can
operate at throughput rates up to 1 MSPS.
The serial clock input accesses data from the part and provides
the clock source for the successive approximation ADC. The
AD7324 has an on-chip 2.± ꢁ reference. However, the AD7324
can also work with an external reference. On power-up, the
external reference operation is the default option. If the internal
reference is the preferred option, the user must write to the
reference bit in the control register to select the internal
reference operation.
The AD7324 requires ꢁDD and ꢁSS dualsupplies for the high voltage
analog input structures. These supplies must be equal to or greater
than the analog input range. See Table 6 for the requirements of
these supplies for each analog input range. The AD7324 requires
a low voltage 2.7 ꢁ to ±.2± ꢁ ꢁCC supply to power the ADC core.
Table 6. Reference and Supply Requirements
for Each Analog Input Range
The AD7324 also features power-down options to allow power
saving between conversions. The power-down modes are
selected by programming the on-chip control register as
described in the Modes of Operation section.
Selected Analog
Input Range (V)
Reference
Voltage (V)
Full-Scale
Minimum
VDD/VSS (V)
Input Range (V)
AVCC (V)
3/5
10
2.5
3.0
2.5
3.0
2.5
3.0
2.5
3.0
10
10
12
3/5
12
CONVERTER OPERATION
5
5
3/5
5
The AD7324 is a successive approximation analog-to-digital
converter built around two capacitive DACs. Figure 23 and
Figure 24 show simplified schematics of the ADC in single-
ended mode during the acquisition and conversion phases,
respectively. Figure 2± and Figure 26 show simplified
6
3/5
6
2.5
2.5
3/5
5
3
3/5
5
0 to +10
0 to +10
0 to +12
3/5
+10/AGND
+12/AGND
3/5
schematics of the ADC in differential mode during acquisition
and conversion phases, respectively. The ADC is composed of
control logic, a SAR, and capacitive DACs. In Figure 23 (the
acquisition phase), SW2 is closed and SW1 is in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor array acquires the signal on the input.
To meet the specified performance specifications when the
AD7324 is configured with the minimum ꢁDD and ꢁSS supplies
for a chosen analog input range, the throughput rate should be
decreased from the maximum throughput range (see the
Typical Performance Characteristics section). Figure 18 and
Figure 19 show the change in INL and DNL as the ꢁDD and ꢁSS
voltages are varied. When operating at the maximum throughput
rate, as the ꢁDD and ꢁSS supply voltages are reduced, the INL
and DNL error increases. However, as the throughput rate is
reduced with the minimum ꢁDD and ꢁSS supplies, the INL and
DNL error is reduced.
CAPACITIVE
DAC
COMPARATOR
C
S
B
A
V
0
IN
CONTROL
LOGIC
SW1
SW2
AGND
Figure 31 shows the change in THD as the ꢁDD and ꢁSS supplies
are reduced. At the maximum throughput rate, the THD degrades
significantly as ꢁDD and ꢁSS are reduced. It is therefore necessary
to reduce the throughput rate when using minimum ꢁDD and
ꢁSS supplies so that there is less degradation of THD and the
specified performance can be maintained. The degradation is
due to an increase in the on resistance of the input multiplexer
when the ꢁDD and ꢁSS supplies are reduced.
Figure 23. ADC Acquisition Phase (Single-Ended)
When the ADC starts a conversion (Figure 24), SW2 opens and
SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the capacitive DAC to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
Rev. 0 | Page 16 of 36
AD7324
CAPACITIVE
DAC
The ideal transfer characteristic for the AD7324 when twos
complement coding is selected is shown in Figure 27. The ideal
transfer characteristic for the AD7324 when straight binary
coding is selected is shown in Figure 28.
COMPARATOR
C
S
B
A
V
0
IN
CONTROL
LOGIC
SW1
SW2
AGND
011...111
011...110
Figure 24. ADC Conversion Phase (Single-Ended)
Figure 2± shows the differential configuration during the
acquisition phase. For the conversion phase, SW3 opens and
SW1 and SW2 move to Position B (Figure 26). The output
impedances of the source driving the ꢁIN+ and ꢁIN− pins must
be matched; otherwise, the two inputs will have different
settling times, resulting in errors.
000...001
000...000
111...111
100...010
100...001
100...000
AGND – 1LSB
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB UNIPOLAR RANGE
ANALOG INPUT
CAPACITIVE
DAC
Figure 27. Twos Complement Transfer Characteristic (Bipolar Ranges)
COMPARATOR
C
S
B
V
V
+
111...111
111...110
IN
A
A
SW1
SW2
CONTROL
LOGIC
SW3
–
IN
B
C
S
111...000
011...111
V
REF
CAPACITIVE
DAC
Figure 25. ADC Differential Configuration During Acquisition Phase
000...010
000...001
000...000
CAPACITIVE
DAC
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB UNIPOLAR RANGE
ANALOG INPUT
COMPARATOR
C
S
B
Figure 28. Straight Binary Transfer Characteristic (Bipolar Ranges)
V
V
+
IN
A
A
SW1
SW2
CONTROL
LOGIC
SW3
ANALOG INPUT STRUCTURE
–
IN
B
C
S
The analog inputs of the AD7324 can be configured as single-
ended, true differential, or pseudo differential via the control
register mode bits (see Table 1ꢀ). The AD7324 can accept true
bipolar input signals. On power-up, the analog inputs operate as
four single-ended analog input channels. If true differential or
pseudo differential is required, a write to the control register is
necessary after power-up to change this configuration.
V
REF
CAPACITIVE
DAC
Figure 26. ADC Differential Configuration During Conversion Phase
Output Coding
The AD7324 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When
operating in sequence mode, the output coding for each
channel in the sequence is the value written to the coding bit
during the last write to the control register.
Figure 29 shows the equivalent analog input circuit of the
AD7324 in single-ended mode. Figure 3ꢀ shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
V
DD
Transfer Functions
D
C2
R1
V
0
The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is
dependent on the analog input range selected.
IN
C1
D
V
SS
Table 7. LSB Sizes for Each Analog Input Range
Figure 29. Equivalent Analog Input Circuit (Single-Ended)
Input Range
10 V
5 V
2.5 V
Full-Scale Range/8192 Codes
LSB Size
2.441 mV
1.22 mV
0.61 mV
1.22 mV
20 V
10 V
5 V
0 V to +10 V
10 V
Rev. 0 | Page 17 of 36
AD7324
V
DD
The AD7324 enters track mode on the 14th SCLK rising edge.
When running the AD7324 at a throughput rate of 1 MSPS with
a 2ꢀ MHz SCLK signal, the ADC has approximately
D
C2
R1
V
+
IN
C1
D
1.± SCLK + t8 + tQUIET
V
SS
to acquire the analog input signal. The ADC goes back into
V
DD
CS
hold mode on the
falling edge.
D
C2
R1
As the ꢁDD/ꢁSS supply voltage is reduced, the on resistance of
the input multiplexer increases. Therefore, based on the
equation for tACQ, it is necessary to increase the amount of
acquisition time provided to the AD7324 and, hence, decrease
the overall throughput rate. Figure 31 shows that if the
throughput rate is reduced when operating with minimum ꢁDD
and ꢁSS supplies, the specified THD performance is maintained.
V
–
IN
C1
D
V
SS
Figure 30. Equivalent Analog Input Circuit (Differential)
Care should be taken to ensure that the analog input does not
exceed the ꢁDD and ꢁSS supply rails by more than 3ꢀꢀ mꢁ.
Exceeding this value causes the diodes to become forward
biased and to start conducting into either the ꢁDD supply rail or
SS supply rail. These diodes can conduct up to 1ꢀ mA without
causing irreversible damage to the part.
–50
V
= V
= 5V
CC
DRIVE
INTERNAL REFERENCE
–55
–60
–65
–70
–75
–80
–85
–90
–95
T
F
= 25°C
= 10kHz
A
ꢁ
IN
±5V RANGE
SE MODE
In Figure 29 and Figure 3ꢀ, Capacitor C1 is typically 4 pF and
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
1MSPS
750kSPS
500kSPS
17
Track-and-Hold Section
5
7
9
11
13
15
19
The track-and-hold on the analog input of the AD7324 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the track-
and-hold is greater than the Nyquist rate of the ADC. The
AD7324 can handle frequencies up to 22 MHz.
±V /V SUPPLIES (V)
DD SS
Figure 31. THD vs.
V
DD/VSS Supply Voltage at 500 kSPS, 750 kSPS,
and 1 MSPS
Unlike other bipolar ADCs, the AD7324 does not have a
resistive analog input structure. On the AD7324, the bipolar
analog signal is sampled directly onto the sampling capacitor.
This gives the AD7324 high analog input impedance. An
approximation for the analog input impedance can be
calculated from the following formula:
The track-and-hold enters its tracking mode on the 14th SCLK
CS
rising edge after the
falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With ꢀ source impedance, 3ꢀ± ns is
sufficient to acquire the signal to the 13-bit level. The
acquisition time required is calculated using the following
formula:
Z = 1/(fS × CS)
where fS is the sampling frequency, and CS is the sampling
capacitor value.
t
ACQ = 1ꢀ × ((RSOURCE + R) C)
where C is the sampling capacitance and R is the resistance seen
by the track-and-hold amplifier looking back on the input. For
the AD7324, the value of R includes the on resistance of the
input multiplexer and is typically 3ꢀꢀ Ω. RSOURCE should include
any extra source impedance on the analog input.
CS depends on the analog input range chosen (see the
Specifications section). When operating at 1 MSPS, the analog
input impedance is typically 7± kꢂ for the ±1ꢀꢁ range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases the
current required to drive the analog input therefore decreases.
Rev. 0 | Page 18 of 36
AD7324
V+
5V
TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7324.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7324 can be configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7324 can operate
with either an internal or external reference. In Figure 32, the
AD7324 is configured to operate with the internal 2.± ꢁ reference.
A 68ꢀ nF decoupling capacitor is required when operating with
the internal reference.
AGND
V
+
IN
V
V
DD
CC
AD73241
V
SS
V–
ADDITIONAL PINS OMITTED FOR CLARITY.
1
Figure 33. Single-Ended Mode Typical Connection Diagram
True Differential Mode
The ꢁCC pin can be connected to either a 3 ꢁ supply voltage or a
± ꢁ supply voltage. The ꢁDD and ꢁSS are the dual supplies for the
high voltage analog input structures. The voltage on these pins
must be equal to or greater than the highest analog input range
selected on the analog input channels (see Table 6). The ꢁDRIꢁE
pin is connected to the supply voltage of the microprocessor.
The voltage applied to the ꢁDRIꢁE input controls the voltage of
the serial interface. ꢁDRIꢁE can be set to 3 ꢁ or ± ꢁ.
The AD7324 can have a total of two true differential analog
input pairs. Differential signals have some benefits over single-
ended signals, including better noise immunity based on the
device’s common-mode rejection and improvements in
distortion performance. Figure 34 defines the configuration of
the true differential analog inputs of the AD7324.
V
+
IN
+15V
V
+2.7V TO +5.25V
CC
+
+
AD73241
0.1µF
10µF
10µF
0.1µF
V
–
IN
1
V
V
CC
DD
+3V SUPPLY
V
DRIVE
+
10µF
0.1µF
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD7324
Figure 34. True Differential Inputs
CS
V
V
V
V
0
DOUT
SCLK
DIN
IN
IN
IN
IN
µC/µP
ANALOG INPUTS
±10V, ±5V, ±2.5V
0V TO +10V
The amplitude of the differential signal is the difference
between the signals applied to the ꢁIN+ and ꢁIN− pins in
each differential pair (ꢁIN+ − ꢁIN−). ꢁIN+ and ꢁIN− should
be simultaneously driven by two signals of equal amplitude,
dependent on the input range selected, that are 18ꢀ° out of
phase. Assuming the ±4 × ꢁREF mode, the amplitude of the
differential signal is −2ꢀ ꢁ to +2ꢀ ꢁ p-p (2 × 4 × ꢁREF),
regardless of the common mode.
1
2
3
DGND
SERIAL
INTERFACE
REFIN/OUT
1
680nF
AGND
V
SS
–15V
1
0.1µF
10µF
MINIMUM V AND V SUPPLY VOLTAGES
DD SS
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
+
The common mode is the average of the two signals
Figure 32. Typical Connection Diagram
(VIN+ + VIN−)/2
ANALOG INPUT
and is therefore the voltage on which the two input signals
are centered.
Single-Ended Inputs
The AD7324 has a total of four analog inputs when operating in
single-ended mode. Each analog input can be independently
programmed to one of the four analog input ranges. In applications
where the signal source is high impedance, it is recommended
to buffer the signal before applying it to the ADC analog inputs.
Figure 33 shows the configuration of the AD7324 in single-
ended mode.
This voltage is set up externally, and its range varies with
reference voltage. As the reference voltage increases, the
common-mode range decreases. When driving the differential
inputs with an amplifier, the actual common mode range is
determined by the amplifier’s output swing. If the differential
inputs are not driven from an amplifier, the common-mode
range is determined by the supply voltage on the ꢁDD supply pin
and the ꢁSS supply pin.
When a conversion takes place, the common mode is rejected,
resulting in a noise-free signal of amplitude −2 × (4 × ꢁREF) to
+2 × (4 × ꢁREF) corresponding to Digital Codes −4ꢀ96 to +4ꢀ9±.
Rev. 0 | Page 19 of 36
AD7324
5
8
6
±5V RANGE
±5V RANGE
4
±2.5V
RANGE
±10V
RANGE
±5V RANGE
3
±2.5V
RANGE
4
2
±10V
RANGE
1
2
0
0
±10V
RANGE
–1
–2
–3
–4
±2.5V
RANGE
–2
–4
–6
–8
±10V
RANGE
±5V RANGE
V
V
= 3V
CC
±2.5V
RANGE
V
V
= 5V
–5
–6
CC
= 3V
REF
= 2.5V
REF
±16.5V V /V
±12V V /V
±16.5V V /V
DD SS
±12V V /V
DD SS
DD SS
DD SS
Figure 35. Common-Mode Range for VCC = 3 V and REFIN/OUT = 3 V
Figure 38. Common-Mode Range for VCC = 5 V and REFIN/OUT = 2.5 V
8
Pseudo Differential Inputs
±5V RANGE
±5V RANGE
The AD7324 can have two pseudo differential pairs or three
pseudo differential inputs referenced to a common ꢁIN− pin.
The ꢁIN+ inputs are coupled to the signal source and must have
an amplitude within the selected range for that channel as
programmed in the range register. A dc input is applied to the
ꢁIN− pin. The voltage applied to this input provides an offset for
the ꢁIN+ input from ground or a pseudo ground. Pseudo
differential inputs separate the analog input signal ground from
the ADC ground, allowing cancellation of dc common-mode
voltages. Figure 39 shows the AD7328 configured in pseudo
differential mode.
6
±2.5V
RANGE
±2.5V
RANGE
4
2
±10V
RANGE
±10V
RANGE
0
–2
–4
V
V
= 5V
CC
= 3V
REF
±16.5V V /V
DD SS
±12V V /V
DD SS
When a conversion takes place, the pseudo ground corresponds
to Code −4ꢀ96 and the maximum amplitude corresponds to
Code +4ꢀ9±.
Figure 36. Common-Mode Range for VCC = 5 V and REFIN/OUT = 3 V
6
V+
5V
4
±5V RANGE
±5V RANGE
2
0
V
V
+
IN
V
V
CC
DD
AD73241
V
–2
–4
–6
–8
–
SS
IN
±2.5V
±10V
RANGE RANGE
±10V
±2.5V
RANGE
RANGE
V–
V
V
= 3V
CC
= 2.5V
1
ADDITIONAL PINS OMITTED FOR CLARITY.
REF
Figure 39. Pseudo Differential Inputs
±16.5V V /V
DD SS
±12V V /V
DD SS
Figure 37. Common-Mode Range for VCC = 3 V and REFIN/OUT = 2.5 V
Figure 4ꢀ and Figure 41 show the typical voltage range on the
ꢁIN− pin for the different analog input ranges when configured
in the pseudo differential mode.
For example, when the AD7324 is configured to operate in
pseudo differential mode and the ±± ꢁ range is selected with
±16.± ꢁ ꢁDD/ꢁSS supplies and ± ꢁ ꢁCC, the voltage on the ꢁIN−
pin can vary from −6.± ꢁ to +6.± ꢁ.
Rev. 0 | Page 20 of 36
AD7324
8
6
The driver amplifier must be able to settle for a full-scale step to
a 13-bit level, ꢀ.ꢀ122%, in less than the specified acquisition
time of the AD7324. An op amp such as the AD8ꢀ21 meets this
requirement when operating in single-ended mode. The
AD8ꢀ21 needs an external compensating NPO type of
capacitor. The AD8ꢀ22 can also be used in high frequency
applications where a dual version is required. For lower
frequency applications, op amps such as the AD797, AD84±,
and AD861ꢀ can be used with the AD7324 in single-ended
mode configuration.
±5V RANGE
±2.5V
RANGE
±5V RANGE
±2.5V
RANGE
±10V
RANGE
4
2
0
–2
–4
–6
–8
±10V
RANGE
0V TO +10V
RANGE
0V TO +10V
RANGE
V
V
= 5V
REF
CC
Differential operation requires that ꢁIN+ and ꢁIN− be
simultaneously driven with two signals of equal amplitude that
are 18ꢀ° out of phase. The common mode must be set up
externally to the AD7324. The common-mode range is
determined by the REFIN/OUT voltage, the ꢁCC supply voltage,
and the particular amplifier used to drive the analog inputs.
Differential mode with either an ac input or a dc input provides
the best THD performance over a wide frequency range. Because
not all applications have a signal preconditioned for differential
operation, there is often a need to perform the single-ended-to-
differential conversion.
= 2.5V
±16.5V V /V
DD SS
±12V V /V
DD SS
Figure 40. Pseudo Input Range with VCC= 5 V
4
2
±5V RANGE
±5V RANGE
±2.5V
RANGE
0
–2
–4
–6
–8
This single-ended-to-differential conversion can be performed
using an op amp pair. Typical connection diagrams for an op
amp pair are shown in Figure 42 and Figure 43. In Figure 42,
the common-mode signal is applied to the noninverting input
of the second amplifier.
±10V
RANGE
±2.5V
RANGE
±10V
RANGE
0V TO +10V
RANGE
0V TO +10V
RANGE
V
REF
= 3V
= 2.5V
CC
V
1.5kΩ
±16.5V V /V
DD SS
±12V V /V
DD SS
3kΩ
V
IN
Figure 41. Pseudo Input Range with VCC = 3 V
V+
DRIVER AMPLIFIER CHOICE
1.5kΩ
1.5kΩ
1.5kΩ
10kΩ
In applications where the harmonic distortion and signal-to-
noise ratio are critical specifications, the analog input of the
AD7324 should be driven from a low impedance source. Large
source impedances significantly affect the ac performance of the
ADC and can necessitate the use of an input buffer amplifier.
V–
V
COM
20kΩ
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated in the application. The THD increases as the source
impedance increases and performance degrades. Figure 21 and
Figure 22 show graphs of the THD vs. the analog input
frequency for various source impedances. Depending on the
input range and analog input configuration selected, the
AD7324 can handle source impedances of up to 4.7 kΩ before
the THD starts to degrade.
Figure 42. Single-Ended-to-Differential Configuration with the AD845
442Ω
442Ω
AD8021
V
IN
V+
442Ω
442Ω
442Ω
442Ω
Due to the programmable nature of the analog inputs on the
AD7324, the choice of op amp used to drive the inputs is a
function of the particular application and depends on the input
configuration and the analog input voltage ranges selected.
V–
AD8021
100Ω
Figure 43. Single-Ended-to-Differential Configuration with the AD8021
Rev. 0 | Page 21 of 36
AD7324
REGISTERS
The AD7324 has three programmable registers, the control register, the sequence register, and the range register. These registers are write-
only registers.
ADDRESSING REGISTERS
A serial transfer on the AD7324 consists of 16 SCLK cycles. The three MSBs on the DIN line during the 16 SCLK transfer are decoded to
determine which register is addressed. The three MSBs consist of the write bit, Register Select 1 bit, and Register Select 2 bit. The register
select bits are used to determine which of the three on-board registers is selected. The write bit determines if the data on the DIN line
following the register select bits loads into the addressed register. If the write bit is 1, the bits load into the register addressed by the
register select bits. If the write bit is ꢀ, the data on the DIN line does not load into any register.
Table 8. Decoding Register Select Bits and Write Bit
Write Register Select 1
Register Select 2
Comment
0
1
0
0
0
0
Data on the DIN line during this serial transfer is ignored.
This combination selects the control register. The subsequent 12 bits are loaded into
the control register.
1
1
0
1
1
1
This combination selects the range register. The subsequent 8 bits are loaded into the
range register.
This combination selects the sequence register. The subsequent 4 bits are loaded into
the sequence register.
Rev. 0 | Page 22 of 36
AD7324
CONTROL REGISTER
The control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. The
control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7324 configuration for the next
conversion. If the sequence register is being used, data should be loaded into the control register after the range register and the sequence
register have been initialized. The bit functions of the control register are shown in Table 9 (the power-up status of all bits is ꢀ).
MSB
15
LSB
14
13
12
11
10
9
8
7
6
5
1
3
2
1
0
0
Write
Register Select 1
Register Select 2
ZERO
ADD1
ADD0
Mode 1
Mode 0
PM1
PM0
Coding
Ref
Seq1
Seq2
ZERO
Table 9. Control Register Details
Bit
Mnemonic
Description
12, 1
11, 10
ZERO
ADD1, ADD0
A 0 must be written to this bit to ensure correct operation of the device
These two channel address bits are used to select the analog input channel for the next conversion if the
sequencer is not being used. If the sequencer is being used, the two channel address bits are used to
select the final channel in a consecutive sequence.
9, 8
Mode 1, Mode 0
These two mode bits are used to select the configuration of the four analog input pins, VIN0 to VIN3. These
pins are used in conjunction with the channel address bits. On the AD7324, the analog inputs can be
configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or
three pseudo differential inputs (see Table 10).
7, 6
5
PM1, PM0
Coding
The power management bits are used to select different power mode options on the AD7324 (see Table 11).
This bit is used to select the type of output coding the AD7324 uses for the next conversion result. If
coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary.
When operating in sequence mode, the output coding for each channel is the value written to the coding
bit during the last write to the control register.
4
Ref
The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is
enabled and used for the next conversion, and the internal reference is disabled. If Ref = 1, the internal
reference is used for the next conversion. When operating in sequence mode, the reference used for each
channel is the value written to the Ref bit during the last write to the control register.
3, 2
Seq1, Seq2
The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12).
The four analog input channels can be configured as three pseudo differential analog inputs, two pseudo differential inputs, two true
differential input pairs, or four single-ended analog inputs.
Table 10. Analog Input Configuration Selection
Mode 1 = 1, Mode 0 = 1
Mode 1 = 1, Mode 0 = 0 Mode 1 = 0, Mode 0 =1
Mode 1 = 0, Mode 0 = 0
Channel Address Bits 3 Pseudo Differential I/Ps 2 Fully Differential I/Ps
2 Pseudo Differential I/Ps 4 Single-Ended I/Ps
ADD1
ADD0
VIN+
VIN0
VIN1
VIN2
VIN−
VIN3
VIN3
VIN3
VIN+
VIN0
VIN0
VIN2
VIN2
VIN−
VIN1
VIN1
VIN3
VIN3
VIN+
VIN0
VIN0
VIN2
VIN2
VIN−
VIN1
VIN1
VIN3
VIN3
VIN+
VIN0
VIN1
VIN2
VIN3
VIN−
0
0
1
1
0
1
0
1
AGND
AGND
AGND
AGND
Not a valid selection
Rev. 0 | Page 23 of 36
AD7324
Table 11. Power Mode Selection
PM1 PM0 Description
1
1
0
0
1
0
1
0
Full Shutdown Mode. In this mode, all internal circuitry on the AD7324 is powered down. Information in the control register
is retained when the AD7324 is in full shutdown mode.
Autoshutdown Mode. The AD7324 enters autoshutdown on the 15th SCLK rising edge when the control register is updated.
All internal circuitry is powered down in autoshutdown.
Autostandby Mode. In this mode, all internal circuitry is powered down excluding the internal reference. The AD7324 enters
autostandby mode on the 15th SCLK rising edge after the control register is updated.
Normal Mode. All internal circuitry is powered up at all times.
Table 12. Sequencer Selection
Seq1 Seq2 Sequence Type
0
0
The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
0
1
Uses sequence of channels that were previously programmed in the sequence register for conversion. The AD7324 starts
converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted, the
AD7324 keeps converting the sequence. The range for each channel defaults to the range previously written into the
range register.
1
1
0
1
Used in conjunction with the channel address bits in the control register. This allows continuous conversions on a
consecutive sequence of channels, from Channel 0 up to and including a final channel selected by the channel address bits
in the control register. The range for each channel defaults to the range previously written into the range register.
The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
Rev. 0 | Page 24 of 36
AD7324
SEQUENCE REGISTER
The sequence register on the AD7324 is a 4-bit, write-only register. Each of the four analog input channels has one corresponding bit in
the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.
MSB
16
LSB
15
14
13
12
11
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Write
Register Select 1
Register Select 2
VIN0
VIN1
VIN2
VIN3
RANGE REGISTER
The range register is used to select one analog input range per analog input channel. It is an 8-bit, write-only register with two dedicated
range bits for each of the analog input channels from Channel ꢀ to Channel 3. There are four analog input ranges, ±1ꢀ ꢁ, ±± ꢁ, ±2.± ꢁ, and
ꢀ ꢁ to +1ꢀ ꢁ. A write to the range register is selected by setting the write bit to 1 and the register select bits to ꢀ and 1. After the initial write to
the range register occurs, each time an analog input is selected, the AD7324 automatically configures the analog input to the appropriate
range, as indicated by the range register. The ±1ꢀ ꢁ input range is selected by default on each analog input channel (see Table 13).
MSB
LSB
1
16
15
14
13
12
11
10
9
8
7
6
5
0
4
0
3
0
2
0
Write Register Select 1
Register Select 2
VIN0A VIN0B VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B
0
Table 13. Range Selection
VINxA
VINxB
Description
0
0
1
1
0
1
0
1
This combination selects the 10 V input range on VINx.
This combination selects the 5 V input range on VINx.
This combination selects the 2.5 V input range on VINx.
This combination selects the 0 V to +10 V input range on VINx.
Rev. 0 | Page 25 of 36
AD7324
SEQUENCER OPERATION
POWER ON.
CS
DIN: WRITE TO RANGE REGISTER TO SELECT THE RANGE
FOR EACH ANALOG INPUT CHANNEL.
DOUT: CONVERSION RESULT FROM CHANNEL 0, ± 10V
RANGE, SINGLE-ENDED MODE.
CS
DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE
ANALOG INPUT CHANNELS TO BE INCLUDED IN
THE SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER.
CS
DIN: WRITE TO CONTROL REGISTER TO START THE
SEQUENCE, Seq1 = 0, Seq2 = 1.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER.
CS
DIN: TIE DIN LOW/WRITE BIT = 0TO CONTINUE TO CONVERT
THROUGH THE SEQUENCE OF CHANNELS.
CS
DOUT: CONVERSION RESULT FROM FIRST CHANNEL IN
THE SEQUENCE.
DIN TIED LOW/WRITE BIT = 0.
DIN: WRITE TO CONTROL
REGISTER TO STOP THE
SEQUENCE, Seq1 = 0, Seq2 = 0.
CONTINUOUSLY CONVERT
STOPPING
ON THE SELECTED SEQUENCE
A SEQUENCE.
OF CHANNELS.
DOUT: CONVERSION RESULT
FROM CHANNEL IN SEQUENCE.
SELECTING A NEW SEQUENCE.
CS
DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE
NEW SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL X IN
THE FIRST SEQUENCE.
Figure 44. Programmable Sequence Flowchart
The AD7324 can be configured to automatically cycle through
a number of selected channels using the on-chip sequence
register with the Seq1 bit and the Seq2 bit in the control register.
Figure 44 shows how to program the AD7324 register to
operate in sequence mode.
This initial serial transfer is only necessary if input ranges other
than the default ranges are required. After the analog input ranges
are configured, a write to the sequence register is necessary to
select the channels to be included in the sequence. Once the
channels for the sequence have been selected, the sequence can
be initiated by writing to the control register and setting Seq1 to
ꢀ and Seq2 to 1. The AD7324 continues to convert the selected
sequence without interruption provided that the sequence register
remains unchanged, and Seq1 = ꢀ and Seq2 = 1 in the control
register.
After power-up, all of the three on-chip registers contain default
values. Each analog input has a default input range of ±1ꢀ ꢁ. If
different analog input ranges are required, a write to the range
register is required. This is shown in the first serial transfer of
Figure 44.
Rev. 0 | Page 26 of 36
AD7324
If a change to the range register is required during a sequence, it
is necessary to first stop the sequence by writing to the control
register and setting Seq1 to ꢀ and Seq2 to ꢀ. Next, the write to
the range register should be completed to change the required
range. The previously selected sequence should then be initiated
again by writing to the control register and setting Seq1 to ꢀ and
Seq2 to 1. The ADC converts on the first channel in the
sequence.
Once the control register is configured to operate the AD7324
in this mode, the DIN line can be held low, or the write bit can
be set to ꢀ. To return to traditional multichannel operation, a
write to the control register to set Seq1 to ꢀ and Seq2 to ꢀ is
necessary.
When the Seq1 and Seq2 are both set to ꢀ, or when both are set
to 1, the AD7324 is configured to operate in traditional multi-
channel mode, where a write to Channel Address Bit ADD1 to
Bit ADDꢀ in the control register selects the next channel for
conversion.
The AD7324 can be configured to convert a sequence of
consecutive channels (see Figure 4±). This sequence begins by
converting on Channel ꢀ and ends with a final channel as
selected by Bit ADD1 to Bit ADDꢀ in the control register. In
this configuration, there is no need for a write to the sequence
register. To operate the AD7324 in this mode, set Seq1 to 1 and
Seq2 to ꢀ in the control register, and then select the final channel
in the sequence by programming Bit ADD1 to Bit ADDꢀ in the
control register.
POWER ON.
CS
DIN: WRITE TO RANGE REGISTER TO SELECT THE RANGE
FOR ANALOG INPUT CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 0, ± 10V
RANGE, SINGLE-ENDED MODE.
CS
DIN: WRITE TO CONTROL REGISTER TO SELECT THE FINAL
CHANNEL IN THE CONSECUTIVE SEQUENCE, SET Seq1 = 1
AND Seq2 = 0. SELECT OUTPUT CODING FOR SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
RANGE SELECTED IN RANGE REGISTER,
SINGLE-ENDED MODE.
CS
DIN: WRITE BIT = 0 OR DIN LINE HELD LOWTO CONTINUE TO
CONVERT THROUGH THE SEQUENCE OF
CONSECUTIVE CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
RANGE SELECTED IN RANGE REGISTER.
CS
DIN: WRITE BIT = 0 OR DIN LINE HELD LOWTO CONTINUE
THROUGH SEQUENCE OF CONSECUTIVE CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 1,
RANGE SELECTED IN RANGE REGISTER.
DIN TIED LOW/WRITE BIT = 0.
CONTINUOUSLY CONVERT
ON CONSECUTIVE SEQUENCE
OF CHANNELS.
STOPPING
A SEQUENCE.
CS
DIN: WRITE TO CONTROL
REGISTER TO STOP THE
SEQUENCE, Seq1 = 0, Seq2 = 0.
DOUT: CONVERSION RESULT
FROM CHANNEL IN SEQUENCE.
Figure 45. Flowchart for Consecutive Sequence of Channels
Rev. 0 | Page 27 of 36
AD7324
to set the Ref bit to 1. During the control register write, the
conversion result from the first initial conversion is invalid. The
reference buffer requires ±ꢀꢀ ꢃs to power up and charge the
68ꢀ nF decoupling capacitor during the power-up time.
REFERENCE
The AD7324 can operate with either the internal 2.± ꢁ on-chip
reference or an externally applied reference. The internal reference
is selected by setting the Ref bit in the control register to 1. On
power-up, the Ref bit is ꢀ, selecting the external reference for the
AD7324 conversion. Suitable reference sources for the AD7324
include AD78ꢀ, AD1±82, ADR431, REF193, and ADR391.
The AD7324 is specified for a 2.± ꢁ to 3 ꢁ reference range.
When a 3 ꢁ reference is selected, the ranges are ±12 ꢁ, ±6 ꢁ,
±3 ꢁ, and ꢀ ꢁ to +12 ꢁ. For these ranges, the ꢁDD and ꢁSS supply
must be equal to or greater than the maximum analog input
range selected, see Table 6.
The internal reference circuitry consists of a 2.± ꢁ band gap
reference and a reference buffer. When operating the AD7324
in internal reference mode, the 2.± ꢁ internal reference is available
at the REFIN/OUT pin, which should be decoupled to AGND
using a 68ꢀ nF capacitor. It is recommended that the internal
reference be buffered before applying it elsewhere in the system.
The internal reference is capable of sourcing up to 9ꢀ μA.
VDRIVE
The AD7324 has a ꢁDRIꢁE feature to control the voltage at which
the serial interface operates. ꢁDRIꢁE allows the ADC to easily
interface to both 3 ꢁ and ± ꢁ processors. For example, if the
AD7324 is operated with a ꢁCC of ± ꢁ, the ꢁDRIꢁE pin can be
powered from a 3 ꢁ supply. This allows the AD7324 to accept
large bipolar input signals with low voltage digital processing.
On power-up, if the internal reference operation is required for
the ADC conversion, a write to the control register is necessary
Rev. 0 | Page 28 of 36
AD7324
MODES OF OPERATION
The AD7324 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7324 is controlled by the power manage-
ment bits, Bit PM1 and Bit PMꢀ, in the control register as shown
in Table 11. The default mode is normal mode, where all internal
circuitry is fully powered up.
The AD7324 remains fully powered up at the end of the
conversion if both PM1 and PMꢀ contain ꢀ in the control
register.
To complete the conversion and access the conversion result
16 serial clock cycles are required. At the end of the conversion,
CS
can idle either high or low until the next conversion.
Once the data transfer is complete, another conversion can be
initiated after the quiet time, tQUIET, has elapsed.
NORMAL MODE
(PM1 = PM0 = 0)
FULL SHUTDOWN MODE
(PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate
performance, with the AD7324 being fully powered up at all
times. Figure 46 shows the general operation of the AD7324
in normal mode.
In this mode, all internal circuitry on the AD7324 is powered
down. The part retains information in the registers during full
shutdown. The AD7324 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PMꢀ, in the
control register are changed.
CS
The conversion is initiated on the falling edge of , and the
track-and-hold enters hold mode as described in the Serial
Interface section. Data on the DIN line during the 16 SCLK
transfer is loaded into one of the on-chip registers if the write
bit is set. The register is selected by programming the register
select bits (see Figure 46).
A write to the control register with PM1 = 1 and PMꢀ = 1 places
the part into full shutdown mode. The AD7324 enters full shut-
down mode on the 1±th SCLK rising edge rising edge once the
control register is updated.
CS
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PMꢀ, set to ꢀ (normal mode), the part begins to power up
on the 1±th SCLK rising edge once the control register is
updated. Figure 47 shows how the AD7324 is configured to exit
full shutdown mode. To ensure the AD7324 is fully powered up,
1
16
SCLK
LEADING ZERO, 2 CHANNEL I.D. BITS, SIGN BIT +
CONVERSION RESULT
DOUT
DIN
DATA INTO CONTROL/SEQUENCE/RANGE REGISTER
t
POWER-UP for full shutdown mode should elapse before the next
CS
falling edge
Figure 46. Normal Mode
THE PART IS FULLY POWERED UP
ONCE tPOWER-UP HAS ELAPSED
PART IS IN FULL
SHUTDOWN
PART BEGINS TO POWER UP ON THE 15TH
SCLK RISING EDGE AS PM1 = PM0 = 0
tPOWER-UP
CS
1
16
1
16
SCLK
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
SDATA
DIN
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
PM1 = 0, PM0 = 0
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
IN CONTROL REGISTER
Figure 47. Exiting Full Shutdown Mode
Rev. 0 | Page 29 of 36
AD7324
As is the case with the autoshutdown mode, the AD7324 enters
standby on the 1±th SCLK rising edge once the control register is
updated (see Figure 48). The part retains information in the
AUTOSHUTDOWN MODE
(PM1 = 1, PM0 = 0)
Once the autoshutdown mode is selected, the AD7324 auto-
matically enters shutdown on the 1±th SCLK rising edge. In
autoshutdown mode, all internal circuitry is powered down. The
AD7324 retains information in the registers during autoshutdown.
The track-and-hold is in hold mode during autoshutdown. On
CS
registers during standby. Once in autostandby mode, the
signal must remain low to keep the part in autostandby mode.
CS
The AD7324 remains in standby until it receives a
rising
rising edge. On
rising edge, the track-and-hold, which was in hold mode
CS
edge. The ADC begins to power up on the
CS
the
CS
the rising
edge, the track-and-hold, which was in hold during
while the part was in standby, returns to track. The power-up
time from standby is 7ꢀꢀ ns.
shutdown, returns to track as the AD7324 begins to power up.
The power-up from autoshutdown is ±ꢀꢀ ꢃs.
The user should ensure that 7ꢀꢀ ns have elapsed before bringing
When the control register is programmed to transition to
autoshutdown mode, it does so on the 1±th SCLK rising edge.
Figure 48 shows the part entering autoshutdown mode. Once in
CS
low to attempt a valid conversion. Once this valid conversion
is complete, the AD7324 again returns to standby on the 1±th SCLK
CS
rising edge. The
standby mode.
signal must remain low to keep the part in
CS
autoshutdown mode, the
part in autoshutdown mode. The AD7324 automatically begins to
CS
signal must remain low to keep the
power up on the
is required before a valid conversion, initiated by bringing the
CS
rising edge. The tPOWER-UP for autoshutdown
Figure 48 shows the part entering autoshutdown mode. The
sequence of events is the same when entering autostandby
mode. In Figure 48, the power management bits are configured
for autoshutdown. For autostandby mode, the power
management bits, PM1 and PMꢀ, should be set to ꢀ and 1,
respectively.
signal low, can take place. Once this valid conversion is
complete, the AD7324 powers down again on the 1±th SCLK
CS
rising edge. The
signal must remain low again to keep the
part in autoshutdown mode.
AUTOSTANDBY MODE
(PM1 = 0, PM0 =1)
In autostandby mode, portions of the AD7324 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to
autoshutdown, but allows the AD7324 to power up much faster.
This allows faster throughput rates to be achieved.
PART BEGINS TO POWER
UP ON CS RISING EDGE
THE PART IS FULLY POWERED UP
ONCE tPOWER-UP HAS ELAPSED
PART ENTERS SHUTDOWN MODE
ON THE 15TH RISING SCLK EDGE
AS PM1 = 1, PM0 = 0
tPOWER-UP
CS
1
15 16
1
15 16
SCLK
VALID DATA
VALID DATA
SDATA
DIN
DATA INTO CONTROL REGISTER
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
PM1 = 1, PM0 = 0
Figure 48. Entering Autoshutdown/Autostandby Mode
Rev. 0 | Page 30 of 36
AD7324
20
18
16
14
12
10
8
POWER VS. THROUGHPUT RATE
The power consumption of the AD7324 varies with throughput
rate. The static power consumed by the AD7324 is very low, and
a significant power savings can be achieved as the throughput
rate is reduced. Figure 49 and Figure ±ꢀ shows the power vs.
throughput rate for the AD7324 at a ꢁCC of 3 ꢁ and ± ꢁ,
respectively. Both plots clearly show that the average power
consumed by the AD7324 is greatly reduced as the sample
frequency is reduced. This is true whether a fixed SCLK value is
used or if it is scaled with the sampling frequency. Figure 49 and
Figure ±ꢀ show the power consumption when operating in
normal mode for a fixed 2ꢀ MHz SCLK and a variable SCLK
that scales with the sampling frequency.
VARIABLE SCLK
20MHz SCLK
6
4
V
V
= 5V
CC
/V = ±12V
DD SS
2
T
= 25°C
A
INTERNAL REFERENCE
100 200 300 400 500 600 700 800 900 1000
THROUGHPUT RATE (kHz)
0
0
12
Figure 50. Power vs. Throughput Rate with 5 V VCC
10
20MHz SCLK
8
VARIABLE SCLK
6
4
V
V
= 3V
CC
2
0
/V = ±12V
DD SS
T
= 25°C
A
INTERNAL REFERENCE
100 200 300 400 500 600 700 800 900 1000 1100
THROUGHPUT RATE (kSPS)
0
Figure 49. Power vs. Throughput Rate with 3 V VCC
Rev. 0 | Page 31 of 36
AD7324
SERIAL INTERFACE
Figure ±1 shows the timing diagram for the serial interface of
the AD7324. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7324 during a conversion.
Data is clocked into the AD7324 on the SCLK falling edge. The
3 MSBs on the DIN line are decoded to select which register is
being addressed. The control register is a 12-bit register. If the
control register is addressed by the 3 MSBs, the data on the DIN
line is loaded into the control on the 1±th SCLK rising edge. If the
sequence register or the range register is addressed, the data on
the DIN line is loaded into the addressed register on the 11th SCLK
falling edge.
CS
The
signal initiates the data transfer and the conversion
CS
process. The falling edge of
puts the track-and-hold into
hold mode and takes the bus out of three-state. Then the analog
input signal is sampled. Once the conversion is initiated,
it requires 16 SCLK cycles to complete.
Conversion data is clocked out of the AD7324 on each SCLK
falling edge. Data on the DOUT line consists of a leading ZERO
bit, two channel identifier bits, a sign bit, and a 12-bit conversion
result. The channel identifier bits are used to indicate which
channel corresponds to the conversion result. The leading ZERO
The track-and-hold goes back into track mode on the 14th SCLK
rising edge. On the 16th SCLK falling edge, the DOUT line returns
to three-state. If the rising edge of occurs before 16 SCLK cycles
have elapsed, the conversion is terminated, and the DOUT line
returns to three-state. Depending on where the signal is brought
CS
CS
bit is clocked out on the
falling edge, and the first channel
CS
identifier bit is clocked out on the first SCLK falling edge.
high, the addressed register may be updated.
t1
CS
tCONVERT
t2
t6
1
2
3
4
5
13
14
t5
15
16
SCLK
DOUT
2 IDENTIFICATION BITS
t3
t7
t8
t4
tQUIET
ADD1
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
ZERO
THREE-STATE
t10
t9
REG
SEL1
REG
SEL2
DON’T
CARE
WRITE
MSB
LSB
DIN
Figure 51. Serial Interface Timing Diagram (Control Register Write)
Rev. 0 | Page 32 of 36
AD7324
MICROPROCESSOR INTERFACING
The serial interface on the AD7324 allows the part to be directly
connected to a range of different microprocessors. This section
explains how to interface the AD7324 with some common
microcontroller and DSP serial interface protocols.
The frequency of the serial clock is set in the SCLKDIꢁ register.
When the instruction to transmit with TFS is given (AXꢀ = TXꢀ),
the state of the serial clock is checked. The DSP waits until the
SCLK has gone high, low, and high again before starting the
transmission. If the timer and SCLK are chosen, so that the
instruction to transmit occurs on or near the rising edge of SCLK,
data can be transmitted immediately or at the next clock edge.
AD7324 TO ADSP-218x
The ADSP-21xx family of DSPs interface directly to the AD7324
without requiring glue logic. The ꢁDRIꢁE pin of the AD7324 takes
the same supply voltage as that of the ADSP-21xx. This allows
the ADC to operate at a higher supply voltage than its serial
interface. The SPORTꢀ on the ADSP-21xx should be configured
as shown in Table 14.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIꢁ register is loaded with the value 3, an
SCLK of 2 MHz is obtained, and eight master clock periods elapse
for every one SCLK period. If the timer registers are loaded
with the value 8ꢀ3, 1ꢀꢀ.± SCLKs occur between interrupts and,
subsequently, between transmit instructions. This situation leads
to nonequidistant sampling because the transmit instruction
occurs on an SCLK edge. If the number of SCLKs between
interrupts is an integer of N, equidistant sampling is implemented
by the DSP.
Table 14. SPORT0 Control Register Setup
Setting
Description
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
Alternative framing
Active low frame signal
Right justify data
16-bit data word
Internal serial clock
Frame every word
AD7324 TO ADSP-BF53x
TFSR = RFSR = 1
IRFS = 0
The ADSP-BF±3x family of DSPs interface directly to the
AD7324 without requiring glue logic, as shown in Figure ±3.
The SPORTꢀ Receive Configuration 1 register should be set up
as outlined in Table 15.
ITFS = 1
The connection diagram is shown in Figure ±2. The ADSP-21xx
has TFSꢀ and RFSꢀ tied together. TFSꢀ is set as an output, and
RFSꢀ is set as an input. The DSP operates in alternative framing
mode, and the SPORTꢀ control register is set up as described in
Table 14. The frame synchronization signal generated on the
1
AD73241
ADSP-BF53x
SCLK
RSCLK0
RFS0
CS
CS
TFS is tied to
and, as with all signal processing applications,
DIN
DT0
DR0
requires equidistant sampling. However, as in this example, the
timer interrupt is used to control the sampling rate of the ADC
and under certain conditions equidistant sampling cannot be
achieved.
DOUT
V
DRIVE
1
AD73241
ADSP-21xx
V
DD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
SCLK0
Figure 53. Interfacing the AD7324 to the ADSP-BF53x
TFS0
RFS0
CS
Table 15. SPORT0 Receive Configuration 1 Register
Setting
Description
DIN
DT0
DR0
RCKFE = 1
LRFS = 1
RFSR = 1
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
Internal RFS used
Receive MSB first
Zero fill
Internal receive clock
Receive enable
DOUT
V
DRIVE
IRFS = 1
V
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
TFSR = RFSR = 1
DD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 52. Interfacing the AD7324 to the ADSP-21xx
The timer registers are loaded with a value that provides an
interrupt at the required sampling interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, hence, the
reading of data.
16-bit data-word
Rev. 0 | Page 33 of 36
AD7324
APPLICATION HINTS
To avoid radiating noise to other sections of the board,
components, such as clocks, with fast switching signals should
be shielded with digital ground and never run near the analog
inputs. Avoid crossover of digital and analog signals. To reduce
the effects of feedthrough within the board, traces should be
run at right angles to each other. A microstrip technique is the
best method, but its use may not be possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes, and signals are placed on the
other side.
LAYOUT AND GROUNDING
The printed circuit board that houses the AD7324 should be
designed so that the analog and digital sections are confined to
certain areas of the board. This design facilitates the use of
ground planes that can easily be separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All AGND pins on the AD7324
should be connected to the AGND plane. Digital and analog
ground pins should be joined in only one place. If the AD7324
is in a system where multiple devices require an AGND and
DGND connection, the connection should still be made at only
one point. A star point should be established as close as possible
to the ground pins on the AD7324.
Good decoupling is also important. All analog supplies should
be decoupled with 1ꢀ ꢃF tantalum capacitors in parallel with
ꢀ.1 ꢃF capacitors to AGND. To achieve the best results from
these decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
ꢀ.1 ꢃF capacitors should have a low effective series resistance
(ESR) and low effective series inductance (ESI), such as is
typical of common ceramic and surface mount types of
capacitors. These low ESR, low ESI capacitors provide a low
impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
Good connections should be made to the power and ground
planes. This can be done with a single via or multiple vias for
each supply and ground pin.
Avoid running digital lines under the AD7324 device because
this couples noise onto the die. However, the analog ground
plane should be allowed to run under the AD7324 to avoid
noise coupling. The power supply lines to the AD7324 device
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
Rev. 0 | Page 34 of 36
AD7324
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 54. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions show in millimeters
ORDERING GUIDE
Model
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
AD7324BRUZ1
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation Board
Controller Board
RU-16
RU-16
RU-16
AD7324BRUZ-REEL1
AD7324BRUZ-REEL71
EVAL-AD7324CB2
EVAL-CONTROL BRD23
–40°C to +85°C
1 Z = Pb-free part.
2 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.
3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete
evaluation kit, the particular ADC evaluation board (for example, EVAL-AD7324CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the relevant
evaluation board technical note for more information.
Rev. 0 | Page 35 of 36
AD7324
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04864–0–12/05(0)
Rev. 0 | Page 36 of 36
相关型号：
EVAL-AD7327CB
500 kSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
ADI
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