EVAL-AD73322EB [ADI]
EvaluationBoardforLowCost,LowPower, CMOSGerneralPurposeDualAnalogFrontEnd; EvaluationBoardforLowCost ，低功耗， CMOSGerneralPurposeDualAnalogFrontEnd
| 型号： | EVAL-AD73322EB |
| 厂家： | 
ADI |
| 描述： | EvaluationBoardforLowCost,LowPower, CMOSGerneralPurposeDualAnalogFrontEnd |
| 文件： | 总12页 (文件大小：733K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EvaluationBoardforLowCost,LowPower,
CMOSGerneralPurposeDualAnalogFrontEnd
a
EVAL-AD73322EB
FEATURES
I N T R O D U C T I O N
T he AD 73322 is a dual front-end processor for general
purpose applications including speech and telephony. It
features two 16-bit A/D conversion channel and two 16-bit D/
A conversion channel. Each channel provides 70 dB signal-
to-noise ratio over a voiceband signal bandwidth.
Up to 4 CODECS (2 Devices)Can Be Configured In
Cascade.
Interfaces To The ADSP-2181 EZ-KIT LITE.
Stand Alone Capabiliy.
T he AD73322 is suitable for a variety of applications in the
speech and telephony area including low bit rate, high quality
compression, speech enhancement, recognition and synthe-
sis. T he low group delay characteristic of the part makes it
suitable for single or multichannel active control applications.
Daughter Board for Quick Demo of CODECS
Various Link Options For Setting Configuration.
On Board +5V Regulator.
On Board Clock Generator.
T he gains of the A/D and D /A conversion channels are
programmable over 38dB and 21dB ranges respectively. An
on-chip reference voltage is included to allow single supply
operation. A serial port (SPORT ) allows easy interfacing of
single or cascaded devices to industry standard DSP engines.
On Board Anti-Aliasing.
E VAL-AD 73322E Z / E VAL-AD 73322E B
T he AD73322 Evaluation board can be supplied either
with or without an ADSP2181 EZ-KIT LIT E Board.
EVAL-AD 73322EZ contains an AD73322 evaluation board
and a modified EZ-KIT LIT E board. EVAL-AD 73322EB
contains an AD73322 evaluation board and the material
needed to modify a customers existing EZ-KIT LIT E
board.
T he AD73322 is available in both 28-lead SOIC and 44-lead
LQFP packages.
Full data on the AD73322 is available in the AD73322 data
sheet available from Analog Devices and should be consulted
in conjunction with this T echnical N ote when using the
Evaluation Board.
An existing EZ-KIT LIT E board can easily be modified to
interface with the EVAL-AD73322EB board by carrying out
the following modification:
Included on the evaluation board, along with the two AD73322
Codecs are a power supply circuit, a clock generator circuit,
a cascade selector circuit and a daughter board. T hese are
explained in detail on the next page.
- Solder the 40 pin right angle header (included in the EVAL-
AD 73322EB package) onto the EZ-KIT LIT E board in
position P3, pins 11-50, with the header pins facing the edge
of the board.
F UNC T IO NAL BLO C K D IAG RAM
Stereo Inputs (4x)
Power Supply
EZ-KIT
Connector
External
Connector
Codec1
Codec2
Cascade
Select Circuit
Push-button
Switch. (S1)
Clock Generator
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for
its use, nor for any infringem ents of patents or other rights of third
parties which m ay result from its use. No license is granted by
im plication or otherwise under any patent or patent rights of Analog
Devices.
© Analog Devices, Inc., 1998
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106,
U.S.A. Tel: 617/329-4700
8703
Fax: 617/326-
EVAL-AD73322EB
P ower Su pply C ir cu it.
D.C. power between 8V & 12V is applied to the board through either connector J9 or J10 (positive is on the outer sleeve).
T hese connectors are connected together in a loop through arrangement which is intended for supplying the external voltage
to the EZ-KIT LIT E which accompanies this evaluation board. T he power supply shipped with the EZ-KIT Lite is suitable
for powering both the AD73322 board and the EZ-KIT LIT E board. Diode, D1, prevents damage due to accidental reversal
of the supply. Regulator, U5, generates the +5V necessary for all the analog and digital circuitry on the board.
C lock G en er a tor C ir cu it.
T he oscillator, U8, provides two stable crystal controlled outputs of 16.384MHz or 8.192MHz. One of these frequencies
is selected by LK4 to produce the on-board generated clock signal. LK5 is used to select this clock signal or the EZ-KIT LIT E
clock signal as the master clock (MCLK). MCLK is used as the main clock for the AD73322 and is also used for the external
synchronisation circuit for the SE and RESET signals. T he board is shipped with 16.384MHz selected as the default clock
frequency.
C ascade Selector cir cu it.
T his is programmed by software to determine the number of codecs in cascade. T he 74H C253(U3) is a 2 channel 4-1
multiplexer which is automatically controlled by software to select which codec has its SDO and SDOFS returned to the DSP.
T he process of downloading a user program automatically sets the multiplexer to the required setting. If the user develops
their own sample programs, then it is necessary to select the correct multiplexer settings for the cascade configuration. See
T able 1 for details of required multiplexer settings for various cascade settings.
D a u gh ter B oa r d .
T he daughter board is used to provide easy configuration for using the demonstation programs provided with the evaluation
board. It provides circuitry for a stereo line input at stereo jack J13. T hese inputs are single-ended but are put through a pair
of single-ended to differential converters to provide two fully differential inputs at the two input channels of device U1. T he
analog outputs of U1 are connected in a single-ended mode through an ac-coupling RC filter to provide an output which can
drive either the inputs of computer speakers or walkman headsets.
It is possible for the user to configure their own input circuitry on a similar daughter board. T he daughter board dimensions
are detailed in Figure 9 .
O P E RAT ING T H E AD 73322 E VALUAT IO N BO ARD
T he AD73322 EVAL BOARD is designed to be interfaced directly to the EZ-KIT LIT E which is an entry level demonstration
tool for the ADSP-2181 DSP. T he interface to the EZ-KIT LIT E is provided through the connector J11. Alternatively, the
board may be connected to the T exas Instrument T MS320C5XX EVM via connector J12.
Before applying power and signals to the evaluation board it is essential to ensure that all links are set as required for the desired
operating mode. T he function of all links is explained below.
L in k
B oa r d
F u n c t io n
LK 1
LK 2
LK 3
LK 4
LK 5
M ain Board
M ain Board
M ain Board
M ain Board
M ain Board
Connects T FS to RFS on DSP.
Connects SE to VDD or FL0 of DSP.
Connects RESET to FL2 or FL2 of DSP.
Selects between the 16.384MHz or 8.192MHz outputs from the on-board clock circuit.
Selects the on-board generated clock or DSP clock as the master clock for the board.
–2–
REV. A
EVAL-AD73322EB
Boards are shipped with the following link settings.
LIN K N O. P O SIT IO N
F U N C T I O N
LK 1
LK 2
LK 3
LK 4
LK 5
1 to 2
1 to 2
1 to 2
1 to 2
2 to 3
T FS tied to RFS.
SE tied to FL0 of DSP.
RESET tied to FL2 of DSP.
16.384MHz selected as the output of the crystal oscillator.
CLK tied to on board crystal oscillator.
INT E RF AC ING T O T H E E Z-KIT LIT E
T he EZ-KIT LIT E board must be modified by the inclusion of a right-angled male header strip (20 x 2) in positions 11 to
50 of connector P3. T his header mates to a matching female connector (J11) on the AD73322 Evaluation board.
•
•
•
•
•
Connect the AD73322 EVAL BOARD to the EZ-KIT LIT E BOARD using J11.
Plug the daughter board onto the EVAL BOARD using J1, J2, J5 and J6.
Connect the serial cable between PC and EZ-KIT LIT E.
Attach the power loop through cable between J10 of the EVAL BOARD and the power input of the EZ-KIT BOARD.
Apply power to the setup via J9 using the DC PSU supplied with the eval board.
When power is applied the green LED on EZ-KIT BOARD should remain lit while red LED should flash to indicate system
is ready to accept a program. If any difficulty is experienced please refer to the EZ-KIT LIT E REFERENCE MANUAL.
An a log I/O .
T he analog I/O to each codec is designed to be flexible and the evaluation board provides some prototyping space for
user supplied input/output circuitry. Codecs 1(U1) uses a pair of stereo (3 pole) 3.5 mm miniature jack plugs (J13
through J16) to connect signals to/from the evaluation board via single-in-line sockets J12 and J2 and from the
prototyping space through J5 and J6. Codecs 2(U2) uses single-in-line sockets J3 and J4 and from the prototyping area
through J7 and J8.
DC PSU
J9
EZ-KIT LITE
Board
Analog
Devices
J5
J6
J2
J1
Daughter Board
J11
EVAL-AD73322
Main Board
J10
RS232 Cable
to Computer
Loop-Through
Power Cable
Fig. 1: Interfacing to the EZ-KIT LITE.
REV. A
–3–
EVAL-AD73322EB
LO AD ING D E M O P RO G RAM S.
Follow EZ-KIT instructions for installation of EZ-KIT software. Activate the windows FILE MANAGER and create a
directory for the AD73322 diskette (example C:\ADI_DSP\EZ-73322) Copy the contents of the AD73322 demo programs
diskette into this directory. Alternatively the demo programs can be run from the diskette drive. C lose down FILE
M AN AG E R.
T he AD73322 evaluation board uses the user program facility of the EZ-KIT LIT E PC based software to download its
demonstration programs. T herefore it does not have a menu of demonstration options but instead the various demonstrations
must be downloaded as one would download a user program under the existing EZ-KIT LIT E software. Please refer to the
EZ-KIT LIT E reference manual for more details of this feature (page 6-13).
Activate the EZ-KIT LIT E -Monitor host program and select the LOADING option. T he red LED on the EZ-KIT LIT E
board must be flashing while doing this operation. Use the RESET button on the EZ-KIT board to make the LED flash if
necessary.
Fig. 2: Download User Program and Go menu
From this select the DOWNLOAD USER PROGRAM AND GO menu. T his opens the window shown in Fig. 2.
AD 73322 SING LE C O D E C D E M O P RO G RAM S
T hese demo programs use a single channel on an AD73322 device. T he other channel is powered-down except for the
SPORT section which must remain active to support cascading operation.
Loop- T h r ou gh (64 kH z) (a :\E Z_73322\sin gle\1in 1ou t.exe)
In this demo a single AD73322 codec is configured for loop-through operation with input samples being passed through
to the output at a 64 kHz rate. T his sampling rate gives low group delay sampling which is suitable for active control
applications.
File(s) used are: \EZ_73322\single\1in1out.dsp
Build using: \EZ_73322\single\make.bat
Loop- T h r ou gh (8 kH z) (a :\E Z_73322\sin gle\1in ou t8k.exe)
T his demo is similar to the 64 kHz sampling demo except that the sampling rate is reducedto 8 kHz.
File(s) used are: \EZ_73322\single\1inout8k.dsp
Build using: \EZ_73322\single\make.bat
T on e G en er a tor (a :\E Z_73322\sin gle\sin e_gen .exe)
T his demo generates a 1 kHz tone by updating a function generation algorithm at an 8 kHz rate. T he AD73322 channel
is set for a sample rate of 8 kHz which is uses to determine the function generation update points.
File(s) used are: \EZ_73322\single\init_cod.dsp
Build using: \EZ_73322\single\up.bat
\EZ_73322\single\sin.dsp
\EZ_73322\single\sine_gen.dsp
–4–
REV. A
EVAL-AD73322EB
D T M F (a:\E Z_73322\sin gle\dtm f\dtm f.exe)
T his program uses the DAC section of the CODEC to output a series of Dual-T one Multi-Frequency (DT MF) tones
which are used in telephony applications. T here are two possible settings for this demo
1
2
Generate a dial tone (the default setting) indicated by the LED on the EZKIT board being OFF
Generate a series of tones corresponding to a telephone number to be dialled indicated by the LED on the EZKIT
board being ON.
Use the pushbutton (S1) on the AD73322 eval board to toggle between the two options. T o close the demo please push
the INT ERRUPT button on the EZKIT board to return to the monitor program. T his program processes output
samples at an 8 kHz ratewhich is set by the AD73322 sample rate setting in Control Register B.
File(s) used are: \EZ_73322\single\dtmf\dtmf.dsp
Build using: \EZ_73322\single\dtmf\dtmf.bat
AD P C M (a :\E Z_73322\sin gle\a dpcm \a dpcm .exe)
T his program demonstrates an Adaptive Differential Pulse Code Modulation (ADPCM) algorithm providing
compression to 32 kbits/sec. T he AD73322 samples at an 8 kHz rate which determines the rate at which the ADPCM
algorithm runs. T he program allows the input/output channel to be configured for loop-through at 8 kHz or for the
ADPCM algorithm to be run in a loop-through mode. T he ADPCM algorithm takes the 16 bit ADC output and
compresses it to an 8 bit PCM value using µ-Law coding. T he 8-bit PCM value is input to the ADPCM encoder which
generates a 4-bit output update value. In the loop-through, this 4-bit value is input to the ADPCM decoder whose 8-bit
output is further expanded from µ-Law to 16-bit linear coding.
T here are two possible settings for this demo:
1
Loop-through of input to output at 8 kHz with no compression indicated by the LED on the EZKIT board being
O F F
2
Loop-through of input to output at 8 kHz featuring ADPCM indicated by the LED of the EZKIT board being
O N
Use the pushbutton (S1) on the AD73322 eval board to toggle between the two options. T o close the demo please push
the INT ERRUPT button on the EZKIT board to return to the monitor program. T his program processes input and
output samples at an 8 kHz rate.
File(s) used are: \EZ_73322\single\adpcm\adpcms.dsp
\EZ_73322\single\adpcm\Am_thr.dsp
\EZ_73322\single\adpcm\U _compre.dsp
\EZ_73322\single\adpcm\U _expand.dsp
Build using: \EZ_73322\single\adpcm\adpcm.bat
AD 73322 D UAL C O D E C D E MO P RO G RAMS
Ster eo E m u la tion (a :\E Z_73322\d u a l\2in 2ou t.exe)
T his program configures a dual codec cascade to emulate a stereo codec in that one codec converts the right channel
while the other codec converts the left channel. T his program’s code serves as a useful introduction to configuring the
AD73322 for cascaded operation.
File(s) used are: \EZ_73322\dual\2in2out.dsp
Build using: \EZ_73322\dual\dual.bat
M ixed M ode Ster eo E m u lation (a:\E Z_73322\du al\m m _m u te.exe)
T his program configures a dual codec cascade, in mixed mode, to emulate a stereo codec in that one codec converts the
right channel while the other codec converts the left channel. T he mixed mode mode function allows the codecs to be
controlled while processing ADC and DAC samples. In this demo the pushbutton switch (S1) toggles the outputs
between MUT E OFF and MUT E ON. T he red LED on the EZKIT LIT E board is ON when MUT E is enabled.
File(s) used are: \EZ_73322\dual\mm_mute.dsp
Build using: \EZ_73322\dual\mix_mode.bat
AD 73322 MULT I C O D E C D E MO P RO G RAMS
T h r ee C h a n n els (a :\E Z_73322\m u lti\3in 3ou t.exe)
T his program configures a three codec cascade.
File(s) used are: \EZ_73322\multi\3in3out.dsp
Build using: \EZ_73322\multi\make.bat
REV. A
–5–
EVAL-AD73322EB
F ou r C h a n n els (a :\E Z_73322\m u lti\4in 4ou t. exe)
T his program configures a four codec cascade.
File(s) used are: \EZ_73322\multi\4in4out.dsp
Build using: \EZ_73322\multi\make.bat
NOTE: New demonstration programs and revised versions of existing programs will be available for download at Analog's
Website http://www.analog.com . Please search for the AD73322 page and choose either the Evaluation Tools or Related
Topics option.
G E NE R AL NO T E S.
T he number of devices configured in cascade is programmed using the PF4 and PF5 flag I/O bits from the ADSP-2181.
T hese bits are used to program a 74HC253 dual 4:1 multiplexer which selects the SDO/SDOFS combination from one
of the four possible AD73322 codecs on the evaluation board. T he settings of PF4 and PF5 for each of the possible
cascade configurations is shown in the table below:
P F 5
P F 4
C ascade Selection
Single C odec
T wo Codecs
0
0
1
1
0
1
0
1
T hree Codecs
Four Codecs
Table I. Program settings for cascade configurations
–6–
REV. A
EVAL-AD73322EB
Fig. 3: EVAL-AD73322EB Main Board Component Side Artwork.
Fig. 4: EVAL-AD73322EB Main Board Solder Side Art-
REV. A
–7–
EVAL-AD73322EB
Fig. 5: EVAL-AD73322EB Main Board Silkscreen
Fig. 6:EVAL-AD73322EB Daughter Board
–8–
REV. A
-1 - Mon Apr 06 13:36:47 1998
Fig. 7: EVAL-AD73322EB Main Board Schematic.
EVAL-AD73322EB
F8:VL-A732EDugBordShematic.
–10–
REV. A
EVAL-AD73322EB
E VAL-AD 73322E B (MAIN BO ARD ) BILL O F MATE RIALS.
Qty Reference Designator
Description/Value
Manuf. No.
Supplier No.
2
1
1
1
1
1
1
1
U1-2
U3
U4
U5
U6
U7
U8
D1
AD73322
74HC253D
74HC14D
7805CT
74HC126D
74HC74D
ADI AD73322AR
Motorala - MC74HC253D
Motorala - MC74HC14D
Motorala - MC7805CT
Motorala - MC74HC126D
Motorala - MC74HC74D
Kinseki
FEC 492-310
FEC 701-853
FEC 492-358
FEC 221-740
FEC 365-117
16.384MHz Prog. XTAL
IN4002
Philips IN4002
9
C1 C3 C5 C8 C10 C12 C15
C18-19
10uF 16V Tant. TAJ-B Case
0.1uF Ceramic 0805 Case
AVXTAJB106K016R
FEC498-737
FEC499-687
16 C2 C11 C6 C13-14 C7
C16-17C4C9C20-25
AVXCM21X7R104K25VAT
1
1
1
R1
R2
R3
10kW 5% 0.1W 0805 Case
100kW 5% 0.1W 0805 Case
2kW 5% 0.1W 0805 Case
Multicomp
Multicomp
Multicomp
FEC613-216
FEC613-332
FEC771-375
7
L1-7
RFI Suppression Bead. 1206 Case
Steward 25Z1206-0SR
6
2
2
2
1
J1-4 J7-8
J5-6
J9-10
J9-10
J11
9884006
J12
J13 J14 J15 J16
J13 J14 J15 J16
LK1-5
Pin Header Socket (Top Entry) 9 way Precidip 801-91-009-10-001
Pin Header Socket (Top Entry) 6 way Precidip 801-91-006-10-001
Futura
Futura
FEC 224-959
FEC 224-923
Harwin M20-
PCB Mount Power Connector
Power Plug
ITT-Cannon
ITT-Cannon
Pin Header Socket (Side Entry) 40 way
FEC 148-532
1
4
4
5
5
1
4
Pin Header (Dual Row) (5+5)
3 Pole Stereo PCB Socket
Harwin M20-9951006
Marushin
FEC 511-808
FEC 152-204
FEC 152-203
FEC 511-717
FEC 528-456
FEC 176-986
FEC 148-922
Stereo plug (supply loose with pcb) Marushin
Pin Header (Single Row) (3 way)
Shorting Plugs
Push Button Switch
Rubber Stick-on-feet
Harwin M20-9990306
LK1-5
SW1
each corner
Harwin M7567-05
Omron B3W1000
3M SJ5076
Wire - 300mm strips - Red & Black (attach to power plugs J9 and J10, supply assembled cable with pcb)
REV. A
–11–
EVAL-AD73322EB
E VAL-AD 73322E B (D AUGH T E R BO ARD ) BILL O F MAT E RIALS.
In ter gr a ted C ir cu its
Component
Location
Vendor - Part Number
AD 8042AR
U1 U2 U3
Analog D evices -AD 8042AR
C a p a cit or s
Component
Location
Vendor
1uF (T EH -X Case)
470pF (0805 Case)
0.1uF (0805 Case)
10uF 6.3V X T EH T ant.
C1 C2 C3 C4
C5 C6 C7 C8
C9 C11 C13
C10 C12 C14
FEC - 247-583
FEC - 499-195
FEC - 499-687
FEC - 286-254
Resistor s
Component
Location
Vendor
47KΩ ±2% 0.1W (0805 Case) R1 R2
10KΩ ±2% 0.1W (0805 Case) R3 - R10
FEC - 109-322
FEC - 109-318
C on n ector s / H eader s/Lin ks
Component
Location
J1 J2
Vendor
9 Way SIL Header
6 Way SIL Header
Preci-D ip 800-10-009-10-002
Preci-D ip 800-10-006-10-002
J5 J6
Fig. 9: EVAL-AD73322EB Daughter Board Dimensions (Not to Scale)
–12–
REV. A
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