CMP04FS [ADI]
Quad Low Power, Precision Comparator; 四通道，低功耗，精密比较器
| 型号： | CMP04FS |
| 厂家： | 
ADI |
| 描述： | Quad Low Power, Precision Comparator |
| 文件： | 总8页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Low Power,
Precision Comparator
a
CMP04
PIN CONNECTIONS
FEATURES
High Gain: 200 V/mV Typ
Single- or Dual-Supply Operation
Input Voltage Range Includes Ground
Low Power Consumption (1.5 mW/Comparator)
Low Input Bias Current: 100 nA Max
Low Input Offset Current: 10 nA Max
Low Offset Voltage: 1 mV Max
Low Output Saturation Voltage: 250 mV @ 4 mA
Logic Output Compatible with TTL, DTL, ECL, MOS,
and CMOS
14-Lead SOIC
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT 3
OUT 4
GND
OUT 2
OUT 1
V+
4
1
IN 1–
IN 1+
IN 2–
IN 2+
IN 4+
IN 4–
IN 3+
IN 3–
2
3
Directly Replaces LM139/LM239/LM339 Comparators
8
CMP04
GENERAL DESCRIPTION
TYPICAL INTERFACE
Four precision independent comparators comprise the CMP04.
Performance highlights include a very low offset voltage, low
output saturation voltage, and high gain in a single-supply
design. The input voltage range includes ground for single-
supply operation and V– for split supplies. A low power
supply current of 2 mA, which is independent of supply voltage,
makes this the preferred comparator for precision applications
requiring minimal power consumption. Maximum logic inter-
face flexibility is offered by the open-collector TTL output.
5.0
1/4
CD4011
3
100k⍀
1/4
CMP04
12
Figure 2a. Driving CMOS
5.0
V+
3
10k⍀
3.5A
100A
3.5A
100A
1/4
OUTPUT
–INPUT
CMP04
Q8
1/4 SN7400
Q3
Q2
12
Q1
+INPUT
Q4
*
*
Q7
Figure 2b. Driving TTL
Q5
Q6
*SUBSTRATE DIODES
Figure 1. Simplified Schematic (1/4 CMP04)
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
CMP04–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V+ = 5 V, TA = 25؇C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input Offset Voltage
Input Offset Current
Input Bias Current
Voltage Gain
VOS
IOS
IB
AV
tr
RS = 0 Ω, RL = 5.1 kΩ, VO = 1.4 V1
IIN(+) – IIN(–), RL = 5.1 kΩ, VO = 1.4 V
IIN(+) or IIN(–)
0.4
2
25
200
1
10
100
mV
nA
nA
RL ≥ 15 kΩ, V+ = 15 V2
80
V/mV
Large Signal Response Time
VIN = TTL Logic Swing, VREF = 1.4 V3
VRL = 5 V, RL = 5.1 kΩ
300
1.3
ns
Small Signal Response Time
Input Voltage Range
Common-Mode Rejection Ratio CMRR
Power Supply Rejection Ratio
Saturation Voltage
Output Sink Current
Output Leakage Current
Supply Current
tr
VIN = 100 mV Step3, 5 mV Overdrive
VRL = 5 V, RL = 5.1 kΩ
µs
V
CMVR
Note 4
0
80
80
V+ – 1.5
400
Notes 2, 5
100
100
250
16
0.1
0.8
dB
dB
mV
mA
nA
mA
PSRR
VOL
ISINK
ILEAK
I+
V+ = 5 V to 18 V2
VIN(–) ≥ 1 V, VIN(+) = 0, ISINK ≤ 4 mA
VIN(–) ≥ 1 V, VIN(+) = 0, VO ≤ 1.5 V
VIN(+) ≥ 1 V, VIN(–) = 0, VO = 30 V
6
100
2.0
RL =
∞
, All Comps V+ = 30 V
NOTES
1At output switch point, VO = 1.4 V, RS = 0 Ω with V+ from 5 V, and over the full input common-mode range (0 V to V+ – 1.5 V).
2Guaranteed by design.
3Sample tested.
4The input common-mode voltage or input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range
is V+ – 1.5 V, but either or both inputs can go to 30 V without damage.
5RL ≥ 15 kΩ, V+ = 15 V, VCM = 1.5 V to 13.5 V.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
2
Package Type
JA
Unit
JC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +36 V or 18 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 36 V dc
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +36 V
Operating Temperature Range
CMP04FS . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature (TJ) . . . . . . . . . . . . . –65°C to +150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Input Current (VIN < –3.0 V) . . . . . . . . . . . . . . . . . . . 50 mA
Output Short Circuit to GND . . . . . . . . . . . . . . . .Continuous
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
14-Lead SOIC
120
36
°C/W
NOTES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2θJA is specified for worst-case mounting conditions, i.e., θJA is specified for device
soldered to printed circuit board for SOIC package.
ORDERING GUIDE
TA = 25؇C
VOS
Temperature
Ranges
Package
Descriptions
Package
Options
Model
CMP04FS
1 mV
–40°C to +85°C
14-Lead SOIC
R-14
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the CMP04 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–2–
REV. D
CMP04
(@ V+ = 5 V, –40؇C ≤ TA ≤ +85؇C for CMP04FS, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
CMP04F1
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input Offset Voltage
VOS
RS = 0 Ω, RL = 5.1 kΩ
VO = 1.4 V2
IIN(+) – IIN(–)
RL = 5.1 kΩ
VO = 1.4 V
1
1
4
4
2
2
20
20
20
200
mV
mV
nA
nA
nA
nA
V/mV
ns
Input Offset Current
IOS
4
Input Bias Current
Voltage Gain
Large Signal Response Time
IB
AV
tr
IIN(+) or IIN(–)
40
125
300
300
300
1.3
1.3
1.3
RL ≥ 15 kΩ, V+ = 15 V3
VIN = TTL Logic Swing
70
V
REF = 1.4 V4
ns
ns
VRL = 5 V, RL = 5.1 kΩ
VIN = 100 mV Step4
5 mV Overdrive
VRL = 5 V, RL = 5.1 kΩ
Note 5
Small Signal Response Time
tr
µs
µs
µs
Input Voltage Range
CMVR
0
V+ – 1.5
V
Common-Mode Rejection Ratio CMRR
Notes 1, 3
60
80
100
100
250
250
16
dB
dB
mV
mV
mA
mA
nA
nA
mA
mA
Power Supply Rejection Ratio
Saturation Voltage
PSRR
VOL
V+ = 5 V to 18 V
VIN(–) ≥ 1 V, VIN(+) = 0,
ISINK ≤ 4 mA
VIN(–) ≥ 1 V,
VIN(+) = 0, VO ≤ 1.5 V
VIN(+) ≥ 1 V,
VIN(–) = 0, VO = 30 V
RL = ∞, All Comps
V+ = 30 V
700
700
Output Sink Current
Output Leakage Current
Supply Current
ISINK
ILEAK
I+
5
5
16
0.1
0.1
1.2
1.2
200
200
3.0
3.0
NOTES
1RL ≥ 15 kΩ, V+ = 15 V, VCM = 1.5 V to 13.5 V.
2At output switch point, VO = 1.4 V, RS = 0 Ω with V+ from 5 V; and over the full input common-mode range (0 V to V+ –1.5 V).
3Guaranteed by design.
4Sample tested.
5The input common-mode voltage or input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode
voltage range is V+ – 1.5 V, but either or both inputs can go to +30 V without damage.
Specifications subject to change without notice.
–18V
–18V
3.6k⍀
3.6k⍀
14
13
12
11
10
9
8
4
1
2
CMP04
3
3
1
2
4
5
6
7
100k⍀
3.6k⍀
3.6k⍀
+18V
+18V
ZENER
5.8V TO 6.2V
1 WATT
ONE EACH
PER BOARD
470k⍀
30V
MIL-STD-883, METHOD 1015, CONDITION B
TO ADJACENT SOCKETS
Figure 3. Burn-In Circuit
–3–
REV. D
CMP04–Typical Performance Characteristics
3.0
2.0
80
60
40
20
0
0.3
0.2
1.0
0.1
T
= 0؇C
A
0
0
T
= +25؇C/70؇C
A
–1.0
–2.0
–3.0
–0.1
–0.2
–0.3
–60
–40 –20
0
20 40 60 80 100 120 140
0
5
10
15 20
25
30
DC
35
40
–60
–40 –20
0
20 40 60 80 100 120 140
V+ – SUPPLY VOLTAGE (V
)
TEMPERATURE (؇C)
TEMPERATURE (؇C)
TPC 1. Offset Voltage vs.
Temperature
TPC 2. Input Bias Current vs. V+
and Temperature
TPC 3. Input Offset Current vs.
Temperature
10
1.1
160
OUT OF SATURATION
1.0
150
140
130
120
110
100
90
T
= 0؇C
A
0.9
0.7
0.5
0.3
0.1
T
= +25؇C
A
0.1
T
= +70؇C
A
0.01
T
= +25؇C
80
A
70
0.001
0.01
60
–60
0
5
10
15
20
25
30
35
40
0.1
1.0
10
100
–40 –20
0
20 40 60 80 100 120 140
SUPPLY VOLTAGE (V
)
I
– OUTPUT SINK CURRENT (mA)
DC
O
TEMPERATURE (؇C)
TPC 5. Supply Current vs. Supply
Voltage
TPC 6. Output Voltage vs. Output
Current and Temperature
TPC 4. Voltage Gain vs.
Temperature
6.0
5.0
6.0
INPUT OVERDRIVE =
5.0mV
T
= 25؇C
INPUT OVERDRIVE =
100mV
A
5.0
4.0
3.0
2.0
1.0
0
5VDC
4.0
20mV
20mV
V
IN
3.0
5.1k⍀
5mV
2.0
V
100mV
OUT
1.0
0
5VDC
5.1k⍀
V
IN
0
0
V
OUT
–50
–100
–50
–100
T
= 25؇C
A
0
0.5
1.0
TIME (s)
1.5
2.0
0
0.5
1.0
TIME (s)
1.5
2.0
TPC 8. Response Time for Various Input
Overdrives—Positive Transition
TPC 7. Response Time for Various Input
Overdrives—Negative Transition
–4–
REV. D
CMP04
TYPICAL APPLICATIONS
V+
3k⍀
V+
+V
IN
1/4
CMP04
6.2k⍀
1M⍀
1/4
CMP04
V+
V
O
V
O
1M⍀
STROBE
INPUT
*
1M⍀
*OR LOGIC WITHOUT
PULLUP RESISTOR
Figure 4. Output Strobing
Figure 7. Inverting Comparator with Hysteresis
V+
4.3k⍀
100k⍀
2R
R
S
+V
HIGH
REF
1/4
CMP04
75pF
V+
0
1/4
CMP04
f = 186kHz
S
+V
IN
V
O
100k⍀
100k⍀
1/4
CMP04
V+
2R
S
100k⍀
+V
LOW
REF
Figure 5. Limit Comparator
Figure 8. Square Wave Oscillator
V+
3k⍀
V+
100k⍀
100k⍀
V
IN1
+V
REF
5.1k⍀
1/4
CMP04
1/4
CMP04
1N914
V
O
10k⍀
V
IN2
+V
IN
V
O
10M⍀
Figure 6. Noninverting Comparator with Hysteresis
Figure 9. Comparing Input Voltages of Opposite Polarity
REV. D
–5–
CMP04
V+
15k⍀
V+
V+
R1
D1
1M⍀
1N914
0
t0
1M⍀
10k⍀
R2
100k⍀
D2
1N914
100pF
V+
0
+V
IN
1ms
PW
1/4
CMP04
80pF
1N914
V+
0
1M⍀
t0 t1
1/4
CMP04
V
t0
t1
t2
O
0.01F
1M⍀
1M⍀
V+
FOR LARGE RATIOS OF R1/R2,
D1 CAN BE OMITTED.
1N914
1M⍀
1M⍀
Figure 10. One-Shot Multivibrator
Figure 12. Pulse Generator
V+
V+
200k⍀
39k⍀
3k⍀
3k⍀
100k⍀
100k⍀
0.075V
0.375V
A
B
C
A
1/4
CMP04
1/4
1k⍀
1k⍀
f
f
V+
0
V+
0
CMP04
100k⍀
100k⍀
B
1k⍀
1k⍀
100k⍀
0
1
100k⍀
0
1
1 = A + B + C
1 = A • B • C
C
Figure 11. AND Gate
Figure 13. OR Gate
V+
1M⍀
560k⍀
1M⍀
4V
100k⍀
10M⍀
15k⍀
+V
IN
1S
1/4
CMP04
100k⍀
0
1/4
CMP04
100pF
V+
0
V
T
O
10M⍀
t0
t1
240k⍀
T = 0.3ms
62k⍀
Figure 14. One-Shot Multivibrator with Input Lockout
–6–
REV. D
CMP04
V+
V+
V3
V2
V1
0
3.0k⍀
3.0k⍀
3.0k⍀
10k⍀
15k⍀
200k⍀
10k⍀
10M⍀
V+
0
t0
t3
1/4
CMP04
V
V
C1
O3
V3
V+
51k⍀
10k⍀
t0
t1
t2
t3
t4
10M⍀
V+
0
1/4
CMP04
10k⍀
t0 t2
V+
1/4
CMP04
C1
0.001F
V
+V
IN
O2
0
V2
V+
t0
t4
INPUT GATING SIGNAL
51k⍀
10k⍀
10M⍀
V+
0
t0 t1
1/4
CMP04
V
O1
V1
51k⍀
Figure 15. Time Delay Generator
REV. D
–7–
CMP04
OUTLINE DIMENSIONS
14-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
14
1
8
7
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
؋
45؇ 0.25 (0.0098)
0.10 (0.0039)
8؇
0؇
0.51 (0.0201)
0.33 (0.0130)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.19 (0.0075)
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
3/03—Data Sheet changed from REV. C to REV. D.
Renumbered TPCs and Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
Deletion of 14-Lead CERDIP and 14-Lead PDIP information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Removal of DICE CHARACTERISTICS, WAFER TEST LIMITS, and TYPICAL ELECTRICAL
CHARACTERISTICS sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to TPCs 2, 5, and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
–8–
REV. D
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