ADV8005KBCZ-8N-RL_技术文档

NatureVue Video Signal Processor with

Bitmap OSD, Dual HDMI Tx, and Encoder

ADV8005

Data Sheet

Easy to use software tool for developing OSDs

FEATURES

Video signal processor

HDMI transmitters

Dual 4k × 2k HDMI transmitters

Audio return channel (ARC) support

Full 12-bit, 4:4:4 YCbCr (color space) internal processing

Motion adaptive deinterlacing with ultralow angle

interpolation

Multiple video processing paths with up to 3 simultaneous

video streams including picture-in-picture (PiP) support

Upscaling and downscaling to/from 4k × 2k

Aspect ratio conversion/panorama scaling

Cadence detection for the recovery of original frames from

film-based content

Dual audio insertion from TMDS Rx or from audio input pins

Support for serial audio using the S/PDIF audio pin

8-channel I²S audio inputs supporting up to 192 kHz

sample frequency

6-channel direct stream digital (DSD) audio inputs

Noise shaped video (NSV) 6-DAC video encoder

Six 12-bit NSV video DACs supporting SD, ED and HD video

Rovi Rev. 7.1.L1 (SD) and Rev. 1.4 (ED) compliant

Professional video features

Dual video scalers enable simultaneous output of multiple

different resolutions

Capability to output up to 36-bit TTL pixel data

Full color space converter on the output TTL pixel data

TTL video, audio, SPI, and interrupt pins disabled by default

Ability to synchronize output video to externally applied

reference sync signals

Sharpness and detail enhancement

Noise reduction for random, mosquito, and block noise

Frame rate converter (FRC)

Video metrics readback to enable correct phase and

frequency selection for graphics inputs

On-screen display (OSD)

Internally generated bitmap-based OSD allowing overlay

on one or more video outputs

APPLICATIONS

High end A/V receivers

Upconverting DVD players/recorders

Video conferencing and distribution

HDMI splitters

Overlay on 3D and 4k × 2k video formats

Dedicated OSD scaler

Alpha blending of OSD data on video data

Disturbance free blending of OSD on either of 2 zones

Support for external OSD

Video walls

FUNCTIONAL BLOCK DIAGRAM

DDR2 INTERFACE

ADV8005

60-BIT

TTL PORT

OSD BUILD

AND SCALE

24-BIT/

HDMI Tx1

HDMI Tx2

HDMI

36-BIT/

48-BIT

VIDEO

INPUT

TTL DATA

LOW ANGLE

PROCESSING

DETAIL

ENHANCE

HDMI

CADENCE

DETECTION

NOISE

36-BIT

VIDEO

OUTPUT

REDUCTION

DUAL SCALER

AND

OSD BLEND

MOTION

DETECTION

ENHANCE

FRC

HD VIDEO

DACs

HD VIDEO

SD VIDEO

CUE

CORRECTION

SD VIDEO

DACs

DEINTERLACER

VIDEO PROCESSING

SERIAL VIDEO

FOR EXAMPLE, ADV7850

SERIAL

VIDEO

RECEIVER

OUTPUT

AUDIO INPUT

Figure 1.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADV8005

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Professional Configuration....................................................... 45

External Sync mode ................................................................... 45

Flexible Digital Core .................................................................. 45

Video Signal Processor (VSP)................................................... 45

On-Screen Display (OSD)......................................................... 46

External DDR2 Memory ........................................................... 46

HDMI Transmitters ................................................................... 46

Video Encoder ............................................................................ 46

Typical Application Diagram.................................................... 47

Design Considerations................................................................... 48

Power-Up Sequence................................................................... 48

Thermal Considerations............................................................ 48

Register Map Architecture ............................................................ 49

Outline Dimensions....................................................................... 50

Ordering Guide .......................................................................... 50

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

ADV8005 Models......................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications..................................................................................... 5

Electrical Characteristics............................................................. 5

Analog Specifications................................................................... 7

Data and I²C Timing Characteristics......................................... 7

Absolute Maximum Ratings.......................................................... 17

ESD Caution................................................................................ 17

Pin Configurations and Function Descriptions ......................... 18

Theory of Operation ...................................................................... 45

Video Input.................................................................................. 45

REVISION HISTORY

6/14—Revision 0: Initial Version

Rev. 0 | Page 2 of 52

Data Sheet

ADV8005

GENERAL DESCRIPTION

The ADV8005 is a multiple input video signal processor that can

deinterlace and scale standard definition (SD), enhanced

definition (ED), or high definition (HD) video data to ultra HD

formats; generate a bitmap on-screen display (OSD); and output

the video with OSD overlaid on two High-Definition Multimedia

Interface (HDMI®) transmitters and a video encoder.

like scrolling text and animation in various color depths up to

24-bit true color.

Analog Devices, Inc., provides an OSD development tool (Blimp)

to assist in the design, debug, and emulation of the OSD prior

to integration with the system application. When the design is

complete, the OSD development tool automatically generates

code to which system application programming interfaces

(APIs) can be added before integration with the system

application and an OSD design resource, which must be

downloaded to an external SPI flash memory.

The 60-bit TTL video port can be used to input video to the

ADV8005 in a number of ways: using the 48-bit TTL pixel port,

using the 24-bit external OSD TTL pixel port, or from a device

with an HDMI transmitter such as the ADV7850. The ADV8005

supports many of the formats outlined in the CEA-861-F and

VESA specifications, as well as several other widely used timing

formats.

Video can be output from the ADV8005 using one or both of the

HDMI transmitters and/or the six-DAC SD/HD video encoder.

The six 12-bit NSV® video DACs allow composite (CVBS),

S-Video (Y/C), and component (YPrPb) analog outputs in

standard, enhanced, and high definition video formats.

Oversampling of 216 MHz (SD and ED) and 297 MHz (HD)

removes the requirement for external output filtering. Rovi® and

non-Rovi variants of the ADV8005 are available.

The ADV8005 features primary and secondary video scalers

that enable simultaneous output of multiple different resolutions.

The primary video scaler can upscale to 4k × 2k modes. The

secondary video scaler can upscale to 1080p or UXGA graphics.

4k × 2k downscaling is performed using the secondary video

scaler, leaving the primary video scaler available for other video

processing.

Both of the HDMI transmitters on the ADV8005 support 4k × 2k

and all mandatory and many optional 3D video resolutions. Each

transmitter features an audio return channel receiver (ARC).

The ADV8005 can receive up to eight channels of I²S, S/PDIF,

direct stream digital (DSD), and high bit rate (HBR) audio passed

from either the serial video Rx or from the externally available

audio input pins.

The ADV8005 primary video scaler can perform high

performance, motion adaptive interlaced to progressive

conversion on SD and HD content. Additional functionality has

also been added to ADV8005 to facilitate upscaling and

downscaling to VESA formats with pixel clock frequencies below

300 MHz.

The ADV8005 supports the I²C protocol for communication

with the system microcontroller.

Detail enhancement and image enhancing techniques such as

random, mosquito, and block noise reduction allow improved

final image quality. The frame rate converter of the ADV8005

allows the conversion between common frame rates with support

to output two different frame rates simultaneously under certain

conditions.

ADV8005 MODELS

The ADV8005 includes a number of models, each featuring

different capabilities; all are provided in the same 19 mm ×

19 mm, 425-ball CSP_BGA package (see Table 9).

Note that the functionality of the ADV8005KBCZ-8A is

described throughout this data sheet. Some sections are not

relevant to other models because not all of the blocks found in

the ADV8005KBCZ-8A are included in those models. Table 9

lists the functionality for each model.

The ADV8005 can accept OSD information from an external OSD

source on one of its inputs, or it can internally generate a high

quality, bitmap-based OSD. The internal OSD is highly flexible

and allows the system designer to easily incorporate features

Rev. 0 | Page 3 of 52

ADV8005

Data Sheet

DETAILED FUNCTIONAL BLOCK DIAGRAM

0 - 0 3 2 1 0 7 4

COMPx

RSETx

R E X E L P I T L M U

E T R L S I F N I G L P S A R M E V O 4 / × × 6 1

VREF

s L P L × 2

DSD_CLK

ELPFx

SFL

AUD_IN[5:0]

G N I X M U

SCLK

R

S E S O C O P R

D H / E D

R

S O E S C P R O

S D

MCLK

ALSB

DDR_VREF

SCL

SDA

G N U X M I O D E V I

DDR_CK

CS2

DDR_CK

DDR_CS

SCK2

MISO2

MOSI2

CS1

SCK1

MISO1

MOSI1

DDR_WE

DDR_RAS

DDR_CAS

HEAC_1–

HEAC_1+

HEAC_2–

HEAC_2+

ARC1_OUT

ARC2_OUT

DDR_A[13:0]

DDR_BA[2:0]

REF_CLK

REF_HS

REF_VS

DDR_DM[3:0]

DDR_DQS[3:0]

DVDD_IO

PVDD_DDR

DVDD_DDR

AVDDx

CVDD1

R E H T I D U P

N O I E R V N S C O

C E A P S R O L C O

R H T E D I U P

N O I R E S N V C O

A P C S E R O L C O

N O I R E S N V C O

C A E P S R O L C O

N O

E R S N I V O C

PVDDx

C A E P S R L O C O

DVDD

DDR_DQS[3:0]

DDR_DQ[31:0]

PDN

RESET

Figure 2. ADV8005KBCZ-8A Functional Block Diagram

Rev. 0 | Page 4 of 52

Data Sheet

ADV8005

SPECIFICATIONS

Measured at DVDD = 1.746 V to 1.854 V, DVDD_DDR = 1.746 V to 1.854 V, PVDD1 = 1.746 V to 1.854 V, PVDD2 = 1.746 V to 1.854 V,

PVDD3 = 1.746 V to 1.854 V, PVDD5 = 1.789 V to 1.90 V, PVDD6 = 1.789 V to 1.90 V, PVDD_DDR = 1.746 V to 1.854 V, AVDD3 =

1.746 V to 1.854 V, AVDD4 = 1.746 V to 1.854 V, CVDD1 = 1.746 V to 1.854 V, AVDD1 = 3.20 V to 3.40 V, AVDD2 = 3.20 V to 3.40 V,

DVDD_IO = 3.20 V to 3.40 V, T_MINto T_MAX= 0°C to 70°C, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution (Each DAC)

Integral Nonlinearity, +ve¹

Integral Nonlinearity, −ve¹

12

Bits

LSB

INL

DAC outputs sampled at 500 kHz

0.389

−0.322

0.183

−0.208

Differential Nonlinearity, +ve²DNL

Differential Nonlinearity, −ve²

DNL

DIGITAL INPUTS

Input High Voltage

V_IH

V_IL

I_IN

0.7 ×

DVDD_IO

V

Input Low Voltage

0.3 ×

DVDD_IO

±±0

V

Input Leakage Current

HDMI Ethernet and audio channel

(HEAC_x±) inputs

μA

DDR_DQS[x] inputs

Other digital inputs

RESET

±±0

±10

±±0

μA

pF

Input Capacitance

DIGITAL INPUTS (5 V TOLERANT)

Input High Voltage

Input Low Voltage

Input Leakage Current

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

High Impedance Leakage

Current

C_IN

13

V_IH

V_IL

I_IN

3.4

2.4

V

μA

0.8

±±0

V_OH

V_OL

I_LEAK

V

μA

0.4

±10

Output Capacitance

POWER REQUIREMENTS^{3, 4}

Digital Power Supplies

C_OUT

13

pF

V

DVDD, DVDD_DDR,

PVDD_DDR

1.74±

1.8

1.854

PLL Analog Supply

PLL Digital Supply

Encoder PLL Supply

HDMI PLL Power Supply⁵

Transmitter 1 (Tx1)

Transmitter 2 (Tx2)

HDMI Analog Power Supply

Tx1

PVDD1

PVDD2

PVDD3

1.74±

1.8

1.854

V

PVDD5

PVDD±

1.789

1.845

1.90

V

AVDD3

AVDD4

CVDD1

AVDD1

1.74±

3.20

1.8

3.3

1.854

3.40

V

Tx2

Comparator Power Supply

HDMI Rx Inputs Analog

Supply

Encoder Analog Power

Supply

Digital Interface Supply

AVDD2

3.20

3.3

3.40

V

DVDD_IO

Rev. 0 | Page 5 of 52

ADV8005

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

Digital Power Supply

Currents

I_DVDD, I_{DVDD_DR}, I_{PVDD_DDR}

Mode 1

1693.9

mA

Mode 2

Power-down mode

Mode 1

Mode 2

Power-down mode

Mode 1

Mode 2

Power-down mode

Mode 1

Mode 2

Power-down mode

Mode 1

Mode 2

Power-down mode

Mode 1

Mode 2

Power-down mode

Mode 1

1508.1

11.7

23.0

20.5

0.9

21.3

19.26

0.06

13.8

3.27

0.01

74.9

59.0

0

mA

PLL Analog Supply Current

PLL Digital Supply Current

Encoder PLL Supply Current

I_PVDD1

I_PVDD2

I_PVDD3

HDMI Tx1 PLL Supply Current I_PVDD5

HDMI Tx2 PLL Supply Current I_PVDD6

75.0

0.5

0

HDMI Tx1 Analog Power

Supply Current

I_AVDD3

I_AVDD4

I_CVDD1

I_AVDD1

29.4

Mode 2

Power-down mode

Mode 1

19.7

0

26.6

mA

HDMI Tx2 Analog Power

Supply Current

Mode 2

Power-down mode

Mode 1

0.6

0

78.4

mA

Comparator Power Supply

Current

Mode 2

Power-down mode

Mode 1

73.4

1.1

63.1

mA

HDMI Rx Inputs Analog

Supply Current

Mode 2

Power-down mode

Mode 1

Mode 2

Power-down mode

Mode 1

57.6

0.2

38.0

34.9

2.1

mA

Encoder Analog Power Supply

I_AVDD2

Digital Interface Supply

Current

I_{DVDD_IO}

3.0

Mode 2

Power-down mode

1.3

0

mA

¹Integral nonlinearity (INL) measures the deviation of the actual DAC transfer function from the ideal. For +ve INL, the actual line lies above the ideal line value. For −ve INL,

the actual line lies below the ideal line value.

²Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal

step value. For −ve DNL, the actual step value lies below the ideal step value.

³Mode 1 involves a 1080i, 60 Hz input to the ADV8005 receiver and a 720p, 60 Hz input to the ADV8005 TTL external OSD input. Both inputs are run through the front-

end color space converters. The 1080i, 60 Hz video stream is deinterlaced and upscaled to 4k × 2k at 24 Hz. The 720p video stream is input to the OSD block and is

blended onto the 4k × 2k at 24 Hz video stream using the OSD block scaler. Both HDMI transmitters are then driven using the 4k × 2k at 24 Hz output.

⁴Mode 2 involves a 1080i, 60 Hz input to the ADV8005 receiver. This input is run through the front-end color space converter. The 1080i, 60 Hz video stream is

deinterlaced and is output to HDMI Tx1. The secondary VSP is used to convert the 1080p video stream to 480i and is output using the SD encoder.

⁵For normal operation, set the Tx PVDD5 and PVDD6 supplies to 1.845 V 3ꢀ. However, if the ADV8005 die temperature is kept below 100°C, it is possible to use

PVDD5 and PVDD6 with a reduced nominal voltage supply level of 1.8 V 3ꢀ. It is possible to measure the die temperature (T_J) of the ADV8005 using the method

outlined in the Thermal Considerations section. If using this reduced voltage level with Tx PVDD5 and PVDD6, it is the responsibility of the customer to ensure that the

die temperature is below 100°C when used in the highest power mode of the application and at its highest ambient temperature.

Rev. 0 | Page 6 of 52

Data Sheet

ADV8005

ANALOG SPECIFICATIONS

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

OUTPUT

4.3

Low Drive Output Current (Full Scale)

Output Compliance

Output Capacitance

R_SET= 4.12 kΩ, R_L= 300 Ω

3.95

0

4.5

1.4

mA

V

pF

V_OC

C_OUT

9

DAC1, DAC2, DAC3

DAC4, DAC5, DAC±

DAC

0.9

0.2

DAC-to-DAC Matching

DAC Analog Output Skew

DAC1 to DAC±

%

ns

DATA AND I²C TIMING CHARACTERISTICS

For input timing measurements, V_IH= DVDD_IO and V_IL= GND.

Table 3.

Parameter

Symbol Test Conditions/Comments Min

Typ

Max

Unit

TMDS CLOCK

TMDS Input Clock Frequency

TMDS Output Clock Frequency

CLOCK AND CRYSTAL

Crystal (XTAL) Frequency

Stability

25

297

MHz

27

MHz

ppm

±50

Video Input Clock Frequency

Range

Primary

Secondary

Video Output Clock Frequency

Range

13.5

1±2

MHz

Serial Clock Frequency

Serial Port 1 (SCK1)

Serial Port 2 (SCK2)

Serial Port 3 (VBI_SCK)

Audio Frequency

50

81

27

MHz

11.5

SCLK

MCLK

DSD_CLK

49.152

98.304

5.±448

MHz

FAST I²C PORTS¹

See Figure 3

SCL Frequency

400

kHz

ns

μs

ns

μs

SCL Minimum Pulse Width High

SCL Minimum Pulse Width Low

Start Condition Hold Time

Start Condition Setup Time

SDA Setup Time

SCL and SDA Rise Time

SCL and SDA Fall Time

Stop Condition Setup Time

SERIAL PORT^{2, 3}

t₁

t₂

t₃

t₄

t₅

t_±

t₇

t₈

±00

1.3

±00

100

300

0.±

Master Serial Port (Serial Port 2)

See Figure 4, Figure 5, and

Figure ±

CS2

t₉, t₁₀

t₉or t₁₀, depending on the

values of CPHA and CPOL

1 × SCK2⁴

1.5 × SCK2⁴

ns

Falling Edge to SCK2

Rising/Falling Edge

SCK2 Rising/Falling Edge to

CS2

t₁₁, t₁₂

t₁₁or t₁₂, depending on the

values of CPHA and CPOL

Rising Edge

Rev. 0 | Page 7 of 52

ADV8005

Data Sheet

Parameter

Symbol Test Conditions/Comments Min

Typ

Max

Unit

CS2

t₁₃

t₁₄

1880

1900

ns

Pulse Width

SCK2 High Time

SCK2 Low Time

MOSI2 Start of Data Invalid to

SCK2 Falling Edge

0.45 × SCK2⁴

0.55 × SCK2⁴

1.45

% duty cycle

ns

t₁₅

SPI Mode 0, SPI Mode 3

CS2

1.21

0.08

0.19

ns

Start of Data Invalid to

SCK2 Falling Edge

SCK2 Falling Edge to MOSI2 End t_1±

of Data Invalid

CS2

t_1±

t₁₇

t₁₈

t₁₉

t₂₀

t₂₁

t₂₂

SCK2 Falling Edge to

of Data Invalid

MISO2 Setup Time

End

Valid regardless of the

SCK2 active edge used

Valid regardless of the

SCK2 active edge used

SPI Mode 1, SPI Mode 2

11.19

0.0

MISO2 Hold Time

MOSI2 Start of Data Invalid to

SCK2 Rising Edge

CS2

SCK2 Rising Edge

SCK2 Rising Edge to MOSI2 End

of Data Invalid

1.45

1.21

0.08

0.19

Start of Data Invalid to

CS2

SCK2 Rising Edge to

of Data Invalid

MISO2 Setup Time

End

Valid regardless of the

SCK2 active edge used

Valid regardless of the

SCK2 active edge used

11.19

0.0

MISO2 Hold Time

Slave Mode (Serial Port 1)

See Figure 7, Figure 8, and

Figure 9

CS1

t₂₃, t₂₄

t₂₅, t_2±

t₂₃or t₂₄, depending on the

values of CPHA and CPOL

50.0

ns

Falling Edge to SCK1

Rising/Falling Edge

SCK1 Rising/Falling Edge to

CS1

t₂₅or t_2±, depending on the

values of CPHA and CPOL

Rising Edge

Pulse Width

CS1

t₂₇

t₃₀

5 × SCK1⁴

ns

SCK1 High Time

SCK1 Low Time

MOSI1 Setup Time

MOSI1 Hold Time

SCK1 Falling Edge to MISO1

Start of Data Invalid

0.45 × SCK1⁴

1.±3

0.55 × SCK1⁴

% duty cycle

ns

t₃₁

t₃₂

t₃₃

SPI Mode 0, SPI Mode 3

0.±±

5.7

SCK1 Falling Edge to MISO1 End t₃₄

of Data Invalid

SPI Mode 0, SPI Mode 3

12.1±

ns

MOSI1 Setup Time

MOSI1 Hold Time

SCK1 Rising Edge to MISO1 Start t₃₇

of Data Invalid

t₃₅

t_3±

SPI Mode 1, SPI Mode 2

1.±3

0.±±

ns

5.7

SCK1 Rising Edge to MISO1 End

of Data Invalid

Slave Mode (Serial Port 3)

VBI_SCK High Time

VBI_SCK Low Time

t₃₈

SPI Mode 1, SPI Mode 2

See Figure 10

12.1±

ns

t₃₉

0.45 × VBI_SCK⁴

0.55 × VBI_SCK⁴

% duty cycle

CS

VBI_ Pulse Width

5 × VBI_SCK

ns

CS

VBI_ , VBI_MOSI Setup Time

t₄₀

t₄₁

SPI Mode 0 only

1.27

0.15

CS

VBI_ , VBI_MOSI Hold Time

Rev. 0 | Page 8 of 52

Data Sheet

ADV8005

Parameter

Symbol Test Conditions/Comments Min

Typ

Max

Unit

SPI Passthrough Mode

Data Transition on SCK1 to

Start of Data Invalid on SCK2

See Figure 11

t₄₂

4.97

10.10

5.32

ns

Data Transition on SCK1 to End t₄₃

of Data Invalid on SCK2

Data Transition on MOSI1 to

Start of Data Invalid on

MOSI2

t₄₂

t₄₃

t₄₂

t₄₃

Data Transition on MOSI1 to

End of Data Invalid on

MOSI2

10.82

4.3±

8.85

ns

Data Transition on MISO2 to

Start of Data Invalid on

MISO1

Data Transition on MISO2 to

End of Data Invalid on

MISO1

CS1

t₄₂

t₄₃

5.32

ns

Data Transition on

to

CS2

Start of Data Invalid on

CS1

10.91

Data Transition on

to End

CS2

of Data Invalid on

RESET FUNCTION

Reset Pulse Width

5

ms

VIDEO DATA AND CONTROL INPUTS³

See Figure 12 to Figure 1±

PCLK High Time

PCLK Low Time

OSD_CLK High Time

OSD_CLK Low Time

Main Video Input, SDR and DDR

Modes Setup Time (Data

Latched on Rising Edge)

t₄₄

t₅₁

t₄₅

0.45 × PCLK⁴

0.45 × OSD_CLK⁴

1.28

0.55 × PCLK⁴

0.55 × OSD_CLK⁴% duty cycle

ns

% duty cycle

OSD_CLK signal of Pin A3

Main Video Input, SDR and DDR

Modes Hold Time (Data

Latched on Rising Edge)

Main Video Input, DDR Mode

Setup Time (Data Latched on

Falling Edge)

Main Video Input, DDR Mode

Hold Time (Data Latched on

Falling Edge)

Interleaved Video Input, SDR

Setup Time (Data Latched on

Rising Edge)

Interleaved Video Input, SDR

Hold Time (Data Latched on

Rising Edge)

External OSD Input, SDR and DDR

Modes Setup Time (Data

Latched on Rising Edge)

External OSD Input, SDR and DDR

Modes Hold Time (Data

Latched on Rising Edge)

External OSD Input, DDR Mode

Setup Time (Data Latched on

Rising Edge)

External OSD Input, DDR Mode

Hold Time (Data Latched on

Rising Edge)

t_4±

t₄₇

t₄₈

t₄₉

t₅₀

t₅₂

t₅₃

t₅₄

t₅₅

1.±7

1.28

1.±7

1.28

1.±7

1.28

1.±7

1.28

1.±7

ns

Used for 300 MHz TTL data

Rev. 0 | Page 9 of 52

ADV8005

Data Sheet

Parameter

Symbol Test Conditions/Comments Min

Typ

Max

Unit

VIDEO DATA AND CONTROL

OUTPUTS³

OSD_CLK High Time

OSD_CLK Low Time

Data and Control Start of Data

Invalid to OSD_CLK Active

Edge (Data Latched on Falling

Edge)

OSD_CLK Active Edge to Data

and Control End of Data

Invalid (Data Latched on

Falling Edge)

Data and Control Start of Data

Invalid to OSD_CLK Active

Edge (Data Latched on Rising

Edge)

OSD_CLK Active Edge to Data

and Control End of Data

Invalid (Data Latched on Rising

Edge)

See Figure 17 and Figure 18

t_5±

t₅₇

0.40 × OSD_CLK⁴

0.±0 × OSD_CLK⁴% duty cycle

0.3

ns

t₅₈

t₅₉

t_±0

1.±±

0.±2

1.12

S/PDIF INPUT³

MCLK High Time

See Figure 19 and Figure 20

t_±1

0.45 × MCLK⁴

1.4

0.55 × MCLK⁴

% duty cycle

ns

MCLK Low Time

S/PDIF Data Setup Time

S/PDIF Data Hold Time

I²S PORT, SLAVE MODE³

SCLK High Time

t_±2

t_±3

1.38

See Figure 21

t_±4

0.45 × SCLK⁴

1.91

0.55 × SCLK⁴

% duty cycle

ns

SCLK Low Time

I²S Data Setup Time

I²S Data Hold Time

DSD PORT³

t_±5

t_±±

1.1

See Figure 2±

DSD_CLK High Time

DSD_CLK Low Time

DSD Data Setup Time

DSD Data Hold Time

EXTERNAL SYNC TIMING MODE³

REF_CLK High Time

REF_CLK Low Time

REF Data Setup Time

REF Data Hold Time

t_±7

0.45 × DSD_CLK⁴

1.±±

0.55 × DSD_CLK⁴% duty cycle

t_±8

t_±9

ns

1.44

See Figure 27

t₇₀

0.45 × REF_CLK⁴

1.35

0.55 × REF_CLK⁴

% duty cycle

t₇₁

t₇₂

ns

1.33

¹It is possible to run I²C at faster speeds; however, it has been characterized to run only in fast mode.

²All serial port measurements are for the default polarity and phase settings (clock low in idle state and negative edge used).

³All measurements are guaranteed by design only.

⁴Specification is in clock periods; for example, 1 × SCK2 periods.

Rev. 0 | Page 10 of 52

Data Sheet

ADV8005

Timing Diagrams

t₃

t₅

t₃

SDA

SCL

t₆

t₁

t₂

t₇

t₄

t₈

Figure 3. I²C Timing

t₁₃

t₉

t₁₁

t₁₂

t₁₀

SPI

CS2

SCK2

MODE CPOL CPHA

0

1

0

1

0

1

0

1

2

3

SCK2

INSTRUCTION (0x0B)

24-BIT ADDRESS

DUMMY BYTE

MOSI2

23 22 21 ...

3

2

1

0

7

6

5

4

3

2

1

0

DATA OUT 1

DATA OUT 2

MISO2

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Figure 4. Detailed SPI Master Timing Diagram (Serial Port 2)

t₁₄

t₁₇

t₁₈

t₁₅

t₁₆

SCK2

MOSI2

CS2

MISO2

(FALLING EDGE CAPTURE)

MISO2

(RISING EDGE CAPTURE)

Figure 5. Serial Port 2 Master Mode Timing (SPI Mode 0 and SPI Mode 3)

t₂₁

t₁₉

t₁₄

t₂₂

t₂₀

SCK2

MOSI2

CS2

MISO2

(RISING EDGE CAPTURE)

MISO2

(FALLING EDGE CAPTURE)

Figure 6. Serial Port 2 Master Mode Timing (SPI Mode 1 and SPI Mode 2)

Rev. 0 | Page 11 of 52

ADV8005

Data Sheet

t₂₇

t₂₃

t₂₄

t₂₅

t₂₆

CS1

SPI

MODE CPOL CPHA

0

1

2

3

0

1

0

1

0

1

SCK1

W/R

0

DEVICE ADDRESS

SUBADDRESS

DATA IN 0

DATA IN 1

MOSI1

7

6

5

4

3

2

1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

DUMMY BYTE

DATA OUT 0

DELAY MODE 1

MISO1

5

4

3

2

DATA OUT 0

DATA OUT 1

DELAY MODE 0

MISO1

7

6

5

4

3

2

1

0

5

4

3

2

Figure 7. Detailed SPI Slave Timing Diagram (Serial Port 1)

t₃₄

t₃₀

t₃₁

t₃₂

t₃₃

SCK1

MOSI1

MISO1

Figure 8. Serial Port 1 Slave Mode Timing (SPI Mode 0 and SPI Mode 3)

t₃₈

t₃₀

t₃₅

t₃₇

t₃₆

SCK1

MOSI1

MISO1

Figure 9. Serial Port 1 Slave Mode Timing (SPI Mode 1 and SPI Mode 2)

t₄₀

t₄₁

t₃₉

VBI_SCK

VBI_CS

VBI_MOSI

Figure 10. Serial Port 3 Slave Mode Timing (SPI Mode 0 Only)

Rev. 0 | Page 12 of 52

Data Sheet

ADV8005

t₄₃

t₄₂

SCK1

MISO2

MOSI1

CS1

SCK2

MISO1

MOSI2

CS2

Figure 11. SPI Passthrough Mode (Serial Port 1 and Serial Port 2)

t₄₄

t₄₅

t₄₆

PCLK

P[35] TO P[0]

HS

VS

DE

Figure 12. Main Video Input, Noninterleaved SDR Video Data and Control Timing

t₄₄

PCLK

t₄₇

t₄₆

t₄₈

t₄₅

P[35] TO P[0]

HS

VS

DE

Figure 13. Main Video Input, Noninterleaved DDR Video Data and Control Timing

t₄₄

PCLK

t₄₉

t₅₀

OSD_IN[11] TO OSD_IN[0]

P[35] TO P[24]

P[23] TO P[0]

HS

VS

DE

Figure 14. Interleaved SDR Video Data and Control Input Timing

t₅₁

OSD_CLK

t₅₂

t₅₃

OSD_IN[23] TO OSD_IN[0]

OSD_HS

OSD_VS

OSD_DE

Figure 15. External OSD Input, Noninterleaved SDR Video Data and Control Timing

Rev. 0 | Page 13 of 52

ADV8005

Data Sheet

t₅₁

OSD_CLK

t₅₄

t₅₃

t₅₅

t₅₂

OSD_IN[23] TO OSD_IN[0]

OSD_HS

OSD_VS

OSD_DE

Figure 16. External OSD Input, Noninterleaved DDR Video Data and Control Timing

t₅₆

OSD_CLK

t₅₇

t₅₈

OSD_IN[23] TO OSD_IN[0]

P[35] TO P[24]

OSD_HS

OSD_VS

OSD_DE

Figure 17. SDR Video Data and Control Output Timing (Data Launched on Falling Edge)

t₅₆

OSD_CLK

t₅₉

t₆₀

OSD_IN[23] TO OSD_IN[0]

P[35] TO P[24]

OSD_HS

OSD_VS

OSD_DE

Figure 18. SDR Video Data and Control Output Timing (Data Launched on Rising Edge)

t₆₁

MCLK

t₆₂

t₆₃

AUD_IN[0]

Figure 19. S/PDIF Input Timing, Data Latched on Rising Edge

SYNC IMPULSE

DATA

AUD_IN[0]

1.5 × t_MCLK

t_MCLK

0.5 × t_MCLK

Figure 20. S/PDIF Data Timing

Rev. 0 | Page 14 of 52

Data Sheet

ADV8005

t₆₄

SCLK

t₆₅

t₆₆

AUD_IN[4] TO AUD_IN[1]

AUD_IN[5]

Figure 21. I²S Timing

AUD_IN[5]

SCLK

LEFT

RIGHT

MSB

LEFT

MSB

RIGHT

LSB

AUD_IN[4] TO AUD_IN[1]

32 CLOCK SLOTS

2

I S STANDARD

2

I S FORMAT = 00

Figure 22. I²S Standard Audio—Data Width of 16 Bits to 24 Bits per Channel

AUD_IN[5]

SCLK

LEFT

RIGHT

AUD_IN[4] TO AUD_IN[1]

MSB

MSB – 1

LSB

MSB

MSB – 1

LSB

MSB

EXTENDED

MSB

EXTENDED

32 CLOCK SLOTS

SERIAL AUDIO

RIGHT JUSTIFIED

2

I S FORMAT = 01

Figure 23. Serial Audio—Right Justified

AUD_IN[5]

SCLK

LEFT

RIGHT

AUD_IN[4] TO AUD_IN[1]

MSB

LSB

MSB

LSB

32 CLOCK SLOTS

SERIAL AUDIO

LEFT JUSTIFIED

2

I S FORMAT = 10

Figure 24. Serial Audio—Left Justified

Rev. 0 | Page 15 of 52

ADV8005

Data Sheet

AUD_IN[5]

CHANNEL A

CHANNEL B

SCLK

AUD_IN[4] TO AUD_IN[1]

LSB

MSB

V

U

C

P

LSB

MSB

V

U

C

P

32 CLOCK SLOTS

FRAME n

FRAME n + 1

AES3 DIRECT AUDIO

2

I S FORMAT = 11

Figure 25. AES3 Direct Audio

t₆₇

DSD_CLK

t₆₈

t₆₉

AUD_IN[4] TO AUD_IN[1]

Figure 26. DSD Timing

t₇₀

REF_CLK

t₇₁

t₇₂

REF_HS

REF_VS

Figure 27. External Sync Timing

Rev. 0 | Page 1± of 52

Data Sheet

ADV8005

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter

Stresses at or above those listed under Absolute Maximum

Rating

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

AVDD1, ADDD2, DVDD_IO to GND

DVDD, PVDDx, CVDD1, AVDD3, AVDD4, 2.2 V

DVDD_DDR, PVDD_DDR to GND

3.9 V

DVDD to Other 1.8 V Power Supplies¹

PVDD1 to Other 1.8 V Power Supplies¹

PVDD2 to Other 1.8 V Power Supplies¹

PVDD3 to Other 1.8 V Power Supplies¹

PVDD5 to Other 1.8 V Power Supplies¹

PVDD6 to Other 1.8 V Power Supplies¹

CVDD1 to Other 1.8 V Power Supplies¹

AVDD3 to Other 1.8 V Power Supplies¹

AVDD4 to Other 1.8 V Power Supplies¹

−0.3 V to +0.3 V

ESD CAUTION

DVDD_DDR to Other 1.8 V Power

Supplies¹

PVDD_DDR to Other 1.8 V Power

Supplies¹

−0.3 V to +0.3 V

Digital Inputs to GND

Serial Video Inputs to GND

DDR_VREF to GND

DDR Inputs to GND

DDR Outputs to GND

5 V Tolerant Digital Inputs to GND²

1.8 V Analog Inputs to GND

3.3 V Analog Inputs to GND

HDMI Digital Outputs to GND

Digital Outputs Voltage to GND

Analog Outputs Voltage to GND³

−0.3 V to DVDD_IO + 0.3 V

−0.3 V to CVDD1 + 0.3 V

−0.3 V to DVDD_DDR + 0.3 V

−0.3 V to +5.5 V

−0.3 V to AVDD3 + 0.3 V

−0.3 V to AVDD2 + 0.3 V

−0.3 V to AVDD3 + 0.3 V

−0.3 V to DVDD_IO + 0.3 V

−0.3 V to AVDD2 + 0.3 V

125°C

Maximum Junction Temperature (T_{J MAX}

)

Storage Temperature Range

−65°C to +150°C

Infrared Reflow Soldering (20 sec)

260°C

¹This includes the 1.8 V power supplies (DVDD, PVDD1, PVDD2, PVDD3,

CVDD1, AVDD3, AVDD4, DVDD_DDR, and PVDD_DR) and the 1.845 V

supplies (PVDD5 and PVDD6).

²The following inputs are 5 V tolerant:, DDC1_SCL, DDC2_SCL, DDC1_SDA,

DDC2_SDA, HEAC_1−, HEAC_1+, HEAC_2−, HEAC_2+, RX_5V, and RX_HPD.

³Except the ELPF1 and ELPF2 outputs, which are kept to −0.3 V to PVDD3 +

0.3 V; the RTERM output, which is kept to −0.3 V to CVDD1 + 0.3 V; and the

R_TX1 and R_TX2 outputs, which are kept to −0.3 V to PVDD5 + 0.3 V.

Rev. 0 | Page 17 of 52

ADV8005

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

OSD_

IN[23]/

EXT_

OSD_

CLK/

EXT_

CLK

OSD_

DE

AUD_

IN[1]

AUD_ AUD_ ARC2_

MOSI1 SCK2

CS2 RESET XTALN PVDD2

CVDD1 RX_C– RX_0– RX_1– RX_2– CVDD1 RSET1 VREF

A

B

C

A

B

C

DNC

IN[2]

IN[5]

OUT

DIN[7]

OSD_

IN[21]/

EXT_

OSD_

IN[22]/

EXT_

OSD_

VS

AUD_

IN[0]

AUD_

IN[3]

ARC1_

OUT

SFL

MISO1 MOSI2 MISO2 ALSB XTALP PVDD1

GND RX_C+ RX_0+ RX_1+ RX_2+

RX_

GND COMP1 DAC4

DNC

DIN[5]

DIN[6]

OSD_

IN[19]/

EXT_

OSD_

IN[20]/

EXT_

AUD_

IN[4]

REF_

CLK

DSD_

CLK

GND

SCLK

MCLK

SCL

SDA

SCK1

CS1

GND

INT0

INT1

PDN

INT2

GND

AVDD1

GND

GND AVDD1 AVDD1 DAC5

DAC6

DAC2

HPD

DIN[3]

DIN[4]

OSD_

IN[16]/

EXT_

OSD_

IN[17]/

EXT_

OSD_

IN[18]/

EXT_

DVDD_

IO

DVDD_

IO

REF_

HS

REF_

VS

D

E

D

E

GND

TEST1

RX_5V

DNC

DNC RTERM AVDD2 AVDD2 DAC1

DIN[0]

DIN[1]

DIN[2]

OSD_

IN[13]/

VBI_SCK VBI_MOSI

OSD_

IN[14]/

OSD_

IN[15]/

VBI_CS

DVDD_

IO

TEST2

GND COMP2 DAC3

OSD_ OSD_

IN[9]

OSD_ OSD_

IN[10] IN[11]

IN[12]

RSET2 PVDD3 GND

DNC

F

G

H

F

G

H

OSD_ OSD_

ELPF1 ELPF2

GND AVDD3

GND

DVDD

GND

DVDD

GND

IN[5]

IN[6]

IN[7]

IN[8]

OSD_ OSD_

IN[3] IN[4]

GND

GND TX1_2+ TX1_2–

IN[1]

DE

IN[2]

HS

OSD_ OSD_

HS

IN[0]

DDC1_

SDA

DVDD

J

GND TX1_1+ TX1_1–

GND TX1_0+ TX1_0–

J

DVDD_ DVDD_

DDC1_

SCL

K

L

K

L

VS

PCLK

P[33]

P[29]

GND

IO

HPD_

TX1

DVDD

GND TX1_C+ TX1_C–

HEAC_ HEAC_

P[32]

P[28]

P[34]

P[35]

M

N

R_TX1 PVDD5

M

N

P[30]

P[26]

P[31]

P[27]

GND

DVDD

GND

DVDD

GND

1+

1–

DNC PVDD5 AVDD4 AVDD3

P[24]

P[25]

DDC2_

GND TX2_2+ TX2_2–

SCL

P

R

P[20]

P[16]

P[21]

P[17]

P[22]

P[18]

P[23]

P[19]

P

R

DDC2_

GND TX2_1+ TX2_1–

SDA

HPD_

GND

GND TX2_0+ TX2_0–

TX2

P[14]

P[10]

P[6]

P[15]

P[11]

P[7]

GND

P[12]

P[8]

GND

P[13]

P[9]

T

R_TX2

GND TX2_C+ TX2_C–

DVDD

GND DVDD

DVDD

U

V

U

V

HEAC_ HEAC_

GND PVDD6

2+

2–

W

AVDD4

P[2]

P[3]

P[4]

P[5]

TEST3 PVDD6 AVDD4

DDR_

CAS

DDR_

CK

DDR_

DQS[2]

DDR_

DQ[23]

DDR_

DQS[3]

DDR_

A[11]

DDR_

DQ[9]

DDR_

DQ[14]

DDR_

DQ[6]

DVDD_

DDR

DVDD_

DDR

DVDD_

DDR

DVDD_

DDR

PVDD_

DDR

Y

P[0]

P[1]

GND

A[4]

GND

DDR_

CS

DDR_

DQ[18]

DDR_

DQ[26]

DDR_

A[13]

DDR_

A[8]

DDR_

DQ[11]

DDR_ DDR_

DM[1] DM[0]

DDR_

DQ[3]

DVDD_

DDR

DVDD_ DDR_

DVDD_

DDR

AA

GND

A[2]

GND

DQS[2]

DDR DQS[3]

DDR

CK

DDR_

RAS

DDR_

DDR_ DDR_

DDR_

DDR_ DDR_

A[6]

DDR_ DDR_

DDR_

BA[0]

DDR_ DDR_

DDR_

DDR_ DDR_

DDR_

AB

AC

AB

AC

DQ[21] DQ[19] DQ[17] DM[2] DQ[30] DM[3] DQ[31] DQ[29] A[12]

A[3]

A[0]

CKE DQ[12] DQS[1] DQ[8] DQ[13] DQ[0] DQ[5] DQS[0] DQ[4]

DDR_

WE

DDR_

DDR_ DDR_

DDR_

DDR_ DDR_

BA[1] BA[2]

DDR_

DQ[10]

DDR_ DDR_

DQ[15] DQ[7] DQ[2]

DDR_

DQ[1]

DDR_

VREF

DQ[16] DQ[20] DQ[22] DQ[25] DQ[28] DQ[27] DQ[24] A[9]

A[5]

A[7]

A[1]

11

A[10]

12

DQS[1]

DQS[0]

1

2

3

4

5

6

7

8

9

10

13

14

15

16

17

18

19

20

21

22

23

Figure 28. ADV8005KBCZ-8A and ADV8005KBCZ-8N Pin Configuration

Table 5. ADV8005KBCZ-8A and ADV8005KBCZ-8N Pin Function Descriptions

Pin No. Mnemonic Type Description

External OSD Video Pixel Input Port 23 (OSD_IN[23]).

A1

OSD_IN[23]/EXT_DIN[7] OSD video input/

miscellaneous digital

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[7]).

A2

A3

OSD_DE

OSD_CLK/EXT_CLK

OSD video sync

Data Enable for the OSD Input Port.

Pixel Clock for the OSD Input Port (OSD_CLK).

Pixel Clock for External Video Data (EXT_CLK).

I²S0/DSD1 Audio Input.

I²S1/DSD2 Audio Input.

Left/Right Clock/DSD5 Audio Input.

Audio Return Channel for HDMI Tx2.

Master Output Slave Input (Serial Port 1). Serial Port 1 is used for OSD control.

Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Reset Pin.

A4

A5

A6

A7

A8

A9

A10

A11

AUD_IN[1]

AUD_IN[2]

AUD_IN[5]

ARC2_OUT

MOSI1

Audio input

Audio output

Serial port control

Miscellaneous digital

SCK2

CS2

RESET

Rev. 0 | Page 18 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

A12

XTALN

Miscellaneous 1.8 V

Analog¹

Crystal Output Pin. Leave this pin floating if a clock oscillator is used.

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

PVDD2

DNC

CVDD1

RX_C−

RX_0−

RX_1−

RX_2−

CVDD1

RSET1

Power

PLL Digital Supply Voltage (1.8 V).

Do Not Connect. Do not connect to this pin.

Comparator Supply Voltage (1.8 V).

Rx Clock Complement Input.

Rx Channel 0 Complement Input.

Rx Channel 1 Complement Input.

Rx Channel 2 Complement Input.

Comparator Supply Voltage (1.8 V).

Resistor Current Setting for DAC1, DAC2, and DAC3. Place the RSET1 resistor as close

as possible to the ADV8005.

Optional External Voltage Reference Input for DACx or Voltage Reference Output. Place

VREF voltage components as close as possible to the ADV8005.

External OSD Video Pixel Input Port 21 (OSD_IN[21]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[5]).

Not applicable

Power

Rx input

Power

Miscellaneous analog¹

A23

B1

VREF

Miscellaneous analog¹

OSD_IN[21]/EXT_DIN[5] OSD video input/

miscellaneous digital

B2

OSD_IN[22]/EXT_DIN[6] OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 22 (OSD_IN[22]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[6]).

B3

B4

B5

B6

OSD_VS

AUD_IN[0]

AUD_IN[3]

SFL

OSD video sync

Audio input

Vertical Sync for the OSD Input Port.

S/PDIF/DSD0 Audio Input.

I²S2/DSD3 Audio Input.

SFL

Subcarrier Frequency Lock Signal.

B7

B8

B9

B10

B11

ARC1_OUT

MISO1

MOSI2

MISO2

ALSB

Audio output

Serial port control

I²C control

Audio Return Channel for HDMI Tx1.

Master Input Slave Output (Serial Port 1). Serial Port 1 is used for OSD control.

Master Output Slave Input (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Master Input Slave Output (Serial Port 2). Serial Port 2 is used for the external flash ROM.

This pin sets the LSB of the I²C address. When the ALSB pin is set low, the I²C address is

0x18; when the ALSB pin is set high, the I²C address is 0x1A.

B12

XTALP

Miscellaneous 1.8 V

Analog¹

Input Pin for 27 MHz Crystal or an External 1.8 V, 27 MHz Clock Oscillator Source to

Clock the ADV8005.

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

C1

PVDD1

DNC

Power

PLL Analog Supply Voltage (1.8 V).

Do Not Connect. Do not connect to this pin.

Ground.

Rx Clock True Input.

Rx Channel 0 True Input.

Rx Channel 1 True Input.

Rx Channel 2 True Input.

Ground.

Not applicable

GND

Rx input

GND

RX_C+

RX_0+

RX_1+

RX_2+

GND

COMP1

DAC4

Miscellaneous analog¹

Analog video output

Compensation Pin. Connect a 2.2 nF capacitor from COMP1 to AVDD2.

Encoder DAC4 Output.

External OSD Video Pixel Input Port 19 (OSD_IN[19]).

OSD_IN[19]/EXT_DIN[3] OSD video input/

miscellaneous digital

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[3]).

C2

OSD_IN[20]/EXT_DIN[4] OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 20 (OSD_IN[20]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[4]).

C3

C4

C5

C6

C7

C8

C9

GND

Ground.

AUD_IN[4]

DSD_CLK

SCLK

SCL

SCK1

GND

Audio input

I²C control

Serial port control

GND

I²S3/DSD4 Audio Input.

DSD Audio Clock Input.

I²S Bit Clock Input.

I²C Clock Input. SCL is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.

Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control.

Ground.

C10

C11

C12

C13

INT0

PDN

GND

Miscellaneous digital

GND

Interrupt Pin 0. When the status bits change, this pin is triggered.

Power-Down. This pin controls the power state of the ADV8005.

Ground.

GND

Rev. 0 | Page 19 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

Description

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

D1

DNC

Not applicable

Digital input

Rx input

Power

GND

Power

Analog video output

Do Not Connect. Do not connect to this pin.

Reference Clock Input for the Master Timing Block.

Hot Plug Assert Signal Output for the Rx Input.

HDMI Rx Inputs Analog Supply (3.3 V).

Ground.

REF_CLK

RX_HPD

AVDD1

GND

Ground.

AVDD1

DAC5

HDMI Rx Inputs Analog Supply (3.3 V).

Encoder DAC5 Output.

Encoder DAC6 Output.

External OSD Video Pixel Input Port 16 (OSD_IN[16]).

DAC6

OSD_IN[16]/EXT_DIN[0] OSD video input/

miscellaneous digital

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[0]).

D2

D3

OSD_IN[17]/EXT_DIN[1] OSD video input/

miscellaneous digital

OSD_IN[18]/EXT_DIN[2] OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 17 (OSD_IN[17]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[1]).

External OSD Video Pixel Input Port 18 (OSD_IN[18]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[2]).

D4

D5

D6

D7

D8

D9

D10

GND

Power

Audio input

I²C control

Serial port control

GND

Ground.

Digital Interface Supply (3.3 V).

Master Clock for S/PDIF Input Audio.

I²C Data Input. SDA is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.

Chip Select (Serial Port 1). Serial Port 1 is used for OSD control.

Ground.

Interrupt Pin for HDMI Transmitter Outputs. When the status bits change, an interrupt

is generated on this pin.

DVDD_IO

MCLK

SDA

CS1

GND

INT1

Miscellaneous digital

D11

INT2

Miscellaneous digital

Interrupt Pin for HDMI Receiver Inputs. When the status bits change, an interrupt is

generated on this pin.

D12

D13

D14

D15

D16

D17

D18

D19

DVDD_IO

TEST1

REF_HS

REF_VS

RX_5V

DNC

Power

Digital Interface Supply (3.3 V).

Test Pin. Float this pin.

Miscellaneous digital

Digital input

Rx input

Not applicable

HDMI Rx input

Reference Horizontal Sync Input for the Master Timing Block.

Reference Vertical Sync Input for the Master Timing Block.

5 V Detect Pin for the Receiver Input.

Do Not Connect. Do not connect to this pin.

DNC

RTERM

This pin sets the internal termination resistance. Use a 500 Ω resistor between this pin

and GND. Place the RTERM resistor as close as possible to the ADV8005.

D20

D21

D22

D23

E1

AVDD2

DAC1

DAC2

Power

Analog video output

OSD video input/

Analog Power Supply (3.3 V).

Encoder DAC1 Output.

Encoder DAC2 Output.

External OSD Video Pixel Input Port 13 (OSD_IN[13]).

OSD_IN[13]/VBI_SCK

miscellaneous digital

Serial Clock for Video Blanking Interval (VBI) Data Serial Port 3 (VBI_SCK).

E2

E3

OSD_IN[14]/VBI_MOSI OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 14 (OSD_IN[14]).

Master Output Slave Input for VBI Data Serial Port 3 (VBI_MOSI).

External OSD Video Pixel Input Port 15 (OSD_IN[15]).

CS

OSD video input/

OSD_IN[15]/VBI_

miscellaneous digital

CS

Chip Select for VBI Data Serial Port 3(VBI_ ).

E4

DVDD_IO

TEST2

GND

COMP2

DAC3

OSD_IN[9]

OSD_IN[10]

OSD_IN[11]

OSD_IN[12]

Power

Miscellaneous analog

GND

Miscellaneous analog¹

Analog video output

OSD video input

Digital Interface Supply (3.3 V).

Test Pin. Float this pin.

Ground.

Compensation Pin. Connect a 2.2 nF capacitor to AVDD2.

Encoder DAC3 Output.

External OSD Video Pixel Input Port 9.

External OSD Video Pixel Input Port 10.

External OSD Video Pixel Input Port 11.

External OSD Video Pixel Input Port 12.

E20

E21

E22

E23

F1

F2

F3

F4

OSD video input/

miscellaneous digital

F20

F21

RSET2

Miscellaneous analog¹

Resistor Current Setting for DAC4, DAC5, and DAC6. Place the RSET2 resistor as close

as possible to the ADV8005.

PLL Supply (1.8 V).

Rev. 0 | Page 20 of 52

PVDD3

Power

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

F22

F23

G1

G2

G3

GND

DNC

GND

Ground.

Not applicable

OSD video input

GND

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 5.

External OSD Video Pixel Input Port 6.

External OSD Video Pixel Input Port 7.

External OSD Video Pixel Input Port 8.

Ground.

OSD_IN[5]

OSD_IN[6]

OSD_IN[7]

OSD_IN[8]

GND

G4

G7

G8

GND

Ground.

G9

GND

Ground.

G10

G11

G12

G13

G14

G15

G16

G17

G20

G21

G22

G23

H1

DVDD

GND

DVDD

GND

Power

GND

Power

GND

Digital Power Supply (1.8 V).

Ground.

Digital Power Supply (1.8 V).

Ground.

External Loop Filter for PLL 1. Connect to PVDD3.

External Loop Filter for PLL 2. Connect to PVDD3.

Ground.

HDMI Tx1 Analog Power Supply (1.8 V).

External OSD Video Pixel Input Port 1.

External OSD Video Pixel Input Port 2.

External OSD Video Pixel Input Port 3.

GND

ELPF1

ELPF2

GND

AVDD3

OSD_IN[1]

OSD_IN[2]

OSD_IN[3]

OSD_IN[4]

GND

Miscellaneous analog¹

GND

Power

OSD video input

GND

H2

H3

H4

H7

External OSD Video Pixel Input Port 4.

Ground.

H8

GND

Ground.

H9

GND

Ground.

H10

H11

H12

H13

H14

H15

H16

H17

H20

H21

H22

H23

J1

GND

TX1_2+

TX1_2−

DE

GND

Ground.

GND

Ground.

HDMI Tx1

Digital video sync

OSD video input

Power

HDMI1 Channel 2 True Output.

HDMI1 Channel 2 Complement Output.

Data Enable for Digital Input Video.

Horizontal Sync for Digital Input Video.

Horizontal Sync for the OSD Input Port.

External OSD Video Pixel Input Port 0.

Digital Power Supply (1.8 V).

Ground.

J2

J3

J4

J7

HS

OSD_HS

OSD_IN[0]

DVDD

GND

J8

GND

J9

GND

Ground.

J10

J11

J12

J13

J14

J15

J16

J17

GND

DVDD

GND

Power

Ground.

Digital Power Supply (1.8 V).

Rev. 0 | Page 21 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

Description

J20

DDC1_SDA

HDMI Tx1

HDCP Slave Serial Data for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to

connect this pin to the HDMI transmitter 5 V supply.

J21

J22

J23

K1

K2

K3

GND

Ground.

HDMI1 Channel 1 True Output.

HDMI1 Channel 1 Complement Output.

Vertical Sync for Digital Input Video.

Pixel Clock for Digital Input Video.

Digital Interface Supply (3.3 V).

Ground.

TX1_1+

TX1_1−

VS

HDMI Tx1

Digital video sync

Power

PCLK

DVDD_IO

GND

K4

K7

Power

GND

K8

GND

Ground.

K9

GND

Ground.

K10

K11

K12

K13

K14

K15

K16

K17

K20

GND

Ground.

DDC1_SCL

HDMI Tx1

HDCP Slave Serial Clock for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to

connect this pin to the HDMI transmitter 5 V supply.

K21

K22

K23

L1

L2

L3

L4

L7

L8

GND

Ground.

HDMI1 Channel 0 True Output.

HDMI1 Channel 0 Complement Output.

Digital Video Input 32 of Bus (P[35] to P[0]).

Digital Video Input 33 of Bus (P[35] to P[0]).

Digital Video Input 34 of Bus (P[35] to P[0]).

Digital Video Input 35 of Bus (P[35] to P[0]).

Digital Power Supply (1.8 V).

TX1_0+

TX1_0−

P[32]

P[33]

P[34]

P[35]

DVDD

GND

HDMI Tx1

Digital video input

Power

GND

Ground.

L9

GND

Ground.

L10

L11

L12

L13

L14

L15

L16

L17

L20

L21

L22

L23

M1

M2

M3

M4

M7

M8

M9

M10

M11

M12

M13

M14

GND

Ground.

HPD_TX1

GND

HDMI Tx1

GND

Hot Plug Assert Signal Input for HDMI Tx1.

Ground.

HDMI1 Clock True Output.

HDMI1 Clock Complement Output.

Digital Video Input 28 of Bus (P[35] to P[0]).

Digital Video Input 29 of Bus (P[35] to P[0]).

Digital Video Input 30 of Bus (P[35] to P[0]).

Digital Video Input 31 of Bus (P[35] to P[0]).

Ground.

TX1_C+

TX1_C−

P[28]

P[29]

P[30]

P[31]

GND

HDMI Tx1

Digital video input

GND

Rev. 0 | Page 22 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

Ground.

M15

M16

M17

M20

GND

R_TX1

GND

HDMI Tx1¹

Ground.

This pin sets the internal reference currents. Place a 470 Ω resistor (1% tolerance) between

this pin and ground, as close as possible to the ADV8005.

HDMI Transmitter PLL Power Supply (1.845 V).

HDMI Ethernet and Audio Channel Positive Tx1 from the HDMI Connector.

HDMI Ethernet and Audio Channel Negative Tx1 from the HDMI Connector.

Digital Video Input 24 of Bus (P[35] to P[0]).

Digital Video Input 25 of Bus (P[35] to P[0]).

Digital Video Input 26 of Bus (P[35] to P[0]).

Digital Video Input 27 of Bus (P[35] to P[0]).

M21

M22

M23

N1

N2

N3

PVDD5

HEAC_1+

HEAC_1−

P[24]

P[25]

P[26]

P[27]

GND

Power¹

HDMI Tx1

Digital video input

GND

N4

N7

Ground.

N8

GND

Ground.

N9

GND

Ground.

N10

N11

N12

N13

N14

N15

N16

N17

N20

N21

N22

N23

P1

GND

Ground.

DNC

Not applicable

Power¹

Power

Do Not Connect. Do not connect to this pin.

HDMI Transmitter PLL Power Supply (1.845 V).

HDMI Tx2 Analog Power Supply (1.8 V).

HDMI Tx1 Analog Power Supply (1.8 V).

Digital Video Input 20 of Bus (P[35] to P[0]).

Digital Video Input 21 of Bus (P[35] to P[0]).

Digital Video Input 22 of Bus (P[35] to P[0]).

Digital Video Input 23 of Bus (P[35] to P[0]).

PVDD5

AVDD4

AVDD3

P[20]

P[21]

P[22]

P[23]

DVDD

GND

Power

Digital video input

Power

P2

P3

P4

P7

Digital Power Supply (1.8 V).

Ground.

P8

GND

P9

GND

Ground.

P10

P11

P12

P13

P14

P15

P16

P17

P20

GND

DVDD

DDC2_SCL

GND

Power

Ground.

Digital Power Supply (1.8 V).

HDMI Tx2

HDCP Slave Serial Clock for HDMI Tx2. This pin is open drain; use a 2 kΩ resistor to

connect this pin to the HDMI transmitter 5 V supply.

P21

P22

P23

R1

R2

R3

GND

Ground.

TX2_2+

TX2_2−

P[16]

P[17]

P[18]

P[19]

GND

HDMI Tx2

Digital video input

GND

HDMI2 Channel 2 True Output.

HDMI2 Channel 2 Complement Output.

Digital Video Input 16 of Bus (P[35] to P[0]).

Digital Video Input 17 of Bus (P[35] to P[0]).

Digital Video Input 18 of Bus (P[35] to P[0]).

Digital Video Input 19 of Bus (P[35] to P[0]).

Ground.

R4

R7

R8

GND

Ground.

R9

GND

Ground.

R10

R11

GND

Ground.

Rev. 0 | Page 23 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

GND

HDMI Tx2

Description

Ground.

R12

R13

R14

R15

R16

R17

R20

GND

DDC2_SDA

HDCP Slave Serial Data for HDMI Tx2. This pin is open drain; use a 2 kΩ resistor to

connect this pin to the HDMI transmitter 5 V supply.

R21

R22

R23

T1

T2

T3

GND

Ground.

HDMI2 Channel 1 True Output.

HDMI2 Channel 1 Complement Output.

Digital Video Input 14 of Bus (P[35] to P[0]).

Digital Video Input 15 of Bus (P[35] to P[0]).

Ground.

TX2_1+

TX2_1−

P[14]

P[15]

GND

HDMI Tx2

Digital video input

GND

T4

GND

Ground.

T7

GND

Ground.

T8

GND

Ground.

T9

GND

Ground.

T10

T11

T12

T13

T14

T15

T16

T17

T20

T21

T22

T23

U1

GND

Ground.

HPD_TX2

GND

HDMI Tx2

GND

Hot Plug Assert Signal Input for HDMI Tx2.

Ground.

TX2_0+

TX2_0−

P[10]

P[11]

P[12]

P[13]

GND

HDMI Tx2

Digital video input

GND

HDMI2 Channel 0 True Output.

HDMI2 Channel 0 Complement Output.

Digital Video Input 10 of Bus (P[35] to P[0]).

Digital Video Input 11 of Bus (P[35] to P[0]).

Digital Video Input 12 of Bus (P[35] to P[0]).

Digital Video Input 13 of Bus (P[35] to P[0]).

Ground.

U2

U3

U4

U7

U8

GND

Ground.

U9

DVDD

GND

DVDD

GND

DVDD

GND

Power

GND

Power

GND

Power

GND

Digital Power Supply (1.8 V).

Ground.

Digital Power Supply (1.8 V).

Ground.

Digital Power Supply (1.8 V).

Ground.

This pin sets the internal reference currents. Place a 470 Ω resistor (1% tolerance)

between this pin and ground, as close as possible to the ADV8005.

U10

U11

U12

U13

U14

U15

U16

U17

U20

GND

HDMI Tx2¹

R_TX2

U21

U22

U23

V1

V2

V3

V4

V20

V21

GND

Ground.

HDMI2 Clock True Output.

TX2_C+

TX2_C−

P[6]

P[7]

P[8]

P[9]

GND

PVDD6

HDMI Tx2¹

HDMI2 Clock Complement Output.

Digital Video Input 6 of Bus (P[35] to P[0]).

Digital Video Input 7 of Bus (P[35] to P[0]).

Digital Video Input 8 of Bus (P[35] to P[0]).

Digital Video Input 9 of Bus (P[35] to P[0]).

Ground.

Digital video input

GND

Power¹

HDMI Transmitter PLL Power Supply (1.845 V).

Rev. 0 | Page 24 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

V22

V23

W1

W2

W3

HEAC_2+

HEAC_2−

P[2]

P[3]

P[4]

P[5]

TEST3

PVDD6

AVDD4

P[0]

P[1]

DDR_DQS[2]

GND

HDMI Tx2

HDMI Ethernet and Audio Channel Positive Tx2 from the HDMI Connector.

HDMI Ethernet and Audio Channel Negative Tx2 from the HDMI Connector.

Digital Video Input 2 of Bus (P[35] to P[0]).

Digital Video Input 3 of Bus (P[35] to P[0]).

Digital Video Input 4 of Bus (P[35] to P[0]).

Digital Video Input 5 of Bus (P[35] to P[0]).

Test Pin. Connect this pin to ground through a 0.1 μF capacitor.

HDMI Transmitter PLL Power Supply (1.845 V).

HDMI Tx2 Analog Power Supply (1.8 V).

Digital Video Input 0 of Bus (P[35] to P[0]).

Digital Video Input 1 of Bus (P[35] to P[0]).

Data Strobe for DDR Data Bytes[23:16], True.

Ground.

Digital video input

Miscellaneous digital

Power¹

Power

Digital video input

DDR interface

GND

W4

W20

W21

W22

W23

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

DDR_DQ[23]

DVDD_DDR

DDR_DQS[3]

GND

DDR interface

Power

DDR interface

GND

Data Line 23. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Strobe for DDR Data Bytes[31:24], True.

Ground.

Y9

DDR_A[11]

DVDD_DDR

DDR_A[4]

GND

DDR_CAS

DVDD_DDR

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

GND

DDR interface

GND

DDR interface

Power

DDR interface

Address Line 11. Interface to external RAM address lines.

DDR Interface Supply (1.8 V).

Address Line 4. Interface to external RAM address lines.

Ground.

Column Address Strobe for DDR Memory.

DDR Interface Supply (1.8 V).

DDR Memory Clock. Interface to external DDR RAM clock lines.

Ground.

Data Line 9. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Line 14. Interface to external RAM data lines.

Ground.

Data Line 6. Interface to external RAM data lines.

DDR Interface PLL Supply (1.8 V).

Ground.

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

CK

DDR_

GND

DDR_DQ[9]

DVDD_DDR

DDR_DQ[14]

GND

DDR_DQ[6]

PVDD_DDR

GND

DDR_DQ[18]

GND

DDR_DQS[2]

DDR_DQ[26]

DVDD_DDR

DDR_DQS[3]

DDR_A[13]

Data Line 18. Interface to external RAM data lines.

Ground.

Data Strobe for DDR Data Bytes[23:16], Complement.

Data Line 26. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Strobe for DDR Data Bytes[31:24], Complement.

Address Line 13. Interface to external RAM address lines. For designs that must

maintain consistency with the ADV8002 or the ADV8003, this pin can be grounded or

left unconnected.

AA9

DDR_A[8]

DVDD_DDR

DDR_A[2]

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

Address Line 8. Interface to external RAM address lines.

DDR Interface Supply (1.8 V).

Address Line 2. Interface to external RAM address lines.

Ground.

DDR Chip Select. Interface to external DDR RAM chip selects.

DDR Interface Supply (1.8 V).

DDR Memory Clock. Interface to external DDR RAM clock lines.

Ground.

Data Line 11. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Mask for Data Lines[15:8].

Data Mask for Data Lines[7:0].

Ground.

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

CS

DDR_

DVDD_DDR

DDR_CK

GND

DDR_DQ[11]

DVDD_DDR

DDR_DM[1]

DDR_DM[0]

GND

Rev. 0 | Page 25 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

Description

AA22

AA23

AB1

AB2

AB3

AB4

AB5

AB6

AB7

GND

Ground.

DDR_DQ[3]

DDR_DQ[21]

DDR_DQ[19]

DDR_DQ[17]

DDR_DM[2]

DDR_DQ[30]

DDR_DM[3]

DDR_DQ[31]

DDR_DQ[29]

DDR_A[12]

DDR_A[6]

DDR interface

DDR interface¹

DDR interface

Data Line 3. Interface to external RAM data lines.

Data Line 21. Interface to external RAM data lines.

Data Line 19. Interface to external RAM data lines.

Data Line 17. Interface to external RAM data lines.

Data Mask for Data Lines[23:16].

Data Line 30. Interface to external RAM data lines.

Data Mask for Data Lines[31: 24].

Data Line 31. Interface to external RAM data lines.

Data Line 29. Interface to external RAM data lines.

Address Line 12. Interface to external RAM address lines.

Address Line 6. Interface to external RAM address lines.

Address Line 3. Interface to external RAM address lines.

Address Line 0. Interface to external RAM address lines.

AB8

AB9

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

DDR_A[3]

DDR_A[0]

DDR_BA[0]

DDR_RAS

Bank Address Line 0. Indicates which data bank to write to/read from.

Row Address Strobe for DDR Memory.

DDR_CKE

Clock Enable for External DDR Memory.

Data Line 12. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[15:8], True.

Data Line 8. Interface to external RAM data lines.

Data Line 13. Interface to external RAM data lines.

Data Line 0. Interface to external RAM data lines.

Data Line 5. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[7:0], True.

Data Line 4. Interface to external RAM data lines.

Data Line 16. Interface to external RAM data lines.

Data Line 20. Interface to external RAM data lines.

Data Line 22. Interface to external RAM data lines.

Data Line 25. Interface to external RAM data lines.

Data Line 28. Interface to external RAM data lines.

Data Line 27. Interface to external RAM data lines.

Data Line 24. Interface to external RAM data lines.

Address Line 9. Interface to external RAM address lines.

Address Line 5. Interface to external RAM address lines.

Address Line 7. Interface to external RAM address lines.

Address Line 1. Interface to external RAM address lines.

Address Line 10. Interface to external RAM address lines.

Bank Address Line 1. Indicates which data bank to write to/read from.

Bank Address Line 2. Indicates which data bank to write to/read from.

Write Enable Signal for DDR RAM.

DDR_DQ[12]

DDR_DQS[1]

DDR_DQ[8]

DDR_DQ[13]

DDR_DQ[0]

DDR_DQ[5]

DDR_DQS[0]

DDR_DQ[4]

DDR_DQ[16]

DDR_DQ[20]

DDR_DQ[22]

DDR_DQ[25]

DDR_DQ[28]

DDR_DQ[27]

DDR_DQ[24]

DDR_A[9]

DDR_A[5]

DDR_A[7]

DDR_A[1]

DDR_A[10]

DDR_BA[1]

DDR_BA[2]

WE

DDR_

DDR_VREF

Reference Voltage for DDR RAM.

DDR_DQ[10]

DDR_DQS[1]

DDR_DQ[15]

DDR_DQ[7]

DDR_DQ[2]

DDR_DQS[0]

DDR_DQ[1]

Data Line 10. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[15:8], Complement.

Data Line 15. Interface to external RAM data lines.

Data Line 7. Interface to external RAM data lines.

Data Line 2. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[7:0], Complement.

Data Line 1. Interface to external RAM data lines.

¹Sensitive node. Careful layout is important. Keep the associated circuitry as close as possible to the ADV8005.

Rev. 0 | Page 26 of 52

Data Sheet

ADV8005

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

OSD_

IN[23]/

EXT_

OSD_

CLK/

EXT_

CLK

OSD_

DE

AUD_

IN[1]

AUD_ AUD_

TEST4 MOSI1 SCK2

CS2 RESET XTALN PVDD2

CVDD1 RX_C– RX_0– RX_1– RX_2– CVDD1

A

B

C

A

B

C

DNC

IN[2]

IN[5]

DIN[7]

OSD_

IN[21]/

EXT_

OSD_

IN[22]/

EXT_

OSD_

VS

AUD_

IN[0]

AUD_

IN[3]

ARC1_

SFL

MISO1 MOSI2 MISO2 ALSB XTALP PVDD1

GND RX_C+ RX_0+ RX_1+ RX_2+

RX_

GND AVDD1 AVDD1

GND

DNC

OUT

SCL

DIN[5]

DIN[6]

OSD_

IN[19]/

EXT_

OSD_

IN[20]/

EXT_

AUD_

IN[4]

DSD_

CLK

REF_

CLK

GND

SCLK

MCLK

SCK1

CS1

GND

INT0

INT1

PDN

INT2

GND

AVDD1

GND

HPD

DIN[3]

DIN[4]

OSD_

IN[16]/

EXT_

OSD_

IN[17]/

EXT_

OSD_

IN[18]/

EXT_

DVDD_

IO

DVDD_

IO

REF_

HS

REF_

VS

D

E

D

E

GND

SDA

TEST1

RX_5V DNC

DNC RTERM AVDD2 AVDD2

DNC

DIN[0]

DIN[1]

DIN[2]

OSD_

IN[13]/

VBI_SCK VBI_MOSI

OSD_

IN[14]/

OSD_

IN[15]/

VBI_CS

DVDD_

IO

TEST2

GND

OSD_ OSD_

IN[9]

OSD_ OSD_

IN[10] IN[11]

IN[12]

DNC

PVDD3 GND

DNC

F

G

H

F

G

H

OSD_ OSD_

ELPF1 ELPF2

GND AVDD3

GND

DVDD

GND

DVDD

GND

IN[5]

IN[6]

IN[7]

IN[8]

OSD_ OSD_

GND

GND TX1_2+ TX1_2–

IN[1]

DE

IN[2]

HS

IN[3]

IN[4]

OSD_

HS

OSD_

IN[0]

DDC1_

SDA

DVDD

J

GND TX1_1+ TX1_1–

GND TX1_0+ TX1_0–

DVDD_ DVDD_

DDC1_

SCL

K

L

K

L

VS

PCLK

P[33]

P[29]

GND

IO

HPD_

TX1

DVDD

GND TX1_C+ TX1_C–

HEAC_ HEAC_

P[32]

P[28]

P[34]

P[35]

M

N

R_TX1 PVDD5

M

N

P[30]

P[26]

P[31]

P[27]

GND

DVDD

GND

DVDD

GND

1+

1–

DNC

PVDD5 AVDD4 AVDD3

P[24]

P[25]

GND

DNC

P

R

P[20]

P[16]

P[21]

P[17]

P[22]

P[18]

P[23]

P[19]

P

R

GND

P[14]

P[10]

P[6]

P[15]

P[11]

P[7]

GND

P[12]

P[8]

GND

P[13]

P[9]

T

GND

DVDD

GND DVDD

DVDD

U

V

U

V

GND PVDD6 DNC

DNC

W

AVDD4

W

P[2]

P[3]

P[4]

P[5]

TEST3 PVDD6 AVDD4

DDR_

CAS

DDR_

CK

DDR_

DQS[2]

DDR_

DQ[23]

DDR_

DQS[3]

DDR_

A[11]

DDR_

DQ[9]

DDR_

DQ[14]

DDR_

DQ[6]

DVDD_

DDR

DVDD_

DDR

DVDD_

DDR

DVDD_

DDR

PVDD_

DDR

Y

P[0]

P[1]

GND

A[4]

GND

DDR_

CS

DDR_

DQ[18]

DDR_

DQ[26]

DDR_ DDR_

A[13] A[8]

DDR_

DQ[11]

DDR_ DDR_

DM[1] DM[0]

DDR_

DQ[3]

DVDD_

DDR

DVDD_ DDR_

DVDD_

DDR

AA

GND

A[2]

GND

DQS[2]

DDR DQS[3]

DDR

CK

DDR_

RAS

DDR_

DDR_ DDR_

DDR_

DDR_ DDR_

A[6]

DDR_ DDR_

DDR_

BA[0]

DDR_ DDR_

DDR_

DDR_ DDR_

DDR_

AB

AC

AB

AC

DQ[21] DQ[19] DQ[17] DM[2] DQ[30] DM[3] DQ[31] DQ[29] A[12]

A[3]

A[0]

CKE DQ[12] DQS[1] DQ[8] DQ[13] DQ[0] DQ[5] DQS[0] DQ[4]

DDR_

WE

DDR_

DDR_ DDR_

DDR_

DDR_ DDR_

BA[1] BA[2]

DDR_

DQ[10]

DDR_ DDR_

DQ[15] DQ[7] DQ[2]

DDR_

DQ[1]

DDR_

VREF

DQ[16] DQ[20] DQ[22] DQ[25] DQ[28] DQ[27] DQ[24] A[9]

A[5]

A[7]

A[1]

11

A[10]

12

DQS[1]

DQS[0]

1

2

3

4

5

6

7

8

9

10

13

14

15

16

17

18

19

20

21

22

23

Figure 29. ADV8005KBCZ-8B Pin Configuration

Table 6. ADV8005KBCZ-8B Pin Function Descriptions

Pin No. Mnemonic

Type

Description

A1

OSD_IN[23]/EXT_DIN[7]

OSD video input/

miscellaneous digital

OSD video sync

External OSD Video Pixel Input Port 23 (OSD_IN[23]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[7]).

Data Enable for the OSD Input Port.

Pixel Clock for the OSD Input Port (OSD_CLK).

Pixel Clock for External Video Data (EXT_CLK).

I²S0/DSD1 Audio Input.

I²S1/DSD2 Audio Input.

Left/Right Clock/DSD5 Audio Input.

Test Pin. Connect this pin to ground through a 4.7 kΩ resistor.

Master Output Slave Input (Serial Port 1). Serial Port 1 is used for OSD control.

Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Reset Pin.

A2

A3

OSD_DE

OSD_CLK/EXT_CLK

A4

A5

A6

A7

A8

A9

A10

A11

A12

AUD_IN[1]

AUD_IN[2]

AUD_IN[5]

TEST4

MOSI1

SCK2

Audio input

Miscellaneous digital

Serial port control

Miscellaneous digital

CS2

RESET

XTALN

Miscellaneous 1.8 V

Analog¹

Crystal Output Pin. Leave this pin floating if a clock oscillator is used.

A13

PVDD2

Power

PLL Digital Supply Voltage (1.8 V).

Rev. 0 | Page 27 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

Description

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

B1

DNC

CVDD1

RX_C−

RX_0−

RX_1−

RX_2−

CVDD1

Not applicable

Power

Rx input

Power

Not applicable

Do Not Connect. Do not connect to this pin.

Comparator Supply Voltage (1.8 V).

Rx Clock Complement Input.

Rx Channel 0 Complement Input.

Rx Channel 1 Complement Input.

Rx Channel 2 Complement Input.

Comparator Supply Voltage (1.8 V).

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 21 (OSD_IN[21]).

DNC

OSD_IN[21]/EXT_DIN[5]

OSD video input/

miscellaneous digital

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[5]).

B2

OSD_IN[22]/EXT_DIN[6]

OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 22 (OSD_IN[22]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[6]).

B3

B4

B5

B6

OSD_VS

AUD_IN[0]

AUD_IN[3]

SFL

OSD video sync

Audio input

Vertical Sync for the OSD Input Port.

S/PDIF/DSD0 Audio Input.

I²S2/DSD3 Audio Input.

SFL

Subcarrier Frequency Lock Signal.

B7

B8

B9

B10

B11

ARC1_OUT

MISO1

MOSI2

MISO2

ALSB

Audio output

Serial port control

I²C control

Audio Return Channel for HDMI Tx1.

Master Input Slave Output (Serial Port 1). Serial Port 1 is used for OSD control.

Master Output Slave Input (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Master Input Slave Output (Serial Port 2). Serial Port 2 is used for the external flash ROM.

This pin sets the LSB of the I²C address. When the ALSB pin is set low, the I²C address is

0x18; when the ALSB pin is set high, the I²C address is 0x1A.

B12

XTALP

Miscellaneous 1.8 V

Analog¹

Input Pin for 27 MHz Crystal or an External 1.8 V, 27 MHz Clock Oscillator Source to

Clock the ADV8005.

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

C1

PVDD1

DNC

GND

RX_C+

RX_0+

RX_1+

RX_2+

Power

PLL Analog Supply Voltage (1.8 V).

Do Not Connect. Do not connect to this pin.

Ground.

Rx Clock True Input.

Rx Channel 0 True Input.

Rx Channel 1 True Input.

Rx Channel 2 True Input.

Ground.

Not applicable

GND

Rx input

GND

Not applicable

GND

DNC

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 19 (OSD_IN[19]).

OSD_IN[19]/EXT_DIN[3]

OSD video input/

miscellaneous digital

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[3]).

C2

OSD_IN[20]/EXT_DIN[4]

OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 20 (OSD_IN[20]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[4]).

C3

C4

C5

C6

C7

GND

Ground.

AUD_IN[4]

DSD_CLK

SCLK

Audio input

I²C control

I²S3/DSD4 Audio Input.

DSD Audio Clock Input.

I²S Bit Clock Input.

SCL

I²C Clock Input. This pin is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V

supply.

C8

C9

SCK1

GND

Serial port control

GND

Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control.

Ground.

C10

C11

C12

C13

C14

C15

C16

C17

INT0

PDN

GND

Miscellaneous digital

GND

Interrupt Pin 0. When status bits change, this pin is triggered.

Power-Down. This pin controls the power state of the ADV8005.

Ground.

GND

Ground.

DNC

Not applicable

Digital input

Rx input

Do Not Connect. Do not connect to this pin.

Reference Clock Input for the Master Timing Block.

Hot Plug Assert Signal Output for the Rx Input.

HDMI Rx Inputs Analog Supply (3.3 V).

REF_CLK

RX_HPD

AVDD1

Power

Rev. 0 | Page 28 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

C18

C19

C20

C21

C22

C23

D1

GND

AVDD1

DNC

GND

Power

Not applicable

OSD video input/

Ground.

HDMI Rx Inputs, Analog Supply (3.3 V).

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 16 (OSD_IN[16]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[0]).

OSD_IN[16]/EXT_DIN[0]

miscellaneous digital

D2

D3

OSD_IN[17]/EXT_DIN[1]

OSD_IN[18]/EXT_DIN[2]

OSD video input/

miscellaneous digital

OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 17 (OSD_IN[17]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[1]).

External OSD Video Pixel Input Port 18 (OSD_IN[18]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[2]).

D4

D5

D6

D7

D8

D9

D10

GND

Power

Ground.

Digital Interface Supply (3.3 V).

MCLK for S/PDIF Input Audio.

I²C Data Input. SDA is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.

Chip Select (Serial Port 1). Serial Port 1 is used for OSD control.

Ground.

Interrupt Pin for HDMI Transmitter Outputs. When the status bits change, an interrupt

is generated on this pin.

DVDD_IO

MCLK

SDA

Audio input

I²C control

Serial port control

GND

Miscellaneous

digital

CS1

GND

INT1

D11

INT2

Miscellaneous

digital

Interrupt Pin for HDMI Receiver Inputs. When the status bits change, an interrupt is

generated on this pin.

D12

D13

DVDD_IO

TEST1

Power

Miscellaneous

digital

Digital Interface Supply (3.3 V).

Test Pin. Float this pin.

D14

D15

D16

D17

D18

D19

REF_HS

REF_VS

RX_5V

DNC

RTERM

Digital input

Rx input

Not applicable

HDMI Rx input

Reference Horizontal Sync Input for the Master Timing Block.

Reference Vertical Sync Input for the Master Timing Block.

5 V Detect Pin for the Rx Input.

Do Not Connect. Do not connect to this pin.

This pin sets the internal termination resistance. Use a 500 Ω resistor between this pin

and GND. Place the RTERM resistor as close as possible to the ADV8005.

D20

D21

D22

D23

E1

AVDD2

DNC

Power

Not applicable

OSD video input/

Analog Power Supply (3.3 V).

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 13 (OSD_IN[13]).

OSD_IN[13]/VBI_SCK

miscellaneous digital

Serial Clock for Video Blanking Interval (VBI) Data Serial Port 3 (VBI_SCK).

E2

E3

OSD_IN[14]/VBI_MOSI

OSD video input/

miscellaneous digital

OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 14 (OSD_IN[14]).

Master Output Slave Input for VBI Data Serial Port 3 (VBI_MOSI).

External OSD Video Pixel Input Port 15 (OSD_IN[15]).

CS

OSD_IN[15]/VBI_

CS

Chip Select for VBI Data Serial Port 3 (VBI_ ).

E4

DVDD_IO

TEST2

GND

DNC

OSD_IN[9]

OSD_IN[10]

OSD_IN[11]

OSD_IN[12]

Power

Digital Interface Supply (3.3 V).

E20

E21

E22

E23

F1

F2

F3

F4

Miscellaneous analog Test Pin. Float this pin.

GND

Ground.

Not applicable

OSD video input

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 9.

External OSD Video Pixel Input Port 10.

External OSD Video Pixel Input Port 11.

External OSD Video Pixel Input Port 12.

OSD video input/

miscellaneous digital

F20

F21

F22

F23

G1

DNC

PVDD3

GND

DNC

OSD_IN[5]

OSD_IN[6]

Not applicable

Power

GND

Not applicable

OSD video input

Do Not Connect. Do not connect to this pin.

PLL Supply (1.8 V).

Ground.

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 5.

External OSD Video Pixel Input Port 6.

Rev. 0 | Page 29 of 52

G2

ADV8005

Data Sheet

Pin No. Mnemonic

Type

Description

G3

G4

G7

OSD_IN[7]

OSD_IN[8]

GND

OSD video input

GND

External OSD Video Pixel Input Port 7.

External OSD Video Pixel Input Port 8.

Ground.

G8

GND

Ground.

G9

GND

Ground.

G10

G11

G12

G13

G14

G15

G16

G17

G20

DVDD

GND

DVDD

GND

ELPF1

Power

GND

Power

GND

Miscellaneous

analog¹

Digital Power Supply (1.8 V).

Ground.

Digital Power Supply (1.8 V).

Ground.

External Loop Filter for PLL 1. Connect to PVDD3.

G21

ELPF2

Miscellaneous

analog¹

External Loop Filter for PLL 2. Connect to PVDD3.

G22

G23

H1

H2

H3

GND

Power

Ground.

AVDD3

OSD_IN[1]

OSD_IN[2]

OSD_IN[3]

OSD_IN[4]

GND

HDMI Tx1 Analog Power Supply (1.8 V).

External OSD Video Pixel Input Port 1.

External OSD Video Pixel Input Port 2.

External OSD Video Pixel Input Port 3.

External OSD Video Pixel Input Port 4.

Ground.

OSD video input

GND

H4

H7

H8

GND

Ground.

H9

GND

Ground.

H10

H11

H12

H13

H14

H15

H16

H17

H20

H21

H22

H23

J1

GND

TX1_2+

TX1_2−

DE

GND

Ground.

GND

Ground.

HDMI Tx1

Digital video sync

OSD video input

Power

HDMI1 Channel 2 True Output.

HDMI1 Channel 2 Complement Output.

Data Enable for Digital Input Video.

Horizontal Sync for Digital Input Video.

Horizontal Sync for the OSD Input Port.

External OSD Video Pixel Input Port 0.

Digital Power Supply (1.8 V).

Ground.

J2

J3

J4

J7

HS

OSD_HS

OSD_IN[0]

DVDD

GND

J8

GND

J9

GND

Ground.

J10

J11

J12

J13

J14

J15

J16

J17

J20

GND

DVDD

DDC1_SDA

GND

Power

Ground.

Digital Power Supply (1.8 V).

HDMI Tx1

HDCP Slave Serial Data for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to

connect this pin to the HDMI transmitter 5 V supply.

J21

GND

Ground.

Rev. 0 | Page 30 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

J22

J23

K1

K2

K3

TX1_1+

TX1_1−

VS

HDMI Tx1

Digital video sync

Power

HDMI1 Channel 1 True Output.

HDMI1 Channel 1 Complement Output.

Vertical Sync for Digital Input Video.

Pixel Clock for Digital Input Video.

Digital Interface Supply (3.3 V).

Ground.

PCLK

DVDD_IO

GND

K4

K7

Power

GND

K8

GND

Ground.

K9

GND

Ground.

K10

K11

K12

K13

K14

K15

K16

K17

K20

GND

Ground.

DDC1_SCL

HDMI Tx1

HDCP Slave Serial Clock for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to

connect this pin to the HDMI transmitter 5 V supply.

K21

K22

K23

L1

L2

L3

L4

L7

L8

GND

HDMI Tx1

Digital video input

Power

Ground.

HDMI1 Channel 0 True Output.

HDMI1 Channel 0 Complement Output.

Digital Video Input 32 of Bus (P[35] to P[0]).

Digital Video Input 33 of Bus (P[35] to P[0]).

Digital Video Input 34 of Bus (P[35] to P[0]).

Digital Video Input 35 of Bus (P[35] to P[0]).

Digital Power Supply (1.8 V).

TX1_0+

TX1_0−

P[32]

P[33]

P[34]

P[35]

DVDD

GND

Ground.

L9

GND

Ground.

L10

L11

L12

L13

L14

L15

L16

L17

L20

L21

L22

L23

M1

M2

M3

M4

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

M17

GND

HDMI Tx1

GND

HDMI Tx1

Digital video input

GND

Ground.

HPD_TX1

GND

Hot Plug Assert Signal Input for HDMI Tx1.

Ground.

HDMI1 Clock True Output.

HDMI1 Clock Complement Output.

Digital Video Input 28 of Bus (P[35] to P[0]).

Digital Video Input 29 of Bus (P[35] to P[0]).

Digital Video Input 30 of Bus (P[35] to P[0]).

Digital Video Input 31 of Bus (P[35] to P[0]).

Ground.

TX1_C+

TX1_C−

P[28]

P[29]

P[30]

P[31]

GND

Rev. 0 | Page 31 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

HDMI Tx1¹

Description

M20

R_TX1

This pin sets the internal reference currents. Place a 470 Ω resistor (1% tolerance) between

this pin and ground, as close as possible to the ADV8005.

HDMI Transmitter PLL Power Supply (1.845 V).

Power¹

M21

M22

M23

N1

N2

N3

PVDD5

HEAC_1+

HEAC_1−

P[24]

P[25]

P[26]

P[27]

GND

HDMI Tx1

Digital video input

GND

HDMI Ethernet and Audio Channel Positive Tx1 from the HDMI Connector.

HDMI Ethernet and Audio Channel Negative Tx1 from the HDMI Connector.

Digital Video Input 24 of Bus (P[35] to P[0]).

Digital Video Input 25 of Bus (P[35] to P[0]).

Digital Video Input 26 of Bus (P[35] to P[0]).

Digital Video Input 27 of Bus (P[35] to P[0]).

Ground.

N4

N7

N8

GND

Ground.

N9

GND

Ground.

N10

N11

N12

N13

N14

N15

N16

N17

N20

N21

N22

N23

P1

GND

Ground.

DNC

Not applicable

Power¹

Do Not Connect. Do not connect to this pin.

HDMI Transmitter PLL Power Supply (1.845 V).

PVDD5

AVDD4

AVDD3

P[20]

P[21]

P[22]

P[23]

DVDD

GND

Power

HDMI Tx2 Analog Power Supply (1.8 V).

HDMI Tx1 Analog Power Supply (1.8 V).

Digital Video Input 20 of Bus (P[35] to P[0]).

Digital Video Input 21 of Bus (P[35] to P[0]).

Digital Video Input 22 of Bus (P[35] to P[0]).

Digital Video Input 23 of Bus (P[35] to P[0]).

Digital Power Supply (1.8 V).

Ground.

Digital video input

Power

P2

P3

P4

P7

P8

GND

P9

GND

Ground.

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

R1

R2

R3

R4

R7

R8

R9

GND

DVDD

DNC

GND

DNC

P[16]

P[17]

P[18]

P[19]

GND

Power

Ground.

Digital Power Supply (1.8 V).

Do Not Connect. Do not connect to this pin.

Ground.

Do Not Connect. Do not connect to this pin.

Digital Video Input 16 of Bus (P[35] to P[0]).

Digital Video Input 17 of Bus (P[35] to P[0]).

Digital Video Input 18 of Bus (P[35] to P[0]).

Digital Video Input 19 of Bus (P[35] to P[0]).

Ground.

Not applicable

GND

Not applicable

Digital video input

GND

R10

R11

R12

R13

R14

R15

GND

Rev. 0 | Page 32 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

R16

R17

R20

R21

R22

R23

T1

T2

T3

T4

T7

GND

DNC

GND

DNC

P[14]

P[15]

GND

DNC

GND

DNC

P[10]

P[11]

P[12]

P[13]

GND

DVDD

GND

DVDD

GND

DVDD

GND

DNC

GND

DNC

P[6]

GND

Not applicable

GND

Not applicable

Digital video input

GND

Not applicable

GND

Not applicable

Digital video input

GND

Power

GND

Ground.

Do Not Connect. Do not connect to this pin.

Ground.

Do Not Connect. Do not connect to this pin.

Digital Video Input 14 of Bus (P[35] to P[0]).

Digital Video Input 15 of Bus (P[35] to P[0]).

Ground.

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T20

T21

T22

T23

U1

U2

U3

U4

U7

U8

U9

U10

U11

U12

U13

U14

U15

U16

U17

U20

U21

U22

U23

V1

Do Not Connect. Do not connect to this pin.

Ground.

Do Not Connect. Do not connect to this pin.

Digital Video Input 10 of Bus (P[35] to P[0]).

Digital Video Input 11 of Bus (P[35] to P[0]).

Digital Video Input 12 of Bus (P[35] to P[0]).

Digital Video Input 13 of Bus (P[35] to P[0]).

Ground.

Digital Power Supply (1.8 V).

Ground.

Digital Power Supply (1.8 V).

Ground.

Digital Power Supply (1.8 V).

Ground.

Power

GND

Power

GND

Not applicable

GND

Ground.

Do Not Connect. Do not connect to this pin.

Ground.

Not applicable

Digital video input

GND

Do Not Connect. Do not connect to this pin.

Digital Video Input 6 of Bus (P[35] to P[0]).

Digital Video Input 7 of Bus (P[35] to P[0]).

Digital Video Input 8 of Bus (P[35] to P[0]).

Digital Video Input 9 of Bus (P[35] to P[0]).

Ground.

HDMI Transmitter PLL Power Supply (1.845 V).

Do Not Connect. Do not connect to this pin.

Digital Video Input 2 of Bus (P[35] to P[0]).

Digital Video Input 3 of Bus (P[35] to P[0]).

Digital Video Input 4 of Bus (P[35] to P[0]).

Digital Video Input 5 of Bus (P[35] to P[0]).

V2

V3

V4

P[7]

P[8]

P[9]

GND

PVDD6

DNC

P[2]

V20

V21

V22

V23

W1

W2

W3

W4

Power¹

Not applicable

Digital video input

P[3]

P[4]

P[5]

Rev. 0 | Page 33 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

Description

W20

W21

W22

W23

Y1

Y2

Y3

Y4

TEST3

PVDD6

Miscellaneous digital

Power¹

Test Pin. Connect this pin to ground through a 0.1 μF capacitor.

HDMI Transmitter PLL Power Supply (1.845 V).

HDMI Tx2 Analog Power Supply (1.8 V).

Digital Video Input 0 of Bus (P[35] to P[0]).

Digital Video Input 1 of Bus (P[35] to P[0]).

Data Strobe for DDR Data Bytes[23:16], True.

Ground.

AVDD4

P[0]

P[1]

DDR_DQS[2]

GND

Power

Digital video input

DDR interface

GND

Y5

Y6

Y7

Y8

DDR_DQ[23]

DVDD_DDR

DDR_DQS[3]

GND

DDR interface

Power

DDR interface

GND

Data Line 23. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Strobe for DDR Data Bytes[31:24], True.

Ground.

Y9

DDR_A[11]

DVDD_DDR

DDR_A[4]

GND

DDR_CAS

DVDD_DDR

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

GND

DDR interface

GND

DDR interface

Power

DDR interface

Address Line 11. Interface to external RAM address lines.

DDR Interface Supply (1.8 V).

Address Line 4. Interface to external RAM address lines.

Ground.

Column Address Strobe for DDR Memory.

DDR Interface Supply (1.8 V).

DDR Memory Clock. Interface to external DDR RAM clock lines.

Ground.

Data Line 9. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Line 14. Interface to external RAM data lines.

Ground.

Data Line 6. Interface to external RAM data lines.

DDR Interface PLL Supply (1.8 V).

Ground.

Data Line 18. Interface to external RAM data lines.

Ground.

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

CK

DDR_

GND

DDR_DQ[9]

DVDD_DDR

DDR_DQ[14]

GND

DDR_DQ[6]

PVDD_DDR

GND

DDR_DQ[18]

GND

DDR_DQS[2]

DDR_DQ[26]

DVDD_DDR

DDR_DQS[3]

DDR_A[13]

Ground.

Data Strobe for DDR Data Bytes[23:16], Complement.

Data Line 26. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Strobe for DDR Data Bytes[31:24], Complement.

Address Line 13. Interface to external RAM address lines. For designs that must

maintain consistency with the ADV8002 or the ADV8003, this pin can be grounded or

left unconnected.

AA9

DDR_A[8]

DVDD_DDR

DDR_A[2]

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

Address Line 8. Interface to external RAM address lines.

DDR Interface Supply (1.8 V).

Address Line 2. Interface to external RAM address lines.

Ground.

DDR Chip Select. Interface to external DDR RAM chip selects.

DDR Interface Supply (1.8 V).

DDR Memory Clock. Interface to external DDR RAM clock lines.

Ground.

Data Line 11. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Mask for Data Lines[15:8].

Data Mask for Data Lines[7:0].

Ground.

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AB1

CS

DDR_

DVDD_DDR

DDR_CK

GND

DDR_DQ[11]

DVDD_DDR

DDR_DM[1]

DDR_DM[0]

GND

Ground.

DDR_DQ[3]

DDR_DQ[21]

DDR_DQ[19]

DDR_DQ[17]

DDR_DM[2]

DDR interface

Data Line 3. Interface to external RAM data lines.

Data Line 21. Interface to external RAM data lines.

Data Line 19. Interface to external RAM data lines.

Data Line 17. Interface to external RAM data lines.

Data Mask for Data Lines[23:16].

AB2

AB3

AB4

Rev. 0 | Page 34 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

AB5

AB6

AB7

AB8

DDR_DQ[30]

DDR_DM[3]

DDR_DQ[31]

DDR_DQ[29]

DDR_A[12]

DDR_A[6]

DDR_A[3]

DDR_A[0]

DDR_BA[0]

DDR_RAS

DDR interface

Data Line 30. Interface to external RAM data lines.

Data Mask for Data Lines[31: 24].

Data Line 31. Interface to external RAM data lines.

Data Line 29. Interface to external RAM data lines.

Address Line 12. Interface to external RAM address lines.

Address Line 6. Interface to external RAM address lines.

Address Line 3. Interface to external RAM address lines.

Address Line 0. Interface to external RAM address lines.

Bank Address Line 0. Indicates which data bank to write to/read from.

Row Address Strobe for DDR Memory.

AB9

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

DDR_CKE

Clock Enable for External DDR Memory.

Data Line 12. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[15:8], True.

Data Line 8. Interface to external RAM data lines.

Data Line 13. Interface to external RAM data lines.

Data Line 0. Interface to external RAM data lines.

Data Line 5. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[7:0], True.

Data Line 4. Interface to external RAM data lines.

Data Line 16. Interface to external RAM data lines.

Data Line 20. Interface to external RAM data lines.

Data Line 22. Interface to external RAM data lines.

Data Line 25. Interface to external RAM data lines.

Data Line 28. Interface to external RAM data lines.

Data Line 27. Interface to external RAM data lines.

Data Line 24. Interface to external RAM data lines.

Address Line 9. Interface to external RAM address lines.

Address Line 5. Interface to external RAM address lines.

Address Line 7. Interface to external RAM address lines.

Address Line 1. Interface to external RAM address lines.

Address Line 10. Interface to external RAM address lines.

Bank Address Line 1. Indicates which data bank to write to/read from.

Bank Address Line 2. Indicates which data bank to write to/read from.

Write Enable Signal for DDR RAM.

DDR_DQ[12]

DDR_DQS[1]

DDR_DQ[8]

DDR_DQ[13]

DDR_DQ[0]

DDR_DQ[5]

DDR_DQS[0]

DDR_DQ[4]

DDR_DQ[16]

DDR_DQ[20]

DDR_DQ[22]

DDR_DQ[25]

DDR_DQ[28]

DDR_DQ[27]

DDR_DQ[24]

DDR_A[9]

DDR_A[5]

DDR_A[7]

DDR_A[1]

DDR_A[10]

DDR_BA[1]

DDR_BA[2]

WE

DDR_

DDR interface¹

DDR interface

DDR_VREF

Reference Voltage for DDR RAM.

DDR_DQ[10]

DDR_DQS[1]

DDR_DQ[15]

DDR_DQ[7]

DDR_DQ[2]

DDR_DQS[0]

DDR_DQ[1]

Data Line 10. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[15:8], Complement.

Data Line 15. Interface to external RAM data lines.

Data Line 7. Interface to external RAM data lines.

Data Line 2. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[7:0], Complement.

Data Line 1. Interface to external RAM data lines.

¹Sensitive node. Careful layout is important. Keep the associated circuitry as close as possible to the ADV8005.

Rev. 0 | Page 35 of 52

ADV8005

Data Sheet

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

OSD_

IN[23]/

EXT_

OSD_

CLK/

EXT_

CLK

AUD_

IN[1]

AUD_ AUD_ ARC2_

OSD_

DE

MOSI1 SCK2

CS2 RESET XTALN PVDD2

CVDD1 RX_C– RX_0– RX_1– RX_2– CVDD1

A

B

C

A

B

C

DNC

IN[2]

IN[5]

OUT

DIN[7]

OSD_

IN[21]/

EXT_

OSD_

IN[22]/

EXT_

OSD_

VS

AUD_

IN[0]

AUD_

IN[3]

ARC1_

OUT

SFL

MISO1 MOSI2 MISO2 ALSB XTALP PVDD1

GND RX_C+ RX_0+ RX_1+ RX_2+

RX_

GND

DNC

DIN[5]

DIN[6]

OSD_

IN[19]/

EXT_

OSD_

IN[20]/

EXT_

AUD_

IN[4]

DSD_

CLK

REF_

CLK

GND

SCLK

MCLK

SCL

SDA

SCK1

CS1

GND

INT0

INT1

PDN

INT2

GND

AVDD1

GND

GND AVDD1 AVDD1

HPD

DIN[3]

DIN[4]

OSD_

IN[16]/

EXT_

OSD_

IN[17]/

EXT_

OSD_

IN[18]/

EXT_

DVDD_

IO

DVDD_

IO

REF_

HS

REF_

VS

D

E

D

E

GND

TEST1

RX_5V

DNC

DNC RTERM AVDD2 AVDD2

DNC

DIN[0]

DIN[1]

DIN[2]

OSD_

IN[13]/

VBI_SCK VBI_MOSI

OSD_

IN[14]/

OSD_

IN[15]/

VBI_CS

DVDD_

IO

TEST2

GND

OSD_ OSD_

IN[9]

OSD_ OSD_

IN[10] IN[11]

IN[12]

DNC PVDD3 GND

DNC

F

G

H

F

G

H

OSD_ OSD_

ELPF1 ELPF2

GND AVDD3

GND

DVDD

GND

DVDD

GND

IN[5]

IN[6]

IN[7]

IN[8]

OSD_ OSD_

GND

GND TX1_2+ TX1_2–

IN[1]

DE

IN[2]

HS

IN[3]

IN[4]

OSD_

HS

OSD_

IN[0]

DDC1_

SDA

DVDD

J

GND TX1_1+ TX1_1–

GND TX1_0+ TX1_0–

DVDD_ DVDD_

DDC1_

SCL

K

L

K

L

VS

PCLK

P[33]

P[29]

GND

IO

HPD_

TX1

DVDD

GND TX1_C+ TX1_C–

HEAC_ HEAC_

P[32]

P[28]

P[34]

P[35]

M

N

R_TX1 PVDD5

M

N

P[30]

P[31]

GND

DVDD

GND

DVDD

GND

1+

1–

DNC

PVDD5 AVDD4 AVDD3

GND TX2_2+ TX2_2–

GND TX2_1+ TX2_1–

P[24]

P[20]

P[16]

P[25]

P[21]

P[17]

P[26]

P[22]

P[18]

P[27]

P[23]

P[19]

DDC2_

SCL

P

R

P

R

DDC2_

SDA

HPD_

TX2

GND

GND TX2_0+ TX2_0–

P[14]

P[10]

P[6]

P[15]

P[11]

P[7]

GND

P[12]

P[8]

GND

P[13]

P[9]

T

R_TX2

GND TX2_C+ TX2_C–

HEAC_ HEAC_

DVDD

GND DVDD

DVDD

U

V

U

V

GND PVDD6

2+

2–

W

AVDD4

W

P[2]

P[3]

P[4]

P[5]

TEST3 PVDD6 AVDD4

DDR_

CAS

DDR_

CK

DDR_

DQS[2]

DDR_

DQ[23]

DDR_

DQS[3]

DDR_

A[11]

DDR_

DQ[9]

DDR_

DQ[14]

DDR_

DQ[6]

DVDD_

DDR

DVDD_

DDR

DVDD_

DDR

DVDD_

DDR

PVDD_

DDR

Y

P[0]

P[1]

GND

A[4]

GND

DDR_

CS

DDR_

DQ[18]

DDR_

DQ[26]

DDR_ DDR_

A[13] A[8]

DDR_

DQ[11]

DDR_ DDR_

DM[1] DM[0]

DDR_

DQ[3]

DVDD_

DDR

DVDD_ DDR_

DVDD_

DDR

AA

GND

A[2]

GND

DQS[2]

DDR DQS[3]

DDR

CK

DDR_

RAS

DDR_

DDR_ DDR_

DDR_

DDR_ DDR_

A[6]

DDR_ DDR_

DDR_

BA[0]

DDR_ DDR_

DDR_

DDR_ DDR_

DDR_

AB

AC

AB

AC

DQ[21] DQ[19] DQ[17] DM[2] DQ[30] DM[3] DQ[31] DQ[29] A[12]

A[3]

A[0]

CKE DQ[12] DQS[1] DQ[8] DQ[13] DQ[0] DQ[5] DQS[0] DQ[4]

DDR_

WE

DDR_

DDR_ DDR_

DDR_

DDR_ DDR_

DDR_

DQ[10]

DDR_ DDR_

DQ[15] DQ[7] DQ[2]

DDR_

DQ[1]

DDR_

VREF

DQ[16] DQ[20] DQ[22] DQ[25] DQ[28] DQ[27] DQ[24] A[9]

A[5]

A[7]

A[1]

11

A[10]

12

BA[1]

BA[2]

DQS[1]

DQS[0]

1

2

3

4

5

6

7

8

9

10

13

14

15

16

17

18

19

20

21

22

23

Figure 30. ADV8005KBCZ-8C Pin Configuration

Table 7. ADV8005KBCZ-8C Pin Function Descriptions

Pin No. Mnemonic

Type

Description

External OSD Video Pixel Input Port 23 (OSD_IN[23]).

A1

OSD_IN[23]/EXT_DIN[7]

OSD video input/

miscellaneous digital

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[7]).

A2

A3

OSD_DE

OSD_CLK/EXT_CLK

OSD video sync

Data Enable for the OSD Input Port.

Pixel Clock for the OSD Input Port (OSD_CLK).

Pixel Clock for External Video Data (EXT_CLK).

I²S0/DSD1 Audio Input.

I²S1/DSD2 Audio Input.

Left/Right Clock/DSD5 Audio Input.

Audio Return Channel for HDMI Tx2.

Master Output Slave Input (Serial Port 1). Serial Port 1 is used for OSD control.

Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Reset Pin.

A4

A5

A6

A7

A8

A9

A10

A11

AUD_IN[1]

AUD_IN[2]

AUD_IN[5]

ARC2_OUT

MOSI1

Audio input

Audio output

Serial port control

Miscellaneous digital

SCK2

CS2

RESET

Rev. 0 | Page 36 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

A12

XTALN

Miscellaneous 1.8 V

Analog¹

Crystal Output Pin. Leave this pin floating if a clock oscillator is used.

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

B1

PVDD2

DNC

CVDD1

RX_C−

RX_0−

RX_1−

RX_2−

CVDD1

DNC

Power

PLL Digital Supply Voltage (1.8 V).

Not applicable

Power

Rx input

Power

Not applicable

Do Not Connect. Do not connect to this pin.

Comparator Supply Voltage (1.8 V).

Rx Clock Complement Input.

Rx Channel 0 Complement Input.

Rx Channel 1 Complement Input.

Rx Channel 2 Complement Input.

Comparator Supply Voltage (1.8 V).

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 21 (OSD_IN[21]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[5]).

OSD_IN[21]/EXT_DIN[5]

OSD video input/

miscellaneous digital

B2

OSD_IN[22]/EXT_DIN[6]

OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 22 (OSD_IN[22]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[6]).

B3

B4

B5

B6

B7

B8

B9

B10

B11

OSD_VS

AUD_IN[0]

AUD_IN[3]

SFL

ARC1_OUT

MISO1

MOSI2

MISO2

ALSB

OSD video sync

Audio input

Vertical Sync for the OSD Input Port.

S/PDIF/DSD0 Audio Input.

I²S2/DSD3 Audio Input.

SFL

Subcarrier Frequency Lock Signal.

Audio Return Channel for HDMI Tx1.

Audio output

Serial port control

I²C control

Master Input Slave Output (Serial Port 1). Serial Port 1 is used for OSD control.

Master Output Slave Input (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Master Input Slave Output (Serial Port 2). Serial Port 2 is used for the external flash ROM.

This pin sets the LSB of the I²C address. When the ALSB pin is set low, the I²C address

is 0x18; when the ALSB pin is set high, the I²C address is 0x1A.

B12

XTALP

Miscellaneous 1.8 V

Analog¹

Input Pin for 27 MHz Crystal or an External 1.8 V, 27 MHz Clock Oscillator Source to

Clock the ADV8005.

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

C1

PVDD1

DNC

GND

RX_C+

RX_0+

RX_1+

RX_2+

Power

PLL Analog Supply Voltage (1.8 V).

Do Not Connect. Do not connect to this pin.

Ground.

Rx Clock True Input.

Rx Channel 0 True Input.

Rx Channel 1 True Input.

Rx Channel 2 True Input.

Ground.

Not applicable

GND

Rx input

GND

Not applicable

GND

DNC

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 19 (OSD_IN[19]).

OSD_IN[19]/EXT_DIN[3]

OSD video input/

miscellaneous digital

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[3]).

C2

OSD_IN[20]/EXT_DIN[4]

OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 20 (OSD_IN[20]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[4]).

C3

C4

C5

C6

C7

C8

C9

GND

Ground.

AUD_IN[4]

DSD_CLK

SCLK

SCL

SCK1

Audio input

I²C control

Serial port control

GND

I²S3/DSD4 Audio Input.

DSD Audio Clock Input.

I²S Bit Clock Input.

I²C Clock Input. SCL is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.

Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control.

Ground.

GND

C10

C11

C12

C13

C14

C15

INT0

PDN

GND

DNC

REF_CLK

Miscellaneous digital

GND

Not applicable

Digital input

Interrupt Pin 0. When the status bits change, this pin is triggered.

Power-Down. This pin controls the power state of the ADV8005.

Ground.

Do Not Connect. Do not connect to this pin.

Reference Clock Input for the Master Timing Block.

Rev. 0 | Page 37 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

Description

C16

C17

C18

C19

C20

C21

C22

C23

D1

RX_HPD

AVDD1

GND

AVDD1

DNC

Rx input

Power

GND

Power

Not applicable

OSD video input/

miscellaneous digital

Hot Plug Assert Signal Output for the Rx Input.

HDMI Rx Inputs Analog Supply (3.3 V).

Ground.

HDMI Rx Inputs Analog Supply (3.3 V).

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 16 (OSD_IN[16]).

OSD_IN[16]/EXT_DIN[0]

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[0]).

D2

D3

OSD_IN[17]/EXT_DIN[1]

OSD_IN[18]/EXT_DIN[2]

OSD video input/

miscellaneous digital

OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 17 (OSD_IN[17]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[1]).

External OSD Video Pixel Input Port 18 (OSD_IN[18]).

Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[2]).

D4

D5

D6

D7

D8

D9

D10

GND

Power

Audio input

I²C control

Serial port control

GND

Ground.

Digital Interface Supply (3.3 V).

MCLK for S/PDIF Input Audio.

I²C Data Input. SDA is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.

Chip Select (Serial Port 1). Serial Port 1 is used for OSD control.

Ground.

Interrupt Pin for HDMI Transmitter Outputs. When the status bits change, an

interrupt is generated on this pin.

DVDD_IO

MCLK

SDA

CS1

GND

INT1

Miscellaneous digital

D11

INT2

Miscellaneous digital

Interrupt Pin for HDMI Receiver Inputs. When the status bits change, an interrupt is

generated on this pin.

D12

D13

D14

D15

D16

D17

D18

D19

DVDD_IO

TEST1

REF_HS

REF_VS

RX_5V

DNC

Power

Digital Interface Supply (3.3 V).

Test Pin. Float this pin.

Miscellaneous digital

Digital input

Rx input

Not applicable

HDMI Rx input

Reference Horizontal Sync Input for the Master Timing Block.

Reference Vertical Sync Input for the Master Timing Block.

5 V Detect Pin for the Rx Input.

Do Not Connect. Do not connect to this pin.

DNC

RTERM

This pin sets the internal termination resistance. Use a 500 Ω resistor between this pin

and GND. Place the RTERM resistor as close as possible to the ADV8005.

D20

D21

D22

D23

E1

AVDD2

DNC

Power

Not applicable

OSD video input/

Analog Power Supply (3.3 V).

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 13 (OSD_IN[13]).

OSD_IN[13]/VBI_SCK

miscellaneous digital

Serial Clock for Video Blanking Interval (VBI) Data Serial Port 3 (VBI_SCK).

E2

E3

OSD_IN[14]/VBI_MOSI

OSD video input/

miscellaneous digital

OSD video input/

miscellaneous digital

External OSD Video Pixel Input Port 14 (OSD_IN[14]).

Master Output Slave Input for VBI Data Serial Port 3 (VBI_MOSI).

External OSD Video Pixel Input Port 15 (OSD_IN[15]).

CS

OSD_IN[15]/VBI_

CS

Chip Select for VBI Data Serial Port 3 (VBI_ ).

E4

DVDD_IO

TEST2

GND

DNC

OSD_IN[9]

OSD_IN[10]

OSD_IN[11]

OSD_IN[12]

Power

Miscellaneous analog

GND

Not applicable

OSD video input

Digital Interface Supply (3.3 V).

Test Pin. Float this pin.

Ground.

Do Not Connect. Do not connect to this pin.

External OSD Video Pixel Input Port 9.

External OSD Video Pixel Input Port 10.

External OSD Video Pixel Input Port 11.

External OSD Video Pixel Input Port 12.

E20

E21

E22

E23

F1

F2

F3

F4

OSD video input/

miscellaneous digital

F20

F21

F22

F23

DNC

PVDD3

GND

Not applicable

Power

GND

Do Not Connect. Do not connect to this pin.

PLL Supply (1.8 V).

Ground.

DNC

Not applicable

Do Not Connect. Do not connect to this pin.

Rev. 0 | Page 38 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

G1

G2

G3

G4

OSD_IN[5]

OSD_IN[6]

OSD_IN[7]

OSD_IN[8]

GND

OSD video input

GND

External OSD Video Pixel Input Port 5.

External OSD Video Pixel Input Port 6.

External OSD Video Pixel Input Port 7.

External OSD Video Pixel Input Port.

G7

Ground.

G8

GND

Ground.

G9

GND

Ground.

G10

G11

G12

G13

G14

G15

G16

G17

G20

G21

G22

G23

H1

DVDD

GND

DVDD

GND

Power

GND

Power

GND

Miscellaneous analog¹

GND

Digital Power Supply (1.8 V).

Ground.

Digital Power Supply (1.8 V).

Ground.

GND

ELPF1

ELPF2

GND

AVDD3

OSD_IN[1]

OSD_IN[2]

OSD_IN[3]

OSD_IN[4]

GND

External Loop Filter for PLL 1. Connect to PVDD3.

External Loop Filter for PLL 2. Connect to PVDD3.

Ground.

Power

HDMI Tx1 Analog Power Supply (1.8 V).

External OSD Video Pixel Input Port 1.

External OSD Video Pixel Input Port 2.

External OSD Video Pixel Input Port 3.

External OSD Video Pixel Input Port 4.

Ground.

OSD video input

GND

H2

H3

H4

H7

H8

GND

Ground.

H9

GND

Ground.

H10

H11

H12

H13

H14

H15

H16

H17

H20

H21

H22

H23

J1

GND

TX1_2+

TX1_2−

DE

GND

Ground.

GND

Ground.

HDMI Tx1

Digital video sync

OSD video input

Power

HDMI1 Channel 2 True Output.

HDMI1 Channel 2 Complement Output.

Data Enable for Digital Input Video.

Horizontal Sync for Digital Input Video.

Horizontal Sync for the OSD Input Port.

External OSD Video Pixel Input Port.

Digital Power Supply (1.8 V).

Ground.

J2

J3

J4

J7

HS

OSD_HS

OSD_IN[0]

DVDD

GND

J8

GND

J9

GND

Ground.

J10

J11

J12

J13

J14

J15

J16

J17

J20

GND

DVDD

DDC1_SDA

GND

Power

Ground.

Digital Power Supply (1.8 V).

HDMI Tx1

HDCP Slave Serial Data for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to

connect this pin to the HDMI transmitter 5 V supply.

J21

GND

Ground.

Rev. 0 | Page 39 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

Description

J22

J23

K1

K2

K3

TX1_1+

TX1_1−

VS

HDMI Tx1

Digital video sync

Power

HDMI1 Channel 1 True Output.

HDMI1 Channel 1 Complement Output.

Vertical Sync for Digital Input Video.

Pixel Clock for Digital Input Video.

Digital Interface Supply (3.3 V).

Ground.

PCLK

DVDD_IO

GND

K4

K7

Power

GND

K8

GND

Ground.

K9

GND

Ground.

K10

K11

K12

K13

K14

K15

K16

K17

K20

GND

Ground.

DDC1_SCL

HDMI Tx1

HDCP Slave Serial Clock for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to

connect this pin to the HDMI transmitter 5 V supply.

K21

K22

K23

L1

L2

L3

L4

L7

L8

GND

HDMI Tx1

Digital video input

Power

Ground.

HDMI1 Channel 0 True Output.

HDMI1 Channel 0 Complement Output.

Digital Video Input 32 of Bus (P[35] to P[0]).

Digital Video Input 33 of Bus (P[35] to P[0]).

Digital Video Input 34 of Bus (P[35] to P[0]).

Digital Video Input 35 of Bus (P[35] to P[0]).

Digital Power Supply (1.8 V).

TX1_0+

TX1_0−

P[32]

P[33]

P[34]

P[35]

DVDD

GND

Ground.

L9

GND

Ground.

L10

L11

L12

L13

L14

L15

L16

L17

L20

L21

L22

L23

M1

M2

M3

M4

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

M17

GND

HDMI Tx1

GND

HDMI Tx1

Digital video input

GND

Ground.

HPD_TX1

GND

Hot Plug Assert Signal Input for HDMI Tx1.

Ground.

HDMI1 Clock True Output.

HDMI1 Clock Complement Output.

Digital Video Input 28 of Bus (P[35] to P[0]).

Digital Video Input 29 of Bus (P[35] to P[0]).

Digital Video Input 30 of Bus (P[35] to P[0]).

Digital Video Input 31 of Bus (P[35] to P[0]).

Ground.

TX1_C+

TX1_C−

P[28]

P[29]

P[30]

P[31]

GND

Rev. 0 | Page 40 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

HDMI Tx1¹

Description

M20

R_TX1

This pin sets the internal reference currents. Place a 470 Ω resistor (1% tolerance) between

this pin and ground, as close as possible to the ADV8005.

HDMI Tx PLL Power Supply (1.845 V).

Power¹

M21

M22

M23

N1

N2

N3

PVDD5

HEAC_1+

HEAC_1−

P[24]

P[25]

P[26]

P[27]

GND

HDMI Tx1

Digital video input

GND

HDMI Ethernet and Audio Channel Positive Tx1 from the HDMI Connector.

HDMI Ethernet and Audio Channel Negative Tx1 from the HDMI Connector.

Digital Video Input 24 of Bus (P[35] to P[0]).

Digital Video Input 25 of Bus (P[35] to P[0]).

Digital Video Input 26 of Bus (P[35] to P[0]).

Digital Video Input 27 of Bus (P[35] to P[0]).

Ground.

N4

N7

N8

GND

Ground.

N9

GND

Ground.

N10

N11

N12

N13

N14

N15

N16

N17

N20

N21

N22

N23

P1

GND

Ground.

DNC

Not applicable

Power¹

Do Not Connect. Do not connect to this pin.

HDMI Transmitter PLL Power Supply (1.845 V).

PVDD5

AVDD4

AVDD3

P[20]

P[21]

P[22]

P[23]

DVDD

GND

Power

HDMI Tx2 Analog Power Supply (1.8 V).

HDMI Tx1 Analog Power Supply (1.8 V).

Digital Video Input 20 of Bus (P[35] to P[0]).

Digital Video Input 21 of Bus (P[35] to P[0]).

Digital Video Input 22 of Bus (P[35] to P[0]).

Digital Video Input 23 of Bus (P[35] to P[0]).

Digital Power Supply (1.8 V).

Ground.

Digital video input

Power

P2

P3

P4

P7

P8

GND

P9

GND

Ground.

P10

P11

P12

P13

P14

P15

P16

P17

P20

GND

DVDD

DDC2_SCL

GND

Power

Ground.

Digital Power Supply (1.8 V).

HDMI Tx2

HDCP Slave Serial Clock for HDMI Tx2. This pin is open drain; use a 2 kΩ resistor to

connect this pin to the HDMI transmitter 5 V supply.

P21

P22

P23

R1

R2

R3

R4

R7

R8

R9

R10

R11

R12

R13

R14

GND

Ground.

HDMI2 Channel 2 True Output.

HDMI2 Channel 2 Complement Output.

Digital Video Input 16 of Bus (P[35] to P[0]).

Digital Video Input 17 of Bus (P[35] to P[0]).

Digital Video Input 18 of Bus (P[35] to P[0]).

Digital Video Input 19 of Bus (P[35] to P[0]).

Ground.

TX2_2+

TX2_2−

P[16]

P[17]

P[18]

P[19]

GND

HDMI Tx2

Digital video input

GND

Rev. 0 | Page 41 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

Description

Ground.

R15

R16

R17

R20

GND

DDC2_SDA

GND

HDMI Tx2

Ground.

HDCP Slave Serial Data for HDMI Tx2. This pin is open drain; use a 2 kΩ resistor to

connect this pin to the HDMI transmitter 5 V supply.

R21

R22

R23

T1

T2

T3

GND

Ground.

HDMI2 Channel 1 True Output.

HDMI2 Channel 1 Complement Output.

Digital Video Input 14 of Bus (P[35] to P[0]).

Digital Video Input 15 of Bus (P[35] to P[0]).

Ground.

TX2_1+

TX2_1−

P[14]

P[15]

GND

HDMI Tx2

Digital video input

GND

T4

GND

Ground.

T7

GND

Ground.

T8

GND

Ground.

T9

GND

Ground.

T10

T11

T12

T13

T14

T15

T16

T17

T20

T21

T22

T23

U1

GND

Ground.

HPD_TX2

GND

HDMI Tx2

GND

Hot Plug Assert Signal Input for HDMI Tx2.

Ground.

TX2_0+

TX2_0−

P[10]

P[11]

P[12]

P[13]

GND

HDMI Tx2

Digital video input

GND

HDMI2 Channel 0 True Output.

HDMI2 Channel 0 Complement Output.

Digital Video Input 10 of Bus (P[35] to P[0]).

Digital Video Input 11 of Bus (P[35] to P[0]).

Digital Video Input 12 of Bus (P[35] to P[0]).

Digital Video Input 13 of Bus (P[35] to P[0]).

Ground.

U2

U3

U4

U7

U8

GND

Ground.

U9

DVDD

GND

DVDD

GND

DVDD

GND

Power

GND

Power

GND

Power

GND

Digital Power Supply (1.8 V).

Ground.

Digital Power Supply (1.8 V).

Ground.

Digital Power Supply (1.8 V).

Ground.

This pin sets the internal reference currents. Place a 470 Ω resistor (1% tolerance)

between this pin and ground, as close as possible to the ADV8005.

U10

U11

U12

U13

U14

U15

U16

U17

U20

GND

HDMI Tx2¹

R_TX2

U21

U22

U23

V1

V2

V3

GND

HDMI Tx2

Ground.

HDMI2 Clock True Output.

HDMI2 Clock Complement Output.

TX2_C+

TX2_C−

P[6]

P[7]

P[8]

P[9]

GND

PVDD6

HEAC_2+

HEAC_2−

P[2]

Digital video input

GND

Digital Video Input 6 of Bus (P[35] to P[0]).

Digital Video Input 7 of Bus (P[35] to P[0]).

Digital Video Input 8 of Bus (P[35] to P[0]).

Digital Video Input 9 of Bus (P[35] to P[0]).

Ground.

HDMI Transmitter PLL Power Supply (1.8 V).

HDMI Ethernet and Audio Channel Positive Tx2 from the HDMI Connector.

HDMI Ethernet and Audio Channel Negative Tx2 from the HDMI Connector.

Digital Video Input 2 of Bus (P[35] to P[0]).

V4

V20

V21

V22

V23

W1

Power¹

HDMI Tx2

Digital video input

Rev. 0 | Page 42 of 52

Data Sheet

ADV8005

Pin No. Mnemonic

Type

Description

W2

W3

W4

W20

W21

W22

W23

Y1

P[3]

P[4]

P[5]

TEST3

Digital video input

Miscellaneous digital

Power¹

Digital Video Input 3 of Bus (P[35] to P[0]).

Digital Video Input 4 of Bus (P[35] to P[0]).

Digital Video Input 5 of Bus (P[35] to P[0]).

Test Pin. Connect this pin to ground through a 0.1 μF capacitor.

HDMI Transmitter PLL Power Supply (1.845 V).

HDMI Tx2 Analog Power Supply (1.8 V).

Digital Video Input 0 of Bus (P[35] to P[0]).

Digital Video Input 1 of Bus (P[35] to P[0]).

Data Strobe for DDR Data Bytes[23:16], True.

Ground.

PVDD6

AVDD4

P[0]

P[1]

DDR_DQS[2]

GND

Power

Digital video input

DDR interface

GND

Y2

Y3

Y4

Y5

Y6

Y7

Y8

DDR_DQ[23]

DVDD_DDR

DDR_DQS[3]

GND

DDR interface

Power

DDR interface

GND

Data Line 23. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Strobe for DDR Data Bytes[31:24], True.

Ground.

Y9

DDR_A[11]

DVDD_DDR

DDR_A[4]

GND

DDR_CAS

DVDD_DDR

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

GND

DDR interface

GND

DDR interface

Power

DDR interface

Address Line 11. Interface to external RAM address lines.

DDR Interface Supply (1.8 V).

Address Line 4. Interface to external RAM address lines.

Ground.

Column Address Strobe for DDR Memory.

DDR Interface Supply (1.8 V).

DDR Memory Clock. Interface to external DDR RAM clock lines.

Ground.

Data Line 9. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Line 14. Interface to external RAM data lines.

Ground.

Data Line 6. Interface to external RAM data lines.

DDR Interface PLL Supply (1.8 V).

Ground.

Data Line 18. Interface to external RAM data lines.

Ground.

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

CK

DDR_

GND

DDR_DQ[9]

DVDD_DDR

DDR_DQ[14]

GND

DDR_DQ[6]

PVDD_DDR

GND

DDR_DQ[18]

GND

DDR_DQS[2]

DDR_DQ[26]

DVDD_DDR

DDR_DQS[3]

DDR_A[13]

Ground.

Data Strobe for DDR Data Bytes[23:16], Complement.

Data Line 26. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Strobe for DDR Data Bytes[31:24], Complement.

Address Line 13. Interface to external RAM address lines. For designs that must

maintain consistency with the ADV8002 or the ADV8003, this pin can be grounded or

left unconnected.

AA9

DDR_A[8]

DVDD_DDR

DDR_A[2]

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Address Line 8. Interface to external RAM address lines.

DDR Interface Supply (1.8 V).

Address Line 2. Interface to external RAM address lines.

Ground.

DDR Chip Select. Interface to external DDR RAM chip selects.

DDR Interface Supply (1.8 V).

DDR Memory Clock. Interface to external DDR RAM clock lines.

Ground.

Data Line 11. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Mask for Data Lines[15:8].

Data Mask for Data Lines[7:0].

Ground.

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AB1

CS

DDR_

DVDD_DDR

DDR_CK

GND

DDR_DQ[11]

DVDD_DDR

DDR_DM[1]

DDR_DM[0]

GND

DDR_DQ[3]

DDR_DQ[21]

Ground.

Data Line 3. Interface to external RAM data lines.

Data Line 21. Interface to external RAM data lines.

Rev. 0 | Page 43 of 52

ADV8005

Data Sheet

Pin No. Mnemonic

Type

Description

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

DDR_DQ[19]

DDR_DQ[17]

DDR_DM[2]

DDR_DQ[30]

DDR_DM[3]

DDR_DQ[31]

DDR_DQ[29]

DDR_A[12]

DDR_A[6]

DDR_A[3]

DDR_A[0]

DDR_BA[0]

DDR_RAS

DDR interface

Data Line 19. Interface to external RAM data lines.

Data Line 17. Interface to external RAM data lines.

Data Mask for Data Lines[23:16].

Data Line 30. Interface to external RAM data lines.

Data Mask for Data Lines[31:24].

Data Line 31. Interface to external RAM data lines.

Data Line 29. Interface to external RAM data lines.

Address Line 12. Interface to external RAM address lines.

Address Line 6. Interface to external RAM address lines.

Address Line 3. Interface to external RAM address lines.

Address Line 0. Interface to external RAM address lines.

Bank Address Line 0. Indicates which data bank to write to/read from.

Row Address Strobe for DDR Memory.

DDR_CKE

Clock Enable for External DDR Memory.

Data Line 12. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[15:8], True.

Data Line 8. Interface to external RAM data lines.

Data Line 13. Interface to external RAM data lines.

Data Line 0. Interface to external RAM data lines.

Data Line 5. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[7:0], True.

Data Line 4. Interface to external RAM data lines.

Data Line 16. Interface to external RAM data lines.

Data Line 20. Interface to external RAM data lines.

Data Line 22. Interface to external RAM data lines.

Data Line 25. Interface to external RAM data lines.

Data Line 28. Interface to external RAM data lines.

Data Line 27. Interface to external RAM data lines.

Data Line 24. Interface to external RAM data lines.

Address Line 9. Interface to external RAM address lines.

Address Line 5. Interface to external RAM address lines.

Address Line 7. Interface to external RAM address lines.

Address Line 1. Interface to external RAM address lines.

Address Line 10. Interface to external RAM address lines.

Bank Address Line 1. Indicates which data bank to write to/read from.

Bank Address Line 2. Indicates which data bank to write to/read from.

Write Enable Signal for DDR RAM.

DDR_DQ[12]

DDR_DQS[1]

DDR_DQ[8]

DDR_DQ[13]

DDR_DQ[0]

DDR_DQ[5]

DDR_DQS[0]

DDR_DQ[4]

DDR_DQ[16]

DDR_DQ[20]

DDR_DQ[22]

DDR_DQ[25]

DDR_DQ[28]

DDR_DQ[27]

DDR_DQ[24]

DDR_A[9]

DDR_A[5]

DDR_A[7]

DDR_A[1]

DDR_A[10]

DDR_BA[1]

DDR_BA[2]

WE

DDR_

DDR interface¹

DDR interface

DDR_VREF

Reference Voltage for DDR RAM.

DDR_DQ[10]

DDR_DQS[1]

DDR_DQ[15]

DDR_DQ[7]

DDR_DQ[2]

DDR_DQS[0]

DDR_DQ[1]

Data Line 10. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[15:8], Complement.

Data Line 15. Interface to external RAM data lines.

Data Line 7. Interface to external RAM data lines.

Data Line 2. Interface to external RAM data lines.

Data Strobe for DDR Data Bytes[7:0], Complement.

Data Line 1. Interface to external RAM data lines.

¹Sensitive node. Careful layout is important. Keep the associated circuitry as close as possible to the ADV8005.

Rev. 0 | Page 44 of 52

Data Sheet

ADV8005

THEORY OF OPERATION

VIDEO INPUT

PROFESSIONAL CONFIGURATION

To accommodate professional applications where HDMI and

analog video output are not desired, the ADV8005 offers a 30-bit

TTL input, 30-bit TTL output mode. This mode suits applications

where a video signal processor is required between two TTL

interfaces (for example, an HDMI receiver and an FPGA).

4-BIT VBI

8-BIT

24-BIT

VIDEO

CCIR 656

12-BIT

VIDEO

CORE

48-BIT

VIDEO

EXTERNAL SYNC MODE

To alleviate the challenges involved in synchronizing multiple

video streams, the ADV8005 supports an external sync mode.

In this mode, an external sync (VS and/or HS) is applied to

the ADV8005. The video outputs from the ADV8005 then acts

as a slave to the master sync timing. The ADV8005 can also

synchronize two inputs to externally applied reference sync

signals. An externally applied master sync signal (VS and/or

HS) is. Using this external sync mode, it is possible to

synchronize multiple ADV8005 output video streams to an

external sync input.

SERIAL VIDEO

RECEIVER

Figure 31. Digital Video Interface

The ADV8005 can receive data via the 48-bit input pixel port,

the 24-bit OSD input port, or from the output of an HDMI

transmitter.

The 48-bit input pixel port can receive data from an upstream

analog/HDMI front-end device such as the ADV7619. This bus

can accept multiple input formats in both RGB and YPrPb color

spaces. Single data rate (SDR) and double data rate (DDR) input

formats are supported.

FLEXIBLE DIGITAL CORE

The ADV8005 has a flexible digital core that enables many

different configurations of single, dual, and triple video

processing paths. Video processing can be placed first in the

signal chain to ensure that all outputs are processed to the highest

quality. OSD can be placed at numerous locations within the signal

chain to vary the number of outputs on which the OSD is

displayed. PiP can also be supported via the OSD block, using a

pixel port input that is connected to the OSD block. Several

modes of operation are defined to help the user quickly integrate

the ADV8005 into a system.

The 24-bit input pixel port can also receive video data from an

upstream analog/HDMI front-end device such as the ADV7844

or OSD data from an external OSD generator. This bus can accept

multiple input formats up to UXGA. SDR and DDR input

formats are supported. The video input on the 24-bit pixel port

can be scaled and overlaid onto the main video path.

The serial video receiver can accept the output of an HDMI

transmitter such as the ADV7850 or ADV7623. Using this

configuration, the front-end device can extract HDMI audio for

processing before reinserting the audio into the ADV8005 via

the audio pins, for output through the HDMI transmitters.

Audio can also be passed through the serial video link from the

HDMI transmitter. This input, however, does not support EDID

or HDCP operations.

VIDEO SIGNAL PROCESSOR (VSP)

LOW ANGLE

DETAIL

PROCESSING

ENHANCE

CADENCE

DETECTION

NOISE

DUAL SCALER

REDUCTION

FRC

AND

MOTION

DETECTION

OSD BLEND

ENHANCE

Picture-in-picture (PiP) support is possible when receiving

video data on more than one of the video inputs, such as the

48-bit pixel port and the serial video receiver.

CUE

CORRECTION

DEINTERLACER

Figure 32. Video Processing

The 60-pin TTL video interface supports the following features:

The ADV8005 offers video deinterlacing and scaling. The

deinterlacer, located in the primary VSP, is motion adaptive and

offers high performance on low angle edges. It supports input

video resolutions of 480i, 576i, and 1080i.



Up to 48-bit pixel input port

Up to 24-bit pixel port for external OSD, if the ADV8005

internal OSD is not used

Up to 36-bit pixel output port

An SPI interface enabling video blanking interval (VBI)

data insertion



The dual scalers in the ADV8005 support the Analog Devices

proprietary scaling algorithm, which provides very high quality

video upscaling and downscaling. This scaling algorithm helps

eradicate many of the common problems that are encountered

when scaling video data, such as saw tooth, edge blurring, and

ringing.

The ADV8005 is capable of upscaling and downscaling between

a range of SD, HD, and ultra HD video resolutions (for example,

Rev. 0 | Page 45 of 52

ADV8005

Data Sheet

480p, 576p, 720p, 1080p, and 4k × 2k). The presence of two video

scalers allows the generation of multiple different video resolu-

tions on the ADV8005 outputs. The ADV8005 is also capable of

upscaling and downscaling to and from a wide range of non-CEA

(for example, VESA) formats.

system APIs to link the functionality of the OSD with the

functionality of the system.

The OSD design resource is loaded into external DDR2 memories

on power-up by the OSD coprocessor of the ADV8005. This

coprocessor is responsible for handling upper level commands

from the user and translating them into lower level operations

for the OSD and direct memory access (DMA).

Cadence detection and frame rate conversion are also supported

in the ADV8005, which allows film formats to be displayed

at their native frame rate, as well as being converted to the

native refresh rate of the TV. Additional video processing in

the ADV8005 helps with reduction of common video artifacts

such as mosquito, random, and block noise. The ADV8005 also

includes an aspect ratio converter, as well as a panorama mode

feature.

OSD features include the following:



Pixel-by-pixel alpha blending and priority levels assigned

to the different OSD components



A high performance OSD scaler allows the rendering

of OSDs at a single resolution, as well as blending at

different resolutions

Video metrics readbacks are provided to enable a system

application to select the correct phase and frequency for VGA-

type graphics inputs. These readbacks can be used to assist in

tuning the sampling phase of an ADC front-end device.

EXTERNAL DDR2 MEMORY

DDR2 INTERFACE

The following VSP features are included:

MOTION

ADAPTIVE

DEINTERLACER

VIDEO

SCALING

FRAME RATE

CONVERSION

BIT MAP OSD

DATA



High performance motion adaptive SD/HD deinterlacer

and scaler

Two scalers, allowing independent scaling on ADV8005

outputs

Frame rate converter, supporting conversion between multiple

frame rates (23.976 Hz, 24 Hz, 25 Hz, 29.97 Hz, 30 Hz, 50 Hz,

59.94 Hz, and 60 Hz)

Figure 34. External DDR2 Memory Interface

External DDR2 memory is required for motion adaptive

deinterlacing, scaling, frame rate conversion, and bit map OSD

overlay. The bandwidth of external memory required is

determined by the input video formats that the ADV8005 must

support, as well as the level of video processing required (scaling,

conversion, and OSD). Depending on the exact application

requirements, the ADV8005 can support various combinations

of memory (single or double memories) and memory sizes (up

to two 2 Gb memories).



Noise reduction, which helps with the reduction of random,

block, and mosquito noise

Six manually programmable color space converters that are

distributed between inputs and outputs

Autophase and frequency readbacks

HDMI TRANSMITTERS

ON-SCREEN DISPLAY (OSD)

The ADV8005 features dual HDMI transmitters. The transmitters

support all HDTV formats up to 4k × 2k, all mandatory, and

many optional, 3D formats. Each HDMI transmitter features an

audio return channel (ARC) receiver and on-chip

INTERNAL

DDR2

OSD GENERATOR

EXTERNAL OSD

OSD BUILD

microprocessor units with display data channel (DDC) I²C

masters to perform HDCP operations and EDID operations.

OSD SCALER

HDMI Tx features include the following:

OSD BLEND

VIDEO



Support for all formats up to 4k × 2k

Audio return channel (ARC) support

Mandatory 3D formats and many optional 3D formats

HDMI audio interface with support for multiple audio

formats (S/PDIF, I²S, DSD, HBR); data can be applied

externally or passed through from the serial video receiver

Figure 33. Bit Map-Based OSD

The ADV8005 incorporates a bit map-based OSD block that

allows users to create impressive OSD designs that can include

bit map images, as well as motion and animation. Individual

regions of the OSD can be alpha blended and prioritized over

other regions.

VIDEO ENCODER

An OSD development tool, Blimp, is provided to assist in the

design and development of custom OSDs and to abstract the

OSD hardware from the user. This tool automatically generates

two design elements: a design resource (containing character

sets and images) that must be downloaded to an external SPI

flash on the board, and code that must be integrated with

The ADV8005 features a high speed digital-to-analog video

encoder. Six 12-bit NSV, 3.3 V video DACs provide support for

worldwide composite (CVBS), S-Video (Y/C), and component

(YPrPb/RGB) analog outputs in SD, ED, or HD video formats. It

is also possible to enable the video encoder of the ADV8005 to

work in simultaneous modes where both SD and ED/HD

Rev. 0 | Page 4± of 52

Data Sheet

ADV8005

formats are output. Rovi (ADV8005KBCZ-8A) and non-Rovi

(ADV8005KBCZ-8N) variants of the ADV8005 are available.



Simultaneous SD and ED/HD operation

Copy generation management system (CGMS)

Closed captioning and widescreen signaling (WSS)

Rovi Rev. 7.1.L1 (SD) and Rev. 1.4 (ED) compliant

Encoder features include the following:



Six 12-bit NSV video DACs capable of outputting video

standards of up to 1080p with additional oversampling

Multiformat video output support; composite (CVBS),

S-Video (Y/C), component YPrPb (SD, ED and HD), and

component RGB (SD, ED and HD)

TYPICAL APPLICATION DIAGRAM



See Figure 35 for an example of a typical application diagram.

SPI

FLASH

EXTERNAL DDR2

DDR2 INTERFACE

SYSTEM

MCU

2

SPI/I C

DUAL HIGH SPEED

HDMI Rx

(FOR EXAMPLE,

ADV7619)

HDMI

60-BIT

INPUT

HDMI Tx1

HDMI Tx2

HDMI

COMPOSITE

S-VIDEO

VIDEO

48-BIT

INPUT

VIDEO DECODER/

HDMI Rx

(FOR EXAMPLE,

ADV7844)

COMPONENT

VIDEO SIGNAL

PROCESSING

HDMI

SERIAL

VIDEO

RECEIVER

HD VIDEO

DACs

COMPONENT

HDMI

S-VIDEO

FRONT END

(FOR EXAMPLE,

ADV7850)

SD VIDEO

DACs

COMPOSITE

ADV8005

AUDIO INSERTED INTO

HDMI VIDEO STREAMS

®

SHARC

AUDIO

PROCESSING

AUDIO FROM

HDMI

Figure 35. System Block Diagram

Rev. 0 | Page 47 of 52

ADV8005

Data Sheet

DESIGN CONSIDERATIONS

POWER-UP SEQUENCE

THERMAL CONSIDERATIONS

The power-up sequence of the ADV8005 is as follows:

The thermal performance of the ADV8005 is influenced by a

number of factors, for example, power dissipation of the

ADV8005, printed circuit board (PCB) design, and ambient

temperature.

RESET

1. Hold the

and PDN pins low.

2. Power up the 3.3 V supplies (DVDD_IO, AVDD1,

AVDD2).

These factors, along with any other application specific factors

that may affect the thermal performance of ADV8005, must be

considered to ensure that the junction temperature of the

ADV8005 does not exceed 125°C.

3. A minimum delay of 20 ms is required from the point at

which the 3.3 V reaches its minimum recommended value

(that is, 3.14 V) before powering up the 1.8 V supplies.

4. Power up the 1.8 V supplies (DVDD, PVDD1, PVDD2,

PVDD3, CVDD1, AVDD3, AVDD4, DVDD_DDR,

PVDD_DDR) and the 1.845 V supplies (PVDD5 and

PVDD6). Power these up together, that is, with a difference

of less than 0.3 V between them.

The flexibility of the ADV8005 can, in theory, result in the

device being configured in modes where the junction

temperature exceeds the maximum rated specification. To

ensure that this does not happen, the ADV8005 must be

characterized on the final customer PCB to ensure that the

maximum rated specifications are not exceeded in the planned

modes of operation. Using fewer internal layers on a PCB

reduces the amount of thermal conductivity between the

ADV8005 and the PCB itself. This decreased thermal

conductivity may necessitate some thermal management effort,

or it may affect the modes in which the ADV8005 can be

configured.

RESET

5.

can be pulled high after powering up the supplies.

6. A complete reset is recommended after power-up. This

can be performed by the system microcontroller.

PDN

(C11)

0V

3.3V

RESET

(A11)

0V

Calculate thermal conductivity as follows:

1.8V

1. Configure the ADV8005 in the highest required power

mode of operation.

1.8V

SUPPLY

2. Measure the ambient temperature of the enclosure.

3. Measure the case temperature at the top of the ADV8005.

0V

3.3V

3.14V

3.3V

SUPPLY

T_J= T_C+ 5°C

DELAY ≥

20ms

RESET >

5ms

T_{J MAX}= T_{A MAX}− T_A(actual) + T_C(actual) + 5°C

0V

Figure 36. Supply Power-Up Sequence

where:

T_Jis the junction temperature (inside the ADV8005).

T_Cis the case temperature (top surface of the ADV8005).

T_Ais the ambient temperature (in the locality of the ADV8005).

Maximum specified T_{A MAX}for the ADV8005 is 70°C. Depending

on the result of the previous calculations/measurement for the

specific system, a lower T_{A MAX}limit may need to be specified for

that system to ensure that T_{J MAX}remains safely below 125°C.

Rev. 0 | Page 48 of 52

Data Sheet

ADV8005

REGISTER MAP ARCHITECTURE

The registers of the ADV8005 are controlled via a 2-wire serial

(I²C-compatible) interface. Addressing in the ADV8005 is

16-bit with 8-bit data. This means that I²C writes to the device

are in the following format: <I²C Address>, <Address MSBs>,

<Address LSBs>, <Data>.

For example, to write 0xFF to the encoder register map, which

is Register 0xE4AF, the bytes sent over the I²C interface are:

0x1A, 0xE4, 0xAF, 0xFF. The addresses are outlined in Table 8.

Figure 37 shows the register map architecture for the ADV8005.

The ADV8005 also has a number of SPI register maps used for

OSD functions. These are accessed through the APIs defined in

the Blimp software tool.

Table 8. I²C Address and Register Address Ranges

Register Map Name

I²C Address

Register Address

IO Map

0x1A (when the ALSB pin is set high) or 0x18 (when the ALSB pin is set low)

0x1A00 to 0x1BFF

0xE800 to 0xE8FF

0xE900 to 0xE9FF

0xE±00 to 0xE±FF

0xE000 to 0xE0FF

0xE200 to 0xE2FF

0xE300 to 0xE3FF

0xE400 to 0xE4FF

0xEC00 to 0xECFF

0xEE00 to 0xEEFF

0xF200 to 0xF2FF

0xF300 to 0xF3FF

0xF400 to 0xF4FF

0xF±00 to 0xF±FF

0xFA00 to 0xFAFF

0xFB00 to 0xFBFF

Primary VSP Map 1

Primary VSP Map 2

Secondary VSP Map

DPLL Map

Rx Main Map

Rx InfoFrame Map

Encoder Map

Tx1 Main Map

Tx1 EDID Map

Tx1 UDP Map

Tx1 Test Map

Tx2 Main Map

Tx2 EDID Map

Tx2 UDP Map

Tx2 Test Map

IO

MAP

PRIMARY VSP PRIMARY VSP

SECONDARY

VSP MAP

DPLL

MAP

Rx MAIN

MAP

Rx INFOFRAME

MAP

ENCODER

MAP

Tx1 TEST

MAP

MAP 1

MAP 2

2

I C

ADDRESS

0x18/0x1A

0x1A00 TO

0x1BFF

0xE800 TO

0xE8FF

0xE900 TO

0xE9FF

0xE600 TO

0xE6FF

0xE000 TO

0xE0FF

0xE200 TO

0xE2FF

0xE300 TO

0xE3FF

0xE400 TO

0xE4FF

0xF300 TO

0xF3FF

SCL

SDA

0xEC00 TO

0xECFF

0xEE00 TO

0xEEFF

0xF200 TO

0xF2FF

0xF400 TO

0xF4FF

0xF600 TO

0xF6FF

0xFA00 TO

0xFAFF

0xFB00 TO

0xFBFF

Tx1 MAIN

MAP

Tx1 EDID

MAP

Tx1 UDP

MAP

Tx2 MAIN

MAP

Tx2 EDID

MAP

Tx2 UDP

MAP

Tx2 TEST

MAP

Figure 37. Register Map Architecture

Rev. 0 | Page 49 of 52

ADV8005

Data Sheet

OUTLINE DIMENSIONS

19.20

19.00 SQ

18.80

A1 BALL

CORNER

22 20 18 16 14 12 10

23 21 19 17 15 13 11

8

6

4

2

A1 BALL

CORNER

9

7

5

3

1

A

C

E

G

J

B

D

F

H

K

M

P

T

17.60

BSC SQ

L

N

R

U

W

0.80

BSC

V

Y

AA

AB

AC

TOP VIEW

DETAIL A

BOTTOM VIEW

DETAIL A

1.50

1.36

1.21

1.11

1.01

0.91

0.65

NOM

0.35 NOM

0.30 MIN

0.35

NOM

0.50

0.45

0.40

COPLANARITY

0.12

SEATING

PLANE

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-PPAB-2.

Figure 38. 425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-425-1)

Dimensions shown in millimeters

Table 9. Features Sets of the ADV8005 Models

Maximum

HDMI Tx

Outputs

Analog

Outputs

Rovi

Output

TTL

Model Number

Data Rate

3 Gbps

Maximum Video Format

4k × 2k at 30 Hz (8-bit)

VSP OSD Output

ADV8005KBCZ-8A¹

ADV8005KBCZ-8N

ADV8005KBCZ-8B

ADV8005KBCZ-8C

2

1

2

Six 12-bit DACs Yes

Six 12-bit DACs No

Yes

No

¹Rovi enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are capable of outputting Rovi compliant video. The ADV8005KBCZ-8A

incorporates copy protection technology that is protected by U.S. patents and other intellectual property rights of Rovi Corporation. Reverse engineering and

disassembly are prohibited.

ORDERING GUIDE

Model^{1, 2}

Temperature Range

0°C to 70°C

Package Description

Package Option

BC-425-1

ADV8005KBCZ-8A

ADV8005KBCZ-8A-RL

ADV8005KBCZ-8N

ADV8005KBCZ-8N-RL

ADV8005KBCZ-8B

ADV8005KBCZ-8B-RL

ADV8005KBCZ-8C

ADV8005KBCZ-8C-RL

EVAL-ADV8005-SMZ

425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Evaluation Board

¹Z = RoHS Compliant Part.

²The -RL versions are supplied on 13” reels. The non-RL versions are supplied on trays.

Rev. 0 | Page 50 of 52

Data Sheet

NOTES

ADV8005

Rev. 0 | Page 51 of 52

ADV8005

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D12074-0-6/14(0)

Rev. 0 | Page 52 of 52


型号：	ADV8005KBCZ-8N-RL
厂家：	ADI
描述：	NatureVue Video Signal Processor
文件：	总52页 (文件大小：506K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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