ADVFC32BH [ADI]
Voltage-to-Frequency and Frequency-to-Voltage Converter; 电压 - 频率和频率 - 电压转换器
| 型号： | ADVFC32BH |
| 厂家： | 
ADI |
| 描述： | Voltage-to-Frequency and Frequency-to-Voltage Converter |
| 文件： | 总6页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Voltage-to-Frequency and
Frequency-to-Voltage Converter
a
ADVFC32
FEATURES
High Linearity
P IN CO NFIGURATIO N
(TO P VIEW)
؎0.01% m ax at 10 kHz FS
؎0.05% m ax at 100 kHz FS
؎0.2% m ax at 500 kHz FS
Output TTL/ CMOS Com patible
V/ F or F/ V Conversion
“ N” P ackage
6 Decade Dynam ic Range
Voltage or Current Input
Reliable Monolithic Construction
MIL-STD-883 Com pliant Versions Available
P RO D UCT D ESCRIP TIO N
T he industry standard ADVFC32 is a low cost monolithic
voltage-to-frequency (V/F) converter or frequency-to-voltage
(F/V) converter with good linearity (0.01% max error at
10 kHz) and operating frequency up to 0.5 MHz. In the V/F
configuration, positive or negative input voltages or currents can
be converted to a proportional frequency using only a few exter-
nal components. For F/V conversion, the same components are
used with a simple biasing network to accommodate a wide
range of input logic levels.
“ H ” P ackage – TO -100
T T L or CMOS compatibility is achieved in the V/F operating
mode using an open collector frequency output. T he pullup re-
sistor can be connected to voltages up to 30 volts, or to +15 V
or +5 V for conventional CMOS or T T L logic levels. T his resis-
tor should be chosen to limit current through the open collector
output to 8 mA. A larger resistance can be used if driving a high
impedance load.
Input offset drift is only 3ppm of full scale per °C, and full-
scale calibration drift is held to a maximum of 100 ppm/°C
(ADVFC32BH ) due to a low T .C. Zener diode.
NC = NO CONNECT
2. T he ADVFC32 is easily configured to satisfy a wide range of
system requirements. Input voltage scaling is set by selecting
the input resistor which sets the input current to 0.25 mA at
the maximum input voltage.
T he ADVFC32 is available in commercial, industrial, and ex-
tended temperature grades. T he commercial grade is packaged
in a 14-pin plastic DIP while the two wider temperature range
parts are packaged in hermetically sealed T O-100 cans.
3. T he same components used for V/F conversion can also be
used for F/V conversion by adding a simple logic biasing net-
work and reconfiguring the ADVFC32.
P RO D UCT H IGH LIGH TS
1. T he ADVFC32 uses a charge balancing circuit technique
(see Functional Block Diagram) which is well suited to high
accuracy voltage-to-frequency conversion. T he full-scale
operating frequency is determined by only one precision re-
sistor and capacitor. T he tolerance of other support compo-
nents (including the integration capacitor) is not critical.
Inexpensive ±20% resistors and capacitors can be used with-
out affecting linearity or temperature drift.
4. T he ADVFC32 is intended as a pin-for-pin replacement for
VFC32 devices from other manufacturers.
5. T he ADVFC32 is available in versions compliant with MIL-
ST D-883. Refer to the Analog Devices Military Products
Databook or current ADVFC32/883B data sheet for detailed
specifications.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
ADVFC32–SPECIFICATIONS (typical @ +25؇C with V = ؎15 V unless otherwise noted)
S
AD VFC32K
Typ
AD VFC32B
Typ
AD VFC32S
Typ
Model
Min
Max
Min
Max
Min
Max
Units
DYNAMIC PERFORMANCE
Full Scale Frequency Range
Nonlinearity1
0
500
0
500
0
500
kHz
fMAX = 10 kHz
fMAX = 100 kHz
fMAX = 0.5 MHz
Full-Scale Calibration Error
(Adjustable to Zero)
vs. Supply
–0.01
–0.05
–0.20
±0.01
+0.05
+0.20
–0.01
–0.05
–0.20
+0.01
+0.05
+0.20
–0.01
–0.05
–0.20
+0.01
+0.05
+0.20
%
%
%
±0.05
±5
±0.05
±5
±0.05
±5
%
(Full Scale Frequency = 100 kHz) –0.015
vs. T emperature
(Full Scale Frequency = 10 kHz)
+0.015
–0.015
+0.015
–0.015
+150
+0.015
+150
% of FSR%
ppm/°C
±75
–100
+100
DYNAMIC RESPONSE
Maximum Settling T ime for Full Scale
Step Input
Overload Recovery T ime
1 Pulse of New Frequency Plus 1 µs
1 Pulse of New Frequency Plus 1 µs
1 Pulse of New Frequency Plus 1 µs
1 Pulse of New Frequency Plus 1 µs
1 Pulse of New Frequency Plus 1 µs
1 Pulse of New Frequency Plus 1 µs
ANALOG INPUT AMPLIFIER
(V/F Conversion)
Current Input Range
Voltage Input Range
0
0
+0.25
–10
0
0
+0.25
–10
0
0
+0.25
–10
mA
V2
0.25
0.25
× RIN
0.25
× RIN
mA
3
3
3
× RIN
2 MΩ||10 pF
300 MΩ||3 pF 750 MΩ||3 pF
Differential Impedance
Common-Mode Impedance
Input Bias Current
300 kΩ||10 pF
300 kΩ||10 pF 2 MΩ||10 pF
300 MΩ||3 pF 750 MΩ||10 pF
300 kΩ||10 pF 2 MΩ||10 pF
300 MΩ||3 pF 750 MΩ||10 pF
Noninverting Input
Inverting Input
40
±8
250
+100
40
±8
250
+100
40
±8
250
+100
nA
nA
–100
–100
–100
Input Offset Voltage
(T rimmable to Zero)2, 3
4
4
4
mV
vs. T emperature (T MIN to TMAX
Safe Input Voltage
)
30
30
30
µV/°C
±VS
±VS
±VS
COMPARAT OR (F/V Conversion)
Logic “0” Level
–VS
+1
0.1
–0.6
+VS
0.15/fMAX
–VS
+1
0.1
–0.6
+VS
–VS
+1
–0.6
+VS
0.15/fMAX µs
V
V
Logic “1” Level
Pulse Width Range4
Input Impedance
0.15/fMAX 0.1
50 kΩ||10 pF
50 kΩ||10 pF
250 kΩ
50 kΩ||10 pF
250 kΩ
250 kΩ
OPEN COLLECT OR OUT PUT
(V/F Conversion)
Output Voltage in Logic “0”
ISINK = 8 mA
Output Leakage Current in Logic “1”
Voltage Range
0.4
1
+30
0.4
1
+30
0.4
1
+30
V
µA
V
0
0
0
Fall T imes (Load = 500 pF and
ISINK = 5 mA)
400
+10
400
+10
400
+10
ns
AMPLIFIER OUT PUT (F/V Conversion)
Voltage Range (0 mA≤IO≤7 mA)
Source Current (0≤VO≤7 V)
Capacitive Load (Without Oscillation)
Closed Loop Output Impedance
0
10
0
10
0
10
V
mA
pF
Ω
100
1
100
1
100
1
POWER SUPPLY
Rated Voltage
±15
±15
±15
V
Voltage Range
±9
±18
±9
±18
±9
±18
V
Quiescent Current
6
8
6
8
6
8
mA
T EMPERAT URE RANGE
Specified Range
Operating Range
Storage
0
–25
–25
+70
+85
+85
–25
–55
–65
+85
+125
+150
–55
–55
–65
+125
+125
+150
°C
°C
°C
PACKAGE OPT IONS
Plastic DIP (N-14)
T O–100 (H-10A)
ADVFC32KN
ADVFC32BH
ADVFC32SH
NOT ES
1Nonlinearity defined as deviation from a straight line from zero to full scale, expressed as a percentage of full scale.
2See Figure 3.
3See Figure 1.
4fMAX expressed in units of MHz.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at
final electrical test. Results from those tests are used to calculate
outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested on all production units.
–2–
REV. A
ADVFC32
UNIP O LAR V/F, P O SITIVE INP UT VO LTAGE
When operated as a V/F converter, the transformation from
voltage to frequency is based on a comparison of input signal
magnitude to the 1 mA internal current source.
during the remainder of the cycle to return the integrator to its
original voltage. Since the charge taken out of C2 is equal to the
charge that is put on C2 every cycle,
1
– tOS
(1 mA – IIN) × tOS = IIN
×
A more complete understanding of the ADVFC32 requires a
close examination of the internal circuitry of this part. Consider
the operation of the ADVFC32 when connected as shown in
Figure 1. At the start of a cycle, a current proportional to the
F OUT
or, rearranging terms,
IIN
FOUT
=
1 mA × tOS
T he complete transfer equation can now be derived by substi-
tuting IIN = VIN/RIN and the equation relating C1 and tOS. T he
final equation describing ADVFC32 operation is:
VINI / RIN
1mA × C + 44 pF × 6.7 kΩ
(
)
1
Components should be selected to optimize performance over
the desired input voltage and output frequency range using the
equations listed below:
3.7 ×107 pF / sec
– 44 pF
FOUT FS
10–4 Farads / sec
1000 pF minimum
(
)
C2 =
F OUT FS
Figure 1. Connection Diagram for V/F Conversion,
Positive Input Voltage
VIN FS
RIN
=
input voltage flows through R3 and R1 to charge integration
capacitor C2. As charge builds up on C2, the output voltage of
the input amplifier decreases. When the amplifier output volt-
age (Pin 13) crosses ground (see Figure 2 at time t1), the
comparator triggers a one shot whose time period is determined
0.25 mA
+VLOGIC
8 mA
R2 ≥
Both RIN and C1 should have very low temperature coefficients
as changes in their values will result in a proportionate change in
the V/F transfer function. Other component values and tem-
perature coefficients are not critical.
Table I. Suggested Values for C 1, RIN and C2
VIN FS
FO UT FS
C1
RIN
C2
1 V
10 V
1 V
10 kHz
10 kHz
100 kHz
100 kHz
3650 pF
3650 pF
330 pF
330 pF
4.0 kΩ
40 kΩ
4.0 kΩ
40 kΩ
0.01 µF
0.01 µF
1000 pF
1000 pF
10 V
O RD ERING GUID E
Gain Tem pco Tem p Range P ackage
P art
Num ber 1
ppm /؇C
؇C
O ption
Figure 2. Voltage-to-Frequency Conversion Waveform s
ADVFC32KN
±75 typ
0 to +70
14-Pin
by capacitor C1. Specifically, the one shot time period (in nano-
seconds) is:
Plastic DIP
T O-100
T O-100
ADVFC32BH
ADVFC32SH
±100 max
±150 max
–25 to +85
–55 to +125
tOS (Cl + 44 pF) × 6.7 kΩ
During this period, a current of (1 mA – IIN) flows out of the in-
tegration capacitor. T he total amount of charge depleted during
one cycle is, therefore (1 mA – IIN) × tOS. This charge is replaced
NOT E
1For details on grade and package offerings screened in accordance with
MIL-ST D-883, refer to the Analog Devices Military Products Databook or current
ADVFC32/883B data sheet.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADVFC32 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
ADVFC32
F/V CO NVERSIO N
Input resistance RIN is composed of a fixed resistor (R1) and a
variable resistor (R3) to allow for initial gain error compensation.
T o cover all possible situations, R3 should be 20% of RIN, and
R1 should be 90% of RIN. T his allows a ±10% gain adjustment
to compensate for the ADVFC32 full-scale error and the toler-
ance of C1.
Although the mathematics of F/V conversion can be very com-
plex, the basic principle is easy to understand. Figure 4 shows
the connection diagram for F/V conversion with T T L input
logic levels. Each time the input signal crosses the comparator
threshold going negative, the one shot is activated and switches
1 mA into the integrator input for a measured time period (de-
termined by C1). As the frequency increases, the amount of
charge injected into the integration capacitor increases propor-
tionately. T he voltage across the integration capacitor is stabi-
lized when the leakage current through R1 and R3 equals the
average current being switched into the integrator. T he net re-
sult of these two effects is an average output voltage which is
proportional to the input frequency. Optimum performance can
be obtained by selecting components using the same guidelines
and equations listed in the V/F conversion section.
If more accurate initial offset is required, the circuit of R4 and
R5 can be added. R5 can have a value between 10 kΩ and
100 kΩ, and R4 should be approximately 10 MΩ. T he amount
of current required to trim zero offset will be relatively small, so
the temperature coefficients of these resistors are not critical. If
large offsets are added using this circuit, temperature drift of
both of these resistors is much more important.
BIP O LAR V/F
By adding another resistor from Pin 1 (Pin 2 of T O-100 can) to
a stable positive voltage, the ADVFC32 can be operated with a
bipolar input voltage. For example, an 80 kΩ resistor to +10 V
causes an additional current of 0.125 mA to flow into the inte-
grator so that the net current flow to the integrator is positive
even for negative input voltages. At negative full-scale input
voltage, 0.125 mA will flow into the integrator from VIN cancel-
ling out the 0.125 mA from the offset resistor, resulting in an
output frequency of zero. At positive full scale, the sum of the
two currents will be 0.25 mA and the output will be at its maxi-
mum frequency.
UNIP O LAR V/F, NEGATIVE INP UT VO LTAGE
Figure 3 shows the connection diagram for V/F conversion of
negative input voltages. In this configuration full-scale output
frequency occurs at negative full-scale input, and zero output
frequency corresponds to zero input voltage.
Figure 4. Connection Diagram for F/V Conversion, TTL
Input
D ECO UP LING
Decoupling power supplies at the device is good practice in any
system, but absolutely imperative in high resolution applica-
tions. For the ADVFC32, it is important to remember where
the voltage transients and ground currents flow. For example,
the current drawn through the output pulldown transistor origi-
nates from the logic supply, and is directed to ground through
Pin 11 (Pin 8 of T O-100). T herefore, the logic supply should be
decoupled near the ADVFC32 to provide a low impedance re-
turn path for switching transients. Also, if there is a separate
digital ground it should be connected to the analog ground at
the ADVFC32. T his will prevent ground offsets that could be
created by directing the full 8 mA output current into the analog
ground, and subsequently back to the logic supply.
Figure 3. Connection Diagram for V/F Conversion,
Negative Input Voltage
Although some circuits may operate satisfactorily with the
power supplies decoupled at only one location on each board,
this practice is not recommended for the ADVFC32. For best
results, each supply should be decoupled with 0.1 µF capacitor
at the ADVFC32. In addition, a larger board level decoupling
capacitor of 1 µF to 10 µF should be located relatively close to
the ADVFC32 on each power supply.
A very high impedance signal source may be used since it only
drive the noninverting integrator input. T ypical input imped-
ance at this terminal is 250 MΩ or higher. For V/F conversion
of positive input signals the signal generator must be able to
source 0.25 mA to properly drive the ADVFC32, but for nega-
tive V/F conversion the 0.25 mA integration current is drawn
from ground through R1 and R3.
CO MP O NENT TEMP ERATURE CO EFFICIENTS
T he drift specifications of the ADVFC32 do not include tem-
perature effects of any of the supporting resistors or capacitors.
T he drift of the input resistors R1 and R3 and the timing ca-
pacitor C1 directly affect the overall temperature stability. In the
application of Figure 2, a 10 ppm/°C input resistor used with a
Circuit operation for negative input voltages is very similar to
positive input unipolar conversion described in the previous sec-
tion. For best operating results use component equations listed
in that section.
REV. A
–4–
ADVFC32
100 ppm/°C capacitor may result in a maximum overall circuit
gain drift of:
while the bias current of the inverting input is ±8 nA. T herefore,
any attempt to cancel input offset voltage due to bias currents by
matching input resistors will create worse offsets. Second, the
output of this amplifier will sink only 1 mA, even though it will
source as much as 10 mA. When used in the F/V mode, the am-
plifier must be buffered if large sink currents are required.
100 ppm/°C (ADVFC32BH) + 100 ppm/°C (C1)
+ 10 ppm/°C (RIN) = 210 ppm/°C
Although RIN and C1 have the most pronounced effect on tem-
perature stability, the offset circuit of resistors R4 and R5 may
also have a slight effect on the offset temperature drift of the cir-
cuit. T he offset will change with variations in the resistance of
R4 and supply voltage changes. In most applications the offset
adjustment is very small, and the offset drift attributable to this
circuit will be negligible. In the bipolar mode, however, both the
positive reference and the resistor used to offset the signal range
will have a pronounced effect on offset drift. A high quality
reference and resistor should be used to minimize offset drift
errors.
MICRO P RO CESSO R O P ERATED A/D CO NVERTER
With the addition of a few external components the ADVFC32
can be used as a ±10 V A/D microprocessor front end. Although
the nonlinearity of the ADVFC32 is only 0.05% maximum
(0.01% typ), the resolution is much higher, allowing it to be
used in 16-bit measurement and control systems where a mono-
tonic transfer function is essential. T he resolution of the circuit
shown in Figure 5 is dependent on the amount of time allowed
to count the ADVFC32 frequency output. Using a full scale fre-
quency of 100 kHz, an 8-bit conversion can be made in about
10 ms, and a 2 second time period allows a 16-bit measurement,
including offset and gain calibration cycles.
Other circuit components do not directly influence temperature
performance as long as their actual values are not so different
from nominal value as to preclude operation. T his includes
integration capacitor C2. A change in the capacitance value of
C2 results in a different rate of voltage change across C2, but
this is compensated by an equal effect when C2 is discharged by
the switched 1 mA current source so that no net effect occurs.
As shown in Figure 5, the input signal is selected via the AD7590
input multiplexer. Positive and negative references as well as a
ground input are provided to calibrate the A/D. T his is very im-
portant in systems subject to moderate or extreme temperature
changes since the gain temperature coefficient of the ADVFC32
is as high as ±150 ppm/°C. By using the calibration cycles, the
A/D conversion will be as accurate as the references provided.
T he AD542 following the input multiplexer provides a high im-
pedance input (1012 ohms) and buffers the switch resistance
from the relatively low impedance ADVFC32 input.
T he temperature effects of the components described above are
the same when the ADVFC32 is configured for negative or bi-
polar input ranges, or F/V conversion.
O TH ER CIRCUIT CO NSID ERATIO NS
T he input amplifier connected to Pins 1, 13, and 14 is not a
standard operational amplifier. Although it operates like an op
amp in most applications, two key differences should be noted.
First, the bias current of the positive input is typically 40 nA
If higher linearity is required, the ADVFC32 can be operated at
10 kHz, but this will require a proportionately longer conver-
sion, time. Conversely, the conversion time can be decreased at
the expense of nonlinearity by increasing the maximum fre-
quency to as high as 500 kHz.
Figure 5. High Resolution, Self-Calibrating, Microprocessor
Operated A/D Converter
H IGH NO ISE IMMUNITY, H IGH CMRR ANALO G D ATA
LINK
voltage-to-frequency conversion, this data link is extremely
insensitive to noise and common-mode voltage interference. For
even more protection, an optical fiber link substituted for the
HCPL2630 will provide common-mode rejection of more than
several hundred kilovolts and virtually total immunity to electri-
cal noise. For most applications, however, the frequency modu-
lated signal has sufficient noise immunity without using an optical
In many applications, a signal must be sensed at a remote site
and sent through a very noisy environment to a central location
for further processing. In these cases, even a shielded cable may
not protect the signal from noise pickup. T he circuit of Figure 6
provides a solution in these cases. Due to the optocoupler and
REV. A
–5–
ADVFC32
Figure 6. High Noise Im m unity Data Link
fiber link, and the optocoupler provides common-mode isolation
up to 3000 V dc.
Although the F/V conversion technique used in this circuit is
quite simple, it is also very limited in terms of its frequency re-
sponse and output ripple. T he frequency response is limited by
the integrator time constant and while it is possible to decrease
that time constant, either signal range or output ripple must be
sacrificed. T he performance of the circuit of Figure 6 is shown
in the photograph below. T he top trace is the input signal, the
middle trace is the frequency-modulated signal at the
T he data link input voltage is changed in a frequency modulated
signal by the first ADVFC32. A 42.2 kΩ input resistor and a
100 kΩ offset resistor set the scaling so that a 0 V input signal
corresponds to 50 kHz, and a 10 V input results in the maxi-
mum output frequency of 500 kHz. A high frequency opto-
coupler is then used to transmit the signal across any common-
mode voltage potentials to the receiving ADVFC32. T he opto-
coupler is not necessary in systems where common-mode noise
is either very small or a constant low level dc voltage. In systems
where common-mode voltage may present a problem, the con-
nection between the two locations should be through the opto-
coupler; no power or ground connections need to be made.
optocoupler’s output, and the bottom trace is the recovered
signal at the output of the F/V converter.
T he output of the optocoupler drives an ADVFC32 hooked up
in the F/V configuration. Since the reconstructed signal at Pin
10 has a considerable amount of carrier feedthrough, it is desir-
able to filter out any frequencies in the carrier range of 50 kHz
to 500 kHz. T he frequency response of the F/V converter is only
3 kHz due to the pole made by the integrator, so a second 3 kHz
filter will not significantly limit the bandwidth. With the simple
one pole filter shown in Figure 6, the input to output 3 dB point
is approximately 2 kHz, and the output noise is less than
15 mV. If a lower output impedance drive is needed, a two pole
active filter is recommended as an output stage.
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
14-P in P lastic D IP P ackage
TO -100 P ackage
REV. A
–6–
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