ADV7614BBCZ [ADI]
12-Bit Deep Color with Quad HDMI Receiver; 12位色深与四HDMI接收器
| 型号： | ADV7614BBCZ |
| 厂家： | 
ADI |
| 描述： | 12-Bit Deep Color with Quad HDMI Receiver |
| 文件： | 总20页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit Deep Color with Quad HDMI
Receiver
Data Sheet
ADV7614
FEATURES
APPLICATIONS
Ultralow jitter digital PLL
Advanced TVs
4:1 multiplexed HDMI receiver
HDMI 1.3a support
AVR video receivers
PDP HDTVs
36-/30-/24-bit deep color support
Flexible audio interface (DSD, DST,
Dolby® TrueHD, DTS®-HD master audio, and DTS-HD
high resolution audio)
LCD TVs (HDTV ready)
OLED HDTVs
LCD/DLP front projectors
HDMI switchers
225 MHz HDMI receiver
HDMI repeater support
GENERAL DESCRIPTION
The ADV7614 is a high quality, single-chip integrated 4:1
multiplexed High-Definition Multimedia Interface (HDMI®)
receiver.
High-bandwidth digital content protection (HDCP 1.3)
Programmable/adaptive equalizer for cable lengths up to
30 meters
Internal EDID RAM
EDID with HDMI cable power support
CEC support
On-board audio mute controller
General
Highly flexible output interface
12-/10-/8-bit 4:4:4 or 12-/10-/8-bit 4:2:2 pixel output interface
STDI function support standard identification
Any-to-any 3 × 3 color space conversion matrixes
Free-run time generator
2 programmable interrupt request output pins
Color controls
Low standby power
The ADV7614 incorporatesa quad input HDMIreceiver that
supportsallHDTVformatsupto 1080pand displays resolutions
up to UXGA (1600 ×1200 at60 Hz). Thereception ofencrypted
video is possible with the inclusion of HDCP. The HDMI
receiver also includes programmable/adaptive equalization that
ensures robust operation of the interface with cable lengths up
to 30 meters.
The ADV7614 provides complete audio support foreight chan-
nels of I2S audio, Sony/Philips digital interface format (S/PDIF)
digital audio output, and super audio CD (SACD) and com-
pressed SACDsupport with direct stream digital (DSD) and
direct stream transfer (DST)output interfaces, respectively.
The HDMIreceiver also supports high bit rate (HBR) audio
streaming to allow recovery (and downstreamprocessing)of
compressed losslessaudio formats, including Dolby® TrueHD
and DTS®-HD master audio or DTS-HD high resolution audio.
In addition, it also provides an advanced audio functionality,
such as a mute controllerthat prevents audible extraneous noise
in the audio output.
Fabricated in an advanced CMOS process,the ADV7614 is
providedin a space-saving, 260-ball 15 mm×15 mmCSP_BGA
surface-mount, RoHS-compliant package. The ADV7614 is
specified over the −40°C to +70°C temperaturerange.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
ADV7614
Data Sheet
TABLE OF CONTENTS
Features........................................................................................... 1
ESD Cautio n............................................................................... 8
Pin Configuration and Function Descriptio ns............................ 9
Functional Overview................................................................... 16
HDMI Receiver........................................................................ 16
Component Processor (CP).................................................... 16
CP Pixel Data Output Modes.................................................. 16
I2C Interface ............................................................................. 16
Other Features.......................................................................... 16
Outline Dimensions.................................................................... 17
Ordering Guide........................................................................ 17
Applications................................................................................... 1
General Description...................................................................... 1
Revision History............................................................................ 2
Functional Block Diagram............................................................ 3
Specifications................................................................................. 4
Analog, Digital, HDMI, and AC Specifications...................... 4
Data and I2C Timing Characteristics....................................... 5
Power Specifications.................................................................. 6
Absolute Maximum Ratings......................................................... 8
Package Thermal Performance................................................. 8
REVISION HISTORY
9/13—RevisionC: Initial Version
Rev. C | Page 2 of 20
Data Sheet
ADV7614
FUNCTIONAL BLOCK DIAGRAM
BACK
END
CSC
12
12
12
P0 TO P11
P12 TO P23
P24 TO P35
SYNC PROCESSING
AND
CLOCK GENERATION
HS, VS
LLC
DATA
PREPROCESSOR
AND
LLC
COLOR
COMPONENT
PROCESSOR
SPACE
CONVERTER
CONTROL
AND
INT1
INT2
A
B
C
DATA
CONTROL
INTERFACE
CONTROL
2
I C
HS
VS_FIELD
DE
SCL
SDA
PACKET
/
INFOFRAME
MEMORY
CEC
CONTROLLER
CEC
RXA_C±
RXB_C±
RXC_C±
RXD_C±
36
PLL
MUX
RXA_0±
RXA_1±
RXA_2±
HDMI
PROCESSOR
2
EQUALIZER
EQUALIZER
EQUALIZER
EQUALIZER
SAMPLER
I S0/DSD0B/HBR0
2
I S1/DSD1A/HBR1
2
I S2/DSD1B/HBR2
RXB_0±
RXB_1±
RXB_2±
2
I S3/DSD2A/HBR3
AUDIO
SAMPLER
SAMPLER
SAMPLER
PACKET
LRCLK/DSD2B/DST_FF
SCLK/DST_CLK
PROCESSOR
HDCP
ENGINE
HDCP
EEPROM
RXC_0±
RXC_1±
RXC_2±
MCLKOUT
S/PDIF/DSD0A/DST
RXD_0±
RXD_1±
RXD_2±
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
DDCC_SDA
DDCC_SCL
DDCD_SDA
DDCD_SCL
RXA_5V
EDID
REPEATER
RXB_5V
RXC_5V
CONTROLLER
RXD_5V
EP_MISO
EP_MOSI
EP_CS
EP_SCK
SHARED_EDID
ADV7614
PWRDN
Figure 1.
Rev. C | Page 3 of 20
ADV7614
Data Sheet
SPECIFICATIONS
DVDD = 1.8 V 5%, DVDDIO = 3.3 V 5%, PVDD = 1.8 V 5%, TVDD = 3.3 V 5%, CVDD = 1.8 V 5%, TMIN to TMAX = −40°C to
+70°C, unless otherwise noted.
ANALOG, DIGITAL, HDMI, AND AC SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ Max
Unit
DIGITAL INPUTS
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IIN)
2
V
V
0.8
pin
−60
−10
+60
+10
10
µA
µA
pF
RESET
Other digital inputs
Input Capacitance (CIN)
DIGITAL INPUTS (5 V TOLERANT)1
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IIN)
2.6
V
V
µA
µA
0.8
+60
+82
SHARED_EDID pin
Other 5 V digital inputs
−150
−82
DIGITAL OUTPUTS
Output High Voltage (VOH
Output Low Voltage (VOL)
)
2.4
V
0.4
V
High Impedance Leakage Current (ILEAK
Output Capacitance (COUT
HDMI
)
10
20
µA
pF
)
TMDS Differential Pin Capacitance
0.3
pF
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew for
TMDS Clock Rates up to 222.75 MHz
Intrapair (+ to −) Differential Input Skew for
TMDS Clock Rates Above 222.75 MHz
0.4 TBIT
ps
ps
0.15 TBIT + 112
Channel-to-ChannelDifferentialInput Skew
TMDS Input Clock Range
0.2 tPIXEL + 1.78
225
ns
MHz
TBIT
25
Input Clock Jitter Tolerance
0.5
0.25 TBIT
1 The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, RXA_5V, RXB_5V, RXC_5V,
RXD_5V, SHARED_EDID, , EP_MISO.
PWRDN
Rev. C | Page 4 of 20
Data Sheet
ADV7614
DATA AND I2C TIMING CHARACTERISTICS
DVDD = 1.8V 5%, DVDDIO = 3.3 V 5%, PVDD = 1.8 V 5%, TVDD = 3.3 V 5%, CVDD = 1.8 V 5%, TMIN to TMAX = −40°C to
+70°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
VIDEO SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
LLC Frequency Range
External Clock Source 1
Input High Voltage
24.576/28.6363
MHz
ppm
MHz
50
170
12.825
1.2
External crystal must operate at 1.8 V
Ball H15 (XTALP) driven with external
clock source
Ball H15 (XTALP) driven with external
clock source
VIH
VIL
V
V
Input Low Voltage
0.4
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark Space Ratio
5
ms
t9:t10
45:55
55:45 % duty
cycle
I2C PORTS (FAST MODE)
xCL Frequency2
400
kHz
ns
µs
ns
ns
ns
ns
ns
µs
xCL Minimum Pulse Width High2
xCL Minimum Pulse Width Low2
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time2
t1
t2
t3
t4
t5
t6
t7
t8
600
1.3
600
600
100
xCL and xDA Rise Time2
xCL and xDA Fall Time2
300
300
Setup Time (Stop Condition)
I2C PORTS (NORMAL MODE)
xCL Frequency2
xCL Minimum Pulse Width High2
xCL Minimum Pulse Width Low2
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time2
xCL and xDA Rise Time2
xCL and xDA Fall Time2
Setup Time (Stop Condition)
DATA AND CONTROL OUTPUTS3
Data Output Transition Time SDR (CP)
Data Output Transition Time SDR (CP)
0.6
100
kHz
µs
µs
µs
µs
ns
ns
ns
µs
t1
t2
t3
t4
t5
t6
t7
t8
4.0
4.7
4.0
4.7
250
1000
300
4.0
t11
t12
End of valid data to negative clock edge
Negative clock edge to start of valid data
0.55
1.0
ns
ns
VIDEO I2S PORT
Master Mode
SCLK Mark Space Ratio
t13:t14
45:55
55:45 % duty
cycle
LRCLK Data Transition Time
LRCLK Data Transition Time
I2Sx Data Transition Time 4
I2Sx Data Transition Time4
t15
t16
t17
t18
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
10
10
5
ns
ns
ns
ns
5
1 The XTAL_CTRL bit must be enabled for external oscillator operation. A 1.8 V oscillator must be used.
2 The prefix x refers to S, DDCA_S, DDCB_S, DDCC_S, and DDCD_S.
3 LLC DLL disabled.
4 The suffix x refers to 0, 1, 2, and 3.
Rev. C | Page 5 of 20
ADV7614
Data Sheet
POWER SPECIFICATIONS
DVDD = 1.8 V ꢀ5% DVDDIO = 3.3 V ꢀ5% ꢁVDD = 1.8 V ꢀ5% TVDD = 3.3 V ꢀ5% ꢂVDD = 1.8 V ꢀ5% TMIN to TMAX = −40°ꢂ to
+70°ꢂ% unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLIES
Digital Core Power Supply (DVDD)
Digital I/O Power Supply (DVDDIO)
PLL Power Supply (PVDD)
Terminator Power Supply (TVDD)
Comparator Power Supply (CVDD)
CURRENT CONSUMPTION1, 2, 3, 4
1.71
3.14
1.71
3.14
1.71
1.8
3.3
1.8
3.3
1.8
1.89
3.46
1.89
3.46
1.89
V
V
V
V
V
Comparator Power Supply (ICVDD
Digital Core Power Supply (IDVDD
Digital I/O Power Supply (IDVDDIO
PLL Power Supply (IPVDD
Termination Power Supply (ITVDD
)
102.9
3.7
212.4
2.3
29.7
1.3
74.7
0.2
121.9
4.0
290.2
2.5
167.0
1.4
87.5
0.22
204.5
1.2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1080p 12-bit Deep Color with 4-channel PCM
Power-Down Mode 0
1080p 12-bit Deep Color with 4-channel PCM
Power-Down Mode 0
1080p 12-bit Deep Color with 4-channel PCM
Power-Down Mode 0
1080p 12-bit Deep Color with 4-channel PCM
Power-Down Mode 0
)
)
)
)
185.3
1.1
1080p 12-bit Deep Color with 4-channel PCM
Power-Down Mode 0
1 All maximum current values are guaranteed by characterization to assist in power supply design.
2 Typical current consumption values are recorded with nominal voltage supply levels and a SMPTEBAR pattern.
3 Maximum current consumption values are recorded with maximum rated voltage supply levels and a Moire X pattern.
4 Termination power supply includes TVDD current consumed off chip.
Timing Diagrams
t3
t5
t3
xDA
t6
t1
xCL
t2
t7
t4
t8
NOTES
1. THE PREFIX x REFERS TO S, DDCA_S, DDCB_S, DDCC_S, AND DDCD_S.
Figure 2. I2C Timing
t9
t10
LLC
t11
t12
P0 TO P35, VS,
HS, DE
Figure 3. Pixel Port and Control SDR Output Timing
Rev. C | Page 6 of 20
Data Sheet
ADV7614
t13
SCLK
t14
t15
LRCLK
I2Sx
t16
t17
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
MSB
t18
t17
I2Sx
2
I S MODE
MSB – 1
t18
t17
I2Sx
RIGHT-JUSTIFIED
MODE
MSB
LSB
t18
NOTES
1. THE SUFFIX x REFERS TO 0, 1, 2, AND 3.
Figure 4. I2S Timing
Rev. C | Page 7 of 20
ADV7614
Data Sheet
ABSOLUTEMAXIMUM RATINGS
PACKAGE THERMAL PERFORMANCE
Table 4.
To reduce powerconsumption when using the ADV7614, the
user is advised to turn off unused sections of the part.
Parameter
Rating
2.2 V
2.2 V
4.0 V
2.2 V
DVDD to GND
PVDD to GND
Due to printed circuit board (PCB)metalvariation and, thus,
variation in PCB heat conductivity, the value of θJA may differ
for various PCBs.
DVDDIO to GND
CVDD to GND
TVDD to GND
Digital Inputs Voltage to GND
4.0 V
GND − 0.3 V to
DVDDIO + 0.3 V
The most efficient measurement solution is obtainedusing the
package surface temperatureto estimatethe die temperature
because this eliminatesthe variance associated with the θJA value.
5 V Tolerant Digital Inputs to GND1
Digital Output Voltage to GND
5.3 V
GND − 0.3 V to
DVDDIO + 0.3 V
−0.3 V to PVDD
to 0.3 V
The maximum junction temperature (TJ MAX)of 125°C must not
be exceeded. The following equation calculatesthe junction
temperature using the measuredpackage surface temperature
and applies only when no heat sinkis used on the device under
test (DUT):
XTAL Pins
Maximum Junction Temperature (TJ MAX
Storage Temperature
Infrared Reflow Soldering (20 sec)
)
125°C
150°C
260°C
TJ = TS + (ΨJT × WTOTAL
)
where:
1 The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL,
DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL,
DDCD_SDA, RXA_5V, RXB_5V, RXC_5V, RXD_5V, SHARED_EDID,
TS is the package surface temperature(°C).
ΨJT = 0.3°C/W for a 260-ball CSP_BGA.
,
PWRDN
WTOTAL = ((PVDD × IPVDD) + (0.05 × TVDD × ITVDD) + (CVDD ×
EP_MISO.
I
CVDD) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO)).
Stresses abovethoselisted under AbsoluteMaximumRatings
may cause permanent damageto the device. This is a stress
rating only; functionaloperation of the device at these orany
other conditions above thoseindicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Note that for WT O TA L , 5% of TVDD power is dissipated on the
part itself.
ESD CAUTION
Rev. C | Page 8 of 20
Data Sheet
ADV7614
PIN CONFIGURATIONAND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
B
GND
RXD_2– RXD_1– RXD_0– RXD_C–
GND
RXC_2– RXC_1–
RXC_2+ RXC_1+
RXC_0– RXC_C–
RXC_0+ RXC_C+
TVDD
RXB_2– RXB_1– RXB_0– RXB_C–
RXB_2+ RXB_1+ RXB_0+ RXB_C+
TVDD
TVDD
GND
A
B
C
D
E
F
RXD_5V RXD_2+ RXD_1+ RXD_0+ RXD_C+
TVDD
TVDD
TVDD
TVDD
RXA_2+
RXA_2–
PWRDN
TVDD
TVDD
CVDD
GND
TVDD
GND
GND
GND
GND
TVDD
CVDD
TVDD
GND
GND
GND
GND
RXA_1+
RXA_0+
RXA_1–
RXA_0–
C
D
DDCD_
SDA
DDCD_
SCL
DDCC_
SDA
DDCC_
SCL
DDCB_
SDA
DDCB_
SCL
DDCA_
SCL
DDCA_
SDA
RXC_5V RXB_5V RXA_5V
CVDD
RTERM
TVDD
GND
GND
GND
RXA_C+ RXA_C–
E
F
DE
HS
P1
CEC
NC
NC
VS_
FIELD
TVDD
GND
CVDD
EP_MISO EP_MOSI
P0
P2
EP_CS
NC
EP_SCK
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PVDD
GND
GND
GND
GND
GND
PVDD
GND
NC
NC
TEST1
NC
TEST2
NC
G
H
J
G
H
J
XTALP
PVDD
P3
GND
P4
SPDIF/
DSD0A/
DST
MCLK
OUT
GND
NC
GND
NC
GND
P5
DVDD
DVDD
DVDD
DVDD
GND
GND
XTALN
PVDD
NC
PVDD
PVDD
NC
LRCLK/
DSD2B/
DST_FF
SCLK/
DST_CLK
DVDD
DVDD
DVDD
PVDD
PVDD
PVDD
K
L
K
L
2
2
I S3/
I S2/
DSD2A/
HBR3
DSD1B/
HBR2
NC
NC
P6
P7
P8
GND
GND
GND
NC
NC
GND
GND
M
N
P
R
T
M
N
P
R
T
P9
DVDDIO DVDDIO DVDDIO
NC
PVDD
NC
NC
PVDD
NC
NC
NC
NC
NC
2
2
I S0/
I S1/
DSD0B/
HBR0
DSD1A/
HBR1
P10
P12
P14
P11
P13
P15
SHARED_
EDID
GND
GND
P19
GND
GND
P21
SCL
P25
P23
DVDDIO
DVDDIO
GND
INT1
SDA
P26
NC
DVDDIO
DVDDIO
P28
GND
GND
GND
NC
RESET
P31
NC
NC
GND
GND
GND
GND
NC
GND
NC
INT2
NC
NC
NC
NC
PVDD
NC
U
V
U
V
P16
P17
TEST3
P33
P35
PVDD
NC
GND
1
P18
2
P20
3
P22
4
P24
5
GND
6
P27
7
LLC
8
P29
9
GND
10
P30
11
P32
12
P34
13
GND
14
NC
15
NC
17
GND
18
16
NC = NO CONNECT. DO NOT CONENCT TO THIS PIN.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Description
Pin No. Mnemonic
Type
Ground
A1
GND
Ground.
A2
A3
A4
RXD_2−
RXD_1−
RXD_0−
RXD_C−
GND
HDMI input
HDMI input
HDMI input
HDMI input
Ground
Digital Input Channel 2 Complement of Port D in the HDMI Interface.
Digital Input Channel 1 Complement of Port D in the HDMI Interface.
Digital Input Channel 0 Complement of Port D in the HDMI Interface.
Digital Input Clock Complement of Port D in the HDMI Interface.
Ground.
A5
A6
A7
A8
RXC_2−
RXC_1−
RXC_0−
RXC_C−
TVDD
HDMI input
HDMI input
HDMI input
HDMI input
Power
Digital Input Channel 2 Complement of Port C in the HDMI Interface.
Digital Input Channel 1 Complement of Port C in the HDMI Interface.
Digital Input Channel 0 Complement of Port C in the HDMI Interface.
Digital Input Clock Complement of Port C in the HDMI Interface.
Terminator Supply Voltage (3.3 V ).
A9
A10
A11
A12
RXB_2−
HDMI input
Digital Input Channel 2 Complement of Port B in the HDMI Interface.
Rev. C | Page 9 of 20
ADV7614
Data Sheet
Description
Pin No. Mnemonic
Type
A13
A14
A15
A16
A17
A18
B1
RXB_1−
RXB_0−
RXB_C−
TVDD
HDMI input
HDMI input
HDMI input
Power
Digital Input Channel 1 Complement of Port B in the HDMI Interface.
Digital Input Channel 0 Complement of Port B in the HDMI Interface.
Digital Input Clock Complement of Port B in the HDMI Interface.
Terminator Supply Voltage (3.3 V).
TVDD
GND
Power
Ground
Terminator Supply Voltage (3.3 V).
Ground.
5 V Detect Pin for Port D in the HDMI Interface.
Digital Input Channel 2 True of Port D in the HDMI Interface.
Digital Input Channel 1 True of Port D in the HDMI Interface.
Digital Input Channel 0 True of Port D in the HDMI Interface.
Digital Input Clock True of Port D in the HDMI Interface.
Terminator Supply Voltage (3.3 V).
RXD_5V
RXD_2+
RXD_1+
RXD_0+
RXD_C+
TVDD
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
Power
B2
B3
B4
B5
B6
B7
RXC_2+
RXC_1+
RXC_0+
RXC_C+
TVDD
HDMI input
HDMI input
HDMI input
HDMI input
Power
Digital Input Channel 2 True of Port C in the HDMI Interface.
Digital Input Channel 1 True of Port C in the HDMI Interface.
Digital Input Channel 0 True of Port C in the HDMI Interface.
Digital Input Clock True of Port C in the HDMI Interface.
Terminator Supply Voltage (3.3 V).
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
C1
RXB_2+
RXB_1+
RXB_0+
RXB_C+
TVDD
RXA_2+
RXA_2−
PWRDN
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDMI input
HDMI input
Digital input
Digital Input Channel 2 True of Port B in the HDMI Interface.
Digital Input Channel 1 True of Port B in the HDMI Interface.
Digital Input Channel 0 True of Port B in the HDMI Interface.
Digital Input Clock True of Port B in the HDMI Interface.
Terminator Supply Voltage (3.3 V).
Digital Input Channel 2 True of Port A in the HDMI Interface.
Digital Input Channel 2 Complement of Port A in the HDMI Interface.
Active Low System Power Detect. If low, EDID can be powered from a 5 V signal
of the HDMI port when connected to active equipment.
C2
TVDD
Power
Terminator Supply Voltage (3.3 V ).
C3
TVDD
Power
Terminator Supply Voltage (3.3 V ).
C4
CVDD
Power
Comparator Supply Voltage (1.8 V).
C5
GND
Ground
Ground.
C6
TVDD
Power
Terminator Supply Voltage (3.3 V).
C7
TVDD
Power
Terminator Supply Voltage (3.3 V ).
C8
GND
Ground
Ground.
C9
GND
Ground
Ground.
C10
C11
C12
C13
C14
C15
C16
C17
C18
D1
GND
TVDD
Ground
Power
Ground.
Terminator Supply Voltage (3.3 V).
TVDD
GND
GND
GND
Power
Ground
Ground
Ground
Terminator Supply Voltage (3.3 V).
Ground.
Ground.
Ground.
GND
Ground
Ground.
RXA_1+
RXA_1−
RXC_5V
RXB_5V
RXA_5V
DDCD_SDA
DDCD_SCL
DDCC_SDA
DDCC_SCL
CVDD
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
HDMI input
Power
Digital Input Channel 1 True of Port A in the HDMI interface.
Digital Input Channel 1 Complement of Port A in the HDMI interface.
5 V Detect Pin for Port C in the HDMI Interface.
5 V Detect Pin for Port B in the HDMI Interface.
5 V Detect Pin for Port A in the HDMI Interface.
HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant.
Comparator Supply Voltage (1.8 V).
D2
D3
D4
D5
D6
D7
D8
D9
GND
Ground
Ground.
This pin sets internal termination resistance. Use a 500 Ω resistor between this
D10
RTERM
Miscellaneousanalog
pin and GND.
Rev. C | Page 10 of 20
Data Sheet
ADV7614
Description
Pin No. Mnemonic
Type
D11
D12
D13
D14
D15
D16
D17
D18
E1
CVDD
Power
Comparator Supply Voltage (1.8 V).
DDCB_SDA
DDCB_SCL
DDCA_SCL
DDCA_SDA
TVDD
HDMI input
HDMI input
HDMI input
HDMI input
Power
HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
Terminator Supply Voltage (3.3 V ).
RXA_0+
RXA_0−
DE
HDMI input
HDMI input
Digital Input Channel 0 True of Port A in the HDMI Interface.
Digital Input Channel 0 Complement of Port A in the HDMI Interface.
Digital video output Data Enable. DE is a signal that indicates active pixel data.
E2
CEC
Digital I/O
No connect
No connect
Ground
Ground
HDMI input
HDMI input
Consumer Electronic Control Channel.
E3
E4
NC
NC
GND
GND
RXA_C+
RXA_C−
HS
Do Not Connect.
Do Not Connect.
Ground.
Ground.
Digital Input Clock True of Port A in the HDMI Interface.
Digital Input Clock Complement of Port A in the HDMI Interface.
E15
E16
E17
E18
F1
Digital video output Horizontal Synchronization Output Signal in the HDMI Processor.
VS is a vertical synchronization output signal in the HDMI processor. FIELD is a
field synchronizationoutput signal in all interlaced video modes. VS or FIELD
can be configured for this pin.
F2
VS_FIELD
Digital video output
F3
F4
EP_MISO
EP_MOSI
GND
CVDD
TVDD
GND
P1
Digital input
Digital output
Ground
SPI Master Input/Slave Output for External EDID Interface.
SPI Master Output/Slave Input for External EDID Interface.
Ground.
Comparator Supply Voltage (1.8 V).
Terminator Supply Voltage (3.3 V).
Ground.
F15
F16
F17
F18
G1
Power
Power
Ground
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
G2
P0
G3
EP_CS
EP_SCK
GND
GND
GND
GND
PVDD
PVDD
NC
Digital output
Digital output
Ground
Ground
Ground
Ground
Power
SPI Chip Select for External EDID Interface.
G4
G7
G8
G9
SPI Clock for External EDID Interface.
Ground.
Ground.
Ground.
G10
G11
G12
G15
G16
G17
G18
H1
Ground.
PLL Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Do Not Connect.
Power
No connect
No connect
Test
NC
Do Not Connect.
Connect to GND through a 10 kΩ resistor.
Connect to GND through a 10 kΩ resistor.
TEST1
TEST2
P3
Test
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
H2
P2
H3
H4
H7
NC
NC
No connect
No connect
Ground
Do Not Connect.
Do Not Connect.
Ground.
GND
GND
GND
GND
GND
GND
XTALP
H8
H9
H10
H11
H12
H15
Ground
Ground
Ground
Ground
Ground.
Ground.
Ground.
Ground.
Ground
Ground.
This is the input pin for the 28.6363 MHz crystal, or it can be overdriven by an
external 1.8 V, 28.6363 MHz clock oscillator source to clock the ADV7614. A
crystal frequency of 24.576 MHz is also supported.
Miscellaneousanalog
H16
PVDD
Power
PLL Supply Voltage (1.8 V).
Rev. C | Page 11 of 20
ADV7614
Data Sheet
Description
Pin No. Mnemonic
Type
H17
H18
J1
NC
NC
GND
No connect
No connect
Ground
Do Not Connect.
Do Not Connect.
Ground.
J2
GND
Ground
Ground.
J3
J4
MCLKOUT
S/PDIF/DSD0A/DST
Digital output
Digital output
Audio Master Clock Output.
S/PDIF Digital Audio Output (S/PDIF).
First DSD Data Channel (DSD0A).
DST Stream (DST).
Digital Supply Voltage (1.8 V).
Ground.
Ground.
Ground.
Ground.
J7
J8
J9
J10
J11
J12
J15
DVDD
GND
GND
GND
GND
GND
XTALN
Power
Ground
Ground
Ground
Ground
Ground
Miscellaneousanalog
Ground.
This pin should be connected to the 28.6363 MHz crystal or left as a no connect
pin if an external 1.8 V, 28.6363 MHz clock oscillator source is used to clock the
ADV7614. In crystal mode, the crystal must be a fundamental crystal. A crystal
frequency of 24.576 MHz is also supported.
J16
J17
J18
K1
PVDD
GND
GND
P4
Power
Ground
Ground
PLL Supply Voltage (1.8 V).
Ground.
Ground.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
K2
P5
K3
LRCLK/DSD2B/DST_FF Digital output
Data Output Clock. Left and Right Audio Channels (LRCLK).
Sixth DSD Data Channel (DSD2B).
DST Frame (DST_FF).
K4
SCLK/DST_CLK
Digital output
Audio Serial Clock Output (SCLK).
DST Clock (DST_CLK).
K7
DVDD
Power
Digital Supply Voltage (1.8 V).
Digital Supply Voltage (1.8 V).
Ground.
K8
DVDD
Power
K9
GND
Ground
Ground
Ground
Power
Power
Power
K10
K11
K12
K15
K16
K17
K18
L1
GND
GND
PVDD
PVDD
Ground.
Ground.
PLL Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Do Not Connect.
PVDD
NC
NC
P6
P7
No connect
No connect
Do Not Connect.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
L2
L3
I2S3/DSD2A/HBR3
Digital output
I2S Audio (Channel 7 and Channel 8) (I2S3).
Fifth DSD Data Channel (DSD2A).
Fourth Block of HBR Stream (HBR3).
I2S Audio (Channel 5 and Channel 6) (I2S2).
Fourth DSD Data Channel (DSD1B).
Third Block of HBR Stream (HBR2).
Digital Supply Voltage (1.8 V).
Digital Supply Voltage (1.8 V).
Ground.
Ground.
Ground.
PLL Supply Voltage (1.8 V).
Do Not Connect.
Do Not Connect.
L4
I2S2/DSD1B/HBR2
Digital output
L7
L8
DVDD
DVDD
GND
GND
GND
PVDD
NC
Power
Power
L9
Ground
Ground
Ground
Power
L10
L11
L12
L15
L16
No connect
No connect
NC
Rev. C | Page 12 of 20
Data Sheet
ADV7614
Description
Pin No. Mnemonic
Type
L17
L18
M1
M2
M3
M4
M7
M8
M9
M10
M11
M12
M15
M16
M17
M18
N1
NC
NC
P8
No connect
No connect
Do Not Connect.
Do Not Connect.
Digital video output Video Pixel Output Port.
GND
GND
GND
DVDD
DVDD
GND
GND
GND
PVDD
NC
Ground
Ground
Ground
Power
Ground.
Ground.
Ground.
Digital Supply Voltage (1.8 V).
Digital Supply Voltage (1.8 V).
Ground.
Ground.
Ground.
PLL Supply Voltage (1.8 V).
Do Not Connect.
Do Not Connect.
Ground.
Power
Ground
Ground
Ground
Power
No connect
No connect
Ground
Ground
NC
GND
GND
P9
Ground.
Digital video output Video Pixel Output Port.
N2
N3
N4
N15
N16
N17
N18
P1
DVDDIO
DVDDIO
DVDDIO
NC
Power
Power
Power
No connect
No connect
No connect
No connect
Digital I/O Supply Voltage (3.3 V).
Digital I/O Supply Voltage (3.3 V).
Digital I/O Supply Voltage (3.3 V).
Do Not Connect.
NC
NC
NC
P10
Do Not Connect.
Do Not Connect.
Do Not Connect.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
Digital output
P2
P3
P11
I2S0/DSD0B/HBR0
I2S Audio (Channel 1 and Channel 2) (I2S0).
Second DSD Data Channel (DSD0B).
First Block of HBR Stream (HBR0).
I2S Audio (Channel 3 and Channel 4) (I2S1).
Third DSD Data Channel (DSD1A).
Second Block of HBR Stream (HBR1).
PLL Supply Voltage (1.8 V).
P4
I2S1/DSD1A/HBR1
Digital output
P15
P16
P17
P18
R1
PVDD
PVDD
NC
NC
P12
Power
Power
PLL Supply Voltage (1.8 V).
No connect
No connect
Do Not Connect.
Do Not Connect.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
R2
P13
R3
R4
R5
GND
GND
SCL
Ground
Ground
Digital I/O
Ground.
Ground.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz. SCL is the clock
line for the control port.
R6
R7
DVDDIO
INT1
Power
Digital output
Digital I/O Supply Voltage (3.3 V).
Interrupt Pin 1. This pin can be active low or active high. When status bits change,
this pin is triggered. The events that trigger an interrupt are underuser control.
R8
R9
R10
R11
R12
NC
DVDDIO
GND
No connect
Power
Ground
Do Not Connect.
Digital I/O Supply Voltage (3.3 V).
Ground.
NC
No connect
Digital input
Do Not Connect.
EDID Flag. When high, all four HDMI ports share a common EDID. When low,
Port D does not share a common EDID; Port D operates with a separate EDID.
SHARED_EDID
R13
R14
R15
NC
GND
NC
No connect
Ground
No connect
Do Not Connect.
Ground.
Do Not Connect.
Rev. C | Page 13 of 20
ADV7614
Data Sheet
Description
Pin No. Mnemonic
Type
R16
R17
R18
T1
NC
No connect
Ground
Ground
Do Not Connect.
Ground.
Ground.
GND
GND
P14
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
T2
P15
T3
T4
T5
GND
GND
P25
Ground
Ground
Ground.
Ground.
Digital video output Video Pixel Output Port.
T6
T7
T8
DVDDIO
SDA
INT2
Power
Digital I/O
Digital output
Digital I/O Supply Voltage (3.3 V).
I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
Interrupt Pin 2. This pin canbe active low or activehigh. When statusbits change,
this pin is triggered. The events that trigger an interrupt are underuser control.
T9
T10
T11
DVDDIO
GND
RESET
NC
NC
GND
NC
NC
NC
NC
Power
Ground
Digital input
Digital I/O Supply Voltage (3.3 V).
Ground.
Chip Reset. Active low. The minimum low time for a reset to take place is 5 ms.
T12
T13
T14
T15
T16
T17
T18
U1
U2
U3
U4
U5
No connect
No connect
Ground
Do Not Connect.
Do Not Connect.
Ground.
No connect
No connect
No connect
No connect
Do Not Connect.
Do Not Connect.
Do Not Connect.
Do Not Connect.
P16
P17
P19
P21
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
P23
U6
U7
GND
P26
Ground
Ground.
Digital video output Video Pixel Output Port.
U8
U9
TEST3
P28
Test
Connect to GND through a 10 kΩ resistor.
Digital video output Video Pixel Output Port.
U10
U11
U12
U13
U14
U15
U16
U17
U18
V1
GND
P31
P33
Ground
Ground.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
P35
GND
NC
PVDD
PVDD
NC
GND
P18
P20
Ground
No connect
Power
Ground.
Do Not Connect.
PLL Supply Voltage (1.8 V).
PLL Supply Voltage (1.8 V).
Do Not Connect.
Ground.
Power
No connect
Ground
V2
V3
V4
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
P22
V5
P24
V6
V7
GND
P27
Ground
Ground.
Digital video output Video Pixel Output Port.
V8
V9
LLC
P29
Digital video output Line-Locked Output Clock for the Pixel Data (Range Is 13.5 MHz to 170 MHz).
Digital video output Video Pixel Output Port.
V10
V11
V12
V13
GND
P30
P32
Ground
Ground.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
Digital video output Video Pixel Output Port.
P34
Rev. C | Page 14 of 20
Data Sheet
ADV7614
Description
Pin No. Mnemonic
Type
V14
V15
V16
V17
V18
GND
NC
NC
Ground
Ground.
No connect
No connect
No connect
Ground
Do Not Connect.
Do Not Connect.
Do Not Connect.
Ground.
NC
GND
Rev. C | Page 15 of 20
ADV7614
Data Sheet
FUNCTIONALOVERVIEW
A fully programmable any-to-any 3 × 3 color space conversion
(CSC) matrix is placed between the HDMIprocessor and the
CPsection. This enables YCrCb-to-RGB and YCrCb-to-RGB
conversions. Many other standardsof color space can be
implemented using the color space converter.
HDMI RECEIVER
The HDMI receiver on the ADV7614 incorporates active
equalization of the HDMI data signals. This equalization
compensates for the high frequency lossesinherent in HDMI
and DVI cabling, especially at longer lengths and higher
frequencies. The equalizationis programmable. It is capable
of equalizing for cable lengths up to 30 meters to achieve robust
receiver performance at even the highest HDMIdata rates. The
HDMIreceiver supportsallHDTV formats up to 1080p and all
display resolutionsup to UXGA(1600 × 1200 at 60 Hz).
CP PIXEL DATA OUTPUT MODES
The output section of the CPis highly flexible. It can be confi-
gured in an SDR mode with one data packet perclock cycle
or in a DDR mode wheredata is presented on the rising and
falling edge of the clock. In SDR mode, a 16-/20-/24-bit 4:2:2 or
24-/30-/36-bit 4:4:4 output is possible.In these modes, the HS,
VS, FIELD, and DE(where applicable)timing referencesignals
are provided. In DDR mode, the ADV7614 can beconfiguredin
an 8-/10-/12-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/YCrCb pixel
output interface with corresponding timing signals.
With the inclusionofHDCP, displayscan receiveencryptedvideo
content. The HDMI interface of the ADV7614 allows for authen-
tication of a video receiver, decryption of encoded dataat the
receiver, andrenewabilityofthat authentication during transmis-
sion as specified by the HDCP1.3protocol.
I2C INTERFACE
The HDMIreceiver offersadvanced audio functionality. It sup-
ports multichannel I2S audio for up to eight channels. It also
supportsa six-DSD channel interface with eachchannel carrying
an oversampled 1-bit representation of the audiosignalas
delivered on SACD. It incorporates a DST interfacethat outputs
audio data decoded from DST audio packets.The ADV7614
can also receive HBR audio packet streams and outputs them
through the HBR interface in an S/PDIF format conforming to
the IEC60958 standard. It supports multichannelI2S audio for
up to eight channels. The receiver also contains an audio mute
controller that can detect a variety of conditions that may result
in audible extraneous noisein the audio output. On detection of
these conditions, the audio datacan be ramped to prevent audio
clicks or pops.
The ADV7614 supports a 2-wire serial (I2C-compatible)
microprocessor busdriving multiple peripherals. The
ADV7614 is controlled by an external I2C master device,
such as a microcontroller.
OTHER FEATURES
In addition toHS,VS, andFIELDoutput signals withprogramma-
ble position, polarity, and width, the ADV7614 provides the
following:
•
•
Programmable interrupt request outputpins: INT1 and INT2
Low power consumption: 1.8V digital core, 3.3V digital
input/output, low powerpower-down mode, and green
PC mode
COMPONENTPROCESSOR (CP)
•
15 mm × 15 mm, RoHS-compliant BGA package
The video standardssupported by the CP are525i, 625i, 525p,
625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz,
and many other standards.
For more detailed product information about the ADV7614,
contact a local Analog Devices, Inc., sales office.
Automaticadjustmentswithin the CPinclude gain (contrast)
and offset (brightness); manualadjustment controls arealso
supported.
Rev. C | Page 16 of 20
Data Sheet
ADV7614
OUTLINEDIMENSIONS
15.10
15.00 SQ
14.90
A1 BALL
CORNER
A1 BALL
CORNER
18 16 14 12 10
17 15 13 11
8
6
4
2
9
7
5
3
1
A
B
C
D
F
E
13.60
BSC SQ
G
H
J
L
0.80
BSC
K
M
P
T
N
R
U
V
TOP VIEW
DETAIL A
BOTTOM VIEW
DETAIL A
1.11
1.01
0.91
1.50
1.36
1.21
0.35 NOM
0.30 MIN
0.50
0.45
0.40
COPLANARITY
0.12
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-KKAA-1.
Figure 6. 260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-260-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
−40°C to +70°C
Package Description
Package Option
BC-260-1
ADV7614BBCZ
EVAL-ADV7614EB1Z
260-Ball Chip Scale Package Ball GridArray [CSP_BGA]
ADV7614BBCZ Front-End Evaluation Board
1 Z = RoHS Compliant Part.
2 The ADV7614BBCZ is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing
requirements) to purchase any components with internal HDCP keys.
Rev. C | Page 17 of 20
ADV7614
NOTES
Data Sheet
Rev. C | Page 18 of 20
Data Sheet
NOTES
ADV7614
Rev. C | Page 19 of 20
ADV7614
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and
other countries.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08186-0-9/13(C)
Rev. C | Page 20 of 20
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