ADUM5201ARWZ-RL [ADI]
Dual-Channel, 2.5 kV Isolators with Integrated DC-to-DC Converter; 双通道， 2.5千伏隔离带集成DC - DC转换器
| 型号： | ADUM5201ARWZ-RL |
| 厂家： | 
ADI |
| 描述： | Dual-Channel, 2.5 kV Isolators with Integrated DC-to-DC Converter |
| 文件： | 总28页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual-Channel, 2.5 kV Isolators with
Integrated DC-to-DC Converter
Data Sheet
ADuM5200/ADuM5201/ADuM5202
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
isoPower integrated, isolated dc-to-dc converter
Regulated 3.3 V or 5 V output
Up to 500 mW output power
Dual, dc-to-25 Mbps (NRZ) signal isolation channels
16-lead SOIC package with 7.6 mm creepage
High temperature operation: 105°C maximum
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
OSC
RECT
REG
1
2
3
4
5
6
7
8
16
15
14
13
V
V
ISO
DD1
GND
GND
ISO
1
V
/V
IA OA
V /V
IA OA
2-CHANNEL iCOUPLER CORE
V
/V
IB OB
V /V
IB OB
RC
12 NC
IN
RC
11
10
9
V
V
SEL
SEL
ADuM5200/
ADuM5201/
ADuM5202
UL recognition
V
/NC
/NC
E1
GND
E2
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A)
VDE certificate of conformity (pending)
IEC 60747-5-2 (VDE 0884, Part 2):2003-01
GND
ISO
1
Figure 1.
V
IORM = 560 VPEAK
V
V
V
V
IA
IB
OA
OB
3
4
14
13
APPLICATIONS
ADuM5200
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Power supply start-up bias and gate drives
Isolated sensor interfaces
Figure 2. ADuM5200
Industrial PLCs
V
V
V
IA
OA
IB
3
4
14
13
GENERAL DESCRIPTION
ADuM5201
V
OB
The ADuM5200/ADuM5201/ADuM52021 are dual-channel digital
isolators with isoPower®, an integrated, isolated dc-to-dc converter.
Based on the Analog Devices, Inc., iCoupler® technology, the
dc-to-dc converter provides up to 500 mW of regulated, isolated
power at either 5.0 V or 3.3 V from a 5.0 V input supply, or 3.3 V
from a 3.3 V supply at the power levels shown in Table 1. These
devices eliminate the need for a separate, isolated dc-to-dc converter
in low power isolated designs. The iCoupler chip scale transformer
technology is used to isolate the logic signals and for the magnetic
components of the dc-to-dc converter. The result is a small form
factor, total isolation solution.
Figure 3. ADuM5201
V
V
V
V
OA
IA
IB
3
4
14
13
ADuM5202
OB
Figure 4. ADuM5202
Table 1. Power Levels
Input Voltage (V) Output Voltage (V) Output Power (mW)
The ADuM5200/ADuM5201/ADuM5202 isolators provide two
independent isolation channels in a variety of channel configurations
and data rates (see the Ordering Guide for more information).
5.0
5.0
3.3
5.0
3.3
3.3
500
330
200
isoPower uses high frequency switching elements to transfer power
through its transformer. Special care must be taken during printed
circuit board (PCB) layout to meet emissions standards. See the
AN-0971 Application Note for board layout recommendations.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009-2012 Analog Devices, Inc. All rights reserved.
ADuM5200/ADuM5201/ADuM5202
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configurations and Function Descriptions......................... 12
Truth Table .................................................................................. 14
Typical Performance Characteristics ........................................... 15
Terminology.................................................................................... 18
Applications Information .............................................................. 19
PCB Layout ................................................................................. 19
Start-Up Behavior....................................................................... 19
EMI Considerations................................................................... 20
Propagation Delay Parameters ................................................. 20
DC Correctness and Magnetic Field Immunity.......................... 20
Power Consumption .................................................................. 21
Current Limit and Thermal Overload Protection ................. 22
Power Considerations................................................................ 22
Thermal Analysis ....................................................................... 23
Increasing Available Power ....................................................... 23
Insulation Lifetime..................................................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Primary Input Supply/
5 V Secondary Isolated Supply ................................................... 3
Electrical Characteristics—3.3 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 5
Electrical Characteristics—5 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 7
Package Characteristics ............................................................... 9
Regulatory Information............................................................... 9
Insulation and Safety-Related Specifications............................ 9
IEC 60747-5-2 (VDE 0884, Part 2):2003-01 Insulation
Characteristics ............................................................................ 10
Recommended Operating Conditions .................................... 10
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
REVISION HISTORY
5/12—Rev. A to Rev. B
Changes to Pin 5 Description, Table 22....................................... 13
Changes to Pin 5 Description, Table 23 and Table 24 ............... 14
Changes to Figure 9 to Figure 11.................................................. 15
Added Figure 17 and Figure 18; Renumbered Sequentially ..... 16
Changes to Figure 19 and Figure 20 ............................................ 16
Changes to Terminology Section ................................................. 18
Changes to Applications Information Section ........................... 19
Added Start-Up Behavior Section................................................ 19
Changes to EMI Considerations Section .................................... 20
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Updated Outline Dimensions....................................................... 25
9/11—Rev. 0 to Rev. A
Changes to Product Title, Features Section, and General
Description Section.......................................................................... 1
Added Table 1; Renumbered Sequentially .................................... 1
Changes to Specifications Section.................................................. 3
Changes to Table 19 and Table 20 ................................................ 11
Changes to Pin 5 Description, Table 21....................................... 12
10/08—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. DC-to-DC Converter Static Specifications
Parameter
Symbol
Min Typ Max
Unit
Test Conditions
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PW Modulation Frequency
Output Supply
VISO
4.7
5.0
1
1
5.4
5
V
IISO = 0 mA
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
IISO = 10 mA to 90 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 90 mA
CBO = 0.1 µF||10 µF, IISO = 90 mA
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
mV/V
%
75
mV p-p
mV p-p
MHz
kHz
mA
200
180
625
fPWM
IISO (MAX)
100
VISO > 4.5 V
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
34
8
290
%
mA
mA
IISO = 100 mA
IDD1 (Q)
IDD1 (MAX)
22
Table 3. DC-to-DC Converter Dynamic Specifications
1 Mbps—A Grade or C Grade
25 Mbps—C Grade
Parameter
SUPPLY CURRENT
Input
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions
No VISO load
ADuM5200
ADuM5201
ADuM5202
Available to Load
ADuM5200
ADuM5201
ADuM5202
IDD1
IDD1
IDD1
6
7
7
34
38
41
mA
mA
mA
IISO (LOAD)
IISO (LOAD)
IISO (LOAD)
100
100
100
94
92
90
mA
mA
mA
Table 4. Switching Specifications
A Grade
Typ
C Grade
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
1
100
40
25
60
6
Mbps
ns
ns
ps/°C
ns
ns
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
tPHL, tPLH
PWD
55
45
5
PW
tPSK
1000
40
Within PWD limit
Between any two units
Propagation Delay Skew
Channel Matching
Codirectional1
50
15
tPSKCD
tPSKOD
50
50
6
15
ns
ns
Opposing Directional2
1
7
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
Rev. B | Page 3 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
Table 5. Input and Output Characteristics
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIH
VIL
VOH
0.7 VISO or 0.7 VDD1
V
V
V
V
V
V
0.3 VISO or 0.3 VDD1
VDD1 − 0.3 or VISO − 0.3 5.0
VDD1 − 0.5 or VISO − 0.5 4.8
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDDL, VISO supplies
Logic Low Output Voltages
VOL
0.0
0.2
0.1
0.4
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity1
VUV+
VUV−
VUVH
II
2.7
2.4
0.3
V
V
V
µA
−20
25
+0.01 +20
0 V ≤ VIx ≤ VDDx
10% to 90%
tR/tF
|CM|
2.5
35
ns
kV/µs VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
fr
1.0
Mbps
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 4 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range which is 3.0 V ≤ VDD1, VSEL, VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. DC-to-DC Converter Static Specifications
Parameter
Symbol
Min Typ Max
Unit
Test Conditions
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PW Modulation Frequency
Output Supply
VISO
3.0
3.3
1
1
3.6
5
V
IISO = 0 mA
IISO = 30 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to 54 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 54 mA
CBO = 0.1 µF||10 µF, IISO = 54 mA
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
mV/V
%
50
mV p-p
mV p-p
MHz
kHz
mA
130
180
625
fPWM
IISO (MAX)
60
VISO > 3 V
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
34
6
175
%
mA
mA
IISO = 60 mA
IDD1 (Q)
IDD1 (MAX)
15
Table 7. DC-to-DC Converter Dynamic Specifications
1 Mbps—A Grade or C Grade
25 Mbps—C Grade
Parameter
SUPPLY CURRENT
Input
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions
No VISO load
ADuM5200
ADuM5201
ADuM5202
Available to Load
ADuM5200
ADuM5201
ADuM5202
IDD1
IDD1
IDD1
4
4
5
23
25
27
mA
mA
mA
IISO (LOAD)
IISO (LOAD)
IISO (LOAD)
60
60
60
56
55
54
mA
mA
mA
Table 8. Switching Specifications
A Grade
Typ
C Grade
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
1
100
40
25
60
6
Mbps
ns
ns
ps/°C
ns
ns
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
tPHL, tPLH
PWD
60
45
5
PW
tPSK
1000
40
Within PWD limit
Between any two units
Propagation Delay Skew
Channel Matching
Codirectional1
50
45
tPSKCD
tPSKOD
50
50
6
15
ns
ns
Opposing Directional2
1
7
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
Rev. B | Page 5 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
Table 9. Input and Output Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Logic High Input Threshold VIH
Logic Low Input Threshold VIL
Logic High Output Voltages VOH
0.7 VISO or 0.7 VDD1
V
V
V
V
V
V
0.3 VISO or 0.3 VDD1
VDD1 − 0.3 or VISO − 0.3
VDD1 − 0.5 or VISO − 0.5
3.3
3.1
0.0
0.0
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDDL, VISO supplies
Logic Low Output Voltages VOL
0.1
0.4
Undervoltage Lockout
Positive Going Threshold VUV+
Negative Going Threshold VUV−
2.7
2.4
0.3
V
V
V
Hysteresis
VUVH
Input Currents per Channel II
AC SPECIFICATIONS
−20
25
+0.01 +20
µA
0 V ≤ VIx ≤ VDDx
10% to 90%
Output Rise/Fall Time
tR/tF
2.5
35
ns
Common-Mode Transient
Immunity1
|CM|
kV/µs VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
fr
1.0
Mbps
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 6 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the
entire recommended operation range which is 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise
noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 10. DC-to-DC Converter Static Specifications
Parameter
Symbol
Min Typ Max
Unit
Test Conditions
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PW Modulation Frequency
Output Supply
VISO
3.0
3.3
1
1
3.6
5
V
IISO = 0 mA
IISO = 50 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to 54 mA
20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 90 mA
CBO = 0.1 µF||10 µF, IISO = 90 mA
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
mV/V
%
50
mV p-p
mV p-p
MHz
kHz
mA
130
180
625
fPWM
IISO (MAX)
100
VISO > 3 V
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
30
5
230
%
mA
mA
IISO = 90 mA
IDD1 (Q)
IDD1 (MAX)
15
Table 11. DC-to-DC Converter Dynamic Specifications
1 Mbps—A Grade or C Grade
25 Mbps—C Grade
Parameter
SUPPLY CURRENT
Input
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions
No VISO load
ADuM5200
ADuM5201
ADuM5202
Available to Load
ADuM5200
ADuM5201
ADuM5202
IDD1
IDD1
IDD1
5
5
5
22
23
24
mA
mA
mA
IISO (LOAD)
IISO (LOAD)
IISO (LOAD)
100
100
100
96
95
94
mA
mA
mA
Table 12. Switching Specifications
A Grade
Typ
C Grade
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
1
100
40
25
60
6
Mbps
ns
ns
ps/°C
ns
ns
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
tPHL, tPLH
PWD
60
45
5
PW
tPSK
1000
40
Within PWD limit
Between any two units
Propagation Delay Skew
Channel Matching
Codirectional1
50
15
tPSKCD
tPSKOD
50
50
6
15
ns
ns
Opposing Directional2
1
7
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
Rev. B | Page 7 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
Table 13. Input and Output Characteristics
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
VIH
VIL
0.7 VISO or 0.7 VDD1
V
V
V
V
0.3 VISO or 0.3 VDD1
Logic High Output Voltages VOH
VDD1 − 0.2, VISO − 0.2 VDD1 or VISO
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
VDD1 − 0.5 or
ISO − 0.5
VDD1 − 0.2 or
VISO − 0.2
V
Logic Low Output Voltages
VOL
0.0
0.0
0.1
0.4
V
V
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDDL, VISO supplies
Undervoltage Lockout
Positive Going Threshold
VUV+
2.7
V
Negative Going Threshold VUV−
Hysteresis VUVH
2.4
0.3
V
V
Input Currents per Channel II
AC SPECIFICATIONS
−20
25
+0.01
+20
μA
0 V ≤ VIx ≤ VDDx
10% to 90%
Output Rise/Fall Time
tR/tF
2.5
35
ns
Common-Mode Transient
Immunity1
|CM|
kV/μs VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
fr
1.0
Mbps
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 8 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
PACKAGE CHARACTERISTICS
Table 14. Thermal and Isolation Characteristics
Parameter
Symbol Min Typ Max Unit Test Conditions
RESISTANCE AND CAPACITANCE
Resistance (Input-to-Output)1
Capacitance (Input-to-Output)1
Input Capacitance2
RI-O
CI-O
CI
102
2.2
4.0
45
Ω
pF
pF
f = 1 MHz
IC Junction to Ambient Thermal Resistance θJA
°C/W Thermocouple located at the center of the package
underside; test conducted on a 4-layer board with
thin traces 3
THERMAL SHUTDOWN
Threshold
Hysteresis
TSSD
TSSD-HYS
150
20
°C
°C
TJ rising
1 This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
3 Refer to the Power Considerations section for thermal model definitions.
REGULATORY INFORMATION
The ADuM5200/ADuM5201/ADuM5202 are approved by the organizations listed in Table 15. Refer to Table 20 and the Insulation Lifetime
section for more information about the recommended maximum working voltages for specific cross-insulation waveforms and insulation levels.
Table 15.
UL1
CSA
VDE (Pending)2
Recognized under UL 1577 component
recognition program1
Approved under CSA Component
Acceptance Notice #5A
Certified according to IEC 60747-5-2
(VDE 0884, Part 2):2003-012
Single protection, 2500 V rms
isolation voltage
Testing was conducted per CSA 60950-1-07
Basic insulation, 560 VPEAK
and IEC 60950-1 2nd Ed. at 2.5 kV rated voltage
Basic insulation at 600 V rms (848 VPEAK
)
working voltage
Reinforced insulation at 250 V rms (353 VPEAK
working voltage
)
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM5200/ADuM5201/ADuM5202 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage
detection limit = 10 μA).
2 In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM520x is proof tested by applying an insulation test voltage ≥ 1590 VPEAK for 1 second (partial
discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884, Part 2):2003-01 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 16. Critical Safety-Related Dimensions and Material Properties
Parameter
Symbol Value
Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage
Minimum External Air Gap
2500
8.0
V rms 1-minute duration
L(I01)
L(I02)
mm
Distance measured from input terminals to output
terminals; shortest distance through air along the
PCB mounting plane, as an aid to PC board layout
Minimum External Tracking (Creepage)
7.6
mm
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Distance (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017 min mm
Distance through insulation
DIN IEC 112/VDE 0303, Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
CTI
>175
IIIa
V
Rev. B | Page 9 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
the protective circuits. The asterisk (*) marking branded on the components designates IEC 60747-5-2 (VDE 0884, Part 2):2003-1 approval.
Table 17. VDE Characteristics
Description
Conditions
Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
I to IV
I to III
I to II
40/105/21
2
VIORM
560
1050
VPEAK
VPEAK
VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = Vpd (m)
1 sec, partial discharge < 5 pC
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
Vpd (m)
Vpd (m)
840
672
VPEAK
VPEAK
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Withstand Isolation Voltage
Surge Isolation Voltage
VIOTM
VISO
VIOSM
4000
2500
6000
VPEAK
VRMS
VPEAK
1 minute withstand rating
VPEAK = 6 kV, 1.2 µs rise time, 50 µs, 50% fall time
Safety Limiting Values
Maximum value allowed in the event of a failure
(see Figure 5)
Case Temperature
Side 1 IDD1 Current
Insulation Resistance at TS
TS
IS1
RS
150
555
>109
°C
mA
Ω
VIO = 500 V
600
500
400
300
200
100
0
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 18.
Parameter
Symbol
Min
Max
Unit
Operating Temperature1
Supply Voltages2
VDD1 @ VSEL = 0 V
VDD1 @ VSEL = VISO
TA
−40
+105
°C
VDD1
VDD1
3.0
4.5
5.5
5.5
V
V
1 Operation at 105°C requires reduction of the maximum load current as specified in Table 19.
2 Each voltage is relative to its respective ground.
Rev. B | Page 10 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 19.
Parameter
Rating
Storage Temperature Range (TST)
Ambient Operating Temperature
−55°C to +150°C
−40°C to +105°C
Range (TA)
Supply Voltages (VDD1, VISO
Input Voltage (VIA, VIB, RCIN, RCSEL, VSEL)1, 2 −0.5 V to VDDI + 0.5 V
1
)
−0.5 V to +7.0 V
Output Voltage (VOA, VOB)1, 2
Average Output Current per Pin3
Common-Mode Transients4
−0.5 V to VDDO + 0.5 V
−10 mA to +10 mA
−100 kV/µs to +100 kV/µs
ESD CAUTION
1 Each voltage is relative to its respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PCB Layout section.
3 See Figure 5 for maximum rated current values for various temperatures.
4 Common-mode transients exceeding the absolute maximum slew rate may
cause latch-up or permanent damage.
Table 20. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1
Parameter
Max
Unit
Applicable Certification
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
424
VPEAK
All certifications, 50-year operation
600
353
VPEAK
VPEAK
Working voltage, 50-year operation
Working voltage per IEC 60950-1
Basic Insulation
Reinforced Insulation
600
353
VPEAK
VPEAK
Working voltage, 50-year operation
Working voltage per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
Rev. B | Page 11 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
16
V
ISO
DD1
GND
15 GND
1
IA
IB
IN
ISO
V
V
14
13
V
V
OA
ADuM5200
OB
TOP VIEW
(Not to Scale)
RC
12 NC
RC
11
10
9
V
V
SEL
NC
SEL
E2
GND
GND
ISO
1
NC = NO CONNECT
Figure 6. ADuM5200 Pin Configuration
Table 21. ADuM5200 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8
GND1
Ground 1. Ground reference for the isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and
it is recommended that both pins be connected to a common ground.
3
4
5
VIA
VIB
RCIN
Logic Input A.
Logic Input B.
Regulation Control Input. This pin must be connected to the RCOUT pin of a master isoPower device or tied low. Note
that this pin must not be tied high if RCSEL is low; this combination causes excessive voltage on the secondary side,
damaging the ADuM5200 and possibly the devices that it powers.
6
RCSEL
Control Input. Determines self-regulation mode (RCSEL high) or slave mode (RCSEL low), allowing external regulation.
This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low.
7, 12
9, 15
NC
GNDISO
No Internal Connection.
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended
that both pins be connected to a common ground.
10
11
VE2
Data Enable Input. When this pin is high or not connected, the secondary outputs are active; when this pin is low,
the outputs are in a high-Z state.
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
In slave regulation mode, this pin has no function.
VSEL
13
14
16
VOB
VOA
VISO
Logic Output B.
Logic Output A.
Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.
Rev. B | Page 12 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
V
1
2
3
4
5
6
7
8
16
V
ISO
DD1
GND
15 GND
1
ISO
V
14
13
V
V
IA
OA
ADuM5201
V
OB
IB
TOP VIEW
(Not to Scale)
RC
12 NC
IN
RC
11
10
9
V
V
SEL
SEL
V
E1
E2
GND
GND
1
ISO
NC = NO CONNECT
Figure 7. ADuM5201 Pin Configuration
Table 22. ADuM5201 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8
GND1
Ground 1. Ground reference for isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and it is
recommended that both pins be connected to a common ground.
3
4
5
VIA
VOB
RCIN
Logic Input A.
Logic Output B.
Regulation Control Input. This pin must be connected to the RCOUT pin of a master isoPower device or tied low. Note
that this pin must not be tied high if RCSEL is low; this combination causes excessive voltage on the secondary side,
damaging the ADuM5201 and possibly the devices that it powers.
6
RCSEL
VE1
Control Input. Determines self-regulation mode (RCSEL high) or slave mode (RCSEL low), allowing external regulation.
This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low.
Data Enable Input. When this pin is high or not connected, the primary output is active; when this pin is low, the
output is in a high-Z state.
7
9, 15
10
11
GNDISO
VE2
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended
that both pins be connected to a common ground.
Data Enable Input. When this pin is high or not connected, the secondary output is active; when this pin is low, the
output is in a high-Z state.
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
In slave regulation mode, this pin has no function.
VSEL
12
13
14
16
NC
VIB
VOA
VISO
No Internal Connection.
Logic Input B.
Logic Output A.
Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.
Rev. B | Page 13 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
V
1
2
3
4
5
6
7
8
16
V
ISO
DD1
GND
15 GND
1
OA
OB
ISO
V
V
14
13
V
V
IA
IB
ADuM5202
TOP VIEW
(Not to Scale)
RC
12 NC
11
10 NC
GND
IN
RC
V
SEL
SEL
V
E1
GND
9
1
ISO
NC = NO CONNECT
Figure 8. ADuM5202 Pin Configuration
Table 23. ADuM5202 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8
GND1
Ground 1. Ground reference for the isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and
it is recommended that both pins be connected to a common ground.
3
4
5
VOA
VOB
RCIN
Logic Output A.
Logic Output B.
Regulation Control Input. This pin must be connected to the RCOUT pin of a master isoPower device or tied low. Note
that this pin must not be tied high if RCSEL is low; this combination causes excessive voltage on the secondary side,
damaging the ADuM5202 and possibly the devices that it powers.
6
RCSEL
VE1
Control Input. Determines self-regulation mode (RCSEL high) or slave mode (RCSEL low), allowing external regulation.
This pin is weakly pulled to the high state. In noisy environments, tie this pin either high or low.
Data Enable Input. When this pin is high or not connected, the primary output is active; when this pin is low, the
output is in a high-Z state.
7
9, 15
GNDISO
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended
that both pins be connected to a common ground.
10, 12 NC
No Internal Connection.
11
VSEL
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
In slave regulation mode, this pin has no function.
13
14
16
VIB
VIA
VISO
Logic Input B.
Logic Input A.
Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.
TRUTH TABLE
Table 24. Power Section Truth Table (Positive Logic)1
RCSEL RCIN VSEL VDD1
Input Input
Input Input (V)2
VISO (V) Operation
H
H
H
H
L
X
X
X
X
H
L
H
L
L
H
X
X
X
5.0
5.0
3.3
3.3
X
5.0
3.3
3.3
5.0
X
Self regulation mode, normal operation.
Self regulation mode, normal operation.
Self regulation mode, normal operation.
This supply configuration is not recommended due to extremely poor efficiency.
Part runs at maximum open-loop voltage; therefore, damage can occur.
Power supply is disabled.
L
X
0
L
RCOUT(EXT)
X
X
Slave mode, RCOUT(EXT) supplied by a master isoPower device.
1 H refers to a high logic, L refers to a low logic, and X is don’t care or unknown.
2 VDD1 must be common between all isoPower devices being regulated by a master isoPower part.
Rev. B | Page 14 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
TYPICAL PERFORMANCE CHARACTERISTICS
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
40
35
30
25
20
15
10
POWER
DISSIPATION
I
DD
3.3V INPUT/3.3V OUTPUT
5
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
0.08 0.10
0
0
0.02
0.04
0.06
0.12
3.0
3.5
4.0
V
4.5
5.0
5.5
6.0
OUTPUT CURRENT (A)
(V)
DD1
Figure 9. Typical Power Supply Efficiency
in All Supported Power Configurations
Figure 12. Typical Short-Circuit Input Current and Power
vs. VDD1 Supply Voltage
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
90% LOAD
V
V
V
= 5V, V
= 5V, V
= 3.3V, V
= 5V
= 3.3V
ISO
ISO
DD1
DD1
DD1
10% LOAD
(100µs/DIV)
= 3.3V
ISO
0
0.02
0.04
0.06
(A)
0.08
0.10
0.12
I
ISO
Figure 10. Typical Total Power Dissipation vs. Isolated Output Supply Current
in All Supported Power Configurations
Figure 13. Typical VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
0.12
0.10
0.08
0.06
0.04
90% LOAD
0.02
10% LOAD
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
0.20 0.25 0.30
INPUT CURRENT (A)
0
(100µs/DIV)
0
0.05
0.10
0.15
0.35
Figure 11. Typical Isolated Output Supply Current vs. Input Current
in All Supported Power Configurations
Figure 14. Typical VISO Transient Load Response, 3 V Output,
10% to 90% Load Step
Rev. B | Page 15 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
5
25
BW = 20MHz
20
15
10
5
4
3
2
1
0
10% LOAD
90% LOAD
0
–5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME (ms)
TIME (µs)
Figure 18. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 3.3 V
Figure 15. Typical Output Voltage Ripple at 90% Load, VISO = 5 V
16
20
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
BW = 20MHz
14
16
12
8
12
10
8
6
4
4
2
0
0
0
5
10
15
20
25
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
DATA RATE (Mbps)
TIME (µs)
Figure 16. Typical Output Voltage Ripple at 90% Load, VISO = 3.3 V
Figure 19. Typical ICHn Supply Current per Forward Data Channel
(15 pF Output Load)
7
20
10% LOAD
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
16
6
5
12
8
4
90% LOAD
3
2
1
0
4
0
0
5
10
15
20
25
–1
0
1
2
3
DATA RATE (Mbps)
TIME (ms)
Figure 20. Typical ICHn Supply Current per Reverse Data Channel
(15 pF Output Load)
Figure 17. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 5 V
Rev. B | Page 16 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
5
4
3
2
1
3.0
2.5
2.0
1.5
1.0
0.5
0
5V
5V
3.3V
3.3V
0
0
5
10
15
20
25
0
5
10
15
20
25
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 21. Typical IISO (D) Dynamic Supply Current per Input
Figure 22. Typical IISO (D) Dynamic Supply Current per Output
(15 pF Output Load)
Rev. B | Page 17 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
TERMINOLOGY
IDD1 (Q)
tPLH Propagation Delay
tPLH propagation delay is measured from the 50% level of the
I
DD1 (Q) is the minimum operating current drawn at the VDD1
pin when there is no external load at VISO and the I/O pins are
operating below 2 Mbps, requiring no additional dynamic
supply current. IDD1 (Q) reflects the minimum current operating
condition.
rising edge of the VIx signal to the 50% level of the rising edge
of the VOx signal.
Propagation Delay Skew, tPSK
tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH
IDD1 (D)
that is measured between units at the same operating temperature,
supply voltages, and output load within the recommended
operating conditions.
I
DD1 (D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 25 Mbps with
full capacitive load representing the maximum dynamic load
conditions. Resistive loads on the outputs should be treated
separately from the dynamic load.
Channel-to-Channel Matching, tPSKCD/tPSKOD
Channel-to-channel matching is the absolute value of the
difference in propagation delays between the two channels
when operated with identical loads.
IDD1 (MAX)
I
DD1 (MAX) is the input current under full dynamic and VISO load
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
conditions.
ISO (LOAD)
ISO (LOAD) is the current available to the load.
Maximum Data Rate
tPHL Propagation Delay
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
tPHL propagation delay is measured from the 50% level of the
falling edge of the VIx signal to the 50% level of the falling edge
of the VOx signal.
Rev. B | Page 18 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM5200/ADuM5201/
ADuM5202 works on principles that are common to most
switching power supplies. It has a secondary side controller
architecture with isolated pulse-width modulation (PWM)
feedback. VDD1 power is supplied to an oscillating circuit that
switches current into a chip scale air core transformer. Power
transferred to the secondary side is rectified and regulated to
either 3.3 V or 5 V. The secondary (VISO) side controller regulates
the output by creating a PWM control signal that is sent to the
primary (VDD1) side by a dedicated iCoupler data channel. The
PWM modulates the oscillator circuit to control the power being
sent to the secondary side. Feedback allows for significantly
higher power and efficiency.
Note that the total lead length between the ends of the low ESR
capacitor and the input power supply pin must not exceed 2 mm.
Installing the bypass capacitor with traces more than 2 mm in
length may result in data corruption. Consider bypassing between
Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless both common
ground pins are connected together close to the package.
BYPASS < 2mm
V
V
DD1
ISO
GND
/V
GND
1
ISO
V
V
V
/V
IA OA
OA IA
V
/V
IB OB
/V
OB IB
RC
NC
IN
RC
V
V
SEL
SEL
/NC
E2
V
/NC
E1
GND
GND
ISO
1
The ADuM5200/ADuM5201/ADuM5202 implements under-
voltage lockout (UVLO) with hysteresis on the VDD1 power input.
This feature ensures that the converter does not enter oscillation
due to noisy input power or slow power-on ramp rates.
Figure 23. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur affects all pins equally on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings for the device
(specified in Table 19), thereby leading to latch-up and/or
permanent damage.
The ADuM5200/ADuM5201/ADuM5202 can accept an external
regulation control signal (RCIN) that can be connected to other
isoPower devices. This allows a single regulator to control multiple
power modules without contention. When accepting control from
a master power module, the VISO pins can be connected together,
adding their power. Because there is only one feedback control
path, the supplies work together seamlessly. The ADuM5200/
ADuM5201/ADuM5202 can only regulate themselves or accept
regulation (as slave devices) from another device in this product
line; they cannot provide a regulation signal to other devices.
The ADuM5200/ADuM5201/ADuM5202 is a power device that
dissipates approximately 1 W of power when fully loaded and
running at maximum speed. Because it is not possible to apply a
heat sink to an isolation device, the device primarily depends
on heat dissipation into the PCB through the GND pins. If the
device is used at high ambient temperatures, provide a thermal
path from the GND pins to the PCB ground plane. The board
layout in Figure 23 shows enlarged pads for Pin 2, Pin 8, Pin 9,
and Pin 15. Multiple vias should be implemented from the pad
to the ground plane to significantly reduce the temperature
inside the chip. The dimensions of the expanded pads are at the
discretion of the designer and depend on the available board space.
PCB LAYOUT
The ADuM5200/ADuM5201/ADuM5202 digital isolators
with 0.5 W isoPower, integrated dc-to-dc converter require no
external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins (see
Figure 23). Note that low ESR bypass capacitors are required
between Pin 1 and Pin 2 and between Pin 15 and Pin 16, as
close to the chip pads as possible.
The power supply section of the ADuM5200/ADuM5201/
ADuM5202 uses a 180 MHz oscillator frequency to pass power
efficiently through its chip scale transformers. In addition, the
normal operation of the data section of the iCoupler introduces
switching transients on the power supply pins. Bypass capacitors
are required for several operating frequencies. Noise suppression
requires a low inductance, high frequency capacitor, whereas ripple
suppression and proper regulation require a large value capacitor.
These capacitors are most conveniently connected between
START-UP BEHAVIOR
The ADuM5200/ADuM5201/ADuM5202 do not contain a soft
start circuit. Take the start-up current and voltage behavior into
account when designing with this device.
When power is applied to VDD1, the input switching circuit begins
to operate and draw current when the UVLO minimum voltage
is reached. The switching circuit drives the maximum available
power to the output until it reaches the regulation voltage where
PWM control begins. The amount of current and time this
takes depends on the load and the VDD1 slew rate.
Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VISO
.
To suppress noise and reduce ripple, a parallel combination of
at least two capacitors is required. The recommended capacitor
values are 0.1 μF and 10 μF for VDD1. The smaller capacitor must
With a fast VDD1 slew rate (200 μs or less), the peak current
draws up to 100 mA/V of VDD1. The input voltage goes high
faster than the output can turn on; therefore, the peak current
is proportional to the maximum input voltage.
have a low ESR; for example, use of a ceramic capacitor is advised.
Rev. B | Page 19 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
With a slow VDD1 slew rate (in the millisecond range), the input
voltage is not changing quickly when VDD1 reaches the UVLO
minimum voltage. The current surge is approximately 300 mA
because VDD1 is nearly constant at the 2.7 V UVLO voltage. The
behavior during startup is similar to when the device load is a
short circuit; these values are consistent with the short-circuit
current shown in Figure 12.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than 1 μs, a periodic set
of refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses of more than about 5 μs, the input side is assumed
to be unpowered or nonfunctional, in which case the isolator
output is forced to a default state (see Table 24) by the watchdog
timer circuit.
When starting the device for VISO = 5 V operation, do not limit
the current available to the VDD1 power pin to less than 300 mA.
The ADuM5200/ADuM5201/ADuM5202 devices may not be able
to drive the output to the regulation point if a current-limiting
device clamps the VDD1 voltage during startup. As a result, the
ADuM5200/ADuM5201/ADuM5202 devices can draw large
amounts of current at low voltage for extended periods of time.
The limitation on the magnetic field immunity of the ADuM5200/
ADuM5201/ADuM5202 is set by the condition in which induced
voltage in the receiving coil of the transformer is sufficiently
large to either falsely set or reset the decoder. The following analysis
defines the conditions under which this may occur. The 3 V
operating condition of the ADuM5200/ADuM5201/ADuM5202
is examined because it represents the most susceptible mode of
operation.
The output voltage of the ADuM5200/ADuM5201/ADuM5202
exhibits VISO overshoot during startup. If this could potentially
damage components attached to VISO, then a voltage-limiting
device, such as a Zener diode, can be used to clamp the voltage.
Typical behavior is shown in Figure 17 and Figure 18.
EMI CONSIDERATIONS
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
The dc-to-dc converter section of the ADuM5200/ADuM5201/
ADuM5202 devices must operate at 180 MHz to allow efficient
power transfer through the small transformers. This creates
high frequency currents that can propagate in circuit board
ground and power planes, causing edge emissions and dipole
radiation between the primary and secondary ground planes.
Grounded enclosures are recommended for applications that use
these devices. If grounded enclosures are not possible, follow
good RF design practices in the layout of the PCB. See the
AN-0971 Application Note for board layout recommendations.
2
V = (−dβ/dt)∑πrn ; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM5200/
ADuM5201/ADuM5202 and an imposed requirement that the
induced voltage be, at most, 50% of the 0.5 V margin at the
decoder, a maximum allowable magnetic field is calculated as
shown in Figure 25.
PROPAGATION DELAY PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation delay
to a logic high.
100
INPUT (V
)
50%
IX
10
1
tPLH
tPHL
OUTPUT (V
)
50%
OX
Figure 24. Propagation Delay Parameters
0.1
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of
how accurately timing of the input signal is preserved.
0.01
0.001
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM5200/ADuM5201/ADuM5202 component.
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM5200/
ADuM5201/ADuM5202 components operating under the
same conditions.
Figure 25. Maximum Allowable External Magnetic Flux Density
Rev. B | Page 20 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(and is of the worst-case polarity), it reduces the received pulse
from >1.0 V to 0.75 V—still well above the 0.5 V sensing
threshold of the decoder.
I
I
ISO
DD1(Q)
CONVERTER
PRIMARY
CONVERTER
SECONDARY
I
DD1(D)
I
I
ISO(D)
DDP(D)
PRIMARY
DATA I/O
2-CHANNEL
SECONDARY
DATA I/O
2-CHANNEL
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM5200/
ADuM5201/ADuM5202 transformers. Figure 26 expresses
these allowable current magnitudes as a function of frequency
for selected distances. As shown, the ADuM5200/ADuM5201/
ADuM5202 are extremely immune and can be affected only by
extremely large currents operated at high frequency very close
to the component. For the 1 MHz example noted, a 0.5 kA current
placed 5 mm away from the ADuM5200/ADuM5201/ADuM5202
is required to affect the operation of the component.
1000
Figure 27. Power Consumption Within the ADuM5200/ADuM5201/ADuM5202
Both dynamic input and output current is consumed only when
operating at channel speeds higher than the rate of fr. Because
each channel has a dynamic current determined by its data rate,
Figure 19 shows the current for a channel in the forward direction,
which means that the input is on the primary side of the part.
Figure 20 shows the current for a channel in the reverse direction,
which means that the input is on the secondary side of the part.
Both figures assume a typical 15 pF load. The following
relationship allows the total IDD1 current to be calculated:
I
DD1 = (IISO × VISO)/(E × VDD1) + ∑ ICHn; n = 1 to 4
(1)
DISTANCE = 1m
100
where:
I
I
DD1 is the total supply input current.
CHn is the current drawn by a single channel determined from
10
Figure 19 or Figure 20, depending on channel direction.
ISO is the current drawn by the secondary side external loads.
E is the power supply efficiency at 100 mA load from Figure 9
DISTANCE = 100mm
I
1
DISTANCE = 5mm
at the VISO and VDD1 condition of interest.
0.1
Calculate the maximum external load by subtracting the dynamic
output load from the maximum allowable load.
0.01
I
ISO (LOAD) = IISO (MAX) − ∑ IISO (D)n; n = 1 to 4
where:
ISO (LOAD) is the current available to supply an external secondary
side load.
ISO (MAX) is the maximum external secondary side load current
available at VISO
ISO (D)n is the dynamic load current drawn from VISO by an input
(2)
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 26. Maximum Allowable Current for Various Current-to-
ADuM5200/ADuM5201/ADuM5202 Spacings
I
I
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large enough to trigger the thresholds of
succeeding circuitry. Exercise care in the layout of such traces
to avoid this possibility.
.
I
or output channel, as shown in Figure 19 and Figure 20. Data is
presented assuming a typical 15 pF load.
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the addi-
tional current must be included in the analysis of IDD1 and IISO (LOAD)
POWER CONSUMPTION
The VDD1 power supply input provides power to the iCoupler data
channels as well as to the power converter. For this reason, the
quiescent currents drawn by the data converter and the primary
and secondary input/output channels cannot be determined sepa-
rately. All of these quiescent power demands have been combined
into the IDD1 (Q) current shown in Figure 27. The total IDD1 supply
current is the sum of the quiescent operating current, dynamic
current IDD1 (D) demanded by the I/O channels, and any external
.
To determine IDD1 in Equation 1, additional primary side
dynamic output current (IAOD) is added directly to IDD1
.
Additional secondary side dynamic output current (IAOD) is
added to IISO on a per-channel basis.
To determine IISO (LOAD) in Equation 2, additional secondary
side output current (IAOD) is subtracted from IISO (MAX) on a
per-channel basis.
I
ISO load.
Rev. B | Page 21 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
For each output channel with CL greater than 15 pF, the additional
capacitive supply current is given by
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.
I
AOD = 0.5 × 10−3 × ((CL − 15) × VISO) × (2f − fr); f > 0.5 fr (3)
where:
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because
no data comes from the secondary side inputs until secondary
power is established. The primary side oscillator also begins to
operate, transferring power to the secondary power circuits.
CL is the output load capacitance (pF).
VISO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input channel refresh rate (Mbps).
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The secondary VISO voltage is below its UVLO limit at this point;
the regulation control signal from the secondary is not being
generated. The primary side power oscillator is allowed to free run
in this circumstance, supplying the maximum amount of power to
the secondary, until the secondary voltage rises to its regulation
The ADuM5200/ADuM5201/ADuM5202 are protected against
damage due to excessive power dissipation by thermal overload
protection circuits. Thermal overload protection limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation), when the junction temperature starts to rise
above 150°C, the PWM is turned off, reducing the output
current to zero. When the junction temperature drops below
130°C (typical), the PWM turns on again, restoring the output
current to its nominal value.
setpoint. This creates a large inrush current transient at VDD1
.
When the regulation point is reached, the regulation control
circuit produces the regulation control signal that modulates
the oscillator on the primary side. The VDD1 current is reduced
and is then proportional to the load current. The inrush current
is less than the short-circuit current shown in Figure 12. The
duration of the inrush current depends on the VISO loading
conditions and the current available at the VDD1 pin.
Consider the case where a hard short from VISO to ground occurs.
At first, the ADuM5200/ADuM5201/ADuM5202 reach their
maximum current, which is proportional to the voltage applied
at VDD1. Power dissipates on the primary side of the converter
(see Figure 12). If self-heating of the junction becomes great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates, turning off the PWM, and reducing the
output current to zero. As the junction temperature cools and
drops below 130°C, the PWM turns on, and power dissipates
again on the primary side of the converter, causing the junction
temperature to rise to 150°C again. This thermal oscillation
between 130°C and 150°C causes the part to cycle on and off as
long as the short remains at the output.
As the secondary side converter begins to accept power from
the primary, the VISO voltage starts to rise. When the secondary
side UVLO is reached, the secondary side outputs are initialized
to their default low state until data is received from the correspond-
ing primary side input. It can take up to 1 μs after the secondary
side is initialized for the state of the output to correlate with the
primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 μs after the secondary
side becomes active.
Because the rate of charge of the secondary side power supply
is dependent on loading conditions and the input voltage level
and the output voltage level selected, take care with the design
to allow the converter sufficient time to stabilize before valid
data is required.
Thermal limit protections are intended to protect the device
against accidental overload conditions. For reliable operation,
externally limit device power dissipation to prevent junction
temperatures from exceeding 130°C.
POWER CONSIDERATIONS
When power is removed from VDD1, the primary side converter and
coupler shut down when the UVLO level is reached. The secondary
side stops receiving power and starts to discharge. The outputs on
the secondary side hold the last state that they received from the
primary side. Either the UVLO level is reached and the outputs are
placed in their high impedance state, or the outputs detect a lack of
activity from the primary side inputs and the outputs are set to
their default low value before the secondary power reaches UVLO.
The ADuM5200/ADuM5201/ADuM5202 power input, data
input channels on the primary side and data input channels on
the secondary side are all protected from premature operation
by UVLO circuitry. Below the minimum operating voltage, the
power converter holds its oscillator inactive and all input channel
drivers and refresh circuits are idle. Outputs remain in a high
impedance state to prevent transmission of undefined states
during power-up and power-down operations.
Rev. B | Page 22 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
The ADuM5000 can act as a master or a slave device, the
ADuM5401, ADuM5402, ADuM5403, and ADuM5404 can
only be master/standalone, and the ADuM520x can only be
a slave/standalone device. This means that the ADuM5000,
ADuM520x, and ADuM5401 to ADuM5404 can only be used
in certain master/slave combinations as listed in Table 25.
THERMAL ANALYSIS
The ADuM5200/ADuM5201/ADuM5202 consist of four internal
die, attached to a split lead frame with two die attach paddles. For
the purposes of thermal analysis, it is treated as a thermal unit
with the highest junction temperature reflected in the θJA value in
Table 14. The value of θJA is based on measurements taken with
the part mounted on a JEDEC standard 4-layer board with fine
width traces and still air. Under normal operating conditions, the
ADuM5200/ADuM5201/ADuM5202 operate at full load across
the full temperature range without derating the output current.
However, following the recommendations in the PCB Layout
section decreases the thermal resistance to the PCB, allowing
increased thermal margin at high ambient temperatures.
Table 25. Allowed Combinations of isoPower Parts
Slave
ADuM5401 to
ADuM5404
Master
ADuM5000
ADuM520x
ADuM5000
ADuM520x
Yes
No
Yes
Yes
No
Yes
No
No
No
ADuM5401 to
ADuM5404
INCREASING AVAILABLE POWER
The allowed combinations of master and slave configured parts
listed in Table 25 is sufficient to make any combination of power
and channel count.
The ADuM5200/ADuM5201/ADuM5202 are designed with the
capability of running in combination with other compatible
isoPower devices. The RCIN and RCSEL pins allow the ADuM5200/
ADuM5201/ADuM5202 to receive a PWM signal from another
device through the RCIN pin and act as a slave to that control
signal. The RCSEL pin chooses whether the part acts as a stand-
alone self-regulated device or a slave device. When the
Table 26 illustrates how isoPower devices can provide many
combinations of data channel count and multiples of the single
unit power.
ADuM5200/ADuM5201/ADuM5202 act as a slave, their power
is regulated by a PWM signal coming from a master device. This
allows multiple isoPower parts to be combined in parallel while
sharing the load equally. When the ADuM5200/ADuM5201/
ADuM5202 are configured as standalone units, they generate
their own PWM feedback signal to regulate themselves.
Table 26. Configurations for Power and Data Channels
Number of Data Channels
Power Units
1-Unit Power
0 Channels
2 Channels
4 Channels
6 Channels
ADuM5000 master
ADuM520x master
ADuM5401 to ADuM5404 master
ADuM5401 to ADuM5404 master
ADuM121x
2-Unit Power
3-Unit Power
ADuM5000 master
ADuM5000 slave
ADuM5000 master
ADuM5000 slave
ADuM5000 slave
ADuM5000 master
ADuM520x slave
ADuM5000 master
ADuM5000 slave
ADuM520x slave
ADuM5401 to ADuM5404 master
ADuM520x slave
ADuM5401 to ADuM5404 master
ADuM520x slave
ADuM5401 to ADuM5404 master
ADuM5000 slave
ADuM5401 to ADuM5404 master
ADuM520x slave
ADuM5000 slave
ADuM5000 slave
Rev. B | Page 23 of 28
ADuM5200/ADuM5201/ADuM5202
Data Sheet
In the case of unipolar ac or dc voltage, the stress on the insula-
tion is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 20 can be applied while maintaining the
50-year minimum lifetime, provided the voltage conforms to
either the unipolar ac or dc voltage cases.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to the
testing performed by the regulatory agencies, Analog Devices
carries out an extensive set of evaluations to determine the
lifetime of the insulation structure within the ADuM5200/
ADuM5201/ADuM5202.
Any cross-insulation voltage waveform that does not conform to
Figure 29 or Figure 30 should be treated as a bipolar ac waveform
and its peak voltage limited to the 50-year lifetime voltage value
listed in Table 20. The voltage presented in Figure 29 is shown as
sinusoidal for illustration purposes only. It is meant to represent
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
Analog Devices performs accelerated life testing using voltage levels
higher than the rated continuous working voltage. Acceleration
factors for several operating conditions are determined. These
factors allow calculation of the time to failure at the actual working
voltage. The values shown in Table 20 summarize the peak voltage
for 50 years of service life for a bipolar ac operating condition,
and the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than a 50-year service
life voltage. Operation at these high working voltages can lead to
shortened insulation life in some cases.
RATED PEAK VOLTAGE
0V
Figure 28. Bipolar AC Waveform
RATED PEAK VOLTAGE
The insulation lifetime of the ADuM5200/ADuM5201/
ADuM5202 depends on the voltage waveform type imposed
across the isolation barrier. The iCoupler insulation structure
degrades at different rates depending on whether the waveform
is bipolar ac, unipolar ac, or dc. Figure 28, Figure 29, and Figure 30
illustrate these different isolation voltage waveforms.
0V
Figure 29. Unipolar AC Waveform
RATED PEAK VOLTAGE
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the maximum working voltage recommended by
Analog Devices.
0V
Figure 30. DC Waveform
Rev. B | Page 24 of 28
Data Sheet
ADuM5200/ADuM5201/ADuM5202
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
1.27 (0.0500)
BSC
2.65 (0.1043)
0.25 (0.0098)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Number of Number of Maximum Maximum
Maximum
Data Rate Propagation Pulse Width
(Mbps)
Inputs,
VDD1 Side
Inputs,
VDD2 Side
Temperature
Delay, 5 V (ns) Distortion (ns) Range
Package
Description
Package
Option
Model1, 2
ADuM5200ARWZ
ADuM5200CRWZ
ADuM5201ARWZ
ADuM5201CRWZ
ADuM5202ARWZ
ADuM5202CRWZ
2
0
1
25
1
25
1
25
100
70
40
3
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
2
1
1
0
0
0
1
1
2
2
100
70
40
3
100
70
40
3
1 Z = RoHS Compliant Part.
2 Tape and reel are available. The additional -RL suffix designates a 13-inch (1,000 units) tape and reel option.
Rev. B | Page 25 of 28
ADuM5200/ADuM5201/ADuM5202
NOTES
Data Sheet
Rev. B | Page 26 of 28
Data Sheet
NOTES
ADuM5200/ADuM5201/ADuM5202
Rev. B | Page 27 of 28
ADuM5200/ADuM5201/ADuM5202
NOTES
Data Sheet
©2009-2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07540-0-5/12(B)
Rev. B | Page 28 of 28
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