ADUM5201CRWZ_技术文档

Dual Channel Isolators with

Integrated DC-to-DC Converter

ADuM5200/ADuM5201/ADuM5202

FEATURES

FUNCTIONAL BLOCK DIAGRAM

isoPower integrated isolated dc-to-dc converter

Regulated 3 V or 5 V output

Up to 500 mW output power

Dual dc-to-25 Mbps (NRZ) signal isolation channels

Schmitt trigger inputs

16-lead SOIC package with >8 mm creepage

High temperature operation: 105°C maximum

High common-mode transient immunity: >25 kV/μs

Safety and regulatory approvals

OSC

RECT

REG

1

2

3

4

5

6

7

8

16

15

14

13

V

ISO

DD1

GND

ISO

1

V

/V

IA OA

V /V

IA OA

2-CHANNEL iCOUPLER CORE

V

/V

IB OB

V /V

IB OB

RC

12 NC

IN

RC

11

10

9

V

SEL

ADuM5200/

ADuM5201/

ADuM5202

V

/NC

E1

GND

E2

UL recognition

GND

ISO

1

2500 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice #5A (pending)

VDE certificate of conformity (pending)

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

Figure 1.

V

IA

IB

OA

OB

3

4

14

13

ADuM5200

V

_IORM= 560 V peak

APPLICATIONS

Figure 2. ADuM5200

RS-232/RS-422/RS-485 transceivers

Industrial field bus isolation

Power supply startups and gate drives

Isolated sensor interfaces

V

IA

OA

3

4

14

13

ADuM5201

V

OB

IB

Industrial PLCs

Figure 3. ADuM5201

V

OA

IA

3

4

14

13

ADuM5202

V

OB

IB

Figure 4. ADuM5202

GENERAL DESCRIPTION

The ADuM520x¹are dual channel digital isolators with

isoPower, an integrated, isolated dc-to-dc converter. Based on

the Analog Devices, Inc., iCoupler® technology, the dc-to-dc

converter provides up to 500 mW of regulated, isolated power

with 5.0 V input and 5.0 V output voltage, or 200 mW of power

with 3.3 V input and 3.3 V output voltage. This eliminates the

need for a separate isolated dc-to-dc converter in low power

isolated designs. The Analog Devices chip scale transformer

iCoupler technology is used for the isolation of the logic signals

as well as for the dc-to-dc converter. The result is a small form

factor, total isolation solution.

levels and greater channel counts (see the Increasing Available

Power section).

The ADuM520x isolators provide two independent isolation

channels in a variety of channel configurations and data rates

(see the Ordering Guide for options).

isoPower uses high frequency switching elements to transfer

power through its transformer. Special care must be taken

during printed circuit board (PCB) layout to meet emissions

standards. Refer to the AN-0971 application note for details on

board layout recommendations.

ADuM520x units can be used in combination with the

ADuM5401, ADuM5402, ADuM5403, ADuM5404, and

ADuM5000 with isoPower® to achieve higher output power

¹Protected by U.S. Patents: 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADuM5200/ADuM5201/ADuM5202

TABLE OF CONTENTS

Features .............................................................................................. 1

Pin Configurations and Function Descriptions......................... 11

Typical Performance Characteristics ........................................... 15

Terminology.................................................................................... 17

Applications Information.............................................................. 18

PCB Layout ................................................................................. 18

EMI Considerations................................................................... 18

Propagation Delay Parameters ................................................. 19

DC Correctness and Magnetic Field Immunity........................... 19

Power Consumption .................................................................. 20

Current Limit and Thermal Overload Protection ................. 20

Power Considerations................................................................ 21

Thermal Analysis ....................................................................... 21

Increasing Available Power ....................................................... 21

Insulation Lifetime..................................................................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—5 V Primary Input Supply/5 V

Secondary Isolated Supply .......................................................... 3

Electrical Characteristics—3.3 V Primary Input Supply/3.3 V

Secondary Isolated Supply .......................................................... 5

Package Characteristics ............................................................... 7

Regulatory Information............................................................... 7

Insulation and Safety-Related Specifications............................ 7

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics .............................................................................. 8

Recommended Operating Conditions ...................................... 9

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADuM5200/ADuM5201/ADuM5202

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY

4.5 V ≤ V_DD1≤ 5.5 V, V_SEL= V_ISO; each voltage is relative to its respective ground. All minimum/maximum specifications apply over the

entire recommended operating range, unless otherwise noted. All typical specifications are at T_A= 25°C, V_DD= 5.0 V, V_ISO= 5.0 V, V_SEL= V_ISO

.

Table 1.

Parameter

Symbol

Min

Typ

Max

5.4

5

Unit

Test Conditions

DC-TO-DC CONVERTER POWER SUPPLY

Setpoint

Line Regulation

Load Regulation

Output Ripple

V_ISO

4.7

5.0

1

V

I_ISO= 0 mA

I_ISO= 50 mA, V_DD1= 4.5 V to 5.5 V

I_ISO= 10 mA to 90 mA

V_ISO(LINE)

V_ISO(LOAD)

V_ISO(RIP)

mV/V

%

75

mV p-p 20 MHz bandwidth, C_BO= 0.1 μF||10 μF,

I_ISO= 90 mA

Output Noise

Switching Frequency

Pulse-Width Modulation Frequency

DC-to-2 Mbps Data Rate¹

Maximum Output Supply Current²

V_ISO(N)

f_OSC

f_PWM

200

180

625

mV p-p C_BO= 0.1 μF||10 μF, I_ISO= 90 mA

MHz

kHz

I_ISO(MAX)

100

mA

%

V_ISO> 4.5 V, dc to 1 MHz logic signal

frequency

I_ISO= 100 mA, dc to 1 MHz logic signal

frequency

Efficiency @ Maximum Output Supply

Current³

I_DD1Supply Current, No V_ISOLoad

34

8

I_DD1(Q)

22

mA

I_ISO= 0 mA, dc to 1 MHz logic signal

frequency

25 Mbps Data Rate (CRWZ Grade Only)

I_DD1Supply Current, No V_ISOLoad

ADuM5200

I_DD1(D)

34

38

41

mA

I_ISO= 0 mA, C_L= 15 pF, 12.5 MHz logic

signal frequency

I_ISO= 0 mA, C_L= 15 pF, 12.5 MHz logic

signal frequency

I_ISO= 0 mA, C_L= 15 pF, 12.5 MHz logic

signal frequency

ADuM5201

ADuM5202

Available V_ISOSupply Current⁴

ADuM5200

I_ISO(LOAD)

I_DD1(MAX)

94

mA

C_L= 15 pF, 12.5 MHz logic signal

frequency

C_L= 15 pF, 12.5 MHz logic signal

frequency

C_L= 15 pF, 12.5 MHz logic signal

frequency

C_L= 0 pF, dc to 1 MHz logic signal

frequency, V_DD= 4.5 V, I_ISO= 100 mA

ADuM5201

92

ADuM5202

90

I_DD1Supply Current, Full V_ISOLoad⁵

290

Undervoltage Lockout, V_DD1and V_ISO

Supply⁶

Positive Going Threshold

Negative Going Threshold

Hysteresis

V_UV+

V_UV−

V_UVH

2.7

2.4

0.3

V

iCoupler DATA CHANNELS

I/O Input Currents

Logic High Input Threshold

I_IA, I_IB

V_IH

−20

0.7 × V_ISO,

0.7 × V_IDD1

+0.01 +20

ꢀA

V

Logic Low Input Threshold

V_IL

0.3 × V_ISO,

0.3 × V_IDD1

V

Rev. 0 | Page 3 of 24

ADuM5200/ADuM5201/ADuM5202

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

Logic High Output Voltages

V_OAH, V_OBH

V_DD1− 0.3, 5.0

V_ISO− 0.3

V

I_Ox= −20 ꢀA, V_Ix= V_IxH

V_OAH, V_OBH

V_OAL, V_OBL

V_DD1− 0.5, 4.8

V

I_Ox= −4 mA, V_Ix= V_IxH

V_ISO− 0.5

Logic Low Output Voltages

0.0

0.1

0.4

V

I_Ox= 20 ꢀA, V_Ix= V_IxL

I_Ox= 4 mA, V_Ix= V_IxL

AC SPECIFICATIONS

ADuM520xARWZ⁷

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |t_PLH− t_PHL

Propagation Delay Skew

Channel-to-Channel Matching

ADuM520xCRWZ

Minimum Pulse Width⁷

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |t_PLH− t_PHL

Change vs. Temperature

Propagation Delay Skew

Channel-to-Channel Matching,

Codirectional Channels

PW

1000

ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

1

t_PHL, t_PLH

PWD

t_PSK

55

100

40

50

|

t_PSKCD, t_PSKOD

50

ns

PW

40

ns

Mbps

ns

ps/°C

ns

C_L= 15 pF, CMOS signal levels

25

t_PHL, t_PLH

PWD

45

5

60

6

|

t_PSK

t_PSKCD

15

6

ns

Channel-to-Channel Matching,

t_PSKOD

15

ns

C_L= 15 pF, CMOS signal levels

Opposing-Directional Channels

For All Models

Output Rise/Fall Time (10% to 90%)

Common-Mode Transient Immunity |CM_H|

at Logic High Output

Common-Mode Transient Immunity |CM_L|

at Logic Low Output

Refresh Rate

t_R/t_F

2.5

35

ns

kV/ꢀs

C_L= 15 pF, CMOS signal levels

V_Ix= V_DDor V_ISO, V_CM= 1000 V, transient

magnitude = 800 V

V_Ix= 0 V, V = 1000 V, transient

magnitude = 800 V

25

35

kV/ꢀs

Mbps

f_r

1.0

¹The contributions of supply current values for all four channels are combined at identical data rates.

²V_ISOsupply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, data I/O channels draw additional current

proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the

Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the V_ISOpower budget.

³The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power

consumed by the I/O channels as part of its internal power consumption.

⁴This current is available for driving external loads at the V_ISOpin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load

representing the maximum dynamic load conditions. Refer to the Power Consumption section for the calculation of available current at less than the maximum data rate.

⁵I_DD1(MAX)is the input current under full dynamic and V_ISOload conditions.

⁶Undervoltage lockout (UVLO) holds the outputs in a low state if the corresponding input or output power supply is below the referenced threshold. Hysteresis is built

into the detection threshold to prevent oscillations and noise sensitivity.

⁷The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

Rev. 0 | Page 4 of 24

ADuM5200/ADuM5201/ADuM5202

ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY

3.0 V ≤ V_DD1≤ 3.6 V, V_SEL= GND_ISO; each voltage is relative to its respective ground. All minimum/maximum specifications apply over

the entire recommended operating range, unless otherwise noted. All typical specifications are at T_A= 25°C, V_DD= 3.3 V, V_ISO= 3.3 V, V_SEL

=

GND_ISO

.

Table 2.

Parameter

Symbol

Min

Typ

Max

3.37

5

Unit

Test Conditions

DC-TO-DC CONVERTER POWER SUPPLY

Setpoint

Line Regulation

Load Regulation

Output Ripple

V_ISO

3.13

3.3

1

V

I_ISO= 0 mA

I_ISO= 30 mA, V_DD1= 3.0 V to 3.6 V

I_ISO= 6 mA to 54 mA

V_ISO(LINE)

V_ISO(LOAD)

V_ISO(RIP)

mV/V

%

50

mV p-p 20 MHz bandwidth, C_BO= 0.1 μF||10μF,

I_ISO= 54 mA

Output Noise

Switching Frequency

Pulse-Width Modulation Frequency

DC to 2 Mbps Data Rate¹

Maximum Output Supply Current²

V_ISO(N)

f_OSC

f_PWM

130

180

625

mV p-p C_BO= 0.1μF||10μF, I_ISO= 54 mA

MHz

kHz

V_ISO> 3.0 V, dc to 1 MHz logic signal

mA

I_ISO(MAX)

60

frequency

I_ISO= 60 mA, dc to 1 MHz logic signal

frequency

Efficiency @ Maximum Output Supply

Current³

I_DD1Supply Current, No V_ISOload

36

6

%

I_ISO= 0 mA, dc to 1 MHz logic signal

frequency

I_DD1(Q)

15

mA

I_DD1Supply Current, Full V_ISOload

I_DD1(MAX)

175

C_L= 0 pF, f = 0 MHz, V_DD= 3.3 V, I_ISO

60 mA

=

25 Mbps Data Rate (CRWZ Grade Only)

I_DD1Supply Current, No V_ISOLoad⁴

ADuM5200

I_ISO= 0 mA, C_L= 15 pF, 12.5 MHz logic

signal frequency

I_ISO= 0 mA, C_L= 15 pF, 12.5 MHz logic

signal frequency

I_ISO= 0 mA, C_L= 15 pF, 12.5 MHz logic

signal frequency

I_DD1(D)

23

25

27

mA

ADuM5201

ADuM5202

Available V_ISOSupply Current⁵

ADuM5200

C_L= 15 pF, 12.5 MHz logic signal

frequency

C_L= 15 pF, 12.5 MHz logic signal

frequency

C_L= 15 pF, 12.5 MHz logic signal

frequency

I_ISO(LOAD)

56

55

54

mA

ADuM5201

ADuM5202

Undervoltage Lockout (UVLO), V_DD1and

V_ISOSupply⁶

Positive Going Threshold

Negative Going Threshold

Hysteresis

V_UV+

V_UV−

V_UVH

2.7

2.4

0.3

V

iCoupler DATA CHANNELS

I/O Input Currents

Logic High Input Threshold

I_IA, I_IB

V_IH

−20

0.7 × V_ISO,

0.7 × V_IDD1

+0.01 +20

ꢀA

V

0.3 × V_ISO,

0.3 × V_IDD1

Logic Low Input Threshold

Logic High Output Voltages

V_IL

V

V_DD1− 0.2,

V_ISO− 0.2

V_OAH

V_OBH

V_OAH

V_OBH

,

3.3

3.1

I_Ox= −20 ꢀA, V_Ix= V_IxH

I_Ox= −4 mA, V_Ix= V_IxH

V_DD1− 0.5,

V_1SO− 0.5

Logic Low Output Voltages

V_OAL, V_OBL

0.0

0.1

0.4

V

I_Ox= 20 ꢀA, V_Ix= V_IxL

I_Ox= 4 mA, V_Ix= V_IxL

Rev. 0 | Page 5 of 24

ADuM5200/ADuM5201/ADuM5202

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

AC SPECIFICATIONS

ADuM520xARWZ

Minimum Pulse Width⁷

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |t_PLH− t_PHL

Propagation Delay Skew

Channel-to-Channel Matching

ADuM520xCRWZ

PW

1000

ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

1

t_PHL, t_PLH

PWD

t_PSK

60

100

40

50

|

t_PSKCD, t_PSKOD

50

ns

Minimum Pulse Width⁷

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |t_PLH− t_PHL

Change vs. Temperature

Propagation Delay Skew

PW

40

ns

Mbps

ns

C_L= 15 pF, CMOS signal levels

25

t_PHL, t_PLH

PWD

45

5

60

6

|

ns

ps/°C

ns

t_PSK

t_PSKCD

45

6

Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

t_PSKOD

15

ns

C_L= 15 pF, CMOS signal levels

Opposing-Directional Channels

For All Models

Output Rise/Fall Time (10% to 90%)

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

Refresh Rate

t_R/t_F

|CM_H|

2.5

35

ns

kV/ꢀs

C_L= 15 pF, CMOS signal levels

V_Ix= V_DDor V_ISO, V_CM= 1000 V,

transient magnitude = 800 V

V_Ix= 0 V, V = 1000 V,

transient magnitude = 800 V

25

|CM_L|

f_r

35

kV/ꢀs

Mbps

1.0

¹The contributions of supply current values for all four channels are combined at identical data rates.

²V_ISOsupply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps data I/O channels draw additional current

proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the

Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the V_ISOpower budget.

³The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power

consumed by the I/O channels as part of its internal power consumption.

⁴I_DD1(D)is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load representing the

maximum dynamic load conditions. Treat resistive loads on the outputs separately from the dynamic load.

⁵This current is available for driving external loads at the V_ISOpin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load

representing the maximum dynamic load conditions. Refer to the Power Consumption section for the calculation of available current at less than the maximum data rate.

⁶Undervoltage lockout (UVLO) holds the outputs in a low state if the corresponding input or output power supply is below the referenced threshold. Hysteresis is built

into the detection threshold to prevent oscillations and noise sensitivity.

⁷The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

Rev. 0 | Page 6 of 24

ADuM5200/ADuM5201/ADuM5202

PACKAGE CHARACTERISTICS

Table 3.

Parameter

Symbol Min Typ Max Unit Test Conditions

RESISTANCE AND CAPACITANCE

Resistance (Input-to-Output)¹

Capacitance (Input-to-Output)¹

Input Capacitance²

R_I-O

C_I-O

C_I

10¹²

2.2

4.0

45

Ω

pF

f = 1 MHz

IC Junction to Ambient Thermal Resistance θ_JA

°C/W Thermocouple located at the center of the package

underside; test conducted on a 4-layer board with

thin traces ³

THERMAL SHUTDOWN

Threshold

Hysteresis

TS_SD

TS_SD-HYS

150

20

°C

T_Jrising

¹This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

²Input capacitance is from any input data pin to ground.

³Refer to the Power Considerations section for thermal model definitions.

REGULATORY INFORMATION

The ADuM5200/ADuM5201/ADuM5202 are approved by the organizations listed in Table 4. Refer to Table 9 and the Insulation Lifetime

section for details regarding recommended maximum working voltages for specific cross isolation waveforms and insulation levels.

Table 4.

UL

CSA (Pending)

VDE (Pending)

Recognized under 1577 Component

Recognition Program¹

Approved under CSA Component

Acceptance Notice #5A

Certified according to DIN V VDE V 0884-10

(VDE V 0884-10):2006-12²

Single Protection 2500 V RMS Isolation

Voltage

Reinforced insulation per CSA 60950-1-03

and IEC 60950-1, 400 V rms (566 V peak)

maximum working voltage

Reinforced insulation, 560 V peak

File E214100

File 205078

File 2471900-4880-0001

¹In accordance with UL 1577, each ADuM520x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 sec (current leakage detection limit = 5 ꢀA).

²In accordance with DIN V VDE V 0884-10, each ADuM520x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge detection

limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 5.

Parameter

Symbol Value

Unit Conditions

Rated Dielectric Insulation Voltage

Minimum External Air Gap (Clearance)

2500

>8 min

V rms 1-minute duration

L(I01)

L(I02)

mm

Measured from input terminals to output terminals,

shortest distance through air

Minimum External Tracking (Creepage)

>8 min

mm

Measured from input terminals to output terminals,

shortest distance path along body

Minimum Internal Gap (Internal Clearance)

Tracking Resistance (Comparative Tracking Index)

Isolation Group

0.017 min mm

Distance through the insulation

DIN IEC 112/VDE 0303 Part 1

Material group (DIN VDE 0110, 1/89, Table 1)

CTI

>175

IIIa

V

Rev. 0 | Page 7 of 24

ADuM5200/ADuM5201/ADuM5202

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by

protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval.

Table 6.

Description

Conditions

Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 400 V rms

Climatic Classification

Pollution Degree per DIN VDE 0110, Table 1

Maximum Working Insulation Voltage

Input-to-Output Test Voltage

Method b1

I to IV

I to III

I to II

40/105/21

2

V_IORM

560

V peak

V_IORM× 1.875 = V_PR, 100% production test, t_m= 1 sec,

partial discharge < 5 pC

V_IORM× 1.6 = V_PR, t_m= 60 sec, partial discharge < 5 pC

V_PR

1050

Method a

After Environmental Tests Subgroup 1

After Input and/or Safety Test

Subgroup 2 and Subgroup 3

896

672

V peak

V_IORM× 1.2 = V_PR, t_m= 60 sec, partial discharge < 5 pC

Transient overvoltage, t_TR= 10 sec

Maximum value allowed in the event of a failure

(see Figure 5)

Highest Allowable Overvoltage

Safety-Limiting Values

V_TR

4000

V peak

Case Temperature

Side 1 I_DD1Current

Insulation Resistance at T_S

T_S

I_S1

R_S

150

555

>10⁹

°C

mA

Ω

V_IO= 500 V

Thermal Derating Curve

600

500

400

300

200

100

0

50

100

150

200

AMBIENT TEMPERATURE (°C)

Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2

Rev. 0 | Page 8 of 24

ADuM5200/ADuM5201/ADuM5202

RECOMMENDED OPERATING CONDITIONS

Table 7.

Parameter

Symbol

Min

Max

Unit

OPERATING TEMPERATURE

SUPPLY VOLTAGES¹

V_DD1@ V_SEL= 0 V

T_A

−40

+105

°C

V_DD

I_ISO(MIN)

V_SLEW

3.0

4.5

10

3.6

5.5

V

mA

V/ms

V_DD1@ V_SEL= V_DD1

Minimum Load

V

Minimum Power-On Slew Rate

150

¹Each voltage is relative to its respective ground.

Rev. 0 | Page 9 of 24

ADuM5200/ADuM5201/ADuM5202

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted.

Table 9. Maximum Continuous Working Voltage Supporting

a 50-Year Minimum Lifetime¹

Table 8.

Reference Standard

Parameter

Max Unit

Parameter

Rating

AC Voltage

Storage Temperature (T_ST)

Ambient Operating Temperature (T_A)

−55°C to +150°C

−40°C to +105°C

−0.5 V to +7.0 V

100 mA

Bipolar Waveform

424 V peak 50-year minimum

lifetime

1

Supply Voltages (V_DD, V_ISO

V_ISOSupply Current²

Input Voltage

)

Unipolar Waveform

Basic Insulation

600 V peak Maximum approved

working voltage per

−0.5 V to V_DDI+ 0.5 V

1, 3

(V_IA, V_IB, V_E1, V_E2,RC_SEL, V_SEL

)

IEC 60950-1

Output Voltage

(V_OA, V_OB)^{1, 3}

−0.5 V to V_DDO+ 0.5 V

−10 mA to +10 mA

Reinforced Insulation 560 V peak

Maximum approved

working voltage per

IEC 60950-1 and

Average Output Current per Data

Output Pin⁴

VDE V 0884-10

Common-Mode Transients⁵

−100 kV/ꢀs to +100 kV/ꢀs

DC Voltage

Basic Insulation

600 V peak Maximum approved

working voltage per

¹Each voltage is relative to its respective ground.

²The V_ISOprovides current for dc and dynamic loads on the Side 2

input/output channels. This current must be included when determining the

total V_ISOsupply current.

IEC 60950-1

Reinforced Insulation 560 V peak Maximum approved

³V_DDIand V_DDOrefer to the supply voltages on the input and output sides of a

given channel, respectively. See the PCB Layout section.

⁴See Figure 5 for maximum rated current values for various temperatures.

⁵Refers to common-mode transients across the insulation barrier. Common-

mode transients exceeding the absolute maximum ratings may cause latch-up

or permanent damage.

working voltage per

IEC 60950-1 and

VDE V 0884-10

1

Refers to continuous voltage magnitude imposed across the isolation

barrier. See the Insulation Lifetime section for more details.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. 0 | Page 10 of 24

ADuM5200/ADuM5201/ADuM5202

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

1

2

3

4

5

6

7

8

16

V

ISO

DD1

GND

15 GND

1

IA

IB

IN

ISO

V

14

13

V

OA

OB

ADuM5200

V

TOP VIEW

(Not to Scale)

RC

12 NC

RC

11

10

9

V

SEL

NC

SEL

E2

GND

ISO

1

NC = NO CONNECT

Figure 6. ADuM5200 Pin Configuration

Table 10. ADUM5200 Pin Function Descriptions

Pin No. Mnemonic Description

Primary Supply Voltage 3.0 V to 5.5 V.

1

V_DD1

2, 8

GND₁

Ground 1. Ground reference for the isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and it is

recommended that both pins be connected to a common ground.

3

4

5

V_IA

V_IB

RC_IN

Logic Input A.

Logic Input B.

Regulation Control Input. This pin must be connected to an RC_OUTsignal from another device or tied low. Note: This

pin must not be tied high if RC_SELis low; this combination causes excessive voltage on the secondary side, damaging

the ADuM5200 and possibly the devices that it powers.

6

RC_SEL

Control Input. Determines self-regulation (RC_SELhigh) mode or slave mode (RC_SELlow) allowing external regulation.

This pin is weakly pulled to the high state. In noisy environments, tie it either high or low.

7, 12

9, 15

NC

GND_ISO

No Internal Connection.

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that

both pins be connected to a common ground.

10

11

V_E2

Data Enable Input. When high or no connect, the secondary outputs are active; when low, the outputs are in a

high-Z state.

Output Voltage Selection. When V_SEL= V_ISO, the V_ISOsetpoint is 5.0 V. When V_SEL= GND_ISO, the V_ISOsetpoint is 3.3 V. In

slave regulation mode, this pin has no function.

V_SEL

13

14

16

V_OB

V_OA

V_ISO

Logic Output B.

Logic Output A.

Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.

Rev. 0 | Page 11 of 24

ADuM5200/ADuM5201/ADuM5202

V

1

2

3

4

5

6

7

8

16

V

ISO

DD1

GND

15 GND

1

ISO

V

14

13

V

IA

OA

IB

ADuM5201

V

OB

TOP VIEW

(Not to Scale)

RC

12 NC

IN

RC

11

10

9

V

SEL

E2

V

E1

GND

ISO

1

NC = NO CONNECT

Figure 7. ADuM5201 Pin Configuration

Table 11. ADuM5201 Pin Function Descriptions

Pin No. Mnemonic Description

1

V_DD1

Primary Supply Voltage 3.0 V to 5.5 V.

2, 8

GND₁

Ground 1. Ground reference for isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and it is

recommended that both pins be connected to a common ground.

3

4

5

V_IA

V_OB

RC_IN

Logic Input A.

Logic Output B.

Regulation Control Input. This pin must be connected to an RC_OUTsignal from another device or tied low. Note: This pin

must not be tied high if RC_SELis low; this combination causes excessive voltage on the secondary side, damaging the

ADuM5201 and possibly the devices that it powers.

6

RC_SEL

Control Input. Determines self-regulation mode (RC_SELhigh) or slave mode (RC_SELlow) allowing external regulation.

This pin is weakly pulled to the high state. In noisy environments, tie it either high or low.

7

V_E1

Data Enable Input. When high or no connect, the primary output is active; when low, the outputs are in a high-Z state.

9, 15

GND_ISO

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that

both pins be connected to a common ground.

10

11

V_E2

Data Enable Input. When high or no connect, the secondary output is active; when low, the outputs are in a

high-Z state.

Output Voltage Selection. When V_SEL= V_ISO, the V_ISOsetpoint is 5.0 V. When V_SEL= GND_ISO, the V_ISOsetpoint is 3.3 V. In

slave regulation mode, this pin has no function.

V_SEL

12

13

14

16

NC

V_IB

V_OA

V_ISO

No Internal Connection.

Logic Input B.

Logic Output A.

Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.

Rev. 0 | Page 12 of 24

ADuM5200/ADuM5201/ADuM5202

V

1

2

3

4

5

6

7

8

16

V

ISO

DD1

GND

15 GND

1

OA

OB

ISO

V

14

13

V

IA

IB

ADuM5202

TOP VIEW

(Not to Scale)

RC

12 NC

11

10 NC

GND

IN

RC

V

SEL

V

E1

GND

9

1

ISO

NC = NO CONNECT

Figure 8. ADuM5202 Pin Configuration

Table 12. ADuM5202 Pin Function Descriptions

Pin No. Mnemonic Description

1

V_DD1

Primary Supply Voltage 3.0 V to 5.5 V.

2, 8

GND₁

Ground 1. Ground reference for the isolator primary. Pin 2 and Pin 8 are internally connected to each other, and it is

recommended that both pins be connected to a common ground.

3

4

5

V_OA

V_OB

RC_IN

Logic Output A.

Logic Output B.

Regulation Control Input. This pin must be connected to an RC_OUTsignal from another device or tied low. Note: This pin

must not be tied high if RC_SELis low; this combination causes excessive voltage on the secondary side, damaging the

ADuM5202 and possibly the devices that it powers.

6

RC_SEL

Control Input. Determines self-regulation (RC_SELhigh) mode or slave mode (RC_SELlow) allowing external regulation.

This pin is weakly pulled to the high state. In noisy environments, tie it either high or low.

7

V_E1

Data Enable Input. When high or no connect, the primary output is active; when low, the outputs are in a high-Z state.

9, 15

GND_ISO

Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that

both pins be connected to a common ground.

10, 12 NC

No Internal Connection.

11

13

14

16

V_SEL

V_IB

V_IA

Output Voltage Selection. When V_SEL= V_ISO, the V_ISOsetpoint is 5.0 V. When V_SEL= GND_ISO, the V_ISOsetpoint is 3.3 V.

Logic Input B.

Logic Input A.

V_ISO

Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.

Rev. 0 | Page 13 of 24

ADuM5200/ADuM5201/ADuM5202

Table 13. Truth Table (Positive Logic)

RC_IN

Input

RC_SEL

Input

V_SEL

V_DDI

V_ISO

V_IX

V_OX

Output

Input¹Input

Output Input

Operation

X

H

L

H

L

H

L

X

L

X

5.0 V

3.3 V

X

5.0 V

3.3 V

5.0 V

3.3 V

X

0 V

X

H

L

X

H

L

Master mode operation, self-regulating.

Power configuration not supported.

Master mode operation, self-regulating.

Slave mode operation, regulation from another isoPower part.

Low power mode, converter disabled.

Data outputs valid for any active power configuration.

Note: This combination of RC_INand RC_SELis prohibited. Damage

occurs on the secondary side of the converter due to excess

output voltage at V_ISO. RC_INmust be either low or a PWM signal

from a master isoPower part.

EXT-PWM¹

L

X

H

L

X

L

X

¹PWM refers to the regulation control signal. This signal is derived from the secondary side regulator or from the RC_INinput, depending on the value of RC_SEL

.

Rev. 0 | Page 14 of 24

ADuM5200/ADuM5201/ADuM5202

TYPICAL PERFORMANCE CHARACTERISTICS

40

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

35

30

25

20

POWER

DISSIPATION

15

5V IN/5V OUT

3.3V IN/3.3V OUT

10

I

DD

5

0

0.02

0.04

0.06

0.08

0.10

3.0

3.5

4.0

V

4.5

5.0

5.5

6.0

(V)

OUTPUT CURRENT (A)

DD1

Figure 9. Typical Power Supply Efficiency at 5 V/5 V and 3.3 V/3.3 V

Figure 12. Typical Short-Circuit Input Current and Power vs. V_DD1

Supply Voltage

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

90% LOAD

5V IN/5V OUT

0.2

3.3V IN/3.3V OUT

0.1

0

10% LOAD

(100µs/DIV)

0

0.02

0.04

0.06

(A)

0.08

0.10

0.12

I

ISO

Figure 13. Typical V_ISOTransient Load Response 5 V Output

10% to 90% Load Step

Figure 10. Typical Total Power Dissipation vs. I_ISOwith Data Channels Idle

0.12

0.10

0.08

0.06

0.04

90% LOAD

0.02

10% LOAD

5V IN/5V OUT

3.3V IN/3.3V OUT

0

(100µs/DIV)

0

0.05

0.10

0.15

0.20

0.25

0.30

INPUT CURRENT (A)

Figure 11. Typical Isolated Output Supply Current, I_ISOas a Function of

External Load, No Dynamic Current Draw at 5 V/5 V and 3.3 V/3.3 V

Figure 14. Typical Transient Load Response 3 V Output 10% to

90% Load Step

Rev. 0 | Page 15 of 24

ADuM5200/ADuM5201/ADuM5202

20

16

12

8

25

BW = 20MHz

5V IN/5V OUT

3.3V IN/3.3V OUT

20

15

10

5

4

0

–5

0

5

10

15

20

25

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

DATA RATE (Mbps)

TIME (µs)

Figure 18. Typical I_CHSupply Current per Reverse Data Channel

(15 pF Output Load)

Figure 15. Typical V_ISO= 5 V Output Voltage Ripple at 90% Load

5

16

BW = 20MHz

14

5V

4

3.3V

12

10

8

3

2

6

4

1

2

0

5

10

15

20

25

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

DATA RATE (Mbps)

TIME (µs)

Figure 16. Typical V_ISO= 3.3 V Output Voltage Ripple at 90% Load

Figure 19. Typical I_ISO(D)Dynamic Supply Current per Input

20

3.0

5V IN/5V OUT

3.3V IN/3.3V OUT

2.5

2.0

1.5

1.0

0.5

0

16

12

8

5V

3.3V

4

0

5

10

15

20

25

0

5

10

15

20

25

DATA RATE (Mbps)

Figure 17. Typical I_CHSupply Current per Forward Data Channel

(15 pF Output Load)

Figure 20. Typical I_ISO(D)Dynamic Supply Current per Output

(15 pF Output Load)

Rev. 0 | Page 16 of 24

ADuM5200/ADuM5201/ADuM5202

TERMINOLOGY

t_PLHPropagation Delay

_PLHpropagation delay is measured from the 50% level of the

rising edge of the V_Ixsignal to the 50% level of the rising edge of

I_DD1(Q)

t

I_DD1(Q)is the minimum operating current drawn at the V_DD1pin

when there is no external load at V_ISOand the I/O pins are oper-

ating below 2 Mbps, requiring no additional dynamic supply

current. I_DD1(Q)reflects the minimum current operating

condition.

the V_Oxsignal.

Propagation Delay Skew (t_PSK

)

t_PSKis the magnitude of the worst-case difference in t_PHLand/or

t_PLHthat is measured between units at the same operating

temperature, supply voltages, and output load within the

recommended operating conditions.

I_DD1(D)

I

_DD1(D)is the typical input supply current with all channels

simultaneously driven at a maximum data rate of 25 Mbps with

the full capacitive load representing the maximum dynamic

load conditions. Treat resistive loads on the outputs separately

from the dynamic load.

Channel-to-Channel Matching

Channel-to-channel matching is the absolute value of the

difference in propagation delays between the two channels

when operated with identical loads.

I_DD1(MAX)

I

_DD1(MAX)is the input current under full dynamic and V_ISOload

Minimum Pulse Width

The minimum pulse width is the shortest pulse width at which

the specified pulse width distortion is guaranteed.

conditions.

t

_PHLPropagation Delay

t_PHLpropagation delay is measured from the 50% level of the

Maximum Data Rate

falling edge of the V_Ixsignal to the 50% level of the falling edge

of the V_Oxsignal.

The maximum data rate is the fastest data rate at which the

specified pulse width distortion is guaranteed.

Rev. 0 | Page 17 of 24

ADuM5200/ADuM5201/ADuM5202

APPLICATIONS INFORMATION

The dc-to-dc converter section of the ADuM520x works on

principles that are common to most power supplies. It has a

secondary side controller architecture with isolated pulse-width

modulation (PWM) feedback. V_DD1power is supplied to an

oscillating circuit that switches current into a chip scale air core

transformer. Power transferred to the secondary side is rectified

and regulated to either 3.3 V or 5 V. The secondary (V_ISO) side

controller regulates the output by creating a PWM control signal

that is sent to the primary (V_DD1) side by a dedicated iCoupler

data channel. The PWM modulates the oscillator circuit to control

the power being sent to the secondary side. Feedback allows for

significantly higher power and efficiency.

Note that the total lead length between the ends of the low ESR

capacitor and the input power supply pin must not exceed 2 mm.

Installing the bypass capacitor with traces more than 2 mm in

length may result in data corruption. Consider bypassing between

Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless both of the

common ground pins are connected together close to the

package.

BYPASS < 2mm

V

DD1

ISO

GND

/V

GND

1

ISO

V

/V

IA OA

OA IA

V

/V

IB OB

/V

OB IB

RC

NC

IN

The ADuM520x implements undervoltage lockout (UVLO) with

hysteresis on the V_DD1power input. This feature ensures that the

converter does not enter oscillation due to noisy input power or

slow power on ramp rates.

RC

V

SEL

/NC

E2

V

/NC

E1

GND

ISO

1

Figure 21. Recommended PCB Layout

A minimum load current of 10 mA is recommended to ensure

optimum load regulation. Smaller loads can generate excess noise on

chip due to short or erratic PWM pulses. Excess noise generated

this way can cause data corruption in some circumstances.

In applications involving high common-mode transients, ensure

that board coupling across the isolation barrier is minimized.

Furthermore, design the board layout such that any coupling

that does occur equally affects all pins on a given component

side. Failure to ensure this can cause differential voltages

between pins exceeding the absolute maximum ratings for the

device (specified in Table 8) thereby leading to latch-up and/or

permanent damage.

The ADuM520x can accept an external regulation control signal

(RC_IN) that can be connected to other isoPower devices. This

allows a single regulator to control multiple power modules

without contention. When accepting control from a master

power module, the V_ISOpins can be connected together adding

their power. Because there is only one feedback control path, the

supplies work together seamlessly. The ADuM520x can only

regulate itself or accept regulation (slave device) from another

device in this product line; it cannot provide a regulation signal

to other devices.

The ADuM520x is a power device that dissipates approximately

1 W of power when fully loaded and running at maximum speed.

Because it is not possible to apply a heat sink to an isolation

device, the device primarily depends on heat dissipation into

the PCB through the GND pins. If the device is used at high

ambient temperatures, provide a thermal path from the GND

pins to the PCB ground plane. The board layout in Figure 21

shows enlarged pads for Pin 2, Pin 8, Pin 9, and Pin 15. Multiple

vias should be implemented from the pad to the ground plane

to significantly reduce the temperature inside the chip. The

dimensions of the expanded pads are at the discretion of the

designer and depend on the available board space.

PCB LAYOUT

The ADuM520x digital isolators with 0.5 W isoPower integrated

dc-to-dc converters require no external interface circuitry for the

logic interfaces. Power supply bypassing is required at the input and

output supply pins (see Figure 21). Note that low ESR bypass

capacitors are required between Pin 1 and Pin 2 and between Pin

15 and Pin 16, as close to the chip pads as possible.

EMI CONSIDERATIONS

The dc-to-dc converter section of the ADuM520x components

must operate at a very high frequency to allow efficient power

transfer through the small transformers. This creates high

frequency currents that can propagate in circuit board ground

and power planes, causing edge emissions and dipole radiation

between the primary and secondary ground planes. Grounded

enclosures are recommended for applications that use these

devices. If grounded enclosures are not possible, follow good RF

design practices in layout of the PCB. See www.analog.com for the

most current PCB layout recommendations specifically for the

ADuM520x.

The power supply section of the ADuM520x uses a 180 MHz

oscillator frequency to efficiently pass power through its chip

scale transformers. In addition, normal operation of the data

section of the iCoupler introduces switching transients on the

power supply pins. Bypass capacitors are required for several

operating frequencies. Noise suppression requires a low induc-

tance, high frequency capacitor, whereas ripple suppression and

proper regulation require a large value capacitor. These are most

conveniently connected between Pin 1 and Pin 2 for V_DD1and

between Pin 15 and Pin 16 for V_ISO. To suppress noise and reduce

ripple, a parallel combination of at least two capacitors is required.

The recommended capacitor values are 0.1 μF and 10 μF for V_DD1

.

The smaller capacitor must have a low ESR; for example, use of a

ceramic capacitor is advised.

Rev. 0 | Page 18 of 24

ADuM5200/ADuM5201/ADuM5202

50% of the 0.5 V margin at the decoder, a maximum allowable

magnetic field is calculated as shown in Figure 23.

PROPAGATION DELAY PARAMETERS

Propagation delay is a parameter that describes the time it takes a

logic signal to propagate through a component. The propagation

delay to a logic low output may differ from the propagation delay

to a logic high.

100

10

1

INPUT (V

)

50%

IX

t_PLH

t_PHL

OUTPUT (V

)

50%

OX

0.1

Figure 22. Propagation Delay Parameters

0.01

Pulse width distortion is the maximum difference between these

two propagation delay values and is an indication of how

accurately timing of the input signal is preserved.

0.001

1k

10k

100k

1M

10M

100M

Channel-to-channel matching refers to the maximum amount

the propagation delay differs between channels within a single

ADuM520x component.

MAGNETIC FIELD FREQUENCY (Hz)

Figure 23. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the

maximum allowable magnetic field of 0.2 kgauss induces a

voltage of 0.25 V at the receiving coil. This is about 50% of the

sensing threshold and does not cause a faulty output transition.

Similarly, if such an event occurs during a transmitted pulse

(and is of the worst-case polarity), it reduces the received pulse

from >1.0 V to 0.75 V—still well above the 0.5 V sensing

threshold of the decoder.

Propagation delay skew refers to the maximum amount the

propagation delay differs between multiple ADuM520x

components operating under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input

cause narrow (~1 ns) pulses to be sent to the decoder via the

transformer. The decoder is bistable and is, therefore, either set

or reset by the pulses, indicating input logic transitions. In the

absence of logic transitions at the input for more than 1 μs, a

periodic set of refresh pulses indicative of the correct input state

are sent to ensure dc correctness at the output. If the decoder

receives no internal pulses of more than about 5 μs, the input

side is assumed to be unpowered or nonfunctional, in which case

the isolator output is forced to a default state (see Table 13) by

the watchdog timer circuit.

The preceding magnetic flux density values correspond to

specific current magnitudes at given distances from the

ADuM520x transformers. Figure 24 expresses these allowable

current magnitudes as a function of frequency for selected

distances. As shown, the ADuM520x is extremely immune and

can be affected only by extremely large currents operated at

high frequency very close to the component. For the 1 MHz

example noted, a 0.5 kA current placed 5 mm away from the

ADuM520x is required to affect the operation of the

component.

The limitation on the magnetic field immunity of the ADuM520x

is set by the condition in which induced voltage in the receiving

coil of the transformer is sufficiently large to either falsely set or

reset the decoder. The following analysis defines the conditions

under which this may occur. The 3 V operating condition of the

ADuM520x is examined because it represents the most suscept-

ible mode of operation.

1000

DISTANCE = 1m

100

10

The pulses at the transformer output have an amplitude greater

than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus

establishing a 0.5 V margin in which induced voltages can be

tolerated. The voltage induced across the receiving coil is given by

DISTANCE = 100mm

1

DISTANCE = 5mm

0.1

2

V = (−dβ/dt)∑πr_n; n = 1, 2, … , N

where:

0.01

1k

10k

100k

1M

10M

100M

β is the magnetic flux density (gauss).

N is the number of turns in the receiving coil.

r_nis the radius of the n^thturn in the receiving coil (cm).

MAGNETIC FIELD FREQUENCY (Hz)

Figure 24. Maximum Allowable Current

for Various Current-to-ADuM520x Spacings

Given the geometry of the receiving coil in the ADuM520x and

an imposed requirement that the induced voltage be, at most,

Note that at combinations of strong magnetic field and high

frequency, any loops formed by PCB traces can induce error

Rev. 0 | Page 19 of 24

ADuM5200/ADuM5201/ADuM5202

voltages sufficiently large enough to trigger the thresholds of

succeeding circuitry. Exercise care in the layout of such traces

to avoid this possibility.

The preceding analysis assumes a 15 pF capacitive load on each

data output. If the capacitive load is larger than 15 pF, the addi-

tional current must be included in the analysis of I_DD1and I_ISO(LOAD)

.

To determine I_DD1in Equation 1, additional primary side dynamic

output current (I_AOD) is added directly to I_DD1. Additional sec-

ondary side dynamic output current (I_AOD) is added to I_ISOon a

per channel basis.

POWER CONSUMPTION

The V_DD1power supply input provides power to the iCoupler

data channels as well as to the power converter. For this reason,

the quiescent currents drawn by the data converter and the

primary and secondary input/output channels cannot be

determined separately. All of these quiescent power demands

have been combined into the I_DD1(Q)current shown in Figure 25.

The total I_DD1supply current is the sum of the quiescent operating

current, dynamic current I_DD1(D)demanded by the I/O channels,

and any external I_ISOload.

To determine I_ISO(LOAD)in Equation 2, additional secondary side

output current (I_AOD) is subtracted from I_ISO(MAX)on a per

channel basis.

For each output channel with C_Lgreater than 15 pF, the

additional capacitive supply current is given by

I

_AOD= 0.5 × 10⁻³× (C_L− 15) × V_ISO) × (2f − f_r) f > 0.5 f_r(3)

E

where:

I

ISO

DD1(Q)

CONVERTER

PRIMARY

CONVERTER

SECONDARY

C_Lis the output load capacitance (pF).

I

DD1(D)

V

_ISOis the output supply voltage (V).

I

f is the input logic signal frequency (MHz); it is half of the input

DDP(D)

ISO(D)

data rate expressed in units of Mbps.

f_ris the input channel refresh rate (Mbps).

PRIMARY

DATA I/O

2-CHANNEL

SECONDARY

DATA I/O

2-CHANNEL

CURRENT LIMIT AND THERMAL OVERLOAD

PROTECTION

Figure 25. Power Consumption Within the ADuM520x

The ADuM520x is protected against damage due to excessive

power dissipation by thermal overload protection circuits. Thermal

overload protection limits the junction temperature to a maximum

of 150°C (typical). Under extreme conditions (that is, high am-

bient temperature and power dissipation), when the junction

temperature starts to rise above 150°C, the PWM is turned off,

reducing the output current to zero. When the junction temper-

ature drops below 130°C (typical), the PWM turns on again,

restoring the output current to its nominal value.

Both dynamic input and output current is consumed only when

operating at channel speeds higher than the rate of f_r. Because

each channel has a dynamic current determined by its data rate,

Figure 17 shows the current for a channel in the forward direction,

which means that the input is on the primary side of the part.

Figure 18 shows the current for a channel in the reverse direction,

which means that the input is on the secondary side of the part.

Both figures assume a typical 15 pF load. The following relation-

ship allows the total I_DD1current to be calculated:

Consider the case where a hard short from V_ISOto ground

occurs. At first, the ADuM520x reaches its maximum current,

which is proportional to the voltage applied at V_DD1. Power

dissipates on the primary side of the converter (see Figure 12).

If self-heating of the junction becomes great enough to cause its

temperature to rise above 150°C, thermal shutdown activates,

turning off the PWM and reducing the output current to zero.

As the junction temperature cools and drops below 130°C, the

PWM turns on and power dissipates again on the primary side

of the converter, causing the junction temperature to rise to

150°C again. This thermal oscillation between 130°C and 150°C

causes the part to cycle on and off as long as the short remains

at the output.

I

_DD1= (I_ISO× V_ISO)/(E × V_DD1) + ∑ I_CHn; n = 1 to 4

(1)

where :

I

_DD1is the total supply input current.

_CHnis the current drawn by a single channel determined from

Figure 17 or Figure 18, depending on channel direction.

_ISOis the current drawn by the secondary side external loads.

E is the power supply efficiency at 100 mA load from Figure 9 at

the V_ISOand V_DD1condition of interest.

I

Calculate the maximum external load by subtracting the

dynamic output load from the maximum allowable load.

I

_ISO(LOAD)= I_ISO(MAX)− ∑ I_ISO(D)n; n = 1 to 4

where:

_ISO(LOAD)is the current available to supply an external secondary

side load.

_ISO(MAX)is the maximum external secondary side load current

available at V_ISO

_ISO(D)nis the dynamic load current drawn from V_ISOby an input

(2)

Thermal limit protections are intended to protect the device

against accidental overload conditions. For reliable operation,

externally limit device power dissipation to prevent junction

temperatures from exceeding 130°C.

I

.

I

or output channel, as shown in Figure 17 and Figure 18. Data is

presented assuming a typical 15 pF load

Rev. 0 | Page 20 of 24

ADuM5200/ADuM5201/ADuM5202

outputs are placed in their high impedance state, or the outputs

detect a lack of activity from the primary side inputs and the

outputs are set to their default low value before the secondary

power reaches UVLO.

POWER CONSIDERATIONS

The ADuM5200/ADuM5201/ADuM5202 power input, data

input channels on the primary side, and data input channels on

the secondary side are all protected from premature operation by

UVLO circuitry. Below the minimum operating voltage, the

power converter holds its oscillator inactive and all input channel

drivers and refresh circuits are idle. Outputs remain in a high

impedance state to prevent transmission of undefined states

during power-up and power-down operations.

THERMAL ANALYSIS

The ADuM520x consists of four internal die, attached to a split

lead frame with two die attach paddles. For the purposes of

thermal analysis, it is treated as a thermal unit with the highest

junction temperature reflected in the θ_JAfrom Table 3. The

value of θ_JAis based on measurements taken with the part

mounted on a JEDEC standard 4-layer board with fine width

traces and still air. Under normal operating conditions, the

ADuM520x operates at full load across the full temperature

range without derating the output current. However, following

the recommendations in the PCB Layout section decreases the

thermal resistance to the PCB allowing increased thermal margin

at high ambient temperatures.

During application of power to V_DD1, the primary side circuitry is

held idle until the UVLO preset voltage is reached. At that time,

the data channels initialize to their default low output state until

they receive data pulses from the secondary side.

When the primary side is above the UVLO threshold, the data input

channels sample their inputs and begin sending encoded pulses to

the inactive secondary output channels. The outputs on the primary

side remain in their default low state because no data comes from

the secondary side inputs until secondary power is established. The

primary side oscillator also begins to operate, transferring power to

the secondary power circuits. The secondary V_ISOvoltage is below its

UVLO limit at this point; the regulation control signal from the

secondary is not being generated. The primary side power oscillator

is allowed to free run in this circumstance, supplying the maximum

amount of power to the secondary, until the secondary voltage rises

to its regulation setpoint. This creates a large inrush current transient

at V_DD1. When the regulation point is reached, the regulation

control circuit produces the regulation control signal that

modulates the oscillator on the primary side. The V_DD1current is

reduced and is then proportional to the load current. The inrush

current is less than the short-circuit current shown in Figure 12.

The duration of the inrush depends on the V_ISOloading conditions

and the current available at the V_DD1pin.

INCREASING AVAILABLE POWER

The ADuM520x devices are designed with the capability of

running in combination with other compatible isoPower

devices. The RC_INand RC_SELpins allow the ADuM520x to

receive a PWM signal from another device through the RC_IN

pin and act as a slave to that control signal. The RC_SELpin

chooses whether the part acts as a standalone self-regulated

device or a slave device. When the ADuM520x is acting as a

slave, its power is regulated by a PWM signal coming from a

master device. This allows multiple isoPower parts to be

combined in parallel while sharing the load equally. When the

ADuM520x is configured as a standalone unit, it generates its

own PWM feedback signal to regulate itself.

The ADuM5000 can act as a master or a slave device, the

ADuM5401, ADuM5402, ADuM5403, and ADuM5404 can

only be master/standalone, and the ADuM520x can only be a

slave/standalone device. This means that the ADuM5000,

ADuM520x, and ADuM5401 to ADuM5404 can only be used

in certain master/slave combinations as listed in Table 14.

As the secondary side converter begins to accept power from the

primary, the V_ISOvoltage starts to rise. When the secondary side

UVLO is reached, the secondary side outputs are initialized to

their default low state until data is received from the corresponding

primary side input. It can take up to 1 μs after the secondary side

is initialized for the state of the output to correlate with the pri-

mary side input.

Table 14. Allowed Combinations of isoPower Parts

Slave

ADuM5401 to

ADuM5404

Secondary side inputs sample their state and transmit it to the

primary side. Outputs are valid about 1 μs after the secondary

side becomes active.

Master

ADuM5000

ADuM520x

ADuM5000

ADuM520x

Yes

No

Yes

No

Because the rate of charge of the secondary side power supply is

dependent on loading conditions, the input voltage, and the

output voltage level selected, take care with the design to allow

the converter sufficient time to stabilize before valid data is

required.

Yes

ADuM5401 to

ADuM5404

The allowed combinations of master and slave configured parts

listed in Table 14 is sufficient to make any combination of power

and channel count.

When power is removed from V_DD1, the primary side converter

and coupler shut down when the UVLO level is reached. The

secondary side stops receiving power and starts to discharge. The

outputs on the secondary side hold the last state that they received

from the primary side. Either the UVLO level is reached and the

Table 15 illustrates how isoPower devices can provide many

combinations of data channel count and multiples of the single

unit power.

Rev. 0 | Page 21 of 24

ADuM5200/ADuM5201/ADuM5202

Table 15. Configurations for Power and Data Channels

Number of Data Channels

4

Power Units

1-Unit Power

0

2

6

ADuM5000 master

ADuM520x master

ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master

ADuM121x

ADuM5000 master

ADuM5000 slave

ADuM5000 master

ADuM5000 slave

ADuM5000 master

ADuM520x slave

ADuM5000 master

ADuM5000 slave

ADuM520x slave

ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master

2-Unit Power

3-Unit Power

ADuM520x slave

ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master

ADuM5000 slave

ADuM520x slave

ADuM5000 slave

INSULATION LIFETIME

In the case of unipolar ac or dc voltage, the stress on the insula-

tion is significantly lower. This allows operation at higher working

voltages while still achieving a 50-year service life. The working

voltages listed in Table 9 can be applied while maintaining the

50-year minimum lifetime, provided the voltage conforms to

either the unipolar ac or dc voltage cases. Any cross insulation

voltage waveform that does not conform to Figure 27 or Figure 28

should be treated as a bipolar ac waveform and its peak voltage

limited to the 50-year lifetime voltage value listed in Table 9.

The voltage presented in Figure 27 is shown as sinusoidal for

illustration purposes only. It is meant to represent any voltage

waveform varying between 0 V and some limiting value. The

limiting value can be positive or negative, but the voltage cannot

cross 0 V.

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period. The rate of insu-

lation degradation is dependent on the characteristics of the

voltage waveform applied across the insulation. In addition to the

testing performed by the regulatory agencies, Analog Devices

carries out an extensive set of evaluations to determine the

lifetime of the insulation structure within the ADuM520x.

Analog Devices performs accelerated life testing using voltage

levels higher than the rated continuous working voltage. Acce-

leration factors for several operating conditions are determined.

These factors allow calculation of the time to failure at the actual

working voltage. The values shown in Table 9 summarize the

peak voltage for 50 years of service life for a bipolar ac operating

condition, and the maximum CSA/VDE approved working vol-

tages. In many cases, the approved working voltage is higher than

a 50-year service life voltage. Operation at these high working

voltages can lead to shortened insulation life in some cases.

RATED PEAK VOLTAGE

0V

Figure 26. Bipolar AC Waveform

The insulation lifetime of the ADuM520x depends on the voltage

waveform type imposed across the isolation barrier. The iCoupler

insulation structure degrades at different rates depending on

whether the waveform is bipolar ac, unipolar ac, or dc. Figure 26,

Figure 27, and Figure 28 illustrate these different isolation

voltage waveforms.

RATED PEAK VOLTAGE

0V

Figure 27. Unipolar AC Waveform

Bipolar ac voltage is the most stringent environment. The goal

of a 50-year operating lifetime under the ac bipolar condition

determines the maximum working voltage recommended by

Analog Devices.

RATED PEAK VOLTAGE

0V

Figure 28. DC Waveform

Rev. 0 | Page 22 of 24

ADuM5200/ADuM5201/ADuM5202

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

16

1

9

8

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

45°

1.27 (0.0500)

BSC

0.25 (0.0098)

2.65 (0.1043)

2.35 (0.0925)

0.30 (0.0118)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 29. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Number of Number of Maximum Maximum

Maximum

Inputs,

V_DD1Side

Inputs,

V_DD2Side

Data Rate Propagation Pulse Width

(Mbps)

Temperature

Delay, 5 V (ns) Distortion (ns) Range

Package

Description

Package

Option

Model

ADuM5200ARWZ^{1, 2}

ADuM5200CRWZ^{1, 2}

ADuM5201ARWZ^{1, 2}

ADuM5201CRWZ^{1, 2}

ADuM5202ARWZ^{1, 2}

ADuM5202CRWZ^{1, 2}

2

0

1

25

1

25

1

25

100

70

40

3

−40°C to +105°C 16-Lead SOIC_W RW-16

2

1

0

1

2

100

70

40

3

100

70

40

3

1

Tape and reel are available. The additional -RL suffix designates a 13-inch (1,000 units) tape and reel option.

Z = RoHS Compliant Part.

2

Rev. 0 | Page 23 of 24

ADuM5200/ADuM5201/ADuM5202

NOTES

registered trademarks are the property of their respective owners.

D07540-0-10/08(0)

Rev. 0 | Page 24 of 24


型号：	ADUM5201CRWZ
厂家：	ADI
描述：	Dual Channel Isolators with Integrated DC-to-DC Converter 双通道隔离器，集成DC- DC转换器转换器
文件：	总24页 (文件大小：544K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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