ADUM3441CRWZ [ADI]
Quad Channel, High Speed Digital Isolators; 四通道高速数字隔离器
| 型号： | ADUM3441CRWZ |
| 厂家： | 
ADI |
| 描述： | Quad Channel, High Speed Digital Isolators |
| 文件： | 总24页 (文件大小：389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Channel, High Speed
Digital Isolators
Data Sheet
ADuM3440/ADuM3441/ADuM3442
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Low power operation
5 V operation
1
2
3
16
15
14
V
ADuM3440
V
DD2
DD1
GND
V
GND
1
2
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
V
1.7 mA per channel maximum @ 0 Mbps to 2 Mbps
68 mA per channel maximum @ 150 Mbps
3.3 V operation
1.0 mA per channel maximum @ 0 Mbps to 2 Mbps
33 mA per channel maximum @ 150 Mbps
Bidirectional communication
IA
IB
OA
V
4
5
13
12
V
OB
V
V
V
IC
ID
OC
6
7
8
11
10
9
V
OD
NC
GND
V
E2
GND
1
2
Figure 1. ADuM3440 Functional Block Diagram
3.3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 150 Mbps (NRZ)
Precise timing characteristics
5 ns maximum pulse width distortion
5 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE certificate of conformity
ADuM3441
1
2
3
16
15
14
V
V
DD1
DD2
GND
GND
1
2
V
V
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
V
V
V
IA
OA
OB
OC
4
5
13
12
IB
V
IC
6
7
8
11
10
9
V
V
V
OD
ID
V
E1
E2
GND
GND
1
2
Figure 2. ADuM3441 Functional Block Diagram
1
2
3
16
15
14
V
ADuM3442
V
DD1
DD2
GND
GND
1
2
V
V
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
V
V
V
IA
OA
OB
IC
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
4
5
13
12
IB
V
IORM = 560 V peak
V
V
OC
OD
APPLICATIONS
6
7
8
11
10
9
V
V
ID
V
High speed multichannel isolation
SPI interface/data converter isolation
Instrumentation
E1
E2
GND
GND
1
2
Figure 3. ADuM3442 Functional Block Diagram
GENERAL DESCRIPTION
The ADuM344x1 are four channel, digital isolators based on the
Analog Devices, Inc., iCoupler® technology supporting data rates
up to 150 Mbps. Combining high speed CMOS and monolithic
air core transformer technology, these isolation components
provide outstanding performance characteristics superior to
alternatives such as optocoupler devices.
Furthermore, iCoupler devices consume one-tenth to one-sixth
the power of optocouplers at comparable signal data rates.
The ADuM344x isolators provide four independent isolation
channels in a variety of channel configurations (see the
Ordering Guide). The ADuM344x operates with the supply
voltage on either side ranging from 3.0 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling
voltage translation functionality across the isolation barrier. In
addition, the ADuM344x provides low pulse width distortion
and tight channel-to-channel matching. Unlike other opto-
coupler alternatives, the ADuM344x isolators have a patented
refresh feature that ensures dc correctness in the absence of
input logic transitions and during the power-up/power-down
condition.
By avoiding the use of LEDs and photodiodes, iCoupler
devices remove the design difficulties commonly associated
with optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.
ADuM3440/ADuM3441/ADuM3442
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 16
Applications Information .............................................................. 18
PC Board Layout ........................................................................ 18
Propagation Delay-Related Parameters................................... 18
System-Level ESD Considerations and Enhancements ........ 18
DC Correctness and Magnetic Field Immunity........................... 18
Power Consumption .................................................................. 19
Insulation Lifetime..................................................................... 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3.3 V Operation ............................ 5
Electrical Characteristics—Mixed 5 V/3.3 V or 3.3 V/5 V
Operation....................................................................................... 7
Package Characteristics ............................................................. 10
Regulatory Information............................................................. 10
Insulation and Safety-Related Specifications.......................... 10
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 11
Recommended Operating Conditions .................................... 11
REVISION HISTORY
2/12—Rev. C to Rev. D
9/08—Rev. A to Rev. B
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PC Board Layout Section............................................ 18
Updated Outline Dimensions....................................................... 21
Changes to Pulse Width Distortion, |tPLH − tPHL| Parameter and
Channel-to-Channel Matching, Codirectional Channels
Parameter, Table 1 .............................................................................3
Changes to Pulse Width Distortion, |tPLH − tPHL| Parameter and
Channel-to-Channel Matching, Codirectional Channels
Parameter, Table 2 .............................................................................5
Changes to Pulse Width Distortion, |tPLH − tPHL| Parameter and
Channel-to-Channel Matching, Codirectional Channels
Parameter, Table 3 .............................................................................8
1/09—Rev. B to Rev. C
Change to Propagation Delay Parameter (Table 1)...................... 3
Change to Propagation Delay Parameter (Table 2)...................... 5
Change to Propagation Delay Parameter (Table 3)...................... 8
5/08—Rev. 0 to Rev. A
Changes to Ordering Guide.......................................................... 21
11/07—Rev. 0: Initial Version
Rev. D | Page 2 of 24
Data Sheet
ADuM3440/ADuM3441/ADuM3442
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications
apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM3440, Total Supply Current, Four Channels1
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.75
0.5
1.3
1.2
mA
mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
3
2
3.9
3
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (150)
IDD2 (150)
120
47
220 mA
75 MHz logic signal frequency
75 MHz logic signal frequency
55
mA
ADuM3441, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
2.8
2.3
3.6
2.9
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current
VDD2 Supply Current
ADuM3442, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 or VDD2 Supply Current
150 Mbps
VDD1 or VDD2 Supply Current
For All Models
IDD1 (150)
IDD2 (150)
101
65
165 mA
75 MHz logic signal frequency
75 MHz logic signal frequency
80
mA
mA
IDD1 (Q), IDD2 (Q)
2.5
83
3.5
DC to 1 MHz logic signal frequency
75 MHz logic signal frequency
IDD1 (150), IDD2 (150)
130 mA
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
−10
2.0
+0.01 +10 µA
V
0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIH, VEH
VIL, VEL
VOAH, VOBH
0.8
V
V
,
(VDD1 or
VDD2) − 0.1
(VDD1 or
VDD2) − 0.4
5.0
4.8
0.0
IOx = −20 µA, VIx = VIxH
VOCH, VODH
V
V
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
,
0.1
VOCL, VODL
0.04
0.2
0.1
0.4
V
V
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
Minimum Pulse Width2
Maximum Data Rate3
PW
6.67 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
150
20
Propagation Delay4
tPHL, tPLH
PWD
32
2
5
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels5
|
0.5
3
ns
ps/°C
ns
ns
tPSK
tPSKCD
12
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing Directional Channels5
Rev. D | Page 3 of 24
ADuM3440/ADuM3441/ADuM3442
Data Sheet
Parameter
Symbol
tPHZ, tPLH
tPZH, tPZL
Min
Typ
Max Unit
Test Conditions
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output7
Common-Mode Transient Immunity
at Logic Low Output7
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
tR/tF
|CMH|
2.5
35
ns
kV/µs
25
25
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.2
0.196
0.1
Mbps
mA/Mbps
mA/Mbps
Input Dynamic Supply Current per Channel8
Output Dynamic Supply Current per Channel8
IDDI (D)
IDDO (D)
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDO. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. D | Page 4 of 24
Data Sheet
ADuM3440/ADuM3441/ADuM3442
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V.
Table 2.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM3440, Total Supply Current, Four Channels1
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.43
0.3
0.90 mA
0.60 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.7
1.2
2.4
1.7
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (150)
IDD2 (150)
63
17
110
25
mA
mA
75 MHz logic signal frequency
75 MHz logic signal frequency
ADuM3441, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.6
1.3
2.2
1.9
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current
VDD2 Supply Current
ADuM3442, Total Supply Current, Four Channels1
IDD1 (150)
IDD2 (150)
52
29
80
40
mA
mA
75 MHz logic signal frequency
75 MHz logic signal frequency
DC to 2 Mbps
VDD1 or VDD2 Supply Current
150 Mbps
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
1.5
40
2.0
66
mA
mA
DC to 1 MHz logic signal frequency
75 MHz logic signal frequency
IDD1 (150), IDD2 (150)
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
−10
1.6
+0.01 +10 µA
V
0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIH, VEH
VIL, VEL
VOAH, VOBH
0.4
V
V
,
(VDD1 or
VDD2) − 0.1
(VDD1 or
VDD2) − 0.4
3.0
2.8
0.0
IOx = −20 µA, VIx = VIxH
VOCH, VODH
V
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
,
0.1
IOx = 20 µA, VIx = VIxL
VOCL, VODL
0.04
0.2
0.1
0.4
V
V
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
Minimum Pulse Width2
Maximum Data Rate3
PW
6.67 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
150
20
Propagation Delay4
tPHL, tPLH
PWD
36
2
4
0.5
3
ns
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
|
ps/°C
ns
ns
tPSK
tPSKCD
16
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing Directional Channels5
Rev. D | Page 5 of 24
ADuM3440/ADuM3441/ADuM3442
Data Sheet
Parameter
Symbol
tPHZ, tPLH
tPZH, tPZL
Min
Typ
Max Unit
Test Conditions
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
Common-Mode Transient Immunity
at Logic High Output7
Common-Mode Transient Immunity
at Logic Low Output7
|CMH|
25
25
35
kV/µs
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.1
0.076
0.028
Mbps
mA/Mbps
mA/Mbps
Input Dynamic Supply Current per Channel8
Output Dynamic Supply Current per Channel8
IDDI (D)
IDDO (D)
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDO. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. D | Page 6 of 24
Data Sheet
ADuM3440/ADuM3441/ADuM3442
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OR 3.3 V/5 V OPERATION
All voltages are relative to their respective ground. 5 V/3.3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation:
3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted. All typical specifications are at TA = 25°C; VDD1 = 3.3 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.3 V.
Table 3.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
5 V/3.3 V Operation
IDDI (Q)
0.75
0.43
1.3
0.9
mA
mA
3.3 V/5 V Operation
Output Supply Current per Channel, Quiescent
5 V/3.3 V Operation
IDDO (Q)
0.3
0.5
0.7
1.2
mA
mA
3.3 V/5 V Operation
ADuM3440, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
IDD1 (Q)
3
1.7
3.9
2.4
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
VDD2 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
IDD2 (Q)
1.2
2
1.7
3
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
IDD1 (150)
120
63
220
110
mA
mA
75 MHz logic signal frequency
75 MHz logic signal frequency
VDD2 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
IDD2 (150)
17
47
25
55
mA
mA
75 MHz logic signal frequency
75 MHz logic signal frequency
ADuM3441, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
IDD1 (Q)
2.8
1.6
3.6
2.2
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
VDD2 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
IDD2 (Q)
1.3
2.3
1.9
2.9
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
150 Mbps
VDD1 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
IDD1 (150)
101
52
165
80
mA
mA
75 MHz logic signal frequency
75 MHz logic signal frequency
VDD2 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
IDD2 (150)
29
65
40
80
mA
mA
75 MHz logic signal frequency
75 MHz logic signal frequency
ADuM3442, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
IDD1 (Q)
2.5
1.5
3.5
2.0
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
VDD2 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
IDD2 (Q)
1.5
2.5
2.0
3.5
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
Rev. D | Page 7 of 24
ADuM3440/ADuM3441/ADuM3442
Data Sheet
Parameter
150 Mbps
VDD1 Supply Current
Symbol
Min
Typ
Max Unit
Test Conditions
IDD1 (150)
5 V/3.3 V Operation
3.3 V/5 V Operation
VDD2 Supply Current
5 V/3.3 V Operation
3.3 V/5 V Operation
83
40
130
66
mA
mA
75 MHz logic signal frequency
75 MHz logic signal frequency
IDD2 (150)
40
83
66
130
mA
mA
75 MHz logic signal frequency
75 MHz logic signal frequency
For All Models
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
−10
+0.01
+10
µA
0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2
0 ≤ VE1,VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
5 V/3.3 V Operation
3.3 V/5 V Operation
VIH, VEH
2.0
1.6
V
V
Logic Low Input Threshold
5 V/3.3 V Operation
3.3 V/5 V Operation
VIL, VEL
0.8
0.4
V
V
V
Logic High Output Voltages
VOAH, VOBH
,
(VDD1 or
(VDD1 or
IOx = −20 µA, VIx = VIxH
VOCH, VODH
VDD2) − 0.1 VDD2
)
(VDD1 or (VDD1 or
VDD2) − 0.4 VDD2) − 0.2
0.0
V
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
,
0.1
IOx = 20 µA, VIx = VIxL
VOCL, VODL
0.04
0.2
0.1
0.4
V
V
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
PW
6.67
ns
Mbps
ns
ns
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
150
20
0.5
3
tPHL, tPLH
PWD
35
2
4
|
tPSK
tPSKCD
15
2
Channel-to-Channel Matching,
Codirectional Channels6
ns
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing Directional Channels5
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
tPHZ, tPLH
tPZH, tPZL
tR/tF
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
3.0
2.5
ns
ns
Common-Mode Transient Immunity
at Logic High Output7
Common-Mode Transient Immunity
at Logic Low Output7
|CMH|
|CML|
fr
25
25
35
kV/µs
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
35
kV/µs
transient magnitude = 800 V
Refresh Rate
5 V/3.3 V Operation
3.3 V/5 V Operation
Input Dynamic Supply Current per Channel8
5 V/3.3 V Operation
3.3 V/5 V Operation
Output Dynamic Supply Current per Channel8
1.2
1.1
Mbps
Mbps
IDDI (D)
0.196
0.076
mA/Mbps
mA/Mbps
IDDO (D)
5 V/3.3 V Operation
3.3 V/5 V Operation
0.028
0.01
mA/Mbps
mA/Mbps
Rev. D | Page 8 of 24
Data Sheet
ADuM3440/ADuM3441/ADuM3442
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3440/ADuM3441/ADuM3442 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDO. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. D | Page 9 of 24
ADuM3440/ADuM3441/ADuM3442
Data Sheet
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Symbol
RI-O
CI-O
CI
θJCI
Min
Typ
1012
2.2
4.0
33
Max
Unit
Ω
pF
pF
°C/W
Test Conditions
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
f = 1 MHz
IC Junction-to-Case Thermal Resistance, Side 1
Thermocouple located at
center of package underside
1 The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together.
IC Junction-to-Case Thermal Resistance, Side 2
θJCO
28
°C/W
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM344x is approved by the organizations listed in Table 5. Refer to Table 10 and the Insulation Lifetime section for details
regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL
CSA
VDE
Recognized under
Approved under
CSA Component Acceptance Notice #5A
Certified according to
1577 component recognition program1
DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Single protection,
2500 V rms isolation voltage
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 800 V rms (1131 V peak)
maximum working voltage
Reinforced insulation, 560 V peak
Reinforced insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (566 V peak)
maximum working voltage
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM344x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM344x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Symbol Value
Unit Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
7.7 min
V rms 1-minute duration
mm Measured from input terminals to output terminals,
shortest distance through air
mm Measured from input terminals to output terminals,
shortest distance path along body
L(I01)
L(I02)
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
8.1 min
0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI
Isolation Group
>175
IIIa
V
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. D | Page 10 of 24
Data Sheet
ADuM3440/ADuM3441/ADuM3442
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 7.
Description
Conditions
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
I to IV
I to III
I to II
40/105/21
2
VIORM
VPR
560
1050
V peak
V peak
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test
Subgroup 2 and Subgroup 3
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR
896
672
V peak
V peak
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Highest Allowable Overvoltage
Safety-Limiting Values
Transient overvoltage, tTR = 10 seconds
Maximum value allowed in the event of a failure
(see Figure 4)
VTR
4000
V peak
Case Temperature
Side 1 Current
Side 2 Current
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
Insulation Resistance at TS
VIO = 500 V
350
300
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter
Rating
250
SIDE #2
Operating Temperature Range, TA
Supply Voltage Range, VDD1, VDD2
Input Signal Rise and Fall Time
−40°C to +105°C
3.0 V to 5.5 V
1.0 ms
1
200
150
1 All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to external
magnetic fields.
SIDE #1
100
50
0
0
50
100
150
200
CASE TEMPERATURE (°C)
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. D | Page 11 of 24
ADuM3440/ADuM3441/ADuM3442
ABSOLUTE MAXIMUM RATINGS
Data Sheet
Ambient temperature = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 9.
Parameter
Rating
Storage Temperature Range (TST)
−65°C to +150°C
Ambient Operating Temperature Range (TA) −40°C to +105°C
1
Supply Voltages (VDD1, VDD2
)
−0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VID, VE1, VE2)1, 2
Output Voltage (VOA, VOB, VOC, VOD)1, 2
Average Output Current per Pin3
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients (CMH, CML)4
−0.5 V to VDD1 + 0.5 V
−0.5 V to VDDO + 0.5 V
ESD CAUTION
−18 mA to +18 mA
−22 mA to +22 mA
−100 kV/µs to
+100 kV/µs
1 All voltages are relative to their respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PC Board Layout section.
3 See Figure 4 for maximum rated current values for various temperatures.
4 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the Absolute Maximum Ratings can cause latch-
up or permanent damage.
Table 10. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
565
V peak
50-year minimum lifetime
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Basic Insulation
Reinforced Insulation
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 11. Truth Table (Positive Logic)
VIX Input1
VEX Input2 VDDI State1 VDDO State1 VOX Output1 Notes
H
L
X
X
X
X
H or NC
H or NC
L
H or NC
L
X
Powered
Powered
Powered
Unpowered Powered
Unpowered Powered
Powered
Powered
Powered
H
L
Z
H
Z
Outputs return to the input state within 1 µs of VDDI power restoration.
Powered
Unpowered Indeterminate Outputs return to the input state within 1 µs of VDDO power
restoration if VEX state is H or NC. Outputs return to high impedance
state within 8 ns of VDDO power restoration if VEX state is L.
1 VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEX to an external logic high or low is recommended.
Rev. D | Page 12 of 24
Data Sheet
ADuM3440/ADuM3441/ADuM3442
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
GND *
15 GND *
1
2
V
V
V
V
14
13
12
11
10
9
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
E2
ADuM3440
TOP VIEW
(Not to Scale)
NC
GND *
GND *
1
2
NC = NO CONNECT
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO
GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND
1
CONNECTING BOTH TO GND IS RECOMMENDED.
2
Figure 5. ADuM3440 Pin Configuration
Table 12. ADuM3440 Pin Function Descriptions
Pin No. Mnemonic Description
1
2, 8
3
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
VID
Logic Input D.
7
NC
No Connect.
9, 15
10
GND2
VE2
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.
VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external
logic high or low is recommended.
11
12
13
14
16
VOD
VOC
VOB
VOA
VDD2
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V.
Rev. D | Page 13 of 24
ADuM3440/ADuM3441/ADuM3442
Data Sheet
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
GND *
15 GND *
1
2
V
V
V
14
13
12
11
10
9
V
V
V
V
V
IA
IB
IC
OA
OB
OC
ID
ADuM3441
TOP VIEW
(Not to Scale)
V
OD
V
E1
E2
GND *
GND *
1
2
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO
GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND
1
CONNECTING BOTH TO GND IS RECOMMENDED.
2
Figure 6. ADuM3441 Pin Configuration
Table 13. ADuM3441 Pin Function Descriptions
Pin No. Mnemonic Description
1
2, 8
3
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
7
VOD
VE1
Logic Output D.
Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled
when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.
9, 15
10
GND2
VE2
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA,
VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
11
12
13
14
16
VID
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
VOC
VOB
VOA
VDD2
Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
Rev. D | Page 14 of 24
Data Sheet
ADuM3440/ADuM3441/ADuM3442
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
GND *
15 GND *
1
2
V
V
14
13
12
11
10
9
V
V
V
V
V
IA
OA
OB
IC
ADuM3442
IB
TOP VIEW
(Not to Scale)
V
V
OC
OD
ID
V
E1
E2
GND *
GND *
1
2
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO
GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND
1
CONNECTING BOTH TO GND IS RECOMMENDED.
2
Figure 7. ADuM3442 Pin Configuration
Table 14. ADuM3442 Pin Function Descriptions
Pin No. Mnemonic Function
1
2, 8
3
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
4
VIB
Logic Input B.
5
6
7
VOC
VOD
VE1
Logic Output C.
Logic Output D.
Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected. VOC and
VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is
recommended.
9, 15
10
GND2
VE2
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected. VOA and
V
OB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is
recommended.
11
12
13
14
16
VID
VIC
VOB
VOA
VDD2
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2, 3.0 V to 5.5 V.
Rev. D | Page 15 of 24
ADuM3440/ADuM3441/ADuM3442
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
35
30
25
140
120
100
80
20
5V
5V
15
10
60
40
3.3V
3.3V
5
20
0
0
0
50
100
150
0
50
100
150
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 8. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3.3 V Operation
Figure 11. Typical ADuM3440 VDD1 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
14
12
10
50
45
40
35
30
8
5V
5V
25
6
20
15
4
3.3V
3.3V
10
2
5
0
0
0
50
100
150
0
50
100
150
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 9. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3.3 V Operation (No Output Load)
Figure 12. Typical ADuM3440 VDD2 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
20
18
16
14
12
120
100
80
5V
10
60
5V
8
40
6
3.3V
3.3V
4
20
2
0
0
0
50
100
150
0
50
100
150
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 10. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3.3 V Operation (15 pF Output Load)
Figure 13. Typical ADuM3441 VDD1 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
Rev. D | Page 16 of 24
Data Sheet
ADuM3440/ADuM3441/ADuM3442
70
60
50
40
30
20
10
90
80
70
60
50
40
30
20
10
0
5V
5V
3.3V
3.3V
0
0
50
100
150
0
50
100
150
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 14. Typical ADuM3441 VDD2 Supply Current vs. Data Rate
for 5 V and 3.3 V Operation
Figure 15. Typical ADuM3442 VDD1 or VDD2 Supply Current vs.Data Rate
for 5 V and 3.3 V Operation
Rev. D | Page 17 of 24
ADuM3440/ADuM3441/ADuM3442
Data Sheet
APPLICATIONS INFORMATION
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
PC BOARD LAYOUT
The ADuM344x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 16). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16
for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. Bypassing
between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should
be considered unless the ground pair on each package side is
connected close to the package.
System-level ESD reliability (for example, per IEC 61000-4-x)
is highly dependent on system design, which varies widely by
application. The ADuM344x incorporate many enhancements
to make ESD reliability less dependent on system design. The
enhancements include the following:
ESD protection cells added to all input/output interfaces.
Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
The SCR effect inherent in CMOS devices is minimized by
the use of guarding and isolation techniques between
PMOS and NMOS devices.
V
V
DD1
DD2
GND
GND
1
IA
IB
2
V
V
V
V
V
V
V
OA
OB
Areas of high electric field concentration eliminated using
45° corners on metal traces.
V
V
IC/OC
ID/OD
OC/IC
OD/ID
E2
V
E1
GND
GND
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
1
2
Figure 16. Recommended Printed Circuit Board Layout
While the ADuM344x improve system-level ESD reliability,
they are no substitute for a robust system-level design. See the
AN-793 application note, ESD/Latch-Up Considerations with
iCoupler Isolation Products for detailed recommendations on
board layout and system-level design.
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this could
cause voltage differentials between pins exceeding the device’s
absolute maximum ratings, thereby leading to latch-up or
permanent damage.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1 μs, a periodic set
of refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses of more than about 5 μs, the input side is assumed
unpowered or nonfunctional, in which case the isolator output
is forced to a default state (see the Absolute Maximum Ratings
section) by the watchdog timer circuit.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation
delay to a logic high.
INPUT (V
)
50%
Ix
tPLH
tPHL
The limitation on the magnetic field immunity of the ADuM344x
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this can occur. The 3 V operating condition of the
ADuM344x is examined because it represents the most susceptible
mode of operation.
OUTPUT (V
)
50%
Ox
Figure 17. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM344x component.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
thus establishing a 0.5 V margin in which induced voltages can
be tolerated.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM344x
components operating under the same conditions.
Rev. D | Page 18 of 24
Data Sheet
ADuM3440/ADuM3441/ADuM3442
1000
100
The voltage induced across the receiving coil is given by
DISTANCE = 1m
2
V = (−dβ/dt)∑ πrn ; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
10
1
DISTANCE = 100mm
DISTANCE = 5mm
Given the geometry of the receiving coil in the ADuM344x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 18.
100
0.1
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
10
1
Figure 19. Maximum Allowable Current
for Various Current-to-ADuM344x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce error voltages sufficiently large enough to trigger
the thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
0.1
0.01
0.001
POWER CONSUMPTION
The supply current at a given channel of the ADuM344x
isolator is a function of the supply voltage, the channel’s data
rate, and the channel’s output load.
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 18. Maximum Allowable External Magnetic Flux Density
For each input channel, the supply current is given by
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
I
DDI = IDDI (Q)
f ≤ 0.5 fr
f > 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
For each output channel, the supply current is given by
DDO = IDDO (Q) f ≤ 0.5 fr
DDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
I
I
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM344x transformers. Figure 19 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM344x is extremely immune
and can be affected only by extremely large currents operated
at high frequency very close to the component. For the 1 MHz
example noted, one would have to place a 0.5 kA current 5 mm
away from the ADuM344x to affect the component’s operation.
where:
DDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
I
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
V
DD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 10 provides per-
channel supply current as a function of data rate for a 15 pF
output condition. Figure 11 through Figure 15 provide total
VDD1 and VDD2 supply current as a function of data rate for
ADuM3440/ADuM3441/ADuM3442 channel configurations.
Rev. D | Page 19 of 24
ADuM3440/ADuM3441/ADuM3442
Data Sheet
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower, which allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 10 can be applied while maintaining the
50-year minimum lifetime provided the voltage conforms to
either the unipolar ac or dc voltage cases. Any cross insulation
voltage waveform that does not conform to Figure 21 or Figure 22
should be treated as a bipolar ac waveform and its peak voltage
should be limited to the 50-year lifetime voltage value listed in
Table 10.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM344x.
Analog Devices performs accelerated life testing using voltage levels
higher than the rated continuous working voltage. Acceleration
factors for several operating conditions are determined. These
factors allow calculation of the time to failure at the actual working
voltage. The values shown in Figure 20 summarize the peak voltage
for 50 years of service life for a bipolar ac operating condition, and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than the 50-year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life in some cases.
Note that the voltage presented in Figure 21 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
RATED PEAK VOLTAGE
0V
Figure 20. Bipolar AC Waveform
The insulation lifetime of the ADuM344x depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 20, Figure 21, and Figure 22 illustrate these
different isolation voltage waveforms.
RATED PEAK VOLTAGE
0V
Figure 21. Unipolar AC Waveform
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the maximum working voltage recommended by
Analog Devices.
RATED PEAK VOLTAGE
0V
Figure 22. DC Waveform
Rev. D | Page 20 of 24
Data Sheet
ADuM3440/ADuM3441/ADuM3442
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
1.27 (0.0500)
BSC
2.65 (0.1043)
0.25 (0.0098)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 23. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Number of Number of Maximum Maximum
Maximum
Data Rate Propagation Pulse Width
Inputs,
VDD1 Side
Inputs,
VDD2 Side
Temperature
Package
Description
Package
Option
Model1, 2
(Mbps)
Delay, 5 V (ns) Distortion (ns) Range
ADuM3440CRWZ
ADuM3441CRWZ
ADuM3442CRWZ
4
3
2
0
1
2
150
150
150
32
32
32
2
2
2
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
1 Z = RoHS Compliant Part.
2 Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option.
Rev. D | Page 21 of 24
ADuM3440/ADuM3441/ADuM3442
NOTES
Data Sheet
Rev. D | Page 22 of 24
Data Sheet
NOTES
ADuM3440/ADuM3441/ADuM3442
Rev. D | Page 23 of 24
ADuM3440/ADuM3441/ADuM3442
NOTES
Data Sheet
©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06837-0-2/12(D)
Rev. D | Page 24 of 24
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