ADUCM362BCPZ256_技术文档

Low Power, Precision Analog Microcontroller

with Dual Sigma-Delta ADCs, ARM Cortex-M3

Data Sheet

ADuCM362/ADuCM363

Power supply range: 1.8 V to 3.6 V (maximum)

FEATURES

Power consumption, MCU active mode

Core consumes 290 μA/MHz

Pin compatible with the ADuCM360/ADuCM361

Analog input/output

Overall system current consumption of 1.0 mA with core

operating at 500 kHz (both ADCs on, input buffers off,

PGA gain of 4, one SPI port on, and all timers on)

Power consumption, power-down mode: 4 μA (wake-up

timer active)

Dual 24-bit ADCs (ADuCM362)

Single 24-bit ADC (ADuCM363)

Programmable ADC output rate (3.5 Hz to 3.906 kHz)

Simultaneous 50 Hz/60 Hz noise rejection

At 50 SPS continuous conversion mode

At 16.67 SPS single conversion mode

Flexible input mux for input channel selection to both ADCs

Two 24-bit multichannel ADCs (ADC0 and ADC1)

6 differential or 12 single-ended input channels

4 internal channels for monitoring DAC, temperature

sensor, IOVDD/4, and AVDD/4 (ADC1 only)

Programmable gain (1 to 128)

Gain of 1 with input buffer on/off supported

RMS noise: 52 nV at 3.53 Hz, 200 nV at 50 Hz

Programmable sensor excitation current sources

On-chip precision voltage reference

Two external reference options supported by both ADCs

Single 12-bit voltage output DAC

On-chip peripherals

2× UART, I²C, and 2 × SPI serial input/output (I/O)

16-bit pulse-width modulation (PWM) controller

19-pin multifunction GPIO port

2 general-purpose timers

Wake-up timer/watchdog timer

Multichannel DMA and interrupt controller

DMA support for both SPI channels

Package and temperature range

48-lead, 7 mm × 7 mm LFCSP

Specified for −40°C to +125°C operation

Development tools

Low cost QuickStart Development System

Third-party compiler and emulator tool support

Multiple diagnostic functions that support SIL certification

NPN mode for 4 mA to 20 mA loop applications

Microcontroller

ARM Cortex-M3 32-bit processor

Serial wire download and debug

APPLICATIONS

Industrial automation and process control

Intelligent precision sensing systems

4 mA to 20 mA loop-powered smart sensor systems

Medical devices, patient monitoring

Internal watch crystal for wake-up timer

16 MHz oscillator with 8-way programmable divider

Memory

Up to 256 kB Flash/EE memory, 24 kB SRAM

In-circuit debug/download via serial wire and UART

Rev. 0

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ADuCM362/ADuCM363

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

SPI Timing Specifications ......................................................... 16

Absolute Maximum Ratings ......................................................... 18

Thermal Resistance.................................................................... 18

ESD Caution................................................................................ 18

Pin Configuration and Function Descriptions........................... 19

Typical Performance Characteristics ........................................... 22

Typical System Configuration ...................................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

Applications....................................................................................... 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Functional Block Diagrams............................................................. 4

Specifications..................................................................................... 6

Microcontroller Electrical Specifications.................................. 6

RMS Noise Resolution of ADC0 and ADC1 .......................... 11

I²C Timing Specifications.......................................................... 15

REVISION HISTORY

10/2016—Revision 0: Initial Version

Rev. 0| Page 2 of 24

Data Sheet

ADuCM362/ADuCM363

GENERAL DESCRIPTION

The ADuCM362/ADuCM363 are fully integrated, 3.9 kSPS,

24-bit data acquisition systems that incorporate dual, high

performance, multichannel sigma-delta (Σ-Δ) analog-to-digital

converters (ADCs), a 32-bit ARM Cortex™-M3 processor, and

Flash/EE memory on a single chip. The ADuCM362/

ADuCM363 are designed for direct interfacing to external

precision sensors in both wired and battery-powered applications.

The ADuCM363 contains all the features of the ADuCM362,

except that only one 24-bit Σ-Δ ADC (ADC1) is available.

The devices contain a low noise, low drift internal band gap

reference, but they can be configured to accept one or two

external reference sources in ratiometric measurement config-

urations. An option to buffer the external reference inputs is

provided on chip. A single-channel buffered voltage output

DAC is also provided on chip.

The ADuCM362/ADuCM363 integrate a range of on-chip

peripherals, which can be configured under microcontroller

software control as required in the application. The peripherals

include two UARTs, I²C, and dual SPI serial I/O communication

controllers; a 19-pin GPIO port; two general-purpose timers;

a wake-up timer; and a system watchdog timer. A 16-bit PWM

controller with six output channels is also provided.

The ADuCM362/ADuCM363 contain an on-chip 32 kHz

oscillator and an internal 16 MHz high frequency oscillator. The

high frequency oscillator is routed through a programmable clock

divider from which the operating frequency of the processor core

clock is generated. The maximum core clock speed is 16 MHz;

this speed is not limited by operating voltage or temperature.

The ADuCM362/ADuCM363 are specifically designed to operate

in battery-powered applications where low power operation is

critical. The microcontroller core can be configured in a normal

operating mode that consumes 290 μA/MHz (including flash/

SRAM I_DD). An overall system current consumption of 1 mA can

be achieved with both ADCs on (input buffers off), PGA gain of

4, one SPI port on, and all timers on.

The microcontroller core is a low power ARM Cortex-M3

processor, a 32-bit RISC machine that offers up to 20 MIPS peak

performance. The Cortex-M3 processor incorporates a flexible,

11-channel DMA controller that supports all wired communica-

tion peripherals (both SPIs, both UARTs, and I²C). Also

integrated on chip are up to 256 kB of nonvolatile Flash/EE

memory and 24 kB of SRAM.

The ADuCM362/ADuCM363 can be configured in a number of

low power operating modes under direct program control,

including a hibernate mode (internal wake-up timer active) that

consumes only 4 ꢀA. In hibernate mode, peripherals, such as

external interrupts or the internal wake-up timer, can wake up

the devices. This mode allows the devices to operate with ultralow

power while still responding to asynchronous external or

periodic events.

The analog subsystem consists of dual ADCs, each connected to

a flexible input mux. Both ADCs can operate in fully differential

and single-ended modes. Other on-chip ADC features include

dual programmable excitation current sources, diagnostic current

sources, and a bias voltage generator of AVDD_REG/2 (900 mV)

to set the common-mode voltage of an input channel. A low-side

internal ground switch is provided to allow power-down of an

external circuit (for example, a bridge circuit) between conversions.

Optional input buffers are provided for the analog inputs and the

external reference inputs. These buffers can be enabled for all PGA

gain settings.

On-chip factory firmware supports in-circuit serial download

via a serial wire interface (2-pin JTAG system) and UART; non-

intrusive emulation is also supported via the serial wire interface.

These features are incorporated into a low cost QuickStart™

Development System that supports this precision analog micro-

controller family.

The ADCs contain two parallel filters: a sinc3 or sinc4 filter in

parallel with a sinc2 filter. The sinc3 or sinc4 filter is used for

precision measurements. The sinc2 filter is used for fast measure-

ments and for the detection of step changes in the input signal.

The devices operate from an external 1.8 V to 3.6 V voltage

supply and are specified over an industrial temperature range of

−40°C to +125°C.

Rev. 0 | Page 3 of 24

ADuCM362/ADuCM363

Data Sheet

FUNCTIONAL BLOCK DIAGRAMS

ON-CHIP

1.8V ANALOG

LDO

ON-CHIP

1.8V DIGITAL

LDO

12-BIT

DAC

POWER-ON

RESET

BUFFER

DAC

AVDD

AGND

RESET

V

BIAS

GENERATOR

ON-CHIP

OSCILLATOR

(1% TYP)

XTALO

XTALI

16MHz

V

24-BIT

Σ-∆ ADC

REF

ARM

CORTEX-M3

PROCESSOR

AIN0

AIN1

GPIO PORTS

UART PORTS

2 × SPI PORTS

SINC3/

SINC4

FILTER

Σ-∆

MODULATOR

AIN2

MOD2

GAIN

16MHz

AMP

BUF

AIN3

2

I C PORTS

AIN4/IEXC

AIN5/IEXC

TIMER0

TIMER1

19 GENERAL-

PURPOSE

I/O PORTS

AIN6/IEXC

SINC2

MEMORY

FILTER

256kB FLASH

WATCHDOG

AIN7/VBIAS0/IEXC/

EXTREF2IN+

MUX

24kB SRAM WAKE-UP TIMER

PWM

AIN8/EXTREF2IN–

AIN9/DACBUFF+

AIN10

V

24-BIT

Σ-∆ ADC

REF

SERIAL WIRE

DMA AND

DEBUG,

INTERRUPT

CONTROLLER

PROGRAMMING

SINC3/

SINC4

FILTER

Σ-∆

MODULATOR

AIN11/VBIAS1

MOD2

GAIN

AND DEBUG

AMP

BUF

SELECTABLE

REF

SOURCES

SWDIO

SWCLK

V

DAC, TEMP,

IOVDD/4,

AVDD/4

PRECISION

REFERENCE

ADuCM362

DVDD_REG

AVDD_REG

IREF

BUFFER

CURRENT

SOURCES

BUFFER

GND_SW

VREF– VREF+

INT_REF

IOVDD

Figure 1. ADuCM362 Functional Block Diagram

Rev. 0| Page 4 of 24

Data Sheet

ADuCM362/ADuCM363

ON-CHIP

1.8V ANALOG

LDO

ON-CHIP

1.8V DIGITAL

LDO

12-BIT

DAC

POWER-ON

RESET

BUFFER

DAC

RESET

AVDD

AGND

V

BIAS

GENERATOR

ON-CHIP

XTALO

OSCILLATOR

(1% TYP)

16MHz

XTALI

ARM

CORTEX-M3

PROCESSOR

AIN0

AIN1

GPIO PORTS

UART PORTS

2 × SPI PORTS

AIN2

16MHz

AIN3

2

I C PORTS

AIN4/IEXC

AIN5/IEXC

TIMER0

TIMER1

WATCHDOG

WAKE-UP TIMER

PWM

19 GENERAL-

PURPOSE

I/O PORTS

AIN6/IEXC

SINC2

MEMORY

256kB FLASH

24kB SRAM

FILTER

AIN7/VBIAS0/IEXC/

EXTREF2IN+

MUX

AIN8/EXTREF2IN–

AIN9/DACBUFF+

AIN10

V

24-BIT

Σ-∆ ADC

REF

SERIAL WIRE

DEBUG,

PROGRAMMING

AND DEBUG

DMA AND

INTERRUPT

CONTROLLER

SINC3/

SINC4

FILTER

Σ-∆

MODULATOR

AIN11/VBIAS1

MOD2

GAIN

AMP

BUF

SELECTABLE

SWDIO

V

DAC, TEMP,

IOVDD/4,

AVDD/4

REF

SOURCES

SWCLK

PRECISION

REFERENCE

ADuCM363

DVDD_REG

AVDD_REG

IREF

BUFFER

CURRENT

SOURCES

BUFFER

GND_SW

VREF– VREF+

INT_REF

IOVDD

Figure 2. ADuCM363 Functional Block Diagram

Rev. 0 | Page 5 of 24

ADuCM362/ADuCM363

Data Sheet

SPECIFICATIONS

MICROCONTROLLER ELECTRICAL SPECIFICATIONS

AVDD/IOVDD = 1.8 V to 3.6 V, internal 1.2 V reference, f_CORE= 16 MHz, all specifications at T_A= −40°C to +125°C, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

ADC0 and ADC1

Chop off

Min

Typ

Max

Unit

ADC SPECIFICATIONS

Conversion Rate¹

3.5

24

3906

1302

Hz

Bits

Chop on

No Missing Codes¹

Chop off, f_ADC≤ 500 Hz

Chop on, f_ADC≤ 250 Hz

See Table 2 through Table 9

Gain = 1, input buffer off

Gain = 2, 4, 8, or 16

Gain = 32, 64, or 128

Chop off; offset error is in the order of

the noise for the programmed gain and

update rate following calibration

Chop on¹

24

RMS Noise and Data Output Rates

Integral Nonlinearity¹

10

15

20

ppm of FSR

μV

Offset Error^{2, 3, 4, 6, 7}

230ꢀgain

1.0

1ꢀgain

230

μV

μVꢀ°C

nVꢀ°C

Offset Error Drift vs. Temperature^{1, 4, 6}

Chop off, gain ≤ 4

Chop off, gain ≥ 8

Chop on

10

Offset Error Lifetime Stability⁵

Full-Scale Error^{1, 4, 6, 7, 8}

Full-Scale Error Lifetime Stability⁵

Gain Error Drift vs. Temperature^{1, 4, 6}

Gain = 128

1

μVꢀ1000 Hr

mV

μVꢀ1000 Hr

0.5ꢀgain

70

Gain = 128

External reference

Gain = 1, 2, 4, 8, or 16

Gain = 32, 64, or 128

3

6

0.15

ppmꢀ°C

%

PGA Gain Mismatch Error

Power Supply Rejection¹

External reference

Chop on, ADC input = 0.25 V, gain = 4

Chop off, ADC input = 7.8 mV, gain = 128 80

Chop off, ADC input = 1 V, gain = 1

95

dB

90

Absolute Input Voltage Range

Unbuffered Mode

Buffered Mode

AGND

AGND + 0.1

AVDD

V

Available for all gain settings G = 1 to 128

AVDD − 0.1

Differential Input Voltage Ranges¹

For gain = 32, 64, and 128, see Table 3

and Table 7 for allowable input ranges

and noise values

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

V_REF

500

250

125

62.5

AVDD

V

mV

V

1

Common-Mode Voltage, V_CM

Ideally, V_CM= ((AIN+) + (AIN−))ꢀ2; gain = 2

to 128; input current varies with V_CM

(see Figure 9 and Figure 10)

AGND

Rev. 0| Page 6 of 24

Data Sheet

ADuCM362/ADuCM363

Parameter

Input Current⁹

Test Conditions/Comments

Min

Typ

Max

Unit

Buffered Mode

Gain > 1 (excluding AIN4, AIN5, AIN6,

and AIN7 pins)

1

nA

Gain > 1 (AIN4, AIN5, AIN6, and AIN7 pins)

Input current varies with input voltage

2

860

nA

nAꢀV

Unbuffered Mode

Average Input Current Drift¹

Buffered Mode

AIN1, AIN3, AIN5, AIN7, and AIN11

AIN0, AIN4, AIN9, and AIN10

AIN2, AIN6, and AIN8

5

9

15

250

pAꢀ°C

pAꢀVꢀ°C

Unbuffered Mode

Common-Mode Rejection, DC¹

On ADC input

ADC gain = 1, AVDD < 2 V

ADC gain = 1, AVDD > 2 V

ADC gain = 2 to 128

65

80

100

dB

Common-Mode Rejection,

50 Hzꢀ60 Hz¹

50 Hzꢀ60 Hz 1 Hz; f_ADC= 16.67 Hz,

chop on; f_ADC= 50 Hz, chop off

ADC gain = 1

ADC gain = 2 to 128

On ADC input

97

90

dB

Normal Mode Rejection, 50 Hzꢀ60 Hz¹

50 Hzꢀ60 Hz 1 Hz; f_ADC= 16.67 Hz,

chop on; f_ADC= 50 Hz, chop off

60

80

dB

TEMPERATURE SENSOR¹

Voltage Output at 25°C

After user calibration

Processor powered down or in standby

mode before measurement

82.1

mV

Voltage Temperature Coefficient (TC)

Accuracy

250

6

ꢁVꢀ°C

°C

GROUND SWITCH

On Resistance (R_ON

)

3.7

10

19

20

Ω

mA

Allowable Current¹

VOLTAGE REFERENCE

Internal V_REF

20 kΩ resistor off, direct short to ground

ADC internal reference

1.2

V

Initial Accuracy

Measured at T_A= 25°C

−0.1

−15

+0.1

+15

%

Reference Temperature Coefficient

5

ppmꢀ°C

(TC)^{1, 10}

Power Supply Rejection¹

EXTERNAL REFERENCE INPUTS

Input Range

82

90

dB

Buffered Mode

Unbuffered Mode

AGND + 0.1

0

AVDD − 0.1

AVDD

V

Minimum differential voltage between

VREF+ and VREF− pins is 400 mV

Input Current

Buffered Mode

Unbuffered Mode

Normal Mode Rejection¹

Common-Mode Rejection¹

Reference Detect Levels¹

−20

85

+10

500

80

100

400

+27

nA

nAꢀV

dB

mV

Rev. 0 | Page 7 of 24

ADuCM362/ADuCM363

Data Sheet

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

EXCITATION CURRENT SOURCES

Output Current

Available from each current source; value

programmable from 10 ꢁA to 1 mA

10

1000

μA

Initial Tolerance at 25°C¹

Drift¹

I_OUT≥ 50 ꢁA

Using internal reference resistor

Using external 150 kΩ reference resistor

between IREF pin and AGND; resistor

must have drift specification of 5 ppmꢀ°C

5

100

75

%

400

ppmꢀ°C

Initial Current Matching at 25°C¹

Drift Matching¹

Load Regulation, AVDD¹

Output Compliance¹

Matching between both current sources

0.5

50

0.2

%

ppmꢀ°C

%ꢀV

V

AVDD = 3.3 V

I_OUT= 10 ꢁA to 210 ꢁA

I_OUT> 210 ꢁA

AGND − 0.03

AVDD − 0.85

AVDD − 1.1

DAC CHANNEL SPECIFICATIONS

Voltage Range

R_L= 5 kΩ, C_L= 100 pF

Internal reference

External reference

0

V_REF

1.8

V

DC Specifications¹¹

Resolution

Relative Accuracy

Differential Nonlinearity

Offset Error

12

Bits

LSB

mV

%

3

0.5

2

Guaranteed monotonic

1.2 V internal reference

V_REFrange (reference = 1.2 V)

1

10

0.5

Gain Error

NPN Mode¹

Resolution

12

Bits

LSB

mA

Relative Accuracy

Differential Nonlinearity

Offset Error

3

0.5

0.35

0.75

Gain Error

Output Current Range

Interpolation Mode^{1, 12}

Resolution

Relative Accuracy

Differential Nonlinearity

Offset Error

0.008

23.6

Only monotonic to 14 bits

14

6

0.6

2

1

Bits

LSB

mV

%

For 14-bit resolution

Monotonic (14 bits)

1.2 V internal reference

V_REFrange (reference = 1.2 V)

AVDD range

Gain Error

1

%

DAC AC CHARACTERISTICS¹

Voltage Output Settling Time

Digital-to-Analog Glitch Energy

10

20

ꢁs

nV-sec

1 LSB change at major carry (maximum

number of bits changes simultaneously

in the DAC0DAT register)

POWER-ON RESET (POR)

POR Trip Level

Voltage at DVDD pin

Power-on level

1.65

50

V

ms

Power-down level

Timeout from POR¹

WATCHDOG TIMER (WDT)¹

Timeout Period

0.00003

8192

sec

ms

Timeout Step Size

FLASHꢀEE MEMORY¹

Endurance¹³

T3CON[3:2] = 10

T_J= 85°C

7.8125

10,000

10

Cycles

Years

Data Retention¹⁴

Rev. 0| Page 8 of 24

Data Sheet

ADuCM362/ADuCM363

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL INPUTS

Input Leakage Current

All digital inputs

Digital inputs except for the RESET,

SWCLK, and SWDIO pins

V_INH= IOVDD or V_INH= 1.8 V

Internal pull-up disabled

V_INL= 0 V

Logic 1

Logic 0

140

1

160

10

μA

nA

μA

nA

Internal pull-up disabled

RESET, SWCLK, and SWDIO pins

Input Leakage Current

Logic 1

140

160

10

μA

pF

Logic 0

Input Capacitance¹

Logic Input Voltage

Low, V_INL

0.2 × IOVDD

V

High, V_INH

Logic Output Voltage

High, V_OH

0.7 × IOVDD

IOVDD − 0.4

I_SOURCE= 1 mA

I_SINK= 1 mA

V

Low, V_OL

0.4

0.8

CRYSTAL OSCILLATOR¹

Logic Input Voltage, XTALI Only¹⁵

Low, V_INL

32.768 kHz crystal inputs

V

High, V_INH

1.7

V

XTALI Capacitance

XTALO Capacitance

ON-CHIP LOW POWER OSCILLATOR

Oscillator Frequency

Accuracy

6

pF

32.768

10

kHz

%

−30

+30

ON-CHIP HIGH FREQUENCY OSCILLATOR

Oscillator Frequency

Accuracy

16

MHz

%

−40°C to +125°C

−1.8

+1.4

Long Term Stability⁵

PROCESSOR CLOCK RATE¹

0.8

0.5

°Cꢀ1000 Hr

MHz

Nine programmable core clock

selections within specified range

0.0625

16

Using an External Clock

PROCESSOR START-UP TIME¹

At Power-On

0.032768

MHz

Includes kernel power-on execution

time

Includes kernel power-on execution

time

41

ms

f_CLK

μs

After Reset Event

1.44

3 to 5

30.8

From Processor Power-Down

(Mode 1, Mode 2, and Mode 3)

From Total Halt or Hibernate Mode

(Mode 4 or Mode 5)

f_CLKis the Cortex-M3 core clock

Rev. 0 | Page 9 of 24

ADuCM362/ADuCM363

Data Sheet

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER REQUIREMENTS

Power Supply Voltages, V_DD

Power Consumption

I_DD(MCU Active Mode)^{16, 17}

AVDD, IOVDD

1.8

3.6

V

Processor clock rate = 16 MHz;

all peripherals on (CLKSYSDIV = 0)

Processor clock rate = 8 MHz;

all peripherals on (CLKSYSDIV = 1)

Processor clock rate = 500 kHz; both

ADCs on (input buffers off) with PGA

gain = 4, 1 × SPI port on, all timers on

5.5

3

mA

1

I_DD(MCU Powered Down)

Full temperature range, total halt mode

(Mode 4)

4

μA

I_DD, Total (ADC0)¹⁷

PGA

PGA enabled, gain ≥ 32

320

130

180

70

200

120

μA

Gain = 4, 8, or 16, PGA only

Gain = 32, 64, or 128, PGA only

2 × input buffers = 70 μA

Input Buffers

Digital Interface and Modulator

I_DD(ADC1)

Input buffers off, gain = 4, 8, or 16 only

60 μA each

External Reference Input Buffers

¹These numbers are not production tested, but are guaranteed by design andꢀor characterization data at production release.

²Tested at gain = 4 after initial offset calibration.

³Measured with an internal short. A system zero-scale calibration removes this error.

⁴A recalibration at any temperature removes these errors.

⁵The long term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.

⁶These numbers do not include internal reference temperature drift.

⁷Factory calibrated at gain = 1.

⁸System calibration at a specific gain removes the error at this gain.

⁹Input current is measured with one ADC measuring a channel. If both ADCs measure the same input channel, the input current increases (approximately doubles).

¹⁰Measured using the box method.

¹¹Reference DAC linearity is calculated using a reduced code range of 0x0AB to 0xF30.

¹²Measured using a low-pass filter with R = 1 kΩ, C = 100 nF.

¹³Endurance is qualified to 10,000 cycles as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.

¹⁴Retention lifetime equivalent at junction temperature (T_J) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature.

¹⁵Voltage input levels are relevant only if driving XTAL input from a voltage source. If a crystal is connected directly, the internal crystal interface determines the

common-mode voltage.

¹⁶Typical additional supply current consumed during FlashꢀEE memory program and erase cycles is 7 mA.

¹⁷Total I_DDfor ADC includes figures for PGA ≥ 32, input buffers, digital interface, and the Σ-Δ modulator.

Rev. 0| Page 10 of 24

Data Sheet

ADuCM362/ADuCM363

RMS NOISE RESOLUTION OF ADC0 AND ADC1

Internal Reference (1.2 V)

Table 2 through Table 5 provide rms noise specifications for ADC0 and ADC1 using the internal reference (1.2 V). Table 2 and Table 3 list

the rms noise for both ADCs with various gain and output update rate values. Table 4 and Table 5 list the typical output rms noise effective

number of bits (ENOB) in normal mode for both ADCs with various gain and output update rate values. (Peak-to-peak ENOB is shown in

parentheses.)

Table 2. RMS Noise vs. Gain and Output Update Rate, Internal Reference (1.2 V), Gain = 1, 2, 4, 8, and 16

RMS Noise (μV)

Gain = 2,

500 mV,

ADCxMDE =

0x11

Gain = 4,

250 mV,

ADCxMDE =

0x21

Gain = 8,

125 mV,

ADCxMDE =

0x31

Gain = 16,

62.5 mV,

ADCxMDE =

0x41

ADCFLT

Register

Rate (Hz) Chop/Sinc Value

Gain = 1, V_REF

ADCxMDE =

0x01

,

Update

3.53

30

50

100

488

976

1953

3906

Onꢀsinc3

Offꢀsinc3

Offꢀsinc4

0x8E7C

0x007E

0x007D

0x004D

0x100F

0x1007

0x1003

0x1001

1.05

2.1

3.7

5.45

10

13.5

19.3

67.0

0.45

1.37

1.6

2.41

4.7

6.5

10

36

0.23

0.63

0.83

1.13

2.2

3.3

4.7

16.6

0.135

0.37

0.47

0.63

1.3

1.7

2.6

8.8

0.072

0.22

0.29

0.38

0.79

1.1

1.55

4.9

Table 3. RMS Noise vs. Gain and Output Update Rate, Internal Reference (1.2 V), Gain = 32, 64, and 128

RMS Noise (μV)

Gain = 32,¹

62.5 mV,

ADCxMDE =

0x49

Gain = 32,^{1, 2}

22.18 mV,

ADCxMDE =

0x51

Gain = 64,³

15.625 mV,

ADCxMDE =

0x59

Gain = 64,^{3, 4}

10.3125 mV,

ADCxMDE =

0x61

Gain = 128,⁵

7.8125 mV,

ADCxMDE =

0x69

Gain = 128,^{5, 6}

3.98 mV,

ADCxMDE =

0x71

ADCFLT

Register

Value

Update Chop/

Rate (Hz) Sinc

3.53

30

50

100

488

976

1953

3906

Onꢀsinc3

0x8E7C

0x007E

0x007D

0x004D

0x100F

0x1007

0x1003

0x1001

0.067

0.202

0.24

0.35

0.7

0.99

1.78

6.44

0.064

0.2

0.073

0.196

0.25

0.36

0.71

1.01

1.48

3.59

0.055

0.16

0.21

0.27

0.58

0.74

1.15

1.4

0.058

0.174

0.21

0.31

0.62

0.83

1.25

2.2

0.052

0.155

0.2

0.25

0.57

0.7

Offꢀsinc3

Offꢀsinc4

0.24

0.32

0.67

0.91

1.3

1.0

1.4

2.68

¹ADCxMDE = 0x49 sets the PGA for a gain of 16 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the

modulator. ADCxMDE = 0x51 sets the PGA for a gain of 32 with the modulator gain off. ADCxMDE = 0x49 has slightly higher noise but supports a wider input range.

²If AVDD < 2.0 V and ADCxMDE = 0x51, the input range is 17.5 mV.

³ADCxMDE = 0x59 sets the PGA for a gain of 32 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the

modulator. ADCxMDE = 0x61 sets the PGA for a gain of 64 with the modulator gain off. ADCxMDE = 0x59 has slightly higher noise but supports a wider input range.

⁴If AVDD < 2.0 V and ADCxMDE = 0x61, the input range is 8.715 mV.

⁵ADCxMDE = 0x69 sets the PGA for a gain of 64 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the

modulator. ADCxMDE = 0x71 sets the PGA for a gain of 128 with the modulator gain off. ADCxMDE = 0x69 has slightly higher noise but supports a wider input range.

⁶If AVDD < 2.0 V and ADCxMDE = 0x71, the input range is 3.828 mV.

Rev. 0 | Page 11 of 24

ADuCM362/ADuCM363

Data Sheet

Table 4. Typical Output RMS Noise ENOB in Normal Mode, Internal Reference (1.2 V), Gain = 1, 2, 4, 8, and 16

ENOB by Input Voltage Range and Gain¹

Gain = 2,

500 mV,

ADCxMDE = 0x11

Gain = 4,

250 mV,

ADCxMDE = 0x21

Gain = 8,

125 mV,

ADCxMDE = 0x31

Gain = 16,

62.5 mV,

ADCxMDE = 0x41

Update

Rate (Hz)

Gain = 1, V_REF

Chop/Sinc ADCxMDE = 0x01

,

3.53

30

50

100

488

976

1953

3906

Onꢀsinc3

Offꢀsinc3

Offꢀsinc4

21.1 (18.4 p-p)

20.1 (17.4 p-p)

19.3 (16.6 p-p)

18.7 (16.0 p-p)

17.9 (15.2 p-p)

17.4 (14.7 p-p)

16.9 (14.2 p-p)

15.1 (12.4 p-p)

21.1 (18.4 p-p)

19.5 (16.8 p-p)

19.25 (16.5 p-p)

18.66 (15.9 p-p)

17.7 (15.0 p-p)

17.2 (14.5 p-p)

16.6 (13.9 p-p)

14.8 (12.0 p-p)

21.1 (18.3 p-p)

19.6 (16.9 p-p)

19.2 (16.5 p-p)

18.75 (16.0 p-p)

17.8 (15.1 p-p)

17.2 (14.5 p-p)

16.7 (14.0 p-p)

14.9 (12.2 p-p)

20.8 (18.1 p-p)

19.4 (16.6 p-p)

19.0 (16.3 p-p)

18.6 (15.9 p-p)

17.55 (14.8 p-p)

17.2 (14.4 p-p)

16.55 (13.8 p-p)

14.8 (12.1 p-p)

20.7 (18.0 p-p)

19.1 (16.4 p-p)

18.7 (16.0 p-p)

18.3 (15.6 p-p)

17.3 (14.5 p-p)

16.8 (14.1 p-p)

16.3 (13.6 p-p)

14.6 (11.9 p-p)

¹RMS bits are calculated as follows: log₂((2 × Input Range)ꢀRMS Noise); peak-to-peak (p-p) bits are calculated as follows: log₂((2 × Input Range)ꢀ(6.6 × RMS Noise)).

Table 5. Typical Output RMS Noise ENOB in Normal Mode, Internal Reference (1.2 V), Gain = 32, 64, and 128

ENOB by Input Voltage Range and Gain¹

Gain = 32,

62.5 mV,

ADCxMDE =

Gain = 32,

22.18 mV,

ADCxMDE =

0x51

Gain = 64,

15.625 mV,

ADCxMDE =

0x59

Gain = 64,

10.3125 mV,

ADCxMDE =

0x61

Gain = 128,

7.8125 mV,

ADCxMDE =

0x69

Gain = 128,

3.98 mV,

ADCxMDE =

0x71

Update

Rate (Hz)

Chop/Sinc 0x49

3.53

30

50

100

488

976

1953

3906

Onꢀsinc3

Offꢀsinc3

Offꢀsinc4

19.8 (17.1 p-p)

18.2 (15.5 p-p)

18.0 (15.2 p-p)

17.4 (14.7 p-p)

16.4 (13.7 p-p)

15.9 (13.2 p-p)

15.1 (12.4 p-p)

13.2 (10.5 p-p)

19.4 (16.7 p-p)

17.75 (15.0 p-p) 17.3 (14.6 p-p)

17.5 (14.8 p-p)

17.1 (14.35 p-p) 16.4 (13.7 p-p)

16.0 (13.3 p-p)

15.6 (12.85 p-p) 14.91 (12.2 p-p) 14.8 (12.0 p-p)

15.05 (12.3 p-p) 14.4 (11.6 p-p)

14.0 (11.3 p-p) 13.1 (10.4 p-p)

18.7 (16.0 p-p)

18.5 (15.8 p-p)

17.0 (14.25 p-p) 16.45 (13.7 p-p) 15.6 (12.9 p-p)

18.0 (15.3 p-p)

17.2 (14.5 p-p)

16.93 (14.2 p-p) 16.6 (13.86 p-p) 16.2 (13.5 p-p) 15.3 (12.55 p-p)

16.2 (13.5 p-p)

15.1 (12.4 p-p)

15.6 (12.9 p-p)

14.6 (11.9 p-p)

14.2 (11.5 p-p)

13.6 (10.9 p-p)

12.8 (10.1 p-p)

15.0 (12.2 p-p)

13.8 (11.0 p-p)

13.4 (10.75 p-p)

13.0 (10.2 p-p)

12.5 (9.75 p-p)

15.4 (12.7 p-p)

14.1 (11.4 p-p)

13.8 (11.1 p-p)

¹RMS bits are calculated as follows: log₂((2 × Input Range)ꢀRMS Noise); peak-to-peak (p-p) bits are calculated as follows: log₂((2 × Input Range)ꢀ(6.6 × RMS Noise)).

Rev. 0| Page 12 of 24

Data Sheet

ADuCM362/ADuCM363

External Reference (2.5 V)

Table 6 through Table 9 provide rms noise specifications for ADC0 and ADC1 using the external reference (2.5 V). Table 6 and Table 7 list

the rms noise for both ADCs with various gain and output update rate values. Table 8 and Table 9 list the typical output rms noise effective

ENOB in normal mode for both ADCs with various gain and output update rate values. (Peak-to-peak ENOB is shown in parentheses.)

Table 6. RMS Noise vs. Gain and Output Update Rate, External Reference (2.5 V), Gain = 1, 2, 4, 8, and 16

RMS Noise (μV)

Gain = 2,

500 mV,

ADCxMDE =

0x11

Gain = 4,

250 mV,

ADCxMDE =

0x21

Gain = 8,

125 mV,

ADCxMDE =

0x31

Gain = 16,

62.5 mV,

ADCxMDE =

0x41

ADCFLT

Register

Rate (Hz) Chop/Sinc Value

Gain = 1, V_REF

ADCxMDE =

0x01

,

Update

3.53

30

50

100

488

976

1953

3906

Onꢀsinc3

Offꢀsinc3

Offꢀsinc4

0x8E7C

0x007E

0x007D

0x004D

0x100F

0x1007

0x1003

0x1001

1.1

3

3.9

5.2

0.5

1.4

2.2

2.8

5.0

7

0.27

0.85

0.92

1.25

2.5

3.5

5.7

35.0

0.17

0.44

0.46

0.63

1.2

1.75

2.6

17.2

0.088

0.27

0.3

0.38

0.75

1.2

9.3

12.5

20.0

140.0

10

70.0

1.71

8.9

Table 7. RMS Noise vs. Gain and Output Update Rate, External Reference (2.5 V), Gain = 32, 64, and 128

RMS Noise (μV)

Gain = 32,¹

62.5 mV,

ADCxMDE =

0x49

Gain = 32,^{1, 2}

22.18 mV,

ADCxMDE =

0x51

Gain = 64,³

15.625 mV,

ADCxMDE =

0x59

Gain = 64,^{3, 4}

10.3125 mV,

ADCxMDE =

0x61

Gain = 128,⁵

7.8125 mV,

ADCxMDE =

0x69

Gain = 128,^{5, 6}

3.98 mV,

ADCxMDE =

0x71

ADCFLT

Register

Value

Update Chop/

Rate (Hz) Sinc

3.53

30

50

100

488

976

1953

3906

Onꢀsinc3

0x8E7C

0x007E

0x007D

0x004D

0x100F

0x1007

0x1003

0x1001

0.076

0.21

0.265

0.37

0.73

1.1

0.07

0.22

0.21

0.32

0.7

0.83

1.3

4.8

0.088

0.21

0.27

0.366

0.73

1.01

1.6

0.06

0.19

0.2

0.28

0.57

0.77

1.24

2.65

0.068

0.175

0.225

0.32

0.64

0.89

1.3

0.58

0.17

0.19

0.26

0.5

0.75

1.1

1.88

Offꢀsinc3

Offꢀsinc4

2.05

9.4

5.1

3.2