ADUCM363BCPZ128 [ADI]
ADUCM363BCPZ128;型号: | ADUCM363BCPZ128 |
厂家: | ADI |
描述: | ADUCM363BCPZ128 时钟 外围集成电路 |
文件: | 总24页 (文件大小:429K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Low Power, Precision Analog Microcontroller
with Dual Sigma-Delta ADCs, ARM Cortex-M3
Data Sheet
ADuCM362/ADuCM363
Power supply range: 1.8 V to 3.6 V (maximum)
FEATURES
Power consumption, MCU active mode
Core consumes 290 μA/MHz
Pin compatible with the ADuCM360/ADuCM361
Analog input/output
Overall system current consumption of 1.0 mA with core
operating at 500 kHz (both ADCs on, input buffers off,
PGA gain of 4, one SPI port on, and all timers on)
Power consumption, power-down mode: 4 μA (wake-up
timer active)
Dual 24-bit ADCs (ADuCM362)
Single 24-bit ADC (ADuCM363)
Programmable ADC output rate (3.5 Hz to 3.906 kHz)
Simultaneous 50 Hz/60 Hz noise rejection
At 50 SPS continuous conversion mode
At 16.67 SPS single conversion mode
Flexible input mux for input channel selection to both ADCs
Two 24-bit multichannel ADCs (ADC0 and ADC1)
6 differential or 12 single-ended input channels
4 internal channels for monitoring DAC, temperature
sensor, IOVDD/4, and AVDD/4 (ADC1 only)
Programmable gain (1 to 128)
Gain of 1 with input buffer on/off supported
RMS noise: 52 nV at 3.53 Hz, 200 nV at 50 Hz
Programmable sensor excitation current sources
On-chip precision voltage reference
Two external reference options supported by both ADCs
Single 12-bit voltage output DAC
On-chip peripherals
2× UART, I2C, and 2 × SPI serial input/output (I/O)
16-bit pulse-width modulation (PWM) controller
19-pin multifunction GPIO port
2 general-purpose timers
Wake-up timer/watchdog timer
Multichannel DMA and interrupt controller
DMA support for both SPI channels
Package and temperature range
48-lead, 7 mm × 7 mm LFCSP
Specified for −40°C to +125°C operation
Development tools
Low cost QuickStart Development System
Third-party compiler and emulator tool support
Multiple diagnostic functions that support SIL certification
NPN mode for 4 mA to 20 mA loop applications
Microcontroller
ARM Cortex-M3 32-bit processor
Serial wire download and debug
APPLICATIONS
Industrial automation and process control
Intelligent precision sensing systems
4 mA to 20 mA loop-powered smart sensor systems
Medical devices, patient monitoring
Internal watch crystal for wake-up timer
16 MHz oscillator with 8-way programmable divider
Memory
Up to 256 kB Flash/EE memory, 24 kB SRAM
In-circuit debug/download via serial wire and UART
Rev. 0
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ADuCM362/ADuCM363
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SPI Timing Specifications ......................................................... 16
Absolute Maximum Ratings ......................................................... 18
Thermal Resistance.................................................................... 18
ESD Caution................................................................................ 18
Pin Configuration and Function Descriptions........................... 19
Typical Performance Characteristics ........................................... 22
Typical System Configuration ...................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Functional Block Diagrams............................................................. 4
Specifications..................................................................................... 6
Microcontroller Electrical Specifications.................................. 6
RMS Noise Resolution of ADC0 and ADC1 .......................... 11
I2C Timing Specifications.......................................................... 15
REVISION HISTORY
10/2016—Revision 0: Initial Version
Rev. 0| Page 2 of 24
Data Sheet
ADuCM362/ADuCM363
GENERAL DESCRIPTION
The ADuCM362/ADuCM363 are fully integrated, 3.9 kSPS,
24-bit data acquisition systems that incorporate dual, high
performance, multichannel sigma-delta (Σ-Δ) analog-to-digital
converters (ADCs), a 32-bit ARM Cortex™-M3 processor, and
Flash/EE memory on a single chip. The ADuCM362/
ADuCM363 are designed for direct interfacing to external
precision sensors in both wired and battery-powered applications.
The ADuCM363 contains all the features of the ADuCM362,
except that only one 24-bit Σ-Δ ADC (ADC1) is available.
The devices contain a low noise, low drift internal band gap
reference, but they can be configured to accept one or two
external reference sources in ratiometric measurement config-
urations. An option to buffer the external reference inputs is
provided on chip. A single-channel buffered voltage output
DAC is also provided on chip.
The ADuCM362/ADuCM363 integrate a range of on-chip
peripherals, which can be configured under microcontroller
software control as required in the application. The peripherals
include two UARTs, I2C, and dual SPI serial I/O communication
controllers; a 19-pin GPIO port; two general-purpose timers;
a wake-up timer; and a system watchdog timer. A 16-bit PWM
controller with six output channels is also provided.
The ADuCM362/ADuCM363 contain an on-chip 32 kHz
oscillator and an internal 16 MHz high frequency oscillator. The
high frequency oscillator is routed through a programmable clock
divider from which the operating frequency of the processor core
clock is generated. The maximum core clock speed is 16 MHz;
this speed is not limited by operating voltage or temperature.
The ADuCM362/ADuCM363 are specifically designed to operate
in battery-powered applications where low power operation is
critical. The microcontroller core can be configured in a normal
operating mode that consumes 290 μA/MHz (including flash/
SRAM IDD). An overall system current consumption of 1 mA can
be achieved with both ADCs on (input buffers off), PGA gain of
4, one SPI port on, and all timers on.
The microcontroller core is a low power ARM Cortex-M3
processor, a 32-bit RISC machine that offers up to 20 MIPS peak
performance. The Cortex-M3 processor incorporates a flexible,
11-channel DMA controller that supports all wired communica-
tion peripherals (both SPIs, both UARTs, and I2C). Also
integrated on chip are up to 256 kB of nonvolatile Flash/EE
memory and 24 kB of SRAM.
The ADuCM362/ADuCM363 can be configured in a number of
low power operating modes under direct program control,
including a hibernate mode (internal wake-up timer active) that
consumes only 4 ꢀA. In hibernate mode, peripherals, such as
external interrupts or the internal wake-up timer, can wake up
the devices. This mode allows the devices to operate with ultralow
power while still responding to asynchronous external or
periodic events.
The analog subsystem consists of dual ADCs, each connected to
a flexible input mux. Both ADCs can operate in fully differential
and single-ended modes. Other on-chip ADC features include
dual programmable excitation current sources, diagnostic current
sources, and a bias voltage generator of AVDD_REG/2 (900 mV)
to set the common-mode voltage of an input channel. A low-side
internal ground switch is provided to allow power-down of an
external circuit (for example, a bridge circuit) between conversions.
Optional input buffers are provided for the analog inputs and the
external reference inputs. These buffers can be enabled for all PGA
gain settings.
On-chip factory firmware supports in-circuit serial download
via a serial wire interface (2-pin JTAG system) and UART; non-
intrusive emulation is also supported via the serial wire interface.
These features are incorporated into a low cost QuickStart™
Development System that supports this precision analog micro-
controller family.
The ADCs contain two parallel filters: a sinc3 or sinc4 filter in
parallel with a sinc2 filter. The sinc3 or sinc4 filter is used for
precision measurements. The sinc2 filter is used for fast measure-
ments and for the detection of step changes in the input signal.
The devices operate from an external 1.8 V to 3.6 V voltage
supply and are specified over an industrial temperature range of
−40°C to +125°C.
Rev. 0 | Page 3 of 24
ADuCM362/ADuCM363
Data Sheet
FUNCTIONAL BLOCK DIAGRAMS
ON-CHIP
1.8V ANALOG
LDO
ON-CHIP
1.8V DIGITAL
LDO
12-BIT
DAC
POWER-ON
RESET
BUFFER
DAC
AVDD
AGND
RESET
V
BIAS
GENERATOR
ON-CHIP
OSCILLATOR
(1% TYP)
XTALO
XTALI
16MHz
V
24-BIT
Σ-∆ ADC
REF
ARM
CORTEX-M3
PROCESSOR
AIN0
AIN1
GPIO PORTS
UART PORTS
2 × SPI PORTS
SINC3/
SINC4
FILTER
Σ-∆
MODULATOR
AIN2
MOD2
GAIN
16MHz
AMP
BUF
AIN3
2
I C PORTS
AIN4/IEXC
AIN5/IEXC
TIMER0
TIMER1
19 GENERAL-
PURPOSE
I/O PORTS
AIN6/IEXC
SINC2
MEMORY
FILTER
256kB FLASH
WATCHDOG
AIN7/VBIAS0/IEXC/
EXTREF2IN+
MUX
24kB SRAM WAKE-UP TIMER
PWM
AIN8/EXTREF2IN–
AIN9/DACBUFF+
AIN10
V
24-BIT
Σ-∆ ADC
REF
SERIAL WIRE
DMA AND
DEBUG,
INTERRUPT
CONTROLLER
PROGRAMMING
SINC3/
SINC4
FILTER
Σ-∆
MODULATOR
AIN11/VBIAS1
MOD2
GAIN
AND DEBUG
AMP
BUF
SELECTABLE
REF
SOURCES
SWDIO
SWCLK
V
DAC, TEMP,
IOVDD/4,
AVDD/4
PRECISION
REFERENCE
ADuCM362
DVDD_REG
AVDD_REG
IREF
BUFFER
CURRENT
SOURCES
BUFFER
GND_SW
VREF– VREF+
INT_REF
IOVDD
IOVDD
Figure 1. ADuCM362 Functional Block Diagram
Rev. 0| Page 4 of 24
Data Sheet
ADuCM362/ADuCM363
ON-CHIP
1.8V ANALOG
LDO
ON-CHIP
1.8V DIGITAL
LDO
12-BIT
DAC
POWER-ON
RESET
BUFFER
DAC
RESET
AVDD
AGND
V
BIAS
GENERATOR
ON-CHIP
XTALO
OSCILLATOR
(1% TYP)
16MHz
XTALI
ARM
CORTEX-M3
PROCESSOR
AIN0
AIN1
GPIO PORTS
UART PORTS
2 × SPI PORTS
AIN2
16MHz
AIN3
2
I C PORTS
AIN4/IEXC
AIN5/IEXC
TIMER0
TIMER1
WATCHDOG
WAKE-UP TIMER
PWM
19 GENERAL-
PURPOSE
I/O PORTS
AIN6/IEXC
SINC2
MEMORY
256kB FLASH
24kB SRAM
FILTER
AIN7/VBIAS0/IEXC/
EXTREF2IN+
MUX
AIN8/EXTREF2IN–
AIN9/DACBUFF+
AIN10
V
24-BIT
Σ-∆ ADC
REF
SERIAL WIRE
DEBUG,
PROGRAMMING
AND DEBUG
DMA AND
INTERRUPT
CONTROLLER
SINC3/
SINC4
FILTER
Σ-∆
MODULATOR
AIN11/VBIAS1
MOD2
GAIN
AMP
BUF
SELECTABLE
SWDIO
V
DAC, TEMP,
IOVDD/4,
AVDD/4
REF
SOURCES
SWCLK
PRECISION
REFERENCE
ADuCM363
DVDD_REG
AVDD_REG
IREF
BUFFER
CURRENT
SOURCES
BUFFER
GND_SW
VREF– VREF+
INT_REF
IOVDD
IOVDD
Figure 2. ADuCM363 Functional Block Diagram
Rev. 0 | Page 5 of 24
ADuCM362/ADuCM363
Data Sheet
SPECIFICATIONS
MICROCONTROLLER ELECTRICAL SPECIFICATIONS
AVDD/IOVDD = 1.8 V to 3.6 V, internal 1.2 V reference, fCORE = 16 MHz, all specifications at TA = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
ADC0 and ADC1
Chop off
Min
Typ
Max
Unit
ADC SPECIFICATIONS
Conversion Rate1
3.5
3.5
24
3906
1302
Hz
Hz
Bits
Bits
Chop on
No Missing Codes1
Chop off, fADC ≤ 500 Hz
Chop on, fADC ≤ 250 Hz
See Table 2 through Table 9
Gain = 1, input buffer off
Gain = 2, 4, 8, or 16
Gain = 32, 64, or 128
Chop off; offset error is in the order of
the noise for the programmed gain and
update rate following calibration
Chop on1
24
RMS Noise and Data Output Rates
Integral Nonlinearity1
10
15
20
ppm of FSR
ppm of FSR
ppm of FSR
μV
Offset Error2, 3, 4, 6, 7
230ꢀgain
1.0
1ꢀgain
230
μV
μVꢀ°C
nVꢀ°C
nVꢀ°C
Offset Error Drift vs. Temperature1, 4, 6
Chop off, gain ≤ 4
Chop off, gain ≥ 8
Chop on
10
Offset Error Lifetime Stability5
Full-Scale Error1, 4, 6, 7, 8
Full-Scale Error Lifetime Stability5
Gain Error Drift vs. Temperature1, 4, 6
Gain = 128
1
μVꢀ1000 Hr
mV
μVꢀ1000 Hr
0.5ꢀgain
70
Gain = 128
External reference
Gain = 1, 2, 4, 8, or 16
Gain = 32, 64, or 128
3
6
0.15
ppmꢀ°C
ppmꢀ°C
%
PGA Gain Mismatch Error
Power Supply Rejection1
External reference
Chop on, ADC input = 0.25 V, gain = 4
Chop off, ADC input = 7.8 mV, gain = 128 80
Chop off, ADC input = 1 V, gain = 1
95
dB
dB
dB
90
Absolute Input Voltage Range
Unbuffered Mode
Buffered Mode
AGND
AGND + 0.1
AVDD
V
V
Available for all gain settings G = 1 to 128
AVDD − 0.1
Differential Input Voltage Ranges1
For gain = 32, 64, and 128, see Table 3
and Table 7 for allowable input ranges
and noise values
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
VREF
500
250
125
62.5
AVDD
V
mV
mV
mV
mV
V
1
Common-Mode Voltage, VCM
Ideally, VCM = ((AIN+) + (AIN−))ꢀ2; gain = 2
to 128; input current varies with VCM
(see Figure 9 and Figure 10)
AGND
Rev. 0| Page 6 of 24
Data Sheet
ADuCM362/ADuCM363
Parameter
Input Current9
Test Conditions/Comments
Min
Typ
Max
Unit
Buffered Mode
Gain > 1 (excluding AIN4, AIN5, AIN6,
and AIN7 pins)
1
nA
Gain > 1 (AIN4, AIN5, AIN6, and AIN7 pins)
Input current varies with input voltage
2
860
nA
nAꢀV
Unbuffered Mode
Average Input Current Drift1
Buffered Mode
AIN1, AIN3, AIN5, AIN7, and AIN11
AIN0, AIN4, AIN9, and AIN10
AIN2, AIN6, and AIN8
5
9
15
250
pAꢀ°C
pAꢀ°C
pAꢀ°C
pAꢀVꢀ°C
Unbuffered Mode
Common-Mode Rejection, DC1
On ADC input
ADC gain = 1, AVDD < 2 V
ADC gain = 1, AVDD > 2 V
ADC gain = 2 to 128
65
80
80
100
100
dB
dB
dB
Common-Mode Rejection,
50 Hzꢀ60 Hz1
50 Hzꢀ60 Hz 1 Hz; fADC = 16.67 Hz,
chop on; fADC = 50 Hz, chop off
ADC gain = 1
ADC gain = 2 to 128
On ADC input
97
90
dB
dB
Normal Mode Rejection, 50 Hzꢀ60 Hz1
50 Hzꢀ60 Hz 1 Hz; fADC = 16.67 Hz,
chop on; fADC = 50 Hz, chop off
60
80
dB
TEMPERATURE SENSOR1
Voltage Output at 25°C
After user calibration
Processor powered down or in standby
mode before measurement
82.1
mV
Voltage Temperature Coefficient (TC)
Accuracy
250
6
ꢁVꢀ°C
°C
GROUND SWITCH
On Resistance (RON
)
3.7
10
19
20
Ω
mA
Allowable Current1
VOLTAGE REFERENCE
Internal VREF
20 kΩ resistor off, direct short to ground
ADC internal reference
1.2
V
Initial Accuracy
Measured at TA = 25°C
−0.1
−15
+0.1
+15
%
Reference Temperature Coefficient
5
ppmꢀ°C
(TC)1, 10
Power Supply Rejection1
EXTERNAL REFERENCE INPUTS
Input Range
82
90
dB
Buffered Mode
Unbuffered Mode
AGND + 0.1
0
AVDD − 0.1
AVDD
V
V
Minimum differential voltage between
VREF+ and VREF− pins is 400 mV
Input Current
Buffered Mode
Unbuffered Mode
Normal Mode Rejection1
Common-Mode Rejection1
Reference Detect Levels1
−20
85
+10
500
80
100
400
+27
nA
nAꢀV
dB
dB
mV
Rev. 0 | Page 7 of 24
ADuCM362/ADuCM363
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
EXCITATION CURRENT SOURCES
Output Current
Available from each current source; value
programmable from 10 ꢁA to 1 mA
10
1000
μA
Initial Tolerance at 25°C1
Drift1
IOUT ≥ 50 ꢁA
Using internal reference resistor
Using external 150 kΩ reference resistor
between IREF pin and AGND; resistor
must have drift specification of 5 ppmꢀ°C
5
100
75
%
400
400
ppmꢀ°C
ppmꢀ°C
Initial Current Matching at 25°C1
Drift Matching1
Load Regulation, AVDD1
Output Compliance1
Matching between both current sources
0.5
50
0.2
%
ppmꢀ°C
%ꢀV
V
V
AVDD = 3.3 V
IOUT = 10 ꢁA to 210 ꢁA
IOUT > 210 ꢁA
AGND − 0.03
AGND − 0.03
AVDD − 0.85
AVDD − 1.1
DAC CHANNEL SPECIFICATIONS
Voltage Range
RL = 5 kΩ, CL = 100 pF
Internal reference
External reference
0
0
VREF
1.8
V
V
DC Specifications11
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
12
Bits
LSB
LSB
mV
%
3
0.5
2
Guaranteed monotonic
1.2 V internal reference
VREF range (reference = 1.2 V)
1
10
0.5
Gain Error
NPN Mode1
Resolution
12
Bits
LSB
LSB
mA
mA
mA
Relative Accuracy
Differential Nonlinearity
Offset Error
3
0.5
0.35
0.75
Gain Error
Output Current Range
Interpolation Mode1, 12
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
0.008
23.6
Only monotonic to 14 bits
14
6
0.6
2
1
Bits
LSB
LSB
mV
%
For 14-bit resolution
Monotonic (14 bits)
1.2 V internal reference
VREF range (reference = 1.2 V)
AVDD range
Gain Error
1
%
DAC AC CHARACTERISTICS1
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
10
20
ꢁs
nV-sec
1 LSB change at major carry (maximum
number of bits changes simultaneously
in the DAC0DAT register)
POWER-ON RESET (POR)
POR Trip Level
Voltage at DVDD pin
Power-on level
1.65
1.65
50
V
V
ms
Power-down level
Timeout from POR1
WATCHDOG TIMER (WDT)1
Timeout Period
0.00003
8192
sec
ms
Timeout Step Size
FLASHꢀEE MEMORY1
Endurance13
T3CON[3:2] = 10
TJ = 85°C
7.8125
10,000
10
Cycles
Years
Data Retention14
Rev. 0| Page 8 of 24
Data Sheet
ADuCM362/ADuCM363
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL INPUTS
Input Leakage Current
All digital inputs
Digital inputs except for the RESET,
SWCLK, and SWDIO pins
VINH = IOVDD or VINH = 1.8 V
Internal pull-up disabled
VINL = 0 V
Logic 1
Logic 0
140
1
160
10
μA
nA
μA
nA
Internal pull-up disabled
RESET, SWCLK, and SWDIO pins
Input Leakage Current
Logic 1
140
160
10
μA
μA
pF
Logic 0
Input Capacitance1
Logic Input Voltage
Low, VINL
0.2 × IOVDD
V
V
High, VINH
Logic Output Voltage
High, VOH
0.7 × IOVDD
IOVDD − 0.4
ISOURCE = 1 mA
ISINK = 1 mA
V
V
Low, VOL
0.4
0.8
CRYSTAL OSCILLATOR1
Logic Input Voltage, XTALI Only15
Low, VINL
32.768 kHz crystal inputs
V
High, VINH
1.7
V
XTALI Capacitance
XTALO Capacitance
ON-CHIP LOW POWER OSCILLATOR
Oscillator Frequency
Accuracy
6
6
pF
pF
32.768
10
kHz
%
−30
+30
ON-CHIP HIGH FREQUENCY OSCILLATOR
Oscillator Frequency
Accuracy
16
MHz
%
−40°C to +125°C
−1.8
+1.4
Long Term Stability5
PROCESSOR CLOCK RATE1
0.8
0.5
°Cꢀ1000 Hr
MHz
Nine programmable core clock
selections within specified range
0.0625
16
16
Using an External Clock
PROCESSOR START-UP TIME1
At Power-On
0.032768
MHz
Includes kernel power-on execution
time
Includes kernel power-on execution
time
41
ms
ms
fCLK
μs
After Reset Event
1.44
3 to 5
30.8
From Processor Power-Down
(Mode 1, Mode 2, and Mode 3)
From Total Halt or Hibernate Mode
(Mode 4 or Mode 5)
fCLK is the Cortex-M3 core clock
Rev. 0 | Page 9 of 24
ADuCM362/ADuCM363
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER REQUIREMENTS
Power Supply Voltages, VDD
Power Consumption
IDD (MCU Active Mode)16, 17
AVDD, IOVDD
1.8
3.6
V
Processor clock rate = 16 MHz;
all peripherals on (CLKSYSDIV = 0)
Processor clock rate = 8 MHz;
all peripherals on (CLKSYSDIV = 1)
Processor clock rate = 500 kHz; both
ADCs on (input buffers off) with PGA
gain = 4, 1 × SPI port on, all timers on
5.5
3
mA
mA
mA
1
IDD (MCU Powered Down)
Full temperature range, total halt mode
(Mode 4)
4
μA
IDD, Total (ADC0)17
PGA
PGA enabled, gain ≥ 32
320
130
180
70
70
200
120
μA
μA
μA
μA
μA
μA
μA
Gain = 4, 8, or 16, PGA only
Gain = 32, 64, or 128, PGA only
2 × input buffers = 70 μA
Input Buffers
Digital Interface and Modulator
IDD (ADC1)
Input buffers off, gain = 4, 8, or 16 only
60 μA each
External Reference Input Buffers
1 These numbers are not production tested, but are guaranteed by design andꢀor characterization data at production release.
2 Tested at gain = 4 after initial offset calibration.
3 Measured with an internal short. A system zero-scale calibration removes this error.
4 A recalibration at any temperature removes these errors.
5 The long term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
6 These numbers do not include internal reference temperature drift.
7 Factory calibrated at gain = 1.
8 System calibration at a specific gain removes the error at this gain.
9 Input current is measured with one ADC measuring a channel. If both ADCs measure the same input channel, the input current increases (approximately doubles).
10 Measured using the box method.
11 Reference DAC linearity is calculated using a reduced code range of 0x0AB to 0xF30.
12 Measured using a low-pass filter with R = 1 kΩ, C = 100 nF.
13 Endurance is qualified to 10,000 cycles as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
14 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature.
15 Voltage input levels are relevant only if driving XTAL input from a voltage source. If a crystal is connected directly, the internal crystal interface determines the
common-mode voltage.
16 Typical additional supply current consumed during FlashꢀEE memory program and erase cycles is 7 mA.
17 Total IDD for ADC includes figures for PGA ≥ 32, input buffers, digital interface, and the Σ-Δ modulator.
Rev. 0| Page 10 of 24
Data Sheet
ADuCM362/ADuCM363
RMS NOISE RESOLUTION OF ADC0 AND ADC1
Internal Reference (1.2 V)
Table 2 through Table 5 provide rms noise specifications for ADC0 and ADC1 using the internal reference (1.2 V). Table 2 and Table 3 list
the rms noise for both ADCs with various gain and output update rate values. Table 4 and Table 5 list the typical output rms noise effective
number of bits (ENOB) in normal mode for both ADCs with various gain and output update rate values. (Peak-to-peak ENOB is shown in
parentheses.)
Table 2. RMS Noise vs. Gain and Output Update Rate, Internal Reference (1.2 V), Gain = 1, 2, 4, 8, and 16
RMS Noise (μV)
Gain = 2,
500 mV,
ADCxMDE =
0x11
Gain = 4,
250 mV,
ADCxMDE =
0x21
Gain = 8,
125 mV,
ADCxMDE =
0x31
Gain = 16,
62.5 mV,
ADCxMDE =
0x41
ADCFLT
Register
Rate (Hz) Chop/Sinc Value
Gain = 1, VREF
ADCxMDE =
0x01
,
Update
3.53
30
50
100
488
976
1953
3906
Onꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
0x8E7C
0x007E
0x007D
0x004D
0x100F
0x1007
0x1003
0x1001
1.05
2.1
3.7
5.45
10
13.5
19.3
67.0
0.45
1.37
1.6
2.41
4.7
6.5
10
36
0.23
0.63
0.83
1.13
2.2
3.3
4.7
16.6
0.135
0.37
0.47
0.63
1.3
1.7
2.6
8.8
0.072
0.22
0.29
0.38
0.79
1.1
1.55
4.9
Table 3. RMS Noise vs. Gain and Output Update Rate, Internal Reference (1.2 V), Gain = 32, 64, and 128
RMS Noise (μV)
Gain = 32,1
62.5 mV,
ADCxMDE =
0x49
Gain = 32,1, 2
22.18 mV,
ADCxMDE =
0x51
Gain = 64,3
15.625 mV,
ADCxMDE =
0x59
Gain = 64,3, 4
10.3125 mV,
ADCxMDE =
0x61
Gain = 128,5
7.8125 mV,
ADCxMDE =
0x69
Gain = 128,5, 6
3.98 mV,
ADCxMDE =
0x71
ADCFLT
Register
Value
Update Chop/
Rate (Hz) Sinc
3.53
30
50
100
488
976
1953
3906
Onꢀsinc3
0x8E7C
0x007E
0x007D
0x004D
0x100F
0x1007
0x1003
0x1001
0.067
0.202
0.24
0.35
0.7
0.99
1.78
6.44
0.064
0.2
0.073
0.196
0.25
0.36
0.71
1.01
1.48
3.59
0.055
0.16
0.21
0.27
0.58
0.74
1.15
1.4
0.058
0.174
0.21
0.31
0.62
0.83
1.25
2.2
0.052
0.155
0.2
0.25
0.57
0.7
Offꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
0.24
0.32
0.67
0.91
1.3
1.0
1.4
2.68
1 ADCxMDE = 0x49 sets the PGA for a gain of 16 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x51 sets the PGA for a gain of 32 with the modulator gain off. ADCxMDE = 0x49 has slightly higher noise but supports a wider input range.
2 If AVDD < 2.0 V and ADCxMDE = 0x51, the input range is 17.5 mV.
3 ADCxMDE = 0x59 sets the PGA for a gain of 32 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x61 sets the PGA for a gain of 64 with the modulator gain off. ADCxMDE = 0x59 has slightly higher noise but supports a wider input range.
4 If AVDD < 2.0 V and ADCxMDE = 0x61, the input range is 8.715 mV.
5 ADCxMDE = 0x69 sets the PGA for a gain of 64 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x71 sets the PGA for a gain of 128 with the modulator gain off. ADCxMDE = 0x69 has slightly higher noise but supports a wider input range.
6 If AVDD < 2.0 V and ADCxMDE = 0x71, the input range is 3.828 mV.
Rev. 0 | Page 11 of 24
ADuCM362/ADuCM363
Data Sheet
Table 4. Typical Output RMS Noise ENOB in Normal Mode, Internal Reference (1.2 V), Gain = 1, 2, 4, 8, and 16
ENOB by Input Voltage Range and Gain1
Gain = 2,
500 mV,
ADCxMDE = 0x11
Gain = 4,
250 mV,
ADCxMDE = 0x21
Gain = 8,
125 mV,
ADCxMDE = 0x31
Gain = 16,
62.5 mV,
ADCxMDE = 0x41
Update
Rate (Hz)
Gain = 1, VREF
Chop/Sinc ADCxMDE = 0x01
,
3.53
30
50
100
488
976
1953
3906
Onꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
21.1 (18.4 p-p)
20.1 (17.4 p-p)
19.3 (16.6 p-p)
18.7 (16.0 p-p)
17.9 (15.2 p-p)
17.4 (14.7 p-p)
16.9 (14.2 p-p)
15.1 (12.4 p-p)
21.1 (18.4 p-p)
19.5 (16.8 p-p)
19.25 (16.5 p-p)
18.66 (15.9 p-p)
17.7 (15.0 p-p)
17.2 (14.5 p-p)
16.6 (13.9 p-p)
14.8 (12.0 p-p)
21.1 (18.3 p-p)
19.6 (16.9 p-p)
19.2 (16.5 p-p)
18.75 (16.0 p-p)
17.8 (15.1 p-p)
17.2 (14.5 p-p)
16.7 (14.0 p-p)
14.9 (12.2 p-p)
20.8 (18.1 p-p)
19.4 (16.6 p-p)
19.0 (16.3 p-p)
18.6 (15.9 p-p)
17.55 (14.8 p-p)
17.2 (14.4 p-p)
16.55 (13.8 p-p)
14.8 (12.1 p-p)
20.7 (18.0 p-p)
19.1 (16.4 p-p)
18.7 (16.0 p-p)
18.3 (15.6 p-p)
17.3 (14.5 p-p)
16.8 (14.1 p-p)
16.3 (13.6 p-p)
14.6 (11.9 p-p)
1 RMS bits are calculated as follows: log2 ((2 × Input Range)ꢀRMS Noise); peak-to-peak (p-p) bits are calculated as follows: log2 ((2 × Input Range)ꢀ(6.6 × RMS Noise)).
Table 5. Typical Output RMS Noise ENOB in Normal Mode, Internal Reference (1.2 V), Gain = 32, 64, and 128
ENOB by Input Voltage Range and Gain1
Gain = 32,
62.5 mV,
ADCxMDE =
Gain = 32,
22.18 mV,
ADCxMDE =
0x51
Gain = 64,
15.625 mV,
ADCxMDE =
0x59
Gain = 64,
10.3125 mV,
ADCxMDE =
0x61
Gain = 128,
7.8125 mV,
ADCxMDE =
0x69
Gain = 128,
3.98 mV,
ADCxMDE =
0x71
Update
Rate (Hz)
Chop/Sinc 0x49
3.53
30
50
100
488
976
1953
3906
Onꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
19.8 (17.1 p-p)
18.2 (15.5 p-p)
18.0 (15.2 p-p)
17.4 (14.7 p-p)
16.4 (13.7 p-p)
15.9 (13.2 p-p)
15.1 (12.4 p-p)
13.2 (10.5 p-p)
19.4 (16.7 p-p)
17.75 (15.0 p-p) 17.3 (14.6 p-p)
17.5 (14.8 p-p)
17.1 (14.35 p-p) 16.4 (13.7 p-p)
16.0 (13.3 p-p)
15.6 (12.85 p-p) 14.91 (12.2 p-p) 14.8 (12.0 p-p)
15.05 (12.3 p-p) 14.4 (11.6 p-p)
14.0 (11.3 p-p) 13.1 (10.4 p-p)
18.7 (16.0 p-p)
18.5 (15.8 p-p)
17.0 (14.25 p-p) 16.45 (13.7 p-p) 15.6 (12.9 p-p)
18.0 (15.3 p-p)
17.2 (14.5 p-p)
16.93 (14.2 p-p) 16.6 (13.86 p-p) 16.2 (13.5 p-p) 15.3 (12.55 p-p)
16.2 (13.5 p-p)
15.1 (12.4 p-p)
15.6 (12.9 p-p)
14.6 (11.9 p-p)
14.2 (11.5 p-p)
13.6 (10.9 p-p)
12.8 (10.1 p-p)
15.0 (12.2 p-p)
13.8 (11.0 p-p)
13.4 (10.75 p-p)
13.0 (10.2 p-p)
12.5 (9.75 p-p)
15.4 (12.7 p-p)
14.1 (11.4 p-p)
13.8 (11.1 p-p)
1 RMS bits are calculated as follows: log2 ((2 × Input Range)ꢀRMS Noise); peak-to-peak (p-p) bits are calculated as follows: log2 ((2 × Input Range)ꢀ(6.6 × RMS Noise)).
Rev. 0| Page 12 of 24
Data Sheet
ADuCM362/ADuCM363
External Reference (2.5 V)
Table 6 through Table 9 provide rms noise specifications for ADC0 and ADC1 using the external reference (2.5 V). Table 6 and Table 7 list
the rms noise for both ADCs with various gain and output update rate values. Table 8 and Table 9 list the typical output rms noise effective
ENOB in normal mode for both ADCs with various gain and output update rate values. (Peak-to-peak ENOB is shown in parentheses.)
Table 6. RMS Noise vs. Gain and Output Update Rate, External Reference (2.5 V), Gain = 1, 2, 4, 8, and 16
RMS Noise (μV)
Gain = 2,
500 mV,
ADCxMDE =
0x11
Gain = 4,
250 mV,
ADCxMDE =
0x21
Gain = 8,
125 mV,
ADCxMDE =
0x31
Gain = 16,
62.5 mV,
ADCxMDE =
0x41
ADCFLT
Register
Rate (Hz) Chop/Sinc Value
Gain = 1, VREF
ADCxMDE =
0x01
,
Update
3.53
30
50
100
488
976
1953
3906
Onꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
0x8E7C
0x007E
0x007D
0x004D
0x100F
0x1007
0x1003
0x1001
1.1
3
3.9
5.2
0.5
1.4
2.2
2.8
5.0
7
0.27
0.85
0.92
1.25
2.5
3.5
5.7
35.0
0.17
0.44
0.46
0.63
1.2
1.75
2.6
17.2
0.088
0.27
0.3
0.38
0.75
1.2
9.3
12.5
20.0
140.0
10
70.0
1.71
8.9
Table 7. RMS Noise vs. Gain and Output Update Rate, External Reference (2.5 V), Gain = 32, 64, and 128
RMS Noise (μV)
Gain = 32,1
62.5 mV,
ADCxMDE =
0x49
Gain = 32,1, 2
22.18 mV,
ADCxMDE =
0x51
Gain = 64,3
15.625 mV,
ADCxMDE =
0x59
Gain = 64,3, 4
10.3125 mV,
ADCxMDE =
0x61
Gain = 128,5
7.8125 mV,
ADCxMDE =
0x69
Gain = 128,5, 6
3.98 mV,
ADCxMDE =
0x71
ADCFLT
Register
Value
Update Chop/
Rate (Hz) Sinc
3.53
30
50
100
488
976
1953
3906
Onꢀsinc3
0x8E7C
0x007E
0x007D
0x004D
0x100F
0x1007
0x1003
0x1001
0.076
0.21
0.265
0.37
0.73
1.1
0.07
0.22
0.21
0.32
0.7
0.83
1.3
4.8
0.088
0.21
0.27
0.366
0.73
1.01
1.6
0.06
0.19
0.2
0.28
0.57
0.77
1.24
2.65
0.068
0.175
0.225
0.32
0.64
0.89
1.3
0.58
0.17
0.19
0.26
0.5
0.75
1.1
1.88
Offꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
2.05
9.4
5.1
3.2
1 ADCxMDE = 0x49 sets the PGA for a gain of 16 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x51 sets the PGA for a gain of 32 with the modulator gain off. ADCxMDE = 0x49 has slightly higher noise but supports a wider input range.
2 If AVDD < 2.0 V and ADCxMDE = 0x51, the input range is 17.5 mV.
3 ADCxMDE = 0x59 sets the PGA for a gain of 32 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x61 sets the PGA for a gain of 64 with the modulator gain off. ADCxMDE = 0x59 has slightly higher noise but supports a wider input range.
4 If AVDD < 2.0 V and ADCxMDE = 0x61, the input range is 8.715 mV.
5 ADCxMDE = 0x69 sets the PGA for a gain of 64 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x71 sets the PGA for a gain of 128 with the modulator gain off. ADCxMDE = 0x69 has slightly higher noise but supports a wider input range.
6 If AVDD < 2.0 V and ADCxMDE = 0x71, the input range is 3.828 mV.
Rev. 0 | Page 13 of 24
ADuCM362/ADuCM363
Data Sheet
Table 8. Typical Output RMS Noise ENOB in Normal Mode, External Reference (2.5 V), Gain = 1, 2, 4, 8, and 16
ENOB by Input Voltage Range and Gain1
Gain = 16,
62.5 mV,
ADCxMDE = 0x41
Update
Rate (Hz)
Gain = 1, VREF
Chop/Sinc ADCxMDE = 0x01
,
Gain = 2, 500 mV,
ADCxMDE = 0x11
Gain = 4, 250 mV,
ADCxMDE = 0x21
Gain = 8, 125 mV,
ADCxMDE = 0x31
3.53
30
50
100
488
976
1953
3906
Onꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
22.1 (19.4 p-p)
20.7 (18.0 p-p)
20.3 (17.6 p-p)
19.9 (17.2 p-p)
19.0 (16.3 p-p)
18.6 (15.9 p-p)
17.9 (15.2 p-p)
15.1 (12.4 p-p)
20.9 (18.2 p-p)
19.4 (16.7 p-p)
18.8 (16.1 p-p)
18.4 (15.7 p-p)
17.6 (14.9 p-p)
17.1 (14.4 p-p)
16.6 (13.9 p-p)
13.8 (11.1 p-p)
20.8 (18.1 p-p)
19.2 (16.4 p-p)
19.05 (16.3 p-p)
18.6 (15.9 p-p)
17.6 (14.9 p-p)
17.1 (14.4 p-p)
16.4 (13.7 p-p)
13.8 (11.1 p-p)
20.5 (17.7 p-p)
19.1 (16.4 p-p)
19.05 (16.3 p-p)
18.6 (15.9 p-p)
17.7 (14.9 p-p)
17.1 (14.4 p-p)
16.55 (13.8 p-p)
13.8 (11.1 p-p)
20.43 (17.7 p-p)
18.82 (16.1 p-p)
18.66 (15.9 p-p)
18.32 (15.6 p-p)
17.34 (14.6 p-p)
16.66 (13.9 p-p)
16.15 (13.4 p-p)
13.77 (11.05 p-p)
1 RMS bits are calculated as follows: log2 ((2 × Input Range)ꢀRMS Noise); peak-to-peak (p-p) bits are calculated as follows: log2 ((2 × Input Range)ꢀ(6.6 × RMS Noise)).
Table 9. Typical Output RMS Noise ENOB in Normal Mode, External Reference (2.5 V), Gain = 32, 64, and 128
ENOB by Input Voltage Range and Gain1
Gain = 32,
62.5 mV,
ADCxMDE =
Gain = 32,
22.18 mV,
ADCxMDE =
0x51
Gain = 64,
15.625 mV,
ADCxMDE =
0x59
Gain = 64,
10.3125 mV,
ADCxMDE =
0x61
Gain = 128,
7.8125 mV,
ADCxMDE =
0x69
Gain = 128,
3.98 mV,
ADCxMDE =
0x71
Update
Rate (Hz)
Chop/Sinc 0x49
3.53
30
50
100
488
976
1953
3906
Onꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc3
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
Offꢀsinc4
19.6 (16.9 p-p)
18.2 (15.5 p-p)
17.8 (15.1 p-p)
17.4 (14.6 p-p)
16.4 (13.7 p-p)
15.8 (13.1 p-p)
14.9 (12.1 p-p)
12.7 (10.0 p-p)
19.3 (16.55 p-p) 18.4 (15.7 p-p)
18.4 (15.7 p-p)
16.7 (14.0 p-p)
16.65 (13.9 p-p) 16.1 (13.4 p-p)
16.2 (13.4 p-p)
15.1 (12.4 p-p)
14.7 (12.0 p-p)
17.8 (15.1 p-p)
16.4 (13.7 p-p)
17.1 (14.3 p-p)
15.5 (12.8 p-p)
15.35 (12.6 p-p)
17.6 (14.9 p-p)
17.7 (15.0 p-p)
17.2 (14.5 p-p)
16.8 (14.1 p-p)
17.1 (14.35 p-p) 16.4 (13.7 p-p)
15.6 (12.85 p-p) 14.9 (12.2 p-p)
14.6 (11.85 p-p) 14.0 (11.2 p-p)
14.1 (11.4 p-p)
13.55 (10.8 p-p) 12.8 (10.1 p-p)
12.25 (9.5 p-p) 12.0 (9.3 p-p)
16.0 (13.2 p-p)
15.7 (13.0 p-p)
15.1 (12.3 p-p)
13.2 (10.4 p-p)
15.4 (12.7 p-p)
14.9 (12.2 p-p)
14.25 (11.5 p-p) 14.0 (11.3 p-p)
12.6 (9.9 p-p) 12.9 (10.2 p-p)
13.4 (10.6 p-p)
1 RMS bits are calculated as follows: log2 ((2 × Input Range)ꢀRMS Noise); peak-to-peak (p-p) bits are calculated as follows: log2 ((2 × Input Range)ꢀ(6.6 × RMS Noise)).
Rev. 0| Page 14 of 24
Data Sheet
ADuCM362/ADuCM363
I2C TIMING SPECIFICATIONS
The capacitive load for each I2C bus line (CB) is 400 pF maximum as per the I2C bus specifications. I2C timing is guaranteed by design, but
is not production tested.
Table 10. I2C Timing in Fast Mode (400 kHz)
Parameter
Description
Min
1300
600
600
100
0
600
600
1.3
Max
Unit
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
tL
tH
Serial clock (SCL) low pulse width
SCL high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCL and serial data (SDA)
Fall time for both SCL and SDA
Pulse width of suppressed spike
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
20 + 0.1 CB
20 + 0.1 CB
0
300
300
50
tF
tSUP
Table 11. I2C Timing in Standard Mode (100 kHz)
Parameter
Description
Min
4.7
4.0
4.7
250
0
4.0
4.0
4.7
Max
Unit
μs
ns
μs
ns
μs
μs
μs
μs
μs
ns
tL
tH
SCL low pulse width
SCL high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCL and SDA
Fall time for both SCL and SDA
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
1
300
tF
tBUF
tSUP
tR
SDA (I/O)
MSB
LSB
ACK
MSB
tF
tDSU
tDSU
tDHD
tDHD
tPSU
tR
tSHD
tRSU
tH
1
8
9
1
SCL (I)
tL
tSUP
P
S
S(R)
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 3. I2C-Compatible Interface Timing
Rev. 0 | Page 15 of 24
ADuCM362/ADuCM363
Data Sheet
SPI TIMING SPECIFICATIONS
Table 12. SPI Master Mode Timing
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLK low pulse width1
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
0
SCLK high pulse width1
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
Data output valid after SCLK edge
Data output setup time before SCLK edge1
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
35.5
(SPIDIV + 1) × tUCLK
58.7
16
12
12
12
12
35.5
35.5
35.5
35.5
1 tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.
CS
1/2 SCLK
CYCLE
3/4 SCLK
CYCLE
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
tDR
MOSI
MISO
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 1)
CS
1 SCLK CYCLE
tCS
1 SCLK CYCLE
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOSU
tDF
tDR
MOSI
MISO
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 5. SPI Master Mode Timing (Phase Mode = 0)
Rev. 0| Page 16 of 24
Data Sheet
ADuCM362/ADuCM363
Table 13. SPI Slave Mode Timing
Parameter
Description
Min
Typ
Max
Unit
tCS
CS to SCLK edge
62.5
ns
tSL
tSH
SCLK low pulse width1
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK high pulse width1
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
62.5
tDAV
tDSU
tDHD
tDF
tDR
tSR
49.1
20.2
10.1
12
12
12
12
35.5
35.5
35.5
35.5
Data output rise time
SCLK rise time
SCLK fall time
CS high after SCLK edge
tSF
tSFS
0
1 tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
tDR
MISO
MOSI
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 6. SPI Slave Mode Timing (Phase Mode = 1)
CS
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOCS
tDF
tDR
MISO
MSB
BIT 6 TO BIT 1
LSB
MOSI
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 7. SPI Slave Mode Timing (Phase Mode = 0)
Rev. 0 | Page 17 of 24
ADuCM362/ADuCM363
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 14.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
Parameter
Rating
AVDD to AGND
IOVDD to DGND
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−40°C to +125°C
−65°C to +150°C
150°C
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Analog Inputs to AGND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD Rating, All Pins
Table 15. Thermal Resistance
Package Type
θJA
Unit
CP-48-4
27
°CꢀW
ESD CAUTION
Human Body Model (HBM)
2 kV
Field-Induced Charged Device
Model (FICDM)
850 V
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec)
240°C
Pb-Free Assemblies (20 sec to 40 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
product reliability.
Rev. 0| Page 18 of 24
Data Sheet
ADuCM362/ADuCM363
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
36 P0.7/POR/TxD1
35
P0.6/IRQ2/RxD1
RESET
P2.1/SDA/UART1DCD/UARTDCD
3
4
5
6
7
8
9
10
P2.2/BM
XTALO
XTALI
34 P0.5/IRQ1/CTS
33 P0.4/RTS/ECLKO/RTS1
32
P0.3/IRQ0/CS1/RTS1/RTS
31 P0.2/MOSI1/SDA/TxD
ADuCM362/
ADuCM363
TOP VIEW
(Not to Scale)
IOVDD
DVDD_REG
AIN0
30
29
P0.1/SCLK1/SCL/RxD
P0.0/MISO1/UART1DCD/UARTDCD
AIN1
AIN2
28 AIN11/VBIAS1
27 AIN10
11
AIN3
26 AIN9/DACBUFF+
25 AIN8/EXTREF2IN–
AIN4/IEXC 12
NOTES
1. EXPOSED PAD. THE LFCSP HAS AN EXPOSED PAD THAT MUST BE SOLDERED TO A METAL
PLATE ON THE PCB AND TO DGND FOR MECHANICAL REASONS.
Figure 8. Pin Configuration
Table 16. Pin Function Descriptions
Pin No. Mnemonic
Description
1
2
RESET
Reset Pin, Active Low Input. An internal pull-up is provided.
P2.1ꢀSDAꢀUART1DCDꢀUARTDCD General-Purpose InputꢀOutput P2.1ꢀI2C Serial Data PinꢀUART1 Data Carrier Detect PinꢀUART
Data Carrier Detect Pin.
3
P2.2ꢀBM
General-Purpose InputꢀOutput P2.2ꢀBoot Mode Input Select Pin. When this pin is held low
during and for a short time after any reset sequence, the devices enter UART download mode.
4
5
6
7
XTALO
XTALI
IOVDD
DVDD_REG
External Crystal Oscillator Output Pin. Optional 32.768 kHz source for real-time clock.
External Crystal Oscillator Input Pin. Optional 32.768 kHz source for real-time clock.
Digital System Supply Pin. This pin must be connected to DGND via a 0.1 ꢁF capacitor.
Digital Regulator Supply. This pin must be connected to DGND via a 470 nF capacitor and to
Pin 18, AVDD_REG.
8
AIN0
ADC Analog Input 0. This pin can be configured as a positive or negative input to either ADC
in differential or single-ended mode.
9
AIN1
ADC Analog Input 1. This pin can be configured as a positive or negative input to either ADC
in differential or single-ended mode.
10
11
12
AIN2
ADC Analog Input 2. This pin can be configured as a positive or negative input to either ADC
in differential or single-ended mode.
ADC Analog Input 3. This pin can be configured as a positive or negative input to either ADC
in differential or single-ended mode.
ADC Analog Input 4ꢀExcitation Current Source. This pin can be configured as a positive or
negative input to either ADC in differential or single-ended mode (AIN4). This pin can also be
configured as the output pin for Excitation Current Source 0 or Excitation Current Source 1 (IEXC).
AIN3
AIN4ꢀIEXC
Rev. 0 | Page 19 of 24
ADuCM362/ADuCM363
Data Sheet
Pin No. Mnemonic
Description
13
14
GND_SW
VREF+
Sensor Power Switch to Analog Ground Reference.
External Reference Positive Input. An external reference can be applied between the VREF+
and VREF− pins.
15
VREF−
External Reference Negative Input. An external reference can be applied between the VREF+
and VREF− pins.
16
17
18
AGND
AVDD
AVDD_REG
Analog System Ground Reference Pin.
Analog System Supply Pin. This pin must be connected to AGND via a 0.1 ꢁF capacitor.
Internal Analog Regulator Supply Output. This pin must be connected to AGND via a 470 nF
capacitor and to Pin 7, DVDD_REG.
19
20
21
DAC
INT_REF
IREF
DAC Voltage Output.
Internal Reference. This pin must be connected to ground via a 470 nF decoupling capacitor.
Optional Reference Current Resistor Connection for the Excitation Current Sources. The
reference current used for the excitation current sources is set by a low drift (5 ppmꢀ°C)
external resistor connected to this pin.
22
23
24
AIN5ꢀIEXC
ADC Analog Input 5ꢀExcitation Current Source. This pin can be configured as a positive or
negative input to either ADC in differential or single-ended mode (AIN5). This pin can also be
configured as the output pin for Excitation Current Source 0 or Excitation Current Source 1 (IEXC).
ADC Analog Input 6ꢀExcitation Current Source. This pin can be configured as a positive or
negative input to either ADC in differential or single-ended mode (AIN6). This pin can also be
configured as the output pin for Excitation Current Source 0 or Excitation Current Source 1 (IEXC).
ADC Analog Input 7ꢀBias Voltage OutputꢀExcitation Current SourceꢀExternal Reference 2
Positive Input. This pin can be configured as a positive or negative input to either ADC in
differential or single-ended mode (AIN7). This pin can also be configured as an analog output
pin to generate a bias voltage, VBIAS0 of AVDD_REGꢀ2 (VBIAS0); as the output pin for Excitation
Current Source 0 or Excitation Current Source 1 (IEXC); or as the positive input for External
Reference 2 (EXTREF2IN+).
AIN6ꢀIEXC
AIN7ꢀVBIAS0ꢀIEXCꢀEXTREF2IN+
25
26
AIN8ꢀEXTREF2IN−
AIN9ꢀDACBUFF+
ADC Analog Input 8ꢀExternal Reference 2 Negative Input. This pin can be configured as a
positive or negative input to either ADC in differential or single-ended mode (AIN8). This pin
can also be configured as the negative input for External Reference 2 (EXTREF2IN−).
ADC Analog Input 9ꢀNoninverting Input to the DAC Output Buffer. This pin can be configured
as a positive or negative input to either ADC in differential or single-ended mode (AIN9). This
pin can also be configured as the noninverting input to the DAC output buffer when the DAC
is configured for NPN mode (DACBUFF+).
27
28
AIN10
ADC Analog Input 10. This pin can be configured as a positive or negative input to either ADC
in differential or single-ended mode.
ADC Analog Input 11ꢀBias Voltage Output. This pin can be configured as a positive or
negative input to either ADC in differential or single-ended mode (AIN11). This pin can also be
configured as an analog output pin to generate a bias voltage, VBIAS1 of AVDD_REGꢀ2 (VBIAS1).
AIN11ꢀVBIAS1
29
30
31
32
P0.0ꢀMISO1ꢀUART1DCDꢀ
UARTDCD
General-Purpose InputꢀOutput P0.0ꢀSPI1 Master Input, Slave Output PinꢀUART1 Data Carrier
Detect Pinꢀ UART Data Carrier Detect Pin.
General-Purpose InputꢀOutput P0.1ꢀSPI1 Serial Clock PinꢀI2C Serial Clock PinꢀUART Serial
Input (Data Input for the UART Downloader).
General-Purpose InputꢀOutput P0.2ꢀSPI1 Master Output, Slave Input PinꢀI2C Serial Data Pinꢀ
UART Serial Output (Data Output for the UART Downloader).
General-Purpose InputꢀOutput P0.3ꢀExternal Interrupt Request 0ꢀSPI1 Chip Select Pin (Active
Low) (when using SPI1, configure this pin as CS1)ꢀUART1 Request to Send SignalꢀUART
Request to Send Signal.
P0.1ꢀSCLK1ꢀSCLꢀRxD
P0.2ꢀMOSI1ꢀSDAꢀTxD
P0.3ꢀIRQ0ꢀCS1ꢀRTS1ꢀRTS
33
P0.4ꢀRTSꢀECLKOꢀRTS1
General-Purpose InputꢀOutput P0.4ꢀUART Request to Send SignalꢀExternal Clock Output Pin
for Test PurposesꢀUART1 Request to Send Signal.
34
35
36
37
38
P0.5ꢀIRQ1ꢀCTS
General-Purpose InputꢀOutput P0.5ꢀExternal Interrupt Request 1ꢀUART Clear to Send Signal.
General-Purpose InputꢀOutput P0.6ꢀExternal Interrupt Request 2ꢀUART1 Serial Input.
General-Purpose InputꢀOutput P0.7ꢀPower-On Reset Pin (Active High)ꢀUART1 Serial Output.
Digital System Supply Pin. This pin must be connected to DGND via a 0.1 ꢁF capacitor.
General-Purpose InputꢀOutput P1.0ꢀExternal Interrupt Request 3ꢀPWM External
Synchronization InputꢀExternal Clock Input Pin.
P0.6ꢀIRQ2ꢀRxD1
P0.7ꢀPORꢀTxD1
IOVDD
P1.0ꢀIRQ3ꢀPWMSYNCꢀEXTCLK
39
40
P1.1ꢀIRQ4ꢀPWMTRIPꢀDTR
P1.2ꢀPWM0ꢀRI
General-Purpose InputꢀOutput P1.1ꢀExternal Interrupt Request 4ꢀPWM External Trip Inputꢀ
UART Data Terminal Ready Pin.
General-Purpose InputꢀOutput P1.2ꢀPWM0 OutputꢀUART Ring Indicator Pin.
Rev. 0| Page 20 of 24
Data Sheet
ADuCM362/ADuCM363
Pin No. Mnemonic
Description
41
42
P1.3ꢀPWM1ꢀDSR
General-Purpose InputꢀOutput P1.3ꢀPWM1 OutputꢀUART Data Set Ready Pin.
General-Purpose InputꢀOutput P1.4ꢀPWM2 OutputꢀSPI0 Master Input, Slave Output PinꢀI2C
Serial Data Pin.
General-Purpose InputꢀOutput P1.5ꢀExternal Interrupt Request 5ꢀPWM3 OutputꢀSPI0 Serial
Clock Pin.
General-Purpose InputꢀOutput P1.6ꢀExternal Interrupt Request 6ꢀPWM4 OutputꢀSPI0 Master
Output, Slave Input Pin.
P1.4ꢀPWM2ꢀMISO0ꢀSDA
P1.5ꢀIRQ5ꢀPWM3ꢀSCLK0
P1.6ꢀIRQ6ꢀPWM4ꢀMOSI0
P1.7ꢀIRQ7ꢀPWM5ꢀCS0
43
44
45
General-Purpose InputꢀOutput P1.7ꢀExternal Interrupt Request 7ꢀPWM5 OutputꢀSPI0 Chip
Select Pin (Active Low) (when using SPI0, configure this pin as CS0).
46
47
48
P2.0ꢀSCLꢀUARTCLK
General-Purpose InputꢀOutput P2.0ꢀI2C Serial Clock PinꢀInput Clock Pin for UART Block Only.
Serial Wire Debug Clock Input Pin.
Serial Wire Debug Data InputꢀOutput Pin.
Exposed Pad. The LFCSP has an exposed pad that must be soldered to a metal plate on the
PCB and to DGND for mechanical reasons.
SWCLK
SWDIO
EP
Rev. 0 | Page 21 of 24
ADuCM362/ADuCM363
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
60
50
40
30
250
200
150
100
50
I
P
I
20
10
N
I
– I
N
P
BOOST = 0
0
–10
–20
–30
BOOST = 30
400
0
0
200
600
800
1000
1200
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
COMMON-MODE VOLTAGE (V)
CAPACITANCE (nF)
Figure 9. Input Current vs. Common-Mode Voltage (VCM), Gain = 4,
ADC Input = 250 mV, AVDD = 3.6 V, TA = 25°C, VCM = ((AIN+) + (AIN−))/2
Figure 12. VBIASx Output Settling Time vs. Load Capacitance, TA = 25°C,
IOVDD and AVDD = 3.3 V
5
4
30
25
20
15
10
5
3
2
1
0
–1
–2
–3
–4
–5
I
I
I
P
N
P
– I
N
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
COMMON-MODE VOLTAGE (V)
VOLTAGE (V)
Figure 13. Digital Input Pin Pull-Up Resistance Value vs. Voltage Applied
to Digital Pin, TA = 25°C, IOVDD = 3.4 V
Figure 10. Input Current vs. Common-Mode Voltage (VCM), Gain = 128,
ADC Input = 7.8125 mV, AVDD = 3.6 V, TA = 25°C, VCM = ((AIN+) + (AIN−))/2
14000000
12000000
10000000
8000000
6000000
4000000
2000000
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
–40
–20
0
20
40
60
80
100
120
VOLTAGE (V)
TEMPERATURE (°C)
Figure 14. Digital Input Pin Pull-Up Resistance Value vs. Voltage Applied
to Digital Pin, TA = 25°C, IOVDD = 1.8 V
Figure 11. ADC Codes (Decimal Values) vs. Die Temperature
Rev. 0| Page 22 of 24
Data Sheet
ADuCM362/ADuCM363
TYPICAL SYSTEM CONFIGURATION
Figure 15 shows a typical ADuCM362/ADuCM363 configuration.
This figure illustrates some of the hardware considerations. The
bottom of the LFCSP package has an exposed pad that must be
soldered to a metal plate on the PCB for mechanical reasons
and to DGND. The metal plate of the PCB can be connected to
ground. Place the 0.47 ꢀF capacitor on the AVDD_REG and
DVDD_REG pins as close to the pins as possible. In noisy
environments, an additional 1 nF capacitor can be added to
IOVDD and AVDD.
43
42
41
48
47
46
45
44
RESET
1
2
3
4
5
6
7
8
9
RESET
40
39
P1.2/PWM0/RI
P2.1/SDA/UART1DCD/UARTDCD
P1.1/IRQ4/PWMTRIP/DTR
DVDD
12pF
12pF
P2.2/BM
XTALO
XTALI
P1.0/IRQ3/PWMSYNC/EXTC
LK 38
37
36
35
34
IOVDD
0.1µF
DGND
P0.7/POR/TxD1
P0.6/IRQ2/RxD1
P0.5/CTS/IRQ1
DVDD
DGND
IOVDD
DVDD_REG
AIN0
0.1µF
DGND
P0.4/RTS/ECLKO/RTS1 33
P0.3/IRQ0/CS1/RTS1/RTS 32
P0.2/MOSI1/SDA/TxD 31
P0.1/SCLK1/SCL/RxD 30
P0.0/MISO1/UART1DCD/UARTDCD 29
AIN11/VBIAS1 28
ADuCM362/
ADuCM363
AIN1
10 AIN2
11 AIN3
0.47µF
DGND
12 AIN4/IEXC
13 GND_SW
14 VREF+
15 VREF–
16 AGND
AIN10 27
AIN9/DACBUFF+ 26
AIN8/EXTREF2IN– 25
17
18
19
20
21
22
23
24
AVDD
0.1µF
0.47µF
150kΩ
0.47µF
RESET
GND
RESET
SWDIO
DGND
SWIO
TX
SWCLK
RX
SWCLK
5V USB
DVDD
AVDD
ADP1720ARMZ-3.3
1.6Ω
IN
OUT
1µF
560Ω
DGND
EN
4.7µF
0.1µF
4.7µF
0.1µF
GND
DGND
AGND
AGND AGND
DGND
Figure 15. Typical System Configuration
Rev. 0 | Page 23 of 24
ADuCM362/ADuCM363
OUTLINE DIMENSIONS
Data Sheet
7.00
BSC SQ
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
48
37
36
1
0.50
BSC
EXPOSED
PAD
5.20
5.10 SQ
5.00
12
13
25
24
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
Figure 16. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Ordering
Quantity
Model1
ADCs
Flash/SRAM Temperature Range Package Description
Option
CP-48-4
CP-48-4
CP-48-4
CP-48-4
CP-48-4
CP-48-4
CP-48-4
CP-48-4
ADuCM362BCPZ256
Dual 24-Bit
256 kBꢀ24 kB −40°C to +125°C
256 kBꢀ24 kB −40°C to +125°C
128 kBꢀ16 kB −40°C to +125°C
128 kBꢀ16 kB −40°C to +125°C
256 kBꢀ24 kB −40°C to +125°C
256 kBꢀ24 kB −40°C to +125°C
128 kBꢀ16 kB −40°C to +125°C
128 kBꢀ16 kB −40°C to +125°C
48-Lead LFCSP
48-Lead LFCSP
48-Lead LFCSP
48-Lead LFCSP
48-Lead LFCSP
48-Lead LFCSP
48-Lead LFCSP
48-Lead LFCSP
ADuCM362BCPZ256RL7 Dual 24-Bit
ADuCM362BCPZ128 Dual 24-Bit
ADuCM362BCPZ128RL7 Dual 24-Bit
ADuCM363BCPZ256 Single 24-Bit
ADuCM363BCPZ256RL7 Single 24-Bit
ADuCM363BCPZ128 Single 24-Bit
750
750
750
750
ADuCM363BCPZ128RL7 Single 24-Bit
EVAL-ADuCM362QSPZ
ADuCM362 QuickStart Plus
Development System
EVAL-ADuCM363QSPZ
ADuCM363 QuickStart Plus
Development System
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14919-0-10/16(0)
Rev. 0| Page 24 of 24
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