ADSP-BF536BBCZ-4B1_技术文档

Blackfin^®

Embedded Processor

a

Preliminary Technical Data

FEATURES

ADSP-BF536/ADSP-BF537

Two Dual-Channel Memory DMA Controllers

Memory Management Unit Providing Memory Protection

Up to 600 MHz High-Performance Blackfin Processor

Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video

ALUs, 40-Bit Shifter

RISC-Like Register and Instruction Model for Ease of

Programming and Compiler-Friendly Support

Advanced Debug, Trace, and Performance-Monitoring

0.8 V to 1.2 V Core V_DDwith On-chip Voltage Regulation

2.5 V and 3.3 V-Tolerant I/O with Specific 5 V-Tolerant Pins

182-Ball MBGA and 208-Ball Sparse MBGA Packages

Lead Bearing and Lead Free Package Choices

PERIPHERALS

IEEE 802.3-Compliant 10/100 Ethernet MAC

Controller Area Network (CAN) 2.0B Interface

Parallel Peripheral Interface (PPI), Supporting ITU-R 656

Video Data Formats

Two Dual-Channel, Full-Duplex Synchronous Serial Ports

(SPORTs), Supporting Eight Stereo I²S Channels

12 Peripheral DMAs, 2 Mastered by the Ethernet MAC

Two Memory-to-Memory DMAs With External Request Lines

Event Handler With 32 Interrupt Inputs

MEMORY

Serial Peripheral Interface (SPI)-Compatible

Two UARTs with IrDA® Support

Two-Wire Interface (TWI) Controller

Eight 32-Bit Timer/Counters with PWM Support

Real-Time Clock (RTC) and Watchdog Timer

32-Bit Core Timer

48 General-Purpose I/Os (GPIOs), 8 with High Current Drivers

On-Chip PLL Capable of 1x to 63x Frequency Multiplication

Debug/JTAG Interface

Up to 132K Bytes of On-Chip Memory:

16K Bytes of Instruction SRAM/Cache

48K Bytes of Instruction SRAM

32K Bytes of Data SRAM/Cache

32K Bytes of Data SRAM

4K Bytes of Scratchpad SRAM

External Memory Controller with Glueless Support for

SDRAM and Asynchronous 8/16-Bit Memories

Flexible Booting Options from External Flash, SPI and TWI

Memory or from SPI, TWI, and UART Host Devices

EVENT

CONTROLLER/

CORE TIMER

JTAG TEST AND

EMULATION

WATCHDOG TIMER

RTC

GPIO

PORT

ETHERNET MAC

H

VOLTAGE

B

REGULATOR

CAN

PORT

TWI

J

L1

MMU

INSTRUCTION

DATA

SPORT0

MEMORY

SPORT1

GPIO

CORE / SYSTEM BUS INTERFACE

PORT

G

PPI

UART 0-1

DMA

GPIO

PORT

F

CONTROLLER

SPI

TIMERS 0-7

BOOT ROM

EXTERNAL PORT

FLASH, SDRAM

CONTROL

Figure 1. Functional Block Diagram

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ADSP-BF536/BF537

Preliminary Technical Data

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low-Power Architecture ............................. 3

System Integration ................................................ 3

ADSP-BF536/BF537 Processor Peripherals ................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 4

Internal (On-chip) Memory ................................. 5

External (Off-Chip) Memory ................................ 5

I/O Memory Space ............................................. 6

Booting ........................................................... 6

Event Handling ................................................. 6

Core Event Controller (CEC) ................................ 7

System Interrupt Controller (SIC) .......................... 7

Event Control ................................................... 8

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 9

Watchdog Timer .................................................. 9

Timers ............................................................. 10

Serial Ports (SPORTs) .......................................... 10

Serial Peripheral Interface (SPI) Port ....................... 10

UART Ports (UARTs) .......................................... 11

Controller Area Network (CAN) ............................ 11

TWI Controller Interface ...................................... 11

10/100 Ethernet MAC .......................................... 11

Ports ................................................................ 12

General-Purpose I/O (GPIO) .............................. 12

Parallel Peripheral Interface (PPI) ........................... 13

Dynamic Power Management ................................ 13

Full-On Operating Mode – Maximum Performance . 13

Active Operating Mode – Moderate Power Savings .. 13

EZ-KIT Lite Evaluation Board ............................. 17

Designing an Emulator-Compatible Processor

Board (Target) ................................................. 17

Related Documents .............................................. 18

Pin Descriptions .................................................... 19

Specifications ........................................................ 23

Recommended Operating Conditions ...................... 23

Absolute Maximum Ratings ................................... 25

ESD Sensitivity ................................................... 25

Timing Specifications ........................................... 26

Asynchronous Memory Read Cycle Timing ............ 28

Asynchronous Memory Write Cycle Timing ........... 29

SDRAM Interface Timing .................................. 30

External Port Bus Request and Grant Cycle Timing .. 31

External DMA Request Timing ............................ 32

Parallel Peripheral Interface Timing ...................... 33

Serial Ports ..................................................... 34

Serial Peripheral Interface (SPI) Port—

Master Timing .............................................. 39

Serial Peripheral Interface (SPI) Port—

Slave Timing ................................................ 40

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing ..... 41

General-Purpose Port Timing ............................. 42

Timer Cycle Timing .......................................... 43

JTAG Test And Emulation Port Timing ................. 44

TWI Controller Timing ..................................... 45

10/100 Ethernet MAC Controller Timing ............... 49

Output Drive Currents ......................................... 52

Power Dissipation ............................................... 55

Test Conditions .................................................. 55

Output Enable Time ......................................... 55

Output Disable Time ......................................... 55

Example System Hold Time Calculation ................ 56

Environmental Conditions .................................... 56

182-Ball Mini-BGA Pinout ....................................... 57

208-Ball Sparse Mini-BGA Pinout .............................. 60

Outline Dimensions ................................................ 63

Ordering Guide ..................................................... 64

Sleep Operating Mode – High Dynamic

Power Savings .............................................. 13

Deep Sleep Operating Mode – Maximum Dynamic

Power Savings .............................................. 13

Hibernate Operating Mode – Maximum Static Power

Savings ....................................................... 14

Power Savings ................................................. 14

Voltage Regulation .............................................. 14

Clock Signals ..................................................... 14

Booting Modes ................................................... 16

Instruction Set Description ................................... 17

Development Tools ............................................. 17

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Preliminary Technical Data

ADSP-BF536/BF537

REVISION HISTORY

Revision PrE: Corrections to PrD because of changes to Order-

ing Guide, changes to recommended operating conditions,

other minor corrections.

Related Documents ................................................. 18

Recommended Operating Conditions ......................... 23

Figure 9 ............................................................... 25

Tables 10, 11, 12, and 13 ........................................... 26

Figures 49 and 50 ....................................................59

Figures 51 and 52 ................................................... 62

Table 52 ............................................................... 60

Table 53 ............................................................... 61

Figures 53 and 54 ....................................................63

Ordering Guide ..................................................... 64

Changes to:

Figure 2 ................................................................. 5

Dynamic Power Management .................................... 13

Clock Signals ......................................................... 14

Figure 7 ................................................................ 15

Booting Modes ....................................................... 16

Development Tools ................................................. 17

GENERAL DESCRIPTION

The ADSP-BF536/BF537 processors are members of the Black-

fin family of products, incorporating the Analog Devices/Intel

Micro Signal Architecture (MSA). Blackfin processors combine

a dual-MAC state-of-the-art signal processing engine, the

advantages of a clean, orthogonal RISC-like microprocessor

instruction set, and single-instruction, multiple-data (SIMD)

multimedia capabilities into a single instruction-set

architecture.

The ADSP-BF536/BF537 processors are completely code and

pin compatible, differing only with respect to their performance

and on-chip memory. Specific performance and memory con-

figurations are shown in Table 1.

Table 1. Processor Comparison

ADSP-BF536

ADSP-BF537

Maximum performance

Instruction SRAM/Cache

Instruction SRAM

Data SRAM/Cache

Data SRAM

400 MHz

16K bytes

48K bytes

16K bytes

4K bytes

600 MHz

16K bytes

48K bytes

32K bytes

4K bytes

Scratchpad

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like program-

mability, multimedia support and leading-edge signal

processing in one integrated package.

dard interfaces with a high performance signal processing core,

users can develop cost-effective solutions quickly without the

need for costly external components. The system peripherals

include an IEEE-compliant 802.3 10/100 Ethernet MAC, a CAN

2.0B controller, a TWI controller, two UART ports, an SPI port,

two serial ports (SPORTs), nine general purpose 32-bit timers

(eight with PWM capability), a real-time clock, a watchdog

timer, and a Parallel Peripheral Interface.

PORTABLE LOW-POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. Blackfin processors are designed in a low

power and low voltage design methodology and feature on-chip

Dynamic Power Management, the ability to vary both the volt-

age and frequency of operation to significantly lower overall

power consumption. Varying the voltage and frequency can

result in a substantial reduction in power consumption, com-

pared with just varying the frequency of operation. This

translates into longer battery life for portable appliances.

ADSP-BF536/BF537 PROCESSOR PERIPHERALS

The ADSP-BF536/BF537 processor contains a rich set of

peripherals connected to the core via several high bandwidth

buses, providing flexibility in system configuration as well as

excellent overall system performance (see the block diagram

on Page 1). The general-purpose peripherals include functions

such as UARTs, SPI, TWI, Timers with PWM (Pulse Width

Modulation) and pulse measurement capability, general pur-

pose I/O pins, a Real-Time Clock, and a Watchdog Timer. This

set of functions satisfies a wide variety of typical system support

needs and is augmented by the system expansion capabilities of

the part. The ADSP-BF536/BF537 processor contains dedicated

network communication modules and high-speed serial and

SYSTEM INTEGRATION

The ADSP-BF536/BF537 processors are highly integrated sys-

tem-on-a-chip solutions for the next generation of embedded

network connected applications. By combining industry-stan-

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ADSP-BF536/BF537

Preliminary Technical Data

parallel ports, an interrupt controller for flexible management

of interrupts from the on-chip peripherals or external sources,

and power management control functions to tailor the perfor-

mance and power characteristics of the processor and system to

many application scenarios.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

All of the peripherals, except for general-purpose I/O, CAN,

TWI, Real-Time Clock, and timers, are supported by a flexible

DMA structure. There are also separate memory DMA channels

dedicated to data transfers between the processor's various

memory spaces, including external SDRAM and asynchronous

memory. Multiple on-chip buses running at up to 133 MHz

provide enough bandwidth to keep the processor core running

along with activity on all of the on-chip and external

peripherals.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit Index, Modify,

Length, and Base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

The ADSP-BF536/BF537 processor includes an on-chip voltage

regulator in support of the ADSP-BF536/BF537 processor

Dynamic Power Management capability. The voltage regulator

provides a range of core voltage levels when supplied from a sin-

gle 2.25 V to 3.6 V input. The voltage regulator can be bypassed

at the user's discretion.

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

BLACKFIN PROCESSOR CORE

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The Memory Manage-

ment Unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

As shown in Figure 2 on Page 5, the Blackfin processor core

contains two 16-bit multipliers, two 40-bit accumulators, two

40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-

tation units process 8-bit, 16-bit, or 32-bit data from the register

file.

The architecture provides three modes of operation: User mode,

Supervisor mode, and Emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while Supervisor mode has

unrestricted access to the system and core resources.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation are

supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2³²multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations, 16-

bit and 8-bit adds with clipping, 8-bit average operations, and 8-

bit subtract/absolute value/accumulate (SAA) operations. Also

provided are the compare/select and vector search instructions.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). By also using the second

ALU, quad 16-bit operations are possible.

The ADSP-BF536/BF537 processor views memory as a single

unified 4G byte address space, using 32-bit addresses. All

resources, including internal memory, external memory, and

I/O control registers, occupy separate sections of this common

address space. The memory portions of this address space are

arranged in a hierarchical structure to provide a good cost/per-

formance balance of some very fast, low-latency on-chip

memory as cache or SRAM, and larger, lower-cost and perfor-

mance off-chip memory systems. See Figure 3 on Page 6, and

Figure 4 on Page 6.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

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Preliminary Technical Data

ADSP-BF536/BF537

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

P3

P2

P1

P0

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

DAG0

DA1 32

DA0 32

32

PREG

32

RAB

SD 32

LD1 32

LD0 32

ASTAT

32

SEQUENCER

ALIGN

R7.H

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L

R6.L

R5.L

R4.L

R3.L

R2.L

R1.H

R0.L

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

The on-chip L1 memory system is the highest-performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the External Bus Interface Unit

(EBIU), provides expansion with SDRAM, flash memory, and

SRAM, optionally accessing up to 516M bytes of physical

memory.

The third memory block is a 4K byte scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory

devices including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

The memory DMA controller provides high-bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal memory and the external memory

spaces.

The PC133-compliant SDRAM controller can be programmed

to interface to up to 512M bytes of SDRAM. A separate row can

be open for each SDRAM internal bank and the SDRAM con-

troller supports up to 4 internal SDRAM banks, improving

overall performance.

Internal (On-chip) Memory

The ADSP-BF536/BF537 processor has three blocks of on-chip

memory providing high-bandwidth access to the core.

The first block is the L1 instruction memory, consisting of

64K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks will only be contiguous if each is fully popu-

lated with 1M byte of memory.

The second on-chip memory block is the L1 data memory, con-

sisting of up to two banks of up to 32K bytes each. Each memory

bank is configurable, offering both Cache and SRAM function-

ality. This memory block is accessed at full processor speed.

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ADSP-BF536/BF537

Preliminary Technical Data

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 C000

0xFFA0 8000

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 C000

0xFFA0 8000

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM / CACHE (16K BYTE)

RESERVED

INSTRUCTION SRAM / CACHE (16K BYTE)

RESERVED

INSTRUCTION BANK B SRAM (16K BYTE)

INSTRUCTION BANK A SRAM (32K BYTE)

RESERVED

INSTRUCTION BANK B SRAM (16K BYTE)

INSTRUCTION BANK A SRAM (32K BYTE)

RESERVED

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

0xEF00 0800

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0000 0000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

0xEF00 0800

0xEF00 0000

DATA BANK B SRAM / CACHE (16K BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

DATA BANK B SRAM (16K BYTE)

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

DATA BANK A SRAM (16K BYTE)

RESERVED

BOOT ROM (2K BYTE)

RESERVED

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0000 0000

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE - 512M BYTE)

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

SDRAM MEMORY (16M BYTE - 512M BYTE)

Figure 3. ADSP-BF536 Internal/External Memory Map

Figure 4. ADSP-BF537 Internal/External Memory Map

oritization ensures that servicing of a higher-priority event takes

precedence over servicing of a lower-priority event. The con-

troller provides support for five different types of events:

I/O Memory Space

The ADSP-BF536/BF537 processors do not define a separate

I/O space. All resources are mapped through the flat 32-bit

address space. On-chip I/O devices have their control registers

mapped into memory-mapped registers (MMRs) at addresses

near the top of the 4G byte address space. These are separated

into two smaller blocks, one which contains the control MMRs

for all core functions, and the other which contains the registers

needed for setup and control of the on-chip peripherals outside

of the core. The MMRs are accessible only in supervisor mode

and appear as reserved space to on-chip peripherals.

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

• Non-Maskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

Booting

• Exceptions – Events that occur synchronously to program

flow (i.e., the exception will be taken before the instruction

is allowed to complete). Conditions such as data alignment

violations and undefined instructions cause exceptions.

The ADSP-BF536/BF537 processor contains a small on-chip

Boot Kernel, which configures the appropriate peripheral for

booting. If the ADSP-BF536/BF537 processor is configured to

boot from Boot ROM memory space, the processor starts exe-

cuting from the on-chip Boot ROM. For more information, see

Booting Modes on Page 16.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

Event Handling

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

The event controller on the ADSP-BF536/BF537 processor han-

dles all asynchronous and synchronous events to the processor.

The ADSP-BF536/BF537 processor provides event handling

that supports both nesting and prioritization. Nesting allows

multiple event service routines to be active simultaneously. Pri-

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Preliminary Technical Data

ADSP-BF536/BF537

The ADSP-BF536/BF537 processor Event Controller consists of

two stages, the Core Event Controller (CEC) and the System

Interrupt Controller (SIC). The Core Event Controller works

with the System Interrupt Controller to prioritize and control all

system events. Conceptually, interrupts from the peripherals

enter into the SIC, and are then routed directly into the general-

purpose interrupts of the CEC.

Table 3. System Interrupt Controller (SIC)

Peripheral Interrupt Event

Default

Peripheral

Interrupt ID

Mapping

PLL Wakeup

IVG7

IVG8

IVG9

IVG10

IVG11

0

DMA Error (generic)

DMAR0 Block Interrupt

DMAR1 Block Interrupt

DMAR0 Overflow Error

DMAR1 Overflow Error

CAN Error

1

Core Event Controller (CEC)

1

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the ADSP-BF536/BF537 processor.

Table 2 describes the inputs to the CEC, identifies their names

in the Event Vector Table (EVT), and lists their priorities.

1

2

Ethernet Error

2

SPORT 0 Error

2

SPORT 1 Error

2

PPI Error

2

SPI Error

2

Table 2. Core Event Controller (CEC)

UART0 Error

2

UART1 Error

2

Priority

Event Class

EVT Entry

Real-Time Clock

3

(0 is Highest)

DMA Channel 0 (PPI)

DMA Channel 3 (SPORT 0 RX)

DMA Channel 4 (SPORT 0 TX)

DMA Channel 5 (SPORT 1 RX)

DMA Channel 6 (SPORT 1 TX)

TWI

4

0

Emulation/Test Control EMU

Reset RST

Non-Maskable Interrupt NMI

5

1

6

2

7

3

Exception

EVX

8

4

Reserved

—

9

5

Hardware Error

IVHW

IVTMR

IVG7

DMA Channel 7 (SPI)

DMA Channel 8 (UART0 RX)

DMA Channel 9 (UART0 TX)

DMA Channel 10 (UART1 RX)

DMA Channel 11 (UART1 TX)

CAN RX

10

11

12

13

14

15

16

17

18

6

Core Timer

7

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

8

IVG8

9

IVG9

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

CAN TX

DMA Channel 1 (Ethernet RX)

Port H Interrupt A

DMA Channel 2 (Ethernet TX)

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and

routing of events from the many peripheral interrupt sources to

the prioritized general-purpose interrupt inputs of the CEC.

Although the ADSP-BF536/BF537 processor provides a default

mapping, the user can alter the mappings and priorities of

interrupt events by writing the appropriate values into the Inter-

rupt Assignment Registers (IAR). Table 3 describes the inputs

into the SIC and the default mappings into the CEC.

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ADSP-BF536/BF537

Preliminary Technical Data

Table 3. System Interrupt Controller (SIC) (Continued)

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 3 on Page 7.

Peripheral Interrupt Event

Default

Peripheral

Mapping

Interrupt ID

Port H Interrupt B

Timer 0

IVG11

IVG12

IVG13

18

19

20

21

22

23

24

25

26

27

28

29

• SIC Interrupt Mask Register (SIC_IMASK)– This register

controls the masking and unmasking of each peripheral

interrupt event. When a bit is set in the register, that

peripheral event is unmasked and will be processed by the

system when asserted. A cleared bit in the register masks

the peripheral event, preventing the processor from servic-

ing the event.

Timer 1

Timer 2

Timer 3

Timer 4

Timer 5

• SIC Interrupt Status Register (SIC_ISR) – As multiple

peripherals can be mapped to a single event, this register

allows the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

Timer 6

Timer 7

Port F, G Interrupt A

Port G Interrupt B

DMA Channels 12 and 13

(Memory DMA Stream 0)

• SIC Interrupt Wakeup Enable Register (SIC_IWR) – By

enabling the corresponding bit in this register, a peripheral

can be configured to wake up the processor, should the

core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 13.)

DMA Channels 14 and 15

(Memory DMA Stream 1)

IVG13

30

Software Watchdog Timer

Port F Interrupt B

IVG13

31

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

Event Control

The ADSP-BF536/BF537 processor provides the user with a

very flexible mechanism to control the processing of events. In

the CEC, three registers are used to coordinate and control

events. Each register is 16 bits wide:

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC will recognize and queue the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

• CEC Interrupt Latch Register (ILAT) – The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

it may be written only when its corresponding IMASK bit

is cleared.

• CEC Interrupt Mask Register (IMASK) – The IMASK reg-

ister controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and will be processed by the CEC when asserted.

A cleared bit in the IMASK register masks the event, pre-

venting the processor from servicing the event even though

the event may be latched in the ILAT register. This register

may be read or written while in supervisor mode. (Note

that general-purpose interrupts can be globally enabled and

disabled with the STI and CLI instructions, respectively.)

DMA CONTROLLERS

The ADSP-BF536/BF537 processor has multiple, independent

DMA controllers that support automated data transfers with

minimal overhead for the processor core. DMA transfers can

occur between the ADSP-BF536/BF537 processor's internal

memories and any of its DMA-capable peripherals. Addition-

ally, DMA transfers can be accomplished between any of the

DMA-capable peripherals and external devices connected to the

external memory interfaces, including the SDRAM controller

and the asynchronous memory controller. DMA-capable

peripherals include the Ethernet MAC, SPORTs, SPI port,

UARTs, and PPI. Each individual DMA-capable peripheral has

at least one dedicated DMA channel.

• CEC Interrupt Pending Register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

The ADSP-BF536/BF537 processor DMA controller supports

both 1-dimensional (1D) and 2-dimensional (2D) DMA trans-

fers. DMA transfer initialization can be implemented from

registers or from sets of parameters called descriptor blocks.

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Preliminary Technical Data

ADSP-BF536/BF537

The 2D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day. The second alarm is for a day and time of that

day.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch is

enabled and the counter underflows, an interrupt is generated.

Examples of DMA types supported by the ADSP-BF536/BF537

processor DMA controller include:

Like the other peripherals, the RTC can wake up the ADSP-

BF536/BF537 processor from Sleep mode upon generation of

any RTC wakeup event. Additionally, an RTC wakeup event can

wake up the ADSP-BF536/BF537 processor from Deep Sleep

mode, and wake up the on-chip internal voltage regulator from

the Hibernate operating mode.

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 5.

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels provided for transfers between the

various memories of the ADSP-BF536/BF537 processor system.

This enables transfers of blocks of data between any of the

memories—including external SDRAM, ROM, SRAM, and

flash memory—with minimal processor intervention. Memory

DMA transfers can be controlled by a very flexible descriptor-

based methodology or by a standard register-based autobuffer

mechanism.

RTXI

RTXO

R1

X1

C1

C2

The ADSP-BF536/BF537 processors also include an external

DMA controller capability via dual external DMA request pins

when used in conjunction with the External Bus Interface Unit

(EBIU). This functionality can be used when a high speed inter-

face is required for external FIFOs and high bandwidth

communications peripherals such as USB 2.0. It allows control

of the number of data transfers for memDMA. The number of

transfers per edge is programmable. This feature can be pro-

grammed to allow memDMA to have an increased priority on

the external bus relative to the core.

SUGGESTED COMPONENTS:

ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)

EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE)

C1 = 22 PF

C2 = 22 PF

⍀

R1 = 10 M

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.

Figure 5. External Components for RTC

WATCHDOG TIMER

REAL-TIME CLOCK

The ADSP-BF536/BF537 processor includes a 32-bit timer that

can be used to implement a software watchdog function. A soft-

ware watchdog can improve system availability by forcing the

processor to a known state through generation of a hardware

reset, non-maskable interrupt (NMI), or general-purpose inter-

rupt, if the timer expires before being reset by software. The

programmer initializes the count value of the timer, enables the

appropriate interrupt, then enables the timer. Thereafter, the

software must reload the counter before it counts to zero from

the programmed value. This protects the system from remain-

ing in an unknown state where software, which would normally

reset the timer, has stopped running due to an external noise

condition or software error.

The ADSP-BF536/BF537 processor Real-Time Clock (RTC)

provides a robust set of digital watch features, including current

time, stopwatch, and alarm. The RTC is clocked by a

32.768 KHz crystal external to the ADSP-BF536/BF537 proces-

sor. The RTC peripheral has dedicated power supply pins so

that it can remain powered up and clocked even when the rest of

the processor is in a low-power state. The RTC provides several

programmable interrupt options, including interrupt per sec-

ond, minute, hour, or day clock ticks, interrupt on

programmable stopwatch countdown, or interrupt at a pro-

grammed alarm time.

The 32.768 KHz input clock frequency is divided down to a

1 Hz signal by a prescaler. The counter function of the timer

consists of four counters: a 60-second counter, a 60-minute

counter, a 24-hour counter, and an 32,768-day counter.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the ADSP-BF536/BF537 processor

peripherals. After a reset, software can determine if the watch-

dog was the source of the hardware reset by interrogating a

status bit in the watchdog timer control register.

Rev. PrE

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ADSP-BF536/BF537

Preliminary Technical Data

The timer is clocked by the system clock (SCLK), at a maximum

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

frequency of f_SCLK

.

TIMERS

There are nine general-purpose programmable timer units in

the ADSP-BF536/BF537 processor. Eight timers have an exter-

nal pin that can be configured either as a Pulse Width

Modulator (PWM) or timer output, as an input to clock the

timer, or as a mechanism for measuring pulse widths and peri-

ods of external events. These timers can be synchronized to an

external clock input to the several other associated PF pins, an

external clock input to the PPI_CLK input pin, or to the internal

SCLK.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The timer units can be used in conjunction with the two UARTs

and the CAN controller to measure the width of the pulses in

the data stream to provide a software auto-baud detect function

for the respective serial channels.

The ADSP-BF536/BF537 processor has an SPI-compatible port

that enables the processor to communicate with multiple SPI-

compatible devices.

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSI, and Master Input-

Slave Output, MISO) and a clock pin (Serial Clock, SCK). An

SPI chip select input pin (SPISS) lets other SPI devices select the

processor, and seven SPI chip select output pins (SPISEL7–1) let

the processor select other SPI devices. The SPI select pins are

reconfigured Programmable Flag pins. Using these pins, the SPI

port provides a full-duplex, synchronous serial interface, which

supports both master/slave modes and multimaster

environments.

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

In addition to the eight general-purpose programmable timers,

a ninth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTS)

The ADSP-BF536/BF537 processor incorporates two dual-

channel synchronous serial ports (SPORT0 and SPORT1) for

serial and multiprocessor communications. The SPORTs sup-

port the following features:

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA controller,

configurable to support transmit or receive data streams. The

SPI’s DMA controller can only service unidirectional accesses at

any given time.

• I²S capable operation.

The SPI port’s clock rate is calculated as:

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I²S stereo audio.

f

SCLK

SPI Clock Rate = ---------------------------------

2 × SPI_Baud

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

Where the 16-bit SPI_Baud register contains a value of 2 to

65,535.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-bit

first or least-significant-bit first.

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulsewidths and early or late

frame sync.

• Companding in hardware – Each SPORT can perform

A-law or µ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without additional

latencies.

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Preliminary Technical Data

ADSP-BF536/BF537

The ADSP-BF536/BF537 CAN controller offers the following

features:

UART PORTS (UARTS)

The ADSP-BF536/BF537 processor provides two full-duplex

Universal Asynchronous Receiver/Transmitter (UART) ports,

which are fully compatible with PC-standard UARTs. Each

UART port provides a simplified UART interface to other

peripherals or hosts, supporting full-duplex, DMA-supported,

asynchronous transfers of serial data. A UART port includes

support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or

odd parity. Each UART port supports two modes of operation:

• 32 mailboxes (8 receive only, 8 transmit only, 16 config-

urable for receive or transmit).

• Dedicated acceptance masks for each mailbox.

• Additional data filtering on first two bytes.

• Support for both the standard (11-bit) and extended (29-

bit) identifier (ID) message formats.

• Support for remote frames.

• PIO (Programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• Active or passive network support.

• CAN wakeup from Hibernation Mode (lowest static power

consumption mode).

• DMA (Direct Memory Access) – The DMA controller

transfers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

• Interrupts, including: TX Complete, RX Complete, Error,

Global.

The electrical characteristics of each network connection are

very demanding so the CAN interface is typically divided into

two parts: a controller and a transceiver. This allows a single

controller to support different drivers and CAN networks. The

ADSP-BF536/BF537 CAN module represents only the control-

ler part of the interface. The controller interface supports

connection to 3.3V high-speed, fault-tolerant, single-wire

transceivers.

Each UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_SCLK/ 1,048,576) to

(f_SCLK/16) bits per second.

• Supporting data formats from 7 to12 bits per frame.

TWI CONTROLLER INTERFACE

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The ADSP-BF536/BF537 processor includes a Two Wire Inter-

face (TWI) module for providing a simple exchange method of

control data between multiple devices. The TWI is compatible

with the widely used I²C bus standard. The TWI module offers

the capabilities of simultaneous Master and Slave operation,

support for both 7-bit addressing and multimedia data arbitra-

tion. The TWI interface utilizes two pins for transferring clock

(SCL) and data (SDA) and supports the protocol at speeds up to

400k bits/sec. The TWI interface pins are compatible with 5 V

logic levels.

The UART port’s clock rate is calculated as:

f

SCLK

UART Clock Rate = ------------------------------------------------

16 × UART_Divisor

Where the 16-bit UART_Divisor comes from the DLH register

(most significant 8 bits) and DLL register (least significant

8 bits).

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

Additionally, the ADSP-BF536/BF537 processor’s TWI module

is fully compatible with Serial Camera Control Bus (SCCB)

functionality for easier control of various CMOS camera sensor

devices.

The capabilities of the UARTs are further extended with sup-

port for the Infrared Data Association (IrDA®) Serial Infrared

Physical Layer Link Specification (SIR) protocol.

10/100 ETHERNET MAC

CONTROLLER AREA NETWORK (CAN)

The ADSP-BF536/BF537 processor offers the capability to

directly connect to a network by way of an embedded Fast

Ethernet Medium Access Controller (MAC) that supports both

10-BaseT (10Mbits/sec) and 100-BaseT (100Mbits/sec) opera-

tion. The 10/100 Ethernet MAC peripheral on the ADSP-

BF536/BF537 is fully compliant to the IEEE 802.3-2002 stan-

dard and it provides programmable features designed to

minimize supervision, bus utilization, or message processing by

the rest of the processor system.

The ADSP-BF536/BF537 processor offers a CAN controller that

is a communication controller implementing the Controller

Area Network (CAN) 2.0B (active) protocol. This protocol is an

asynchronous communications protocol used in both industrial

and automotive control systems. The CAN protocol is well

suited for control applications due to its capability to communi-

cate reliably over a network since the protocol incorporates

CRC checking message error tracking, and fault node

confinement.

Some standard features are:

• Support of MII and RMII protocols for external PHYs.

• Full Duplex and Half Duplex modes.

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ADSP-BF536/BF537

Preliminary Technical Data

• Data framing and encapsulation: generation and detection

of preamble, length padding, and FCS.

• Programmable MDC clock rate and preamble suppression.

• In RMII operation, 7 unused pins may be configured as

GPIO pins for other purposes.

• Media access management (in Half-Duplex operation): col-

lision and contention handling, including control of

retransmission of collision frames and of back-off timing.

PORTS

Because of the rich set of peripherals, the ADSP-BF536/BF537

processor groups the many peripheral signals to four ports—

Port F, Port G, Port H, and Port J. Most of the associated pins

are shared by multiple signals. The ports function as multiplexer

controls. Eight of the pins (Port F7–0) offer high source/high

sink current capabilities.

• Flow control (in Full-Duplex operation): generation and

detection of PAUSE frames.

• Station management: generation of MDC/MDIO frames

for read-write access to PHY registers.

• SCLK operating range down to 25MHz (Active and Sleep

operating modes).

General-Purpose I/O (GPIO)

• Internal loopback from TX to RX.

Some advanced features are:

The ADSP-BF536/BF537 processor has 48 bi-directional, gen-

eral-purpose I/O (GPIO) pins allocated across three separate

GPIO modules—PORTFIO, PORTGIO, and PORTHIO, asso-

ciated with Port F, Port G, and Port H, respectively. Port J does

not provide GPIO functionality. Each GPIO-capable pin shares

functionality with other ADSP-BF536/BF537 processor periph-

erals via a multiplexing scheme; however, the GPIO

functionality is the default state of the device upon power-up.

Neither GPIO output or input drivers are active by default. Each

general-purpose port pin can be individually controlled by

manipulation of the port control, status, and interrupt registers:

• Buffered crystal output to external PHY for support of a

single crystal system.

• Automatic checksum computation of IP header and IP

payload fields of RX frames.

• Independent 32-bit descriptor-driven RX and TX DMA

channels.

• Frame status delivery to memory via DMA, including

frame completion semaphores, for efficient buffer queue

management in software.

• GPIO Direction Control Register – Specifies the direction

of each individual GPIO pin as input or output.

• TX DMA support for separate descriptors for MAC header

and payload to eliminate buffer copy operations.

• GPIO Control and Status Registers – The ADSP-

BF536/BF537 processor employs a “write one to modify”

mechanism that allows any combination of individual

GPIO pins to be modified in a single instruction, without

affecting the level of any other GPIO pins. Four control

registers are provided. One register is written in order to set

pin values, one register is written in order to clear pin val-

ues, one register is written in order to toggle pin values, and

one register is written in order to specify a pin value. Read-

ing the GPIO status register allows software to interrogate

the sense of the pins.

• Convenient frame alignment modes support even 32-bit

alignment of encapsulated RX or TX IP packet data in

memory after the 14-byte MAC header.

• Programmable Ethernet event interrupt supports any com-

bination of:

• Any selected RX or TX frame status conditions.

• PHY interrupt condition.

• Wakeup frame detected.

• Any selected MAC management counter(s) at half-

full.

• GPIO Interrupt Mask Registers – The two GPIO Interrupt

Mask registers allow each individual GPIO pin to function

as an interrupt to the processor. Similar to the two GPIO

Control Registers that are used to set and clear individual

pin values, one GPIO Interrupt Mask Register sets bits to

enable interrupt function, and the other GPIO Interrupt

Mask register clears bits to disable interrupt function.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

• DMA descriptor error.

• 47 MAC management statistics counters with selectable

clear-on-read behavior and programmable interrupts on

half maximum value.

• Programmable RX address filters, including a 64-bin

address hash table for multicast and/or unicast frames, and

programmable filter modes for broadcast, multicast, uni-

cast, control, and damaged frames.

• GPIO Interrupt Sensitivity Registers – The two GPIO

Interrupt Sensitivity Registers specify whether individual

pins are level- or edge-sensitive and specify—if edge-sensi-

tive—whether just the rising edge or both the rising and

falling edges of the signal are significant. One register

selects the type of sensitivity, and one register selects which

edges are significant for edge-sensitivity.

• Advanced power management supporting unattended

transfer of RX and TX frames and status to/from external

memory via DMA during low-power Sleep mode.

• System wakeup from Sleep operating mode upon magic

packet or any of four user-definable wakeup frame filters.

• Support for 802.3Q tagged VLAN frames.

Rev. PrE

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Preliminary Technical Data

ADSP-BF536/BF537

further reducing power dissipation. Control of clocking to each

of the ADSP-BF536/BF537 processor peripherals also reduces

power consumption. See Table 4 for a summary of the power

settings for each mode.

PARALLEL PERIPHERAL INTERFACE (PPI)

The ADSP-BF536/BF537 processor provides a Parallel Periph-

eral Interface (PPI) that can connect directly to parallel A/D and

D/A converters, ITU-R-601/656 video encoders and decoders,

and other general-purpose peripherals. The PPI consists of a

dedicated input clock pin, up to 3 frame synchronization pins,

and up to 16 data pins.

Full-On Operating Mode – Maximum Performance

In the Full-On mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

In ITU-R-656 modes, the PPI receives and parses a data stream

of 8-bit or 10-bit data elements. On-chip decode of embedded

preamble control and synchronization information is

supported.

Active Operating Mode – Moderate Power Savings

Three distinct ITU-R-656 modes are supported:

In the Active mode, the PLL is enabled but bypassed. Because

the PLL is bypassed, the processor’s core clock (CCLK) and sys-

tem clock (SCLK) run at the input clock (CLKIN) frequency. In

this mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the Full-On mode is

entered. DMA access is available to appropriately configured L1

memories.

• Active Video Only Mode—The PPI does not read in any

data between the End of Active Video (EAV) and Start of

Active Video (SAV) preamble symbols, or any data present

during the vertical blanking intervals. In this mode, the

control byte sequences are not stored to memory; they are

filtered by the PPI.

• Vertical Blanking Only Mode—The PPI only transfers Ver-

tical Blanking Interval (VBI) data, as well as horizontal

blanking information and control byte sequences on VBI

lines.

In the Active mode, it is possible to disable the PLL through the

PLL Control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the Full-On or Sleep modes.

• Entire Field Mode—The entire incoming bitstream is read

in through the PPI. This includes active video, control pre-

amble sequences, and ancillary data that may be embedded

in horizontal and vertical blanking intervals.

Table 4. Power Settings

Though not explicitly supported, ITU-R-656 output functional-

ity can be achieved by setting up the entire frame structure

(including active video, blanking, and control information) in

memory and streaming the data out the PPI in a frame sync-less

mode. The processor’s 2D DMA features facilitate this transfer

by allowing the static frame buffer (blanking and control codes)

to be placed in memory once, and simply updating the active

video information on a per-frame basis.

Full On

Active

Enabled

No

Enabled Enabled On

Enabled/ Yes

Disabled

Sleep

Enabled

-

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

Deep Sleep Disabled

Hibernate Disabled

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications. The

modes are divided into four main categories, each allowing up

to 16 bits of data transfer per PPI_CLK cycle:

Sleep Operating Mode – High Dynamic Power Savings

The Sleep mode reduces dynamic power dissipation by dis-

abling the clock to the processor core (CCLK). The PLL and

system clock (SCLK), however, continue to operate in this

mode. Typically an external event or RTC activity will wake up

the processor. When in the Sleep mode, assertion of wakeup will

cause the processor to sense the value of the BYPASS bit in the

PLL Control register (PLL_CTL). If BYPASS is disabled, the

processor will transition to the Full On mode. If BYPASS is

enabled, the processor will transition to the Active mode.

• Data Receive with Internally Generated Frame Syncs.

• Data Receive with Externally Generated Frame Syncs.

• Data Transmit with Internally Generated Frame Syncs

• Data Transmit with Externally Generated Frame Syncs

These modes support ADC/DAC connections, as well as video

communication with hardware signalling. Many of the modes

support more than one level of frame synchronization. If

desired, a programmable delay can be inserted between asser-

tion of a frame sync and reception/transmission of data.

When in the Sleep mode, system DMA access to L1 memory is

not supported.

Deep Sleep Operating Mode – Maximum Dynamic Power

Savings

DYNAMIC POWER MANAGEMENT

The ADSP-BF536/BF537 processor provides five operating

modes, each with a different performance/power profile. In

addition, Dynamic Power Management provides the control

functions to dynamically alter the processor core supply voltage,

The Deep Sleep mode maximizes dynamic power savings by

disabling the clocks to the processor core (CCLK) and to all syn-

chronous peripherals (SCLK). Asynchronous peripherals, such

as the RTC, may still be running but will not be able to access

Rev. PrE

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ADSP-BF536/BF537

Preliminary Technical Data

internal resources or external memory. This powered-down

mode can only be exited by assertion of the reset interrupt

(RESET) or by an asynchronous interrupt generated by the

RTC. When in Deep Sleep mode, an RTC asynchronous inter-

rupt causes the processor to transition to the Active mode.

Assertion of RESET while in Deep Sleep mode causes the pro-

cessor to transition to the Full On mode.

results in a 25% reduction in power dissipation, while reducing

the voltage by 25% reduces power dissipation by more than

40%. Further, these power savings are additive, in that if the

clock frequency and supply voltage are both reduced, the power

savings can be dramatic.

The Dynamic Power Management feature of the ADSP-

BF536/BF537 processor allows both the processor’s input volt-

age (V_DDINT) and clock frequency (f_CCLK) to be dynamically

controlled.

Hibernate Operating Mode – Maximum Static Power

Savings

As explained above, the savings in power dissipation can be

modeled by the following equations:

The hibernate mode maximizes static power savings by dis-

abling the voltage and clocks to the processor core (CCLK) and

to all the synchronous peripherals (SCLK). The internal voltage

regulator for the processor can be shut off by writing b#00 to the

FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V_DDINT) to 0V to provide the greatest power savings mode.

Any critical information stored internally (memory contents,

register contents, etc.) must be written to a non-volatile storage

device prior to removing power if the processor state is to be

preserved.

Power Savings Factor

2

f

V

T

CCLKRED

DDINTRED

RED

-------------------------------

--------------------------------------

-----------------

=

×

f

V

T

CCLKNOM

DDINTNOM

NOM

% Power Savings = (1 – Power Savings Factor) × 100%

Since V_DDEXTis still supplied in this mode, all of the external

pins tri-state, unless otherwise specified. This allows other

devices that may be connected to the processor to have power

still applied without drawing unwanted current.

where the variables in the equations are:

• f_CCLKNOMis the nominal core clock frequency

• f_CCLKREDis the reduced core clock frequency

• V_DDINTNOMis the nominal internal supply voltage

• V_DDINTREDis the reduced internal supply voltage

• T_NOMis the duration running at f_CCLKNOM

• T_REDis the duration running at f_CCLKRED

The internal supply regulator can be woken up by CAN or by

Ethernet. It can also be woken up by a Real-Time Clock wakeup

event or by asserting the RESET pin, both of which initiate the

hardware reset sequence.

With the exception of the VR_CTL and the RTC registers, all

internal registers and memories lose their content in hibernate

state. State variables may be held in external SRAM or SDRAM.

The CKELOW bit in the VR_CTL register controls whether

SDRAM operates in self-refresh mode to retain its content while

the processor is in reset.

VOLTAGE REGULATION

The ADSP-BF536/BF537 processor provides an on-chip voltage

regulator that can generate processor core voltage levels (0.85V

to 1.2V guaranteed from -5% to 10%) from an external 2.25 V to

3.6 V supply. Figure 6 shows the typical external components

required to complete the power management system. The regu-

lator controls the internal logic voltage levels and is

programmable with the Voltage Regulator Control Register

(VR_CTL) in increments of 50 mV. To reduce standby power

consumption, the internal voltage regulator can be programmed

to remove power to the processor core while keeping I/O power

supplied. While in Hibernate mode, V_DDEXTcan still be applied,

eliminating the need for external buffers. The voltage regulator

can be activated from this power down state by assertion of the

RESET pin, which will then initiate a boot sequence. The regula-

tor can also be disabled and bypassed at the user’s discretion.

Power Savings

As shown in Table 5, the ADSP-BF536/BF537 processor sup-

ports three different power domains. The use of multiple power

domains maximizes flexibility, while maintaining compliance

with industry standards and conventions. By isolating the inter-

nal logic of the ADSP-BF536/BF537 processor into its own

power domain, separate from the RTC and other I/O, the pro-

cessor can take advantage of Dynamic Power Management,

without affecting the RTC or other I/O devices. There are no

sequencing requirements for the various power domains.

Table 5. Power Domains

CLOCK SIGNALS

Power Domain

VDD Range

V_DDINT

The ADSP-BF536/BF537 processor can be clocked by an exter-

nal crystal, a sine wave input, or a buffered, shaped clock

derived from an external clock oscillator.

All internal logic, except RTC

RTC internal logic and crystal I/O

All other I/O

V_DDRTC

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

V_DDEXT

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

Rev. PrE

|

Page 14 of 64

|

July 2005

Preliminary Technical Data

ADSP-BF536/BF537

If the user prefers, a third-overtone crystal can be used ar fre-

quencies above 25 MHz. The circuit is then modified to ensure

crystal operation only at the third overtone, by adding a tuned

inductor circuit as shown in Figure 7. A design procedure for

third-overtone operation is discussed in detail in application

note EE-168.

V

DDEXT

100 µF

2.25V - 3.6V

INPUT VOLTAGE

RANGE

10 µH

0.1 µF

ZHCS1000

V

DDINT

FDS9431A

The CLKBUF pin is an output pin, and is a buffer version of the

input clock. This pin is particularly useful in Ethernet applica-

tions to limit the number of required clock sources in the

system. In this type of application, a single 25 MHz or 50 MHz

crystal may be applied directly to the ADSP-BF536/BF537 pro-

cessor. The 25 MHz or 50 MHz output of CLKBUF can then be

connected to an external Ethernet MII or RMII PHY device.

Note that on the ADSP-BF536, due to the default 10x PLL mul-

tiplier, providing a 50 MHz CLKIN would exceed the

100 µF

1 µF

VR

1-0

OUT

EXTERNAL COMPONENTS

1-0 SHOULD BE TIED TOGETHER EXTERNALLY

NOTE: VR

OUT

AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.

recommended operating conditions of the 300 MHz and

400 MHz speed grades. Because of this restriction, the RMII

PHY cannot be clocked directly from the CLKBUF pin. A sepa-

rate 50 MHz clock source would need to be provided. The

CLKBUF output is active by default and can be disabled by the

VR_CTL register for power savings

Figure 6. Voltage Regulator Circuit

Alternatively, because the ADSP-BF536/BF537 processor

includes an on-chip oscillator circuit, an external crystal may be

used. For fundamental frequency operation, use the circuit

shown in Figure 7. A parallel-resonant, fundamental frequency,

microprocessor-grade crystal is connected across the CLKIN

and XTAL pins. The on-chip resistance between CLKIN and the

XTAL pin is in the 500 kOhm range. Further parallel resistors

are typically not recommended. The two capacitors and the

series resistor shown in Figure 7 fine tune phase and amplitude

of the sine frequency.

The Blackfin core is running at a different clock rate than the

on-chip peripherals. As shown in Figure 8 on Page 15, the core

clock (CCLK) and system peripheral clock (SCLK) are derived

from the input clock (CLKIN) signal. An on-chip PLL is capable

of multiplying the CLKIN signal by a user programmable 1x to

63x multiplication factor (bounded by specified minimum and

maximum VCO frequencies). The default multiplier is 10x, but

it can be modified by a software instruction sequence in the

PLL_CTL register.

The capacitor and resistor values shown in Figure 7 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations on multiple

devices over temperature range.

On-the-fly CCLK and SCLK frequency changes can be effected

by simply writing to the PLL_DIV register. Whereas the maxi-

mum allowed CCLK and SCLK rates depend on the applied

voltages V_DDINTand V_DDEXT, the VCO is always permitted to run

up to the frequency specified by the part’s speed grade. The

CLKOUT pin reflects the SCLK frequency to the off-chip world.

It belongs to the SDRAM interface, but it functions as reference

signal in other timing specifications as well. While active by

default, it can be disabled by the EBIU_SDGCTL and

EBIU_AMGCTL registers.

BLACKFIN

CLKOUT

TO PLL CIRCUITRY

EN

CLKBUF

DYNAMIC MODIFICATION

REQUIRES PLL SEQUENCING

DYNAMIC MODIFICATION

ON-THE-FLY

EN

CLKIN

18 pF*

XTAL

⍀

330

*

+ 1, 2, 4, 8

+ 1:15

CCLK

SCLK

FOR OVERTONE

OPERATION ONLY:

PLL

.5x - 64x

CLKIN

VCO

18 pF*

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED

DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE

ANALYZE CAREFULLY.

SCLK CCLK

SCLK 133 MHZ

Figure 7. External Crystal Connections

Figure 8. Frequency Modification Methods

Rev. PrE

|

Page 15 of 64

|

July 2005

ADSP-BF536/BF537

Preliminary Technical Data

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios:

Table 8. Booting Modes

BMODE2–0

100

Description

Boot from SPI host (slave mode)

101

Boot from serial TWI memory

(EEPROM/flash)

110

111

Boot from TWI host (slave mode)

Boot from UART host (slave mode)

Table 6. Example System Clock Ratios

Signal Name Divider Ratio Example Frequency Ratios

The BMODE pins of the Reset Configuration Register, sampled

during power-on resets and software-initiated resets, imple-

ment the following modes:

SSEL3–0

VCO/SCLK

(MHz)

VCO

100

SCLK

100

50

0001

0110

1010

1:1

• Execute from 16-bit external memory – Execution starts

from address 0x2000 0000 with 16-bit packing. The Boot

ROM is bypassed in this mode. All configuration settings

are set for the slowest device possible (3-cycle hold time;

15-cycle R/W access times; 4-cycle setup).

6:1

300

10:1

500

50

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f_SCLK. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

• Boot from 8-bit and 16-bit external flash memory – The

8-bit or 16-bit flash boot routine located in Boot ROM

memory space is set up using Asynchronous Memory Bank

0. All configuration settings are set for the slowest device

possible (3-cycle hold time; 15-cycle R/W access times;

4-cycle setup). The Boot ROM evaluates the first byte of the

boot stream at address 0x2000 0000. If it is 0x40, 8-bit boot

is performed. A 0x60 byte assumes a 16-bit memory device

and performs 8-bit DMA. A 0x20 byte also assumes 16-bit

memory but performs 16-bit DMA.

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

Table 7. Core Clock Ratios

• Boot from serial SPI memory (EEPROM or flash). Eight-,

16-, or 24-bit addressable devices are supported as well as

AT45DB041, AT45DB081, AT45DB161, AT45DB321,

AT45DB642, and AT45DB1282 DataFlash^®devices from

Atmel. The SPI uses the PF10/SPI SSEL1 output pin to

select a single SPI EEPROM/flash device, submits a read

command and successive address bytes (0x00) until a valid

8-, 16-, or 24-bit, or Atmel addressable device is detected,

and begins clocking data into the processor.

Signal Name Divider Ratio Example Frequency Ratios

CSEL1–0

VCO/CCLK

VCO

300

500

200

CCLK

300

150

125

25

00

01

10

11

1:1

2:1

4:1

8:1

The maximum CCLK frequency not only depends on the part's

speed grade (see page 64), it also depends on the applied V_DDINT

voltage. See Table 10 - Table 13 for details. The maximal system

clock rate (SCLK) depends on the chip package and the applied

• Boot from SPI host device – The Blackfin processor oper-

ates in SPI slave mode and is configured to receive the bytes

of the .LDR file from an SPI host (master) agent. To hold

off the host device from transmitting while the Boot ROM

is busy, the Blackfin processor will assert a GPIO pin, called

host wait (HWAIT), to signal the host device not to send

any more bytes until the flag is de-asserted. The flag is cho-

sen by the user and this information will be transferred to

the Blackfin processor via bits 10:5 of the FLAG header.

V_DDEXTvoltage (see Table 15).

BOOTING MODES

The ADSP-BF536/BF537 processor has six mechanisms (listed

in Table 8) for automatically loading internal and external

memory after a reset. A seventh mode is provided to execute

from external memory, bypassing the boot sequence.

• Boot from UART – Using an autobaud handshake

sequence, a boot-stream-formatted program is downloaded

by the Host. The Host agent selects a baud rate within the

UART’s clocking capabilities. When performing the auto-

baud, the UART expects a “@” (boot stream) character

(eight bits data, one start bit, one stop bit, no parity bit) on

the RXD pin to determine the bit rate. It then replies with

an acknowledgement which is composed of 4 bytes: 0xBF,

the value of UART_DLL, the value of UART_DLH, 0x00.

Table 8. Booting Modes

BMODE2–0

Description

000

Execute from 16-bit external memory

(Bypass Boot ROM)

001

Boot from 8-bit or 16-bit memory

(EPROM/flash)

010

011

Reserved

Boot from serial SPI memory (EEPROM/flash)

Rev. PrE

|

Page 16 of 64

|

July 2005

Preliminary Technical Data

ADSP-BF536/BF537

The Host can then download the boot stream. When the

processor needs to hold off the Host, it de-asserts CTS.

Therefore, the Host must monitor this signal.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

• Boot from serial TWI memory (EEPROM/flash) – The

Blackfin processor operates in master mode and selects the

TWI slave with the unique id 0xA0. It submits successive

read commands to the memory device starting at two byte

internal address 0x0000 and begins clocking data into the

processor. The TWI memory device should comply with

Philips I²C Bus Specification version 2.1 and have the capa-

bility to auto-increment its internal address counter such

that the contents of the memory device can be read

sequentially.

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

• Boot from TWI Host – The TWI Host agent selects the

slave with the unique id 0x5F. The processor replies with an

acknowledgement and the Host can then download the

boot stream. The TWI Host agent should comply with

Philips I²C Bus Specification version 2.1. An I²C multi-

plexer can be used to select one processor at a time when

booting multiple processors from a single TWI.

• Code density enhancements, which include intermixing of

16- and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded in

16 bits.

DEVELOPMENT TOOLS

For each of the boot modes, a 10-byte header is first brought in

from an external device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the start of L1 instruction SRAM.

The ADSP-BF536/BF537 processor is supported with a com-

plete set of CROSSCORE® software and hardware development

tools, including Analog Devices emulators and VisualDSP++®

development environment. The same emulator hardware that

supports other Blackfin processors also fully emulates the

ADSP-BF536/BF537 processor.

In addition, bit 4 of the Reset Configuration Register can be set

by application code to bypass the normal boot sequence during

a software reset. For this case, the processor jumps directly to

the beginning of L1 instruction memory.

EZ-KIT Lite Evaluation Board

For evaluation of ADSP-BF536/BF537 processors, use the

ADSP-BF537 EZ-KIT Lite board available from Analog Devices.

Order part number ADDS-BF537-EZLITE. The board comes

with on-chip emulation capabilities and is equipped to enable

software development. Multiple daughter cards are available.

To augment the boot modes, a secondary software loader can be

added to provide additional booting mechanisms. This second-

ary loader could provide the capability to boot from flash,

variable baud rate, and other sources. In all boot modes except

Bypass, program execution starts from on-chip L1 memory

address 0xFFA0 0000.

DESIGNING AN EMULATOR-COMPATIBLE

PROCESSOR BOARD (TARGET)

The Analog Devices family of emulators are tools that every sys-

tem developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG processor. The emulator

uses the TAP to access the internal features of the processor,

allowing the developer to load code, set breakpoints, observe

variables, observe memory, and examine registers. The proces-

sor must be halted to send data and commands, but once an

operation has been completed by the emulator, the processor

system is set running at full speed with no impact on system

timing.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see Analog Devices JTAG Emulation Technical Reference

Rev. PrE

|

Page 17 of 64 | July 2005

ADSP-BF536/BF537

Preliminary Technical Data

(EE-68) on the Analog Devices web site under

www.analog.com/ee-notes. This document is updated regularly

to keep pace with improvements to emulator support.


型号：	ADSP-BF536BBCZ-4B1
厂家：	ADI
描述：	IC 16-BIT, 40 MHz, OTHER DSP, PBGA208, LEAD FREE, MO-205AM, MBGA-208, Digital Signal Processor 时钟外围集成电路
文件：	总64页 (文件大小：3577K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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