ADSP-BF531_06_技术文档

Blackfin^®

Embedded Processor

a

ADSP-BF531/ADSP-BF532

External memory controller with glueless support for

SDRAM, SRAM, FLASH, and ROM

Flexible memory booting options from SPI^®and

external memory

FEATURES

Up to 400 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

PERIPHERALS

RISC-like register and instruction model for ease of pro-

gramming and compiler-friendly support

Advanced debug, trace, and performance monitoring

0.8 V to 1.2 V core V_DDwith on-chip voltage regulation

1.8 V, 2.5 V, and 3.3 V compliant I/O

Parallel peripheral interface PPI/GPIO, supporting

ITU-R 656 video data formats

Two dual-channel, full duplex synchronous serial ports, sup-

porting eight stereo I²S channels

12-channel DMA controller

160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead

LQFP packages

SPI-compatible port

Three timer/counters with PWM support

UART with support for IrDA^®

Event handler

Real-time clock

Watchdog timer

Debug/JTAG interface

On-chip PLL capable of 0.5

؋

to 64

؋

frequency multiplication

Core timer

MEMORY

Up to 84K bytes of on-chip memory:

16K bytes of instruction SRAM/Cache

32K bytes of instruction SRAM

32K bytes of data SRAM/Cache

4K bytes of scratchpad SRAM

Two dual-channel memory DMA controllers

Memory management unit providing memory protection

EVENT

CONTROLLER/

CORE TIMER

JTAG TEST AND

EMULATION

WATCHDOG TIMER

REAL-TIME CLOCK

VOLTAGE

REGULATOR

B

UART PORT

IrDA

L1

DATA

MMU

INSTRUCTION

MEMORY

TIMER0, TIMER1,

TIMER2

CORE/SYSTEM BUS INTERFACE

PPI / GPIO

DMA

CONTROLLER

SERIAL PORTS (2)

SPI PORT

BOOT ROM

EXTERNAL PORT

FLASH, SDRAM

CONTROL

Figure 1. Functional Block Diagram

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADSP-BF531/ADSP-BF532

TABLE OF CONTENTS

General Description ................................................. 4

Portable Low Power Architecture ............................. 4

System Integration ................................................ 4

ADSP-BF531/ADSP-BF532 Processor Peripherals ........ 4

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 9

Watchdog Timer .................................................. 9

Timers ............................................................. 10

Serial Ports (SPORTs) .......................................... 10

Serial Peripheral Interface (SPI) Port ....................... 10

UART Port ........................................................ 10

Programmable Flags (PFx) .................................... 11

Parallel Peripheral Interface ................................... 11

Dynamic Power Management ................................ 12

Voltage Regulation .............................................. 13

Clock Signals ..................................................... 13

Booting Modes ................................................... 14

Instruction Set Description ................................... 14

Development Tools ............................................. 15

Designing an Emulator-Compatible Processor Board .. 16

Related Documents ............................................. 16

Pin Descriptions .................................................... 17

Specifications ........................................................ 20

Operating Conditions .......................................... 20

Electrical Characteristics ....................................... 21

Absolute Maximum Ratings .................................. 22

Package Information ........................................... 22

ESD Sensitivity ................................................... 22

Timing Specifications .......................................... 23

Clock and Reset Timing .................................... 24

Asynchronous Memory Read Cycle Timing ........... 25

Asynchronous Memory Write Cycle Timing .......... 26

SDRAM Interface Timing .................................. 27

External Port Bus Request and Grant Cycle Timing .. 28

Parallel Peripheral Interface Timing ..................... 29

Serial Ports ..................................................... 32

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing ...... 39

Programmable Flags Cycle Timing ....................... 40

Timer Cycle Timing .......................................... 41

JTAG Test and Emulation Port Timing .................. 42

Output Drive Currents ......................................... 43

Power Dissipation ............................................... 45

Test Conditions .................................................. 45

Environmental Conditions .................................... 48

160-Ball BGA Pinout ............................................... 50

169-Ball PBGA Pinout ............................................. 53

176-Lead LQFP Pinout ............................................ 56

Outline Dimensions ................................................ 58

Ordering Guide ..................................................... 60

Serial Peripheral Interface (SPI) Port

—Master Timing .......................................... 37

Serial Peripheral Interface (SPI) Port

—Slave Timing ............................................. 38

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ADSP-BF531/ADSP-BF532

REVISION HISTORY

8/06—Revision D: Changed from Rev. C to Rev. D

Added 1.8 V I/O to Features ....................................... 1

Changed Text in Figure External Components for RTC .... 9

Added Text to Serial Ports (SPORTs) ........................... 10

Changed Font in Formula in Power Savings .................. 12

Minor Edit to Figure Voltage Regulator Circuit .............. 13

Complete Rewrite of Operating Conditions ................... 20

Complete Rewrite of Electrical Characteristics ............... 21

Added 1.8 V and 125°C Specifications

to Multiple Tables of Timing Specifications .................. 23

Edit to Asynchronous Memory Read Cycle Timing ......... 25

Edit to Asynchronous Memory Write Cycle Timing ........ 26

Changed Data in SDRAM Interface Timing .................. 27

Changed Data in Parallel Peripheral Interface Timing ...... 29

Changed Data in Serial Ports ..................................... 32

Deleted References to Temperature in Figures

in Output Drive Currents ......................................... 43

Added 1.8 V Data to Output Drive Currents .................. 43

Moved Data to Operating Conditions

and Rewrote Power Dissipation ................................. 45

Deleted References to Temperature in Figures

in Test Conditions .................................................. 45

Added 1.8 V References in Test Conditions ................... 45

Added 1.8 V Characterization Data Capacitive Loading ... 45

Changed Thermal Characteristics for BC-160 Package ..... 49

Added Models to Ordering Guide ............................... 60

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ADSP-BF531/ADSP-BF532

GENERAL DESCRIPTION

The ADSP-BF531/ADSP-BF532 processors are members of the

Blackfin family of products, incorporating the Analog Devices/

Intel Micro Signal Architecture (MSA). Blackfin processors

combine a dual-MAC state-of-the-art signal processing engine,

the advantages of a clean, orthogonal RISC-like microprocessor

instruction set, and single instruction, multiple data (SIMD)

multimedia capabilities into a single instruction set architecture.

ADSP-BF531/ADSP-BF532 PROCESSOR

PERIPHERALS

The ADSP-BF531/ADSP-BF532 processor contains a rich set of

peripherals connected to the core via several high bandwidth

buses, providing flexibility in system configuration as well as

excellent overall system performance (see the functional block

diagram in Figure 1 on Page 1). The general-purpose peripher-

als include functions such as UART, timers with PWM (pulse-

width modulation) and pulse measurement capability, general-

purpose flag I/O pins, a real-time clock, and a watchdog timer.

This set of functions satisfies a wide variety of typical system

support needs and is augmented by the system expansion capa-

bilities of the part. In addition to these general-purpose

The Blackfin processors are completely code and pin compati-

ble, differing only with respect to their performance and on-

chip memory. Specific performance and memory configura-

tions are shown in Table 1.

Table 1. Processor Comparison

peripherals, the ADSP-BF531/ADSP-BF532 processor contains

high speed serial and parallel ports for interfacing to a variety of

audio, video, and modem codec functions; an interrupt control-

ler for flexible management of interrupts from the on-chip

peripherals or external sources; and power management control

functions to tailor the performance and power characteristics of

the processor and system to many application scenarios.

ADSP-BF531

ADSP-BF532

Maximum Performance 400 MHz 800 MMACs 400 MHz 800 MMACs

Instruction

SRAM/Cache

16K bytes

Instruction SRAM

16K bytes

32K bytes

Data

SRAM/Cache

All of the peripherals, except for general-purpose I/O, real-time

clock, and timers, are supported by a flexible DMA structure.

There is also a separate memory DMA channel dedicated to

data transfers between the processor’s various memory spaces,

including external SDRAM and asynchronous memory. Multi-

ple on-chip buses running at up to 133 MHz provide enough

bandwidth to keep the processor core running along with activ-

ity on all of the on-chip and external peripherals.

Scratchpad

4K bytes

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next generation applications that require RISC-like program-

mability, multimedia support, and leading-edge signal

processing in one integrated package.

The ADSP-BF531/ADSP-BF532 processor includes an on-chip

voltage regulator in support of the ADSP-BF531/ADSP-BF532

processor dynamic power management capability. The voltage

regulator provides a range of core voltage levels from a single

2.25 V to 3.6 V input. The voltage regulator can be bypassed at

the user’s discretion.

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. Blackfin processors are designed in a low

power and low voltage design methodology and feature

dynamic power management—the ability to vary both the volt-

age and frequency of operation to significantly lower overall

power consumption. Varying the voltage and frequency can

result in a substantial reduction in power consumption, com-

pared with just varying the frequency of operation. This

translates into longer battery life for portable appliances.

BLACKFIN PROCESSOR CORE

As shown in Figure 2 on Page 6, the Blackfin processor core

contains two 16-bit multipliers, two 40-bit accumulators, two

40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-

tation units process 8-bit, 16-bit, or 32-bit data from the

register file.

SYSTEM INTEGRATION

The ADSP-BF531/ADSP-BF532 processors are highly inte-

grated system-on-a-chip solutions for the next generation of

digital communication and consumer multimedia applications.

By combining industry-standard interfaces with a high perfor-

mance signal processing core, users can develop cost-effective

solutions quickly without the need for costly external compo-

nents. The system peripherals include a UART port, an SPI port,

two serial ports (SPORTs), four general-purpose timers (three

with PWM capability), a real-time clock, a watchdog timer, and

a parallel peripheral interface.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation are

supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and

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ADSP-BF531/ADSP-BF532

population count, modulo 2³²multiply, divide primitives, satu-

ration and rounding, and sign/exponent detection. The set of

video instructions includes byte alignment and packing opera-

tions, 16-bit and 8-bit adds with clipping, 8-bit average

operations, and 8-bit subtract/absolute value/accumulate (SAA)

operations. Also provided are the compare/select and vector

search instructions.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF531/ADSP-BF532 processor views memory as a

single unified 4G byte address space, using 32-bit addresses. All

resources, including internal memory, external memory, and

I/O control registers, occupy separate sections of this common

address space. The memory portions of this address space are

arranged in a hierarchical structure to provide a good cost/per-

formance balance of some very fast, low latency on-chip

memory as cache or SRAM, and larger, lower cost and perfor-

mance off-chip memory systems. See Figure 3 on Page 7, and

Figure 4 on Page 7.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). By also using the second

ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

The L1 memory system is the primary highest performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the external bus interface unit

(EBIU), provides expansion with SDRAM, flash memory, and

SRAM, optionally accessing up to 132M bytes of

physical memory.

The memory DMA controller provides high bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal memory and the external

memory spaces.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

Internal (On-Chip) Memory

The ADSP-BF531/ADSP-BF532 processor has three blocks of

on-chip memory providing high bandwidth access to the core.

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

The first is the L1 instruction memory, consisting of up to

48K bytes SRAM, of which 16K bytes can be configured as a

four way set-associative cache. This memory is accessed at full

processor speed.

The second on-chip memory block is the L1 data memory, con-

sisting of one bank of 32K bytes. The memory bank is

configurable, offering both cache and SRAM functionality. This

memory block is accessed at full processor speed.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

The third memory block is a 4K byte scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

External (Off-Chip) Memory

The external bus interface can be used with both asynchronous

devices such as SRAM, FLASH, EEPROM, ROM, and I/O

devices, and synchronous devices such as SDRAMs. The bus

width is always 16 bits. A1 is the least significant address of a

16-bit word. 8-bit peripherals should be addressed as if they

were 16-bit devices, where only the lower eight bits of data

should be used.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

The PC133-compliant SDRAM controller can be programmed

to interface to up to 128M bytes of SDRAM. The SDRAM con-

troller allows one row to be open for each internal SDRAM

bank, for up to four internal SDRAM banks, improving overall

system performance.

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ADSP-BF531/ADSP-BF532

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

P3

P2

P1

P0

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

DAG0

DA1

DA0

32

PREG

32

RAB

SD

LD1

LD0

32

ASTAT

32

SEQUENCER

R7.H

R7.L

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R6.L

R5.L

R4.L

R3.L

R2.L

R1.H

R0.L

ALIGN

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks will only be contiguous if each is fully popu-

lated with 1M byte of memory.

boot from boot ROM memory space, the processor starts exe-

cuting from the on-chip boot ROM. For more information, see

Booting Modes on Page 14.

Event Handling

The event controller on the ADSP-BF531/ADSP-BF532 proces-

sor handles all asynchronous and synchronous events to the

processor. The ADSP-BF531/ADSP-BF532 processor provides

event handling that supports both nesting and prioritization.

Nesting allows multiple event service routines to be active

simultaneously. Prioritization ensures that servicing of a higher

priority event takes precedence over servicing of a lower priority

event. The controller provides support for five different types

of events:

I/O Memory Space

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space.

On-chip I/O devices have their control registers mapped into

memory mapped registers (MMRs) at addresses near the top of

the 4G byte address space. These are separated into two smaller

blocks, one of which contains the control MMRs for all core

functions, and the other of which contains the registers needed

for setup and control of the on-chip peripherals outside of the

core. The MMRs are accessible only in supervisor mode and

appear as reserved space to on-chip peripherals.

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

Booting

• Nonmaskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

The ADSP-BF531/ADSP-BF532 processor contains a small boot

kernel, which configures the appropriate peripheral for booting.

If the ADSP-BF531/ADSP-BF532 processor is configured to

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ADSP-BF531/ADSP-BF532

• Exceptions – Events that occur synchronously to program

flow (i.e., the exception will be taken before the instruction

is allowed to complete). Conditions such as data alignment

violations and undefined instructions cause exceptions.

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM/CACHE (16K BYTE)

INSTRUCTION SRAM (32K BYTE)

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

0xFFA1 0000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

RESERVED

The ADSP-BF531/ADSP-BF532 processor event controller con-

sists of two stages, the core event controller (CEC) and the

system interrupt controller (SIC). The core event controller

works with the system interrupt controller to prioritize and con-

trol all system events. Conceptually, interrupts from the

peripherals enter into the SIC, and are then routed directly into

the general-purpose interrupts of the CEC.

DATA BANK B SRAM/CACHE (16K BYTE)

RESERVED

DATA BANK A SRAM/CACHE (16K BYTE)

RESERVED

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

RESERVED

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of theADSP-BF531/ADSP-BF532 pro-

cessor. Table 2 describes the inputs to the CEC, identifies their

names in the event vector table (EVT), and lists their priorities.

SDRAM MEMORY (16M BYTE TO 128M BYTE)

Figure 3. ADSP-BF532 Internal/External Memory Map

0xFFFF FFFF

Table 2. Core Event Controller (CEC)

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

Priority

(0 is Highest)

Event Class

Emulation/Test Control EMU

Reset RST

Nonmaskable Interrupt NMI

EVT Entry

SCRATCHPAD SRAM (4K BYTE)

RESERVED

0

1

INSTRUCTION SRAM/CACHE (16K BYTE)

RESERVED

2

0xFFA1 0000

0xFFA0 C000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

3

Exception

EVX

INSTRUCTION SRAM (16K BYTE)

RESERVED

4

Reserved

5

Hardware Error

IVHW

IVTMR

IVG7

RESERVED

6

Core Timer

RESERVED

7

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

RESERVED

8

IVG8

DATA BANK A SRAM/CACHE (16K BYTE)

9

IVG9

RESERVED

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

RESERVED

System Interrupt Controller (SIC)

SDRAM MEMORY (16M BYTE TO 128M BYTE)

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Figure 4. ADSP-BF531 Internal/External Memory Map

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ADSP-BF531/ADSP-BF532

Although the ADSP-BF531/ADSP-BF532 processor provides a

default mapping, the user can alter the mappings and priorities

of interrupt events by writing the appropriate values into the

interrupt assignment registers (IAR). Table 3 describes the

inputs into the SIC and the default mappings into the CEC.

preventing the processor from servicing the event even

though the event may be latched in the ILAT register. This

register may be read or written while in supervisor mode.

(Note that general-purpose interrupts can be globally

enabled and disabled with the STI and CLI instructions,

respectively.)

Table 3. System Interrupt Controller (SIC)

• CEC interrupt pending register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

Peripheral Interrupt Event

PLL Wakeup

Default Mapping

IVG7

DMA Error

IVG7

PPI Error

IVG7

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 3.

SPORT 0 Error

IVG7

SPORT 1 Error

IVG7

SPI Error

IVG7

• SIC interrupt mask register (SIC_IMASK) – This register

controls the masking and unmasking of each peripheral

interrupt event. When a bit is set in the register, that

peripheral event is unmasked and will be processed by the

system when asserted. A cleared bit in the register masks

the peripheral event, preventing the processor from servic-

ing the event.

UART Error

IVG7

Real-Time Clock

IVG8

DMA Channel 0 (PPI)

DMA Channel 1 (SPORT 0 Receive)

DMA Channel 2 (SPORT 0 Transmit)

DMA Channel 3 (SPORT 1 Receive)

DMA Channel 4 (SPORT 1 Transmit)

DMA Channel 5 (SPI)

DMA Channel 6 (UART Receive)

DMA Channel 7 (UART Transmit)

Timer 0

IVG8

IVG9

• SIC interrupt status register (SIC_ISR) – As multiple

peripherals can be mapped to a single event, this register

allows the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

IVG10

IVG11

IVG12

IVG13

Timer 1

• SIC interrupt wakeup enable register (SIC_IWR) – By

enabling the corresponding bit in this register, a peripheral

can be configured to wake up the processor, should the

core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 12.)

Timer 2

PF Interrupt A

PF Interrupt B

DMA Channels 8 and 9

(Memory DMA Stream 1)

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

DMA Channels 10 and 11

(Memory DMA Stream 0)

IVG13

Software Watchdog Timer

Event Control

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC will recognize and queue the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

The ADSP-BF531/ADSP-BF532 processor provides the user

with a very flexible mechanism to control the processing of

events. In the CEC, three registers are used to coordinate and

control events. Each register is 16 bits wide:

• CEC interrupt latch register (ILAT) – The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

it may be written only when its corresponding IMASK bit

is cleared.

DMA CONTROLLERS

The ADSP-BF531/ADSP-BF532 processor has multiple, inde-

pendent DMA controllers that support automated data transfers

with minimal overhead for the processor core. DMA transfers

can occur between the ADSP-BF531/ADSP-BF532 processor’s

internal memories and any of its DMA-capable peripherals.

• CEC interrupt mask register (IMASK) – The IMASK regis-

ter controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and will be processed by the CEC when asserted.

A cleared bit in the IMASK register masks the event,

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ADSP-BF531/ADSP-BF532

Additionally, DMA transfers can be accomplished between any

of the DMA-capable peripherals and external devices connected

to the external memory interfaces, including the SDRAM

controller and the asynchronous memory controller. DMA-

capable peripherals include the SPORTs, SPI port, UART, and

PPI. Each individual DMA-capable peripheral has at least one

dedicated DMA channel.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day. The second alarm is for a day and time of

that day.

The stopwatch function counts down from a programmed

value, with one second resolution. When the stopwatch is

enabled and the counter underflows, an interrupt is generated.

The ADSP-BF531/ADSP-BF532 processor DMA controller

supports both 1-dimensional (1-D) and 2-dimensional (2-D)

DMA transfers. DMA transfer initialization can be imple-

mented from registers or from sets of parameters called

descriptor blocks.

Like other peripherals, the RTC can wake up the processor from

sleep mode upon generation of any RTC wakeup event.

Additionally, an RTC wakeup event can wake up the processor

from deep sleep mode, and wake up the on-chip internal voltage

regulator from a powered-down state.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be

de-interleaved on the fly.

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 5.

RTXI

RTXO

R1

X1

Examples of DMA types supported by the ADSP-BF531/

ADSP-BF532 processor DMA controller include:

• A single, linear buffer that stops upon completion

C1

C2

• A circular, autorefreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

SUGGESTED COMPONENTS:

X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)

C1 = 22 pF

C2 = 22 pF

R1 = 10 MΩ

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels provided for transfers between the

various memories of the ADSP-BF531/ADSP-BF532 processor

system. This enables transfers of blocks of data between any of

the memories—including external SDRAM, ROM, SRAM, and

flash memory—with minimal processor intervention. Memory

DMA transfers can be controlled by a very flexible descriptor-

based methodology or by a standard register-based autobuffer

mechanism.

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

Figure 5. External Components for RTC

WATCHDOG TIMER

The ADSP-BF531/ADSP-BF532 processor includes a 32-bit

timer that can be used to implement a software watchdog func-

tion. A software watchdog can improve system availability by

forcing the processor to a known state through generation of a

hardware reset, nonmaskable interrupt (NMI), or general-pur-

pose interrupt, if the timer expires before being reset by

software. The programmer initializes the count value of the

timer, enables the appropriate interrupt, then enables the timer.

Thereafter, the software must reload the counter before it

counts to zero from the programmed value. This protects the

system from remaining in an unknown state where software,

which would normally reset the timer, has stopped running due

to an external noise condition or software error.

REAL-TIME CLOCK

The ADSP-BF531/ADSP-BF532 processor real-time clock

(RTC) provides a robust set of digital watch features, including

current time, stopwatch, and alarm. The RTC is clocked by a

32.768 kHz crystal external to the ADSP-BF531/ADSP-BF532

processor. The RTC peripheral has dedicated power supply pins

so that it can remain powered up and clocked even when the

rest of the processor is in a low power state. The RTC provides

several programmable interrupt options, including interrupt

per second, minute, hour, or day clock ticks, interrupt on pro-

grammable stopwatch countdown, or interrupt at a

If configured to generate a hardware reset, the watchdog timer

resets both the core and the ADSP-BF531/ADSP-BF532 proces-

sor peripherals. After a reset, software can determine if the

watchdog was the source of the hardware reset by interrogating

a status bit in the watchdog timer control register.

programmed alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60 second counter, a 60 minute counter, a 24

hour counter, and a 32,768 day counter.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f_SCLK

.

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ADSP-BF531/ADSP-BF532

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data-word or

after transferring an entire data buffer or buffers

through DMA.

TIMERS

There are four general-purpose programmable timer units in

the ADSP-BF531/ADSP-BF532 processor. Three timers have an

external pin that can be configured either as a pulse-width mod-

ulator (PWM) or timer output, as an input to clock the timer, or

as a mechanism for measuring pulse widths and periods of

external events. These timers can be synchronized to an external

clock input to the PF1 pin, an external clock input to the

PPI_CLK pin, or to the internal SCLK.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1,024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

An additional 250 mV of SPORT input hysteresis can be

enabled by setting Bit 15 of the PLL_CTL register. When this bit

is set, all SPORT input pins have the increased hysteresis.

The timer units can be used in conjunction with the UART to

measure the width of the pulses in the data stream to provide an

autobaud detect function for a serial channel.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The ADSP-BF531/ADSP-BF532 processor has an SPI-compati-

ble port that enables the processor to communicate with

multiple SPI-compatible devices.

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

The SPI interface uses three pins for transferring data: two data

pins (master output-slave input, MOSI, and master input-slave

output, MISO) and a clock pin (serial clock, SCK). An SPI chip

select input pin (SPISS) lets other SPI devices select the proces-

sor, and seven SPI chip select output pins (SPISEL7–1) let the

processor select other SPI devices. The SPI select pins are recon-

figured programmable flag pins. Using these pins, the SPI port

provides a full-duplex, synchronous serial interface which sup-

ports both master/slave modes and multimaster environments.

In addition to the three general-purpose programmable timers,

a fourth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTs)

The ADSP-BF531/ADSP-BF532 processor incorporates two

dual-channel synchronous serial ports (SPORT0 and SPORT1)

for serial and multiprocessor communications. The SPORTs

support the following features:

The baud rate and clock phase/polarities for the SPI port are

programmable, and it has an integrated DMA controller, con-

figurable to support transmit or receive data streams. The SPI

DMA controller can only service unidirectional accesses at any

given time.

• I²S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I²S stereo audio.

The SPI port clock rate is calculated as:

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

f_SCLK

SPI Clock Rate = --------------------------------

2 × SPI_Baud

Where the 16-bit SPI_Baud register contains a value of 2 to

65,535.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

• Word length – Each SPORT supports serial data words

from 3 bits to 32 bits in length, transferred most-signifi-

cant-bit first or least-significant-bit first.

UART PORT

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

The ADSP-BF531/ADSP-BF532 processor provides a full-

duplex universal asynchronous receiver/transmitter (UART)

port, which is fully compatible with PC-standard UARTs. The

UART port provides a simplified UART interface to other

peripherals or hosts, supporting full-duplex, DMA-supported,

asynchronous transfers of serial data. The UART port includes

support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and

none, even, or odd parity. The UART port supports two modes

of operation:

• Companding in hardware – Each SPORT can perform

A-law or µ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without additional

latencies.

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

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ADSP-BF531/ADSP-BF532

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

inputs can be configured to generate hardware interrupts,

while output PFx pins can be triggered by software

interrupts.

• Flag interrupt sensitivity registers – The two flag interrupt

sensitivity registers specify whether individual PFx pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

The baud rate, serial data format, error code generation and sta-

tus, and interrupts for the UART port are programmable.

The UART programmable features include:

• Supporting bit rates ranging from (f_SCLK/1,048,576) bits per

second to (f_SCLK/16) bits per second.

• Supporting data formats from seven bits to 12 bits per

frame.

PARALLEL PERIPHERAL INTERFACE

The processor provides a parallel peripheral interface (PPI) that

can connect directly to parallel A/D and D/A converters,

ITU-R 601/656 video encoders and decoders, and other general-

purpose peripherals. The PPI consists of a dedicated input clock

pin, up to three frame synchronization pins, and up to 16 data

pins. The input clock supports parallel data rates up to half the

system clock rate.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

f_SCLK

UART Clock Rate = -----------------------------------------------

16 × UART_Divisor

Where the 16-bit UART_Divisor comes from the DLH register

(most significant 8 bits) and DLL register (least significant

8 bits).

In ITU-R 656 modes, the PPI receives and parses a data stream

of 8-bit or 10-bit data elements. On-chip decode of embedded

preamble control and synchronization information is

supported.

In conjunction with the general-purpose timer functions,

autobaud detection is supported.

Three distinct ITU-R 656 modes are supported:

The capabilities of the UART are further extended with support

for the Infrared Data Association (IrDA) serial infrared physical

layer link specification (SIR) protocol.

• Active video only – The PPI does not read in any data

between the end of active video (EAV) and start of active

video (SAV) preamble symbols, or any data present during

the vertical blanking intervals. In this mode, the control

byte sequences are not stored to memory; they are filtered

by the PPI.

PROGRAMMABLE FLAGS (PFx)

The ADSP-BF531/ADSP-BF532 processor has 16 bidirectional,

general-purpose programmable flag (PF15–0) pins. Each pro-

grammable flag can be individually controlled by manipulation

of the flag control, status and interrupt registers:

• Vertical blanking only – The PPI only transfers vertical

blanking interval (VBI) data, as well as horizontal blanking

information and control byte sequences on VBI lines.

• Flag direction control register – Specifies the direction of

each individual PFx pin as input or output.

• Entire field – The entire incoming bitstream is read in

through the PPI. This includes active video, control pream-

ble sequences, and ancillary data that may be embedded in

horizontal and vertical blanking intervals.

• Flag control and status registers – The ADSP-BF531/

ADSP-BF532 processor employs a “write one to modify”

mechanism that allows any combination of individual flags

to be modified in a single instruction, without affecting the

level of any other flags. Four control registers are provided.

One register is written in order to set flag values, one regis-

ter is written in order to clear flag values, one register is

written in order to toggle flag values, and one register is

written in order to specify a flag value. Reading the flag sta-

tus register allows software to interrogate the sense of the

flags.

Though not explicitly supported, ITU-R 656 output functional-

ity can be achieved by setting up the entire frame structure

(including active video, blanking, and control information) in

memory and streaming the data out the PPI in a frame sync-less

mode. The processor’s 2-D DMA features facilitate this transfer

by allowing the static frame buffer (blanking and control codes)

to be placed in memory once, and simply updating the active

video information on a per-frame basis.

• Flag interrupt mask registers – The two flag interrupt mask

registers allow each individual PFx pin to function as an

interrupt to the processor. Similar to the two flag control

registers that are used to set and clear individual flag values,

one flag interrupt mask register sets bits to enable interrupt

function, and the other flag interrupt mask register clears

bits to disable interrupt function. PFx pins defined as

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications. The

modes are divided into four main categories, each allowing up

to 16 bits of data transfer per PPI_CLK cycle:

• Data receive with internally generated frame syncs

• Data receive with externally generated frame syncs

• Data transmit with internally generated frame syncs

• Data transmit with externally generated frame syncs

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ADSP-BF531/ADSP-BF532

These modes support ADC/DAC connections, as well as video

communication with hardware signaling. Many of the modes

support more than one level of frame synchronization. If

desired, a programmable delay can be inserted between asser-

tion of a frame sync and reception/transmission of data.

Hibernate Operating Mode—Maximum Static Power

Savings

The hibernate mode maximizes static power savings by dis-

abling the voltage and clocks to the processor core (CCLK) and

to all the synchronous peripherals (SCLK). The internal voltage

regulator for the processor can be shut off by writing b#00 to

the FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V_DDINT) to 0 V to provide the lowest static power dissipation.

Any critical information stored internally (memory contents,

register contents, etc.) must be written to a nonvolatile storage

device prior to removing power if the processor state is to be

preserved. Since V_DDEXTis still supplied in this mode, all of the

external pins three-state, unless otherwise specified. This allows

other devices that may be connected to the processor to have

power still applied without drawing unwanted current. The

internal supply regulator can be woken up either by a real-time

clock wakeup or by asserting the RESET pin.

DYNAMIC POWER MANAGEMENT

The ADSP-BF531/ADSP-BF532 processor provides five operat-

ing modes, each with a different performance/power profile. In

addition, dynamic power management provides the control

functions to dynamically alter the processor core supply voltage,

further reducing power dissipation. Control of clocking to each

of the ADSP-BF531/ADSP-BF532 processor peripherals also

reduces power consumption. See Table 5 for a summary of the

power settings for each mode.

Table 4. Power Domains

Power Domain

V_DDRange

V_DDINT

All internal logic, except RTC

RTC internal logic and crystal I/O

All other I/O

Sleep Operating Mode—High Dynamic Power Savings

V_DDRTC

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally an external event or RTC activity will wake up the

processor. When in the sleep mode, assertion of wakeup will

cause the processor to sense the value of the BYPASS bit in the

PLL control register (PLL_CTL). If BYPASS is disabled, the pro-

cessor will transition to the full-on mode. If BYPASS is enabled,

the processor will transition to the active mode.

V_DDEXT

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

When in the sleep mode, system DMA access to L1 memory is

not supported.

Active Operating Mode—Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. In this

mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the full-on mode is

entered. DMA access is available to appropriately configured L1

memories.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals,

such as the RTC, may still be running but will not be able to

access internal resources or external memory. This powered-

down mode can only be exited by assertion of the reset interrupt

(RESET) or by an asynchronous interrupt generated by the

RTC. When in deep sleep mode, an RTC asynchronous inter-

rupt causes the processor to transition to the active mode.

Assertion of RESET while in deep sleep mode causes the proces-

sor to transition to the full-on mode.

In the active mode, it is possible to disable the PLL through the

PLL control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the full-on or sleep modes.

Table 5. Power Settings

Core

Clock

System

Clock

PLL

Core

Power Savings

Mode

Full-On

Active

PLL

Bypassed (CCLK) (SCLK)

Power

As shown in Table 4, the ADSP-BF531/ADSP-BF532 processor

supports three different power domains. The use of multiple

power domains maximizes flexibility, while maintaining com-

pliance with industry standards and conventions. By isolating

the internal logic of the ADSP-BF531/ADSP-BF532 processor

into its own power domain, separate from the RTC and other

I/O, the processor can take advantage of dynamic power man-

agement, without affecting the RTC or other I/O devices. There

are no sequencing requirements for the various power domains.

Enabled No

Enabled Enabled On

Enabled/ Yes

Disabled

Enabled Enabled On

Sleep

Enabled

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

Deep Sleep Disabled

Hibernate Disabled

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ADSP-BF531/ADSP-BF532

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

results in a 25% reduction in dynamic power dissipation, while

reducing the voltage by 25% reduces dynamic power dissipation

by more than 40%. Further, these power savings are additive, in

that if the clock frequency and supply voltage are both reduced,

the power savings can be dramatic.

V_{DDEX T}

100µF

2.25V TO 3.6V

INPUT VOLTAGE

RANGE

10µH

V_DDINT

0.1µF

ZHCS1000

FDS9431A

100µF

1µF

The dynamic power management feature of the ADSP-BF531/

ADSP-BF532 processor allows both the processor’s input volt-

age (V_DDINT) and clock frequency (f_CCLK) to be dynamically

controlled.

VR_OUT1–0

EXTERNAL COMPONENT S

The savings in power dissipation can be modeled using the

power savings factor and % power savings calculations.

NOTE: VR_OUT1–0 SHOULD BE TIED TOGETHER EXTERNALLY

AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.

The power savings factor is calculated as:

Figure 6. Voltage Regulator Circuit

power savings factor

If an external clock is used, it must not be halted, changed, or

operated below the specified frequency during normal opera-

tion. This signal is connected to the processor’s CLKIN pin.

When an external clock is used, the XTAL pin must be left

unconnected.

2

f_CCLKRED

---------------------

f_CCLKNOM

V_DDINTRED

--------------------------

V_DDINTNOM

t_RED

----------

t_NOM

⎛

⎝

⎞

⎠

⎛

⎝

⎞

⎠

=

×

where the variables in the equations are:

f

_CCLKNOMis the nominal core clock frequency

_CCLKREDis the reduced core clock frequency

Alternatively, because the ADSP-BF531/ADSP-BF532 processor

includes an on-chip oscillator circuit, an external crystal may be

used. The crystal should be connected across the CLKIN and

XTAL pins, with two capacitors connected as shown in Figure 7.

Capacitor values are dependent on crystal type and should be

specified by the crystal manufacturer. A parallel-resonant,

fundamental frequency, microprocessor-grade crystal should

be used.

f

V

_DDINTNOMis the nominal internal supply voltage

_DDINTREDis the reduced internal supply voltage

t

_NOMis the duration running at f_CCLKNOM

_REDis the duration running at f_CCLKRED

t

The percent power savings is calculated as:

% power savings = (1 – power savings factor) × 100%

VOLTAGE REGULATION

XTAL

CLKOUT

CLKIN

The Blackfin processor provides an on-chip voltage regulator

that can generate processor core voltage levels 0.85 V to 1.2 V

from an external 2.25 V to 3.6 V supply. Figure 6 shows the typ-

ical external components required to complete the power

management system.^†The regulator controls the internal logic

voltage levels and is programmable with the voltage regulator

control register (VR_CTL) in increments of 50 mV. To reduce

standby power consumption, the internal voltage regulator can

be programmed to remove power to the processor core while

keeping I/O power (V_DDEXT) supplied. While in hibernation,

Figure 7. External Crystal Connections

As shown in Figure 8 on Page 14, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a user programmable 0.5× to 64× multipli-

cation factor (bounded by specified minimum and maximum

VCO frequencies). The default multiplier is 10×, but it can be

modified by a software instruction sequence. On-the-fly

frequency changes can be effected by simply writing to the

PLL_DIV register.

V

_DDEXTcan still be applied, eliminating the need for external

buffers. The voltage regulator can be activated from this power-

down state either through an RTC wakeup or by asserting

RESET, which will then initiate a boot sequence. The regulator

can also be disabled and bypassed at the user’s discretion.

CLOCK SIGNALS

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

The ADSP-BF531/ADSP-BF532 processor can be clocked by an

external crystal, a sine wave input, or a buffered, shaped clock

derived from an external clock oscillator.

^†See EE-228: Switching Regulator Design Considerations for Blackfin Processors.

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ADSP-BF531/ADSP-BF532

BOOTING MODES

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

The ADSP-BF531/ADSP-BF532 processor has two mechanisms

(listed in Table 8) for automatically loading internal L1 instruc-

tion memory after a reset. A third mode is provided to execute

from external memory, bypassing the boot sequence.

÷ 1, 2, 4, 8

CCLK

SCLK

PLL

0.5× to 64×

CLKIN

VCO

Table 8. Booting Modes

÷ 1 to 15

BMODE1–0

Description

00

Executefrom16-bitexternalmemory(bypass

boot ROM)

SCLK ≤ CCLK

SCLK ≤ 133 MHz

01

10

11

Boot from 8-bit or 16-bit FLASH

Boot from SPI host slave mode

Figure 8. Frequency Modification Methods

Boot from SPI serial EEPROM (8-, 16-, or 24-bit

address range)

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

The BMODE pins of the reset configuration register, sampled

during power-on resets and software-initiated resets, imple-

ment the following modes:

Table 6. Example System Clock Ratios

• Execute from 16-bit external memory – Execution starts

from address 0x2000 0000 with 16-bit packing. The boot

ROM is bypassed in this mode. All configuration settings

are set for the slowest device possible (3-cycle hold time;

15-cycle R/W access times; 4-cycle setup).

Example Frequency Ratios

(MHz)

VCO

100

Signal Name Divider Ratio

SSEL3–0

VCO/SCLK

SCLK

100

0001

1:1

3:1

0011

400

133

• Boot from 8-bit or 16-bit external flash memory – The flash

boot routine located in boot ROM memory space is set up

using asynchronous memory bank 0. All configuration set-

tings are set for the slowest device possible (3-cycle hold

time; 15-cycle R/W access times; 4-cycle setup).

The maximum frequency of the system clock is f_SCLK. Note that

the divisor ratio must be chosen to limit the system clock fre-

quency to its maximum of f_SCLK. The SSEL value can be changed

dynamically without any PLL lock latencies by writing the

appropriate values to the PLL divisor register (PLL_DIV).

• Boot from SPI serial EEPROM (8-, 16-, or 24-bit

addressable) – The SPI uses the PF2 output pin to select a

single SPI EEPROM device, submits successive read com-

mands at addresses 0x00, 0x0000, and 0x000000 until a

valid 8-, 16-, or 24-bit addressable EEPROM is detected,

and begins clocking data into the beginning of L1 instruc-

tion memory.

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

For each of the boot modes, a 10-byte header is first read from

an external memory device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the start of L1 instruction SRAM.

Table 7. Core Clock Ratios

Example Frequency Ratios

(MHz)

Signal Name Divider Ratio

CSEL1–0

VCO/CCLK

VCO

300

400

200

CCLK

300

150

100

25

00

01

10

11

1:1

2:1

4:1

8:1

In addition, Bit 4 of the reset configuration register can be set by

application code to bypass the normal boot sequence during a

software reset. For this case, the processor jumps directly to the

beginning of L1 instruction memory.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

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ADSP-BF531/ADSP-BF532

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

Statistical profiling enables the programmer to nonintrusively

poll the processor as it is running the program. This feature,

unique to VisualDSP++, enables the software developer to pas-

sively gather important code execution metrics without

interrupting the real-time characteristics of the program. Essen-

tially, the developer can identify bottlenecks in software quickly

and efficiently. By using the profiler, the programmer can focus

on those areas in the program that impact performance and take

corrective action.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• Seamlessly integrated DSP/CPU features are optimized for

both 8-bit and 16-bit operations.

• View mixed C/C++ and assembly code (interleaved source

and object information).

• A multi-issue load/store modified Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• Insert breakpoints.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Set conditional breakpoints on registers, memory,

and stacks.

• Trace instruction execution.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data types; and separate user and

supervisor stack pointers.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded in

16 bits.

• Create custom debugger windows.

The VisualDSP++ IDDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all of the Blackfin develop-

ment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

DEVELOPMENT TOOLS

The ADSP-BF531/ADSP-BF532 processor is supported with a

complete set of CROSSCORE^®^†software and hardware develop-

ment tools, including Analog Devices emulators and

• Control how the development tools process inputs and

generate outputs

VisualDSP++^®^‡development environment. The same emulator

hardware that supports other Blackfin processors also fully

emulates the ADSP-BF531/ADSP-BF532 processor.

• Maintain a one-to-one correspondence with the tool’s

command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to processor assembly. The processor

has architectural features that improve the efficiency of com-

piled C/C++ code.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

VCSE is Analog Devices technology for creating, using, and

reusing software components (independent modules of sub-

stantial functionality) to quickly and reliably assemble software

^†CROSSCORE is a registered trademark of Analog Devices, Inc.

^‡VisualDSP++ is a registered trademark of Analog Devices, Inc.

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ADSP-BF531/ADSP-BF532

applications. Components can be downloaded from the Web

and dropped into the application. Component archives can be

published from within VisualDSP++. VCSE supports compo-

nent implementation in C/C++ or assembly language.

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.


型号：	ADSP-BF531_06
厂家：	ADI
描述：	Blackfin Embedded Processor Blackfin嵌入式处理器
文件：	总60页 (文件大小：3025K)
中文：	中文翻译
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ADSP-BF531_06 [ADI]

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