ADP5080_技术文档

High Efficiency Integrated Power Solution

for Multicell Lithium Ion Applications

Data Sheet

ADP5080

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Wide input voltage range: 4.0 V to 15 V

High efficiency architecture

SCL

SDA

2

I C

OSCILLATOR

INTERFACE

Up to 2 MHz switching frequency

VOLTAGE

ENABLE

FAULT

6 synchronous rectification dc-to-dc converters

Channel 1 buck regulator: 3 A maximum

Channel 2 buck regulator: 1.15 A maximum

Channel 3 buck regulator: 1.5 A maximum

Channel 4 buck regulator: 0.8 A maximum

Channel 5 buck regulator: 2 A maximum

Channel 6 configurable buck or buck boost regulator

2 A maximum for buck regulator configuration

1.5 A maximum for buck boost regulator configuration

Channel 7 high voltage, high performance LDO regulator:

30 mA maximum

CONTROL

LOGIC

REFERENCE

CHARGE

PUMP

LDO1

4V TO 15V

5.0V TO 5.5V, 400mA

3V TO 3.3V, 300mA

0.80V TO 1.20V, 3A

1.0V TO 3.3V, 1.15A

1.2V TO 1.8V/ADJ, 1.5A

1.8V TO 3.55V/ADJ, 0.8A

3.0V TO 5.0V, 2A

LDO2

CH1 BUCK

REGULATOR

4V TO 15V

CH2 BUCK

REGULATOR

CH 3 BUCK

REGULATOR

CH 4 BUCK

REGULATOR

2 low quiescent current keep-alive LDO regulators

LDO1 regulator: 400 mA maximum

LDO2 regulator: 300 mA maximum

CH 5 BUCK

REGULATOR

CH 6

BUCK BOOST

REGULATOR

Control circuit

3.5V TO 5.5V/ADJ

BUCK ONLY: 2A

BUCK BOOST: 1.5A

Charge pump for internal switching driver power supply

I²C-programmable output levels and power sequencing

Package: 72-ball, 4.5 mm × 4.0 mm × 0.6 mm WLCSP

(0.5 mm pitch)

CH7 LDO

REGULATOR

5V TO 25V

5V TO 12V, 30mA

Figure 1.

APPLICATIONS

DSLR cameras

Non-reflex (mirrorless) cameras

Portable instrumentation

GENERAL DESCRIPTION

The ADP5080 is a fully integrated, high efficiency power

solution for multicell lithium ion battery applications. The

device can connect directly to the battery, which eliminates

the need for preregulators and, therefore, increases the battery

life of the system.

All these features help to minimize the number of external

components and PCB space required, providing significant

advantages for portable applications. The switching frequency

is selectable on each channel from 750 kHz to 2 MHz.

Key functions for power applications, such as soft start, selectable

preset output voltage, and flexible power-up and power-down

sequences, are provided on chip and are programmable via the

I²C interface with fused factory defaults. The ADP5080 is available

in a 72-ball WLCSP 0.5 mm pitch package.

The ADP5080 integrates two keep-alive LDO regulators, five

synchronous buck regulators, a configurable four-switch buck

boost regulator, and a high voltage LDO regulator. The ADP5080

is a highly integrated power solution that incorporates all power

MOSFETs, feedback loop compensation, voltage setting resistor

dividers, and discharge switches, as well as a charge pump to

generate a global bootstrap voltage.

Rev. A

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ADP5080

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Channel 7: High Voltage LDO Regulator ............................... 29

Charge Pump .............................................................................. 29

Enabling and Disabling the Output Channels........................ 30

Power-Good Function............................................................... 31

Fault Function............................................................................. 31

Undervoltage Protection (UVP) .............................................. 32

Overvoltage Protection (OVP)................................................. 33

Applications Information.............................................................. 34

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Housekeeping Block Specifications ........................................... 4

DC-to-DC Converter Block Specifications .............................. 5

Linear Regulator Block Specifications....................................... 7

I²C Interface Timing Specifications ........................................... 8

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Application Circuit......................................................................... 18

Theory of Operation ...................................................................... 19

UVLO and POR.......................................................................... 19

Discharge Switch ........................................................................ 19

Keep-Alive LDO Regulators ..................................................... 19

DC-to-DC Converter Channels ............................................... 22

Component Selection for the Buck and Buck Boost

Regulators.................................................................................... 34

Component Selection for the LDO Regulators ...................... 36

PCB Layout Recommendations ............................................... 36

Thermal Considerations............................................................ 37

I²C Interface .................................................................................... 38

SDA and SCL Pins...................................................................... 38

I²C Address.................................................................................. 38

Self-Clearing Register Bits......................................................... 38

I²C Interface Timing Diagrams ................................................ 38

Control Register Information ....................................................... 40

Control Register Map ................................................................ 40

Control Register Details ............................................................ 41

Factory Default Options ................................................................ 61

Outline Dimensions....................................................................... 63

Ordering Guide .......................................................................... 63

Light Load and Other Modes of Operation

for the DC-to-DC Converter Channels .................................. 27

Switching Clock.......................................................................... 28

Soft Start Function ..................................................................... 29

REVISION HISTORY

4/14—Revision A: Initial Version

Rev. A | Page 2 of 64

Data Sheet

ADP5080

SPECIFICATIONS

T_J= 25°C, V_VBATT= 7.2 V, V_VREG1= V_VDRx= 5 V, V _VREG2= V_VDDIO= 3.3 V, unless otherwise noted.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT SUPPLY VOLTAGE RANGE

VBATT

V_VBATT

4.0

15

V

Applies to PVIN1, PVIN2, PVIN3,

PVIN4, PVIN5, and PVIN6

VILDO7

VDDIO

V_VILDO7

V_VDDIO

5

1.6

25

3.6

V

QUIESCENT CURRENT

Operating Quiescent Current

VDDIO

I_{Q (VIN)}

8

0.2

12

11

20

mA

µA

All channels on, nonswitching

V_VDDIO= V_SCL= V_SDA= 3.3 V

Includes LDO1 and LDO2, EN low

I_{Q (VDDIO_OP)}

I_{Q (VBATT_STNBY1)}

I_{Q (VBATT_STNBY2)}

Standby Current

1.25

mA

All channels off, EN high,

SEL_FSW = 1, FREQ_CP = 01

UNDERVOLTAGE LOCKOUT

UVLO Rising Threshold

UVLO Falling Threshold

VBATT UVLO Threshold

Reset Threshold

UVLO

V_{UVLO (R)}

V_{UVLO (F)}

V_{UVLO (BATT)}

V_{UVLO (POR)}

3.45

3.7

3.45

3.3

3.85

3.55

V

At PVIN1

At VBATT, falling

At VREG2, falling

2.4

OSCILLATOR CIRCUIT

Switching Frequency

f_SW

1.98

1.48

2.0

1.5

2.02

1.52

MHz

R_OSC= 100 kΩ, SEL_FSW = 0

R_OSC= 100 kΩ, SEL_FSW = 1

SYNC Pin, Input Clock

Frequency Range

Minimum On Pulse Width

Minimum Off Pulse Width

High Logic

f_SYNC

0.5

100

2.0

MHz

ns

V

R_OSC= 100 kΩ

t_{SYNC_MIN_ON}

t_{SYNC_MIN_OFF}

V_{H (SYNC)}

0.8 × V_VREG2

V_VREG2= 3.3 V, −25°C ≤ T_J≤ +85°C

Low Logic

V_{L (SYNC)}

0.3 × V_VREG2

V

LOGIC INPUTS

EN Pin

High Level Threshold

Low Level Threshold

EN34 Pin

V_{IH (EN)}

V_{IL (EN)}

2.15

V

V_VREG2= 3.3 V, −25°C ≤ T_J≤ +85°C

1.45

High Level Threshold

Low Level Threshold

SCL and SDA Pins

High Level Threshold

Low Level Threshold

LOGIC OUTPUTS

SDA Pin

V_{IH (EN34)}

V_{IL (EN34)}

1.25

V

V_VREG2= 3.3 V, −25°C ≤ T_J≤ +85°C

0.70

V_{IH (I2C)}

V_{IL (I2C)}

0.75 × V_VDDIO

V

V_VDDIO= 3.3 V, −25°C ≤ T_J≤ +85°C

0.3 × V_VDDIO

Low Level Output Voltage

V_{OL (SDA)}

I_{LEAK (SDA)}

V_{OH (CLKO)}

V_{OL (CLKO)}

0.4

V

3.0 mA sink current, −25°C ≤ T_J≤

+85°C

V_SDA= 3.3 V

Leakage Current

CLKO Pin

High Level Output Voltage

10

nA

V_VREG2− 0.4

V

3.0 mA sink current, −25°C ≤ T_J≤

+85°C

3.0 mA sink current, −25°C ≤ T_J≤

+85°C

Low Level Output Voltage

0.4

FAULT Pin

Low Level Output Voltage

V_{OL (}

V

3.0 mA source current, −25°C ≤

T_J≤ +85°C

)

FAULT

Leakage Current

I_{LEAK (}

10

nA

V_FAULT= 3.3 V

)

FAULT

Rev. A | Page 3 of 64

ADP5080

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

POWER GOOD

Rising Threshold

Falling Threshold

OVERVOLTAGE/UNDERVOLTAGE

OVP Threshold

V_{PGOOD (R)}

V_{PGOOD (F)}

83

79

%

Measured at V_OUT

V_OVP

V_UVP

125

65

137

%

Measured at V_OUT

UVP Threshold

48

THERMAL SHUTDOWN

Rising Threshold

Hysteresis

TSD

T_TSD

T_{TSD_HYS}

165

15

°C

HOUSEKEEPING BLOCK SPECIFICATIONS

T_J= 25°C, V_VBATT= 7.2 V, V_VREG1= V_VDRx= 5 V, V _VREG2= V_VDDIO= 3.3 V, unless otherwise noted.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

LDO1

Output Voltage (VREG1 Pin)

Fixed Voltage Range, 1 Bit

Voltage Accuracy

Load Regulation

Line Regulation

Current-Limit Threshold

Dropout Voltage

Input Select Switch

On Resistance

V_VREG1

V_{VREG1 (DEFAULT)}−2

∆V_VREG1/I_VREG1

∆V_VREG1/V_VBATT

I_{LDO1_ILIM}

5.0

5.5

+2

V

%

%/A

%/V

mA

V

V_VBATT= V_VREG1+ 0.5 V, I_VREG1= 10 mA

I_VREG1= 4 mA to 95 mA

V_VBATT= (V_VREG1+ 0.5 V) to 15 V

V_VREG1= 90% of nominal

I_VREG1= 100 mA, V_VREG1= 5 V

V_VISW1= 5 V

3.5

0.03

550

0.15

795

390

R_{DSON_VISW1}

R_{DIS_LDO1}

mΩ

C_OUTDischarge Switch

On Resistance

1

kΩ

V_VREG1= 1 V

LDO2

Output Voltage (VREG2 Pin)

Fixed Voltage Range, 2 Bits

Voltage Accuracy

Load Regulation

Current-Limit Threshold

V_VREG2

V_{VREG2 (DEFAULT)}−2

∆V_VREG2/I_VREG2

I_{LDO2_ILIM}

R_{DSON_VISW2}

3.0

3.3

+2

V

%

%/A

mA

mΩ

I_VREG2= 10 mA

I_VREG2= 4 mA to 95 mA

V_VREG2= 90% of nominal

V_VISW2= 3.3 V

5.5

400

1409

290

Input Select Switch

On Resistance

C_OUTDischarge Switch

On Resistance

R_{DIS_LDO2}

12

Ω

V_VREG2= 1 V

CHARGE PUMP

C+ Switch On Resistance

Low-Side

R_{DSON_C+SW1}

R_{DSON_C+SW2}

1.1

1.0

Ω

Source, PVINCP to C+

Sink, C+ to BSTCP

High-Side

C− Switch On Resistance

High-Side

Low-Side

Shunt Switch On Resistance

Charge Pump Start-Up Threshold CP_START

R_{DSON_C−SW1}

R_{DSON_C−SW2}

R_{DSON_CP}

1.0

785

3.3

4.0

Ω

mΩ

Ω

Source, VDR5 to C−

Sink, C− to PGND5

BSTCP to PVINCP, EN low

At VBATT

V

Rev. A | Page 4 of 64

Data Sheet

ADP5080

DC-TO-DC CONVERTER BLOCK SPECIFICATIONS

T_J= 25°C, V_VBATT= 7.2 V, V_VREG1= V_VDRx= 5 V, V _VREG2= V_VDDIO= 3.3 V, unless otherwise noted.

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

CHANNEL 1 SYNC BUCK REGULATOR

Channel 1 Output Voltage (FB1 Pin)

Fixed Voltage Range, 5 Bits

V_FB1

0.89

0.80

−0.8

1.20

1.11

+0.8

V

%

REDUCE_VOUT1 = 0

REDUCE_VOUT1 = 1

Feedback Voltage Accuracy

at Default VID Code

V_{FB1 (DEFAULT)}

−1.3

+1.3

%

−25°C ≤ T_J≤ +85°C

Load Regulation

∆V_FB1/I_LOAD1

∆V_FB1/V_PVIN1

0.15

%/A

I_LOAD1= 20 mA to 2 A,

AUTO-PSM1 = 0

V_PVIN1= 5 V to 15 V, I_LOAD= 1 A

Line Regulation

SW1A Pin

0.004

%/V

High-Side Power FET On Resistance R_{DSON_1AH}

Low-Side Power FET On Resistance R_{DSON_1AL}

SW1B Pin

250

130

mΩ

I_D= 100 mA

High-Side Power FET On Resistance R_{DSON_1BH}

Low-Side Power FET On Resistance R_{DSON_1BL}

SW1A and SW1B Pins

175

95

mΩ

I_D= 100 mA, GATE_SCAL1 = 0

I_D= 100 mA

Switch Current Limit

Minimum Off Time

Minimum Duty Cycle

I_CL1

3.1

4.0

115

0

4

125

A

Valley current, −25°C ≤ T_J≤ +85°C

t_{OFF1 (MIN)}

D_MIN1

t_SS1

ns

%

ms

Ω

Soft Start Time

SS1 = 10

V_FB1= 1 V

C_OUTDischarge Switch On Resistance

CHANNEL 2 SYNC BUCK REGULATOR

Channel 2 Output Voltage (FB2 Pin)

Fixed Voltage Range, 4 Bits

R_DIS1

V_FB2

1.0

3.3

V

Feedback Voltage Accuracy

at Default VID Code

V_{FB2 (DEFAULT)}

−0.8

+0.8

%

−1.3

+1.3

%

−25°C ≤ T_J≤ +85°C

Load Regulation

∆V_FB2/I_LOAD2

∆V_FB2/V_PVIN2

0.25

%/A

I_LOAD2= 10 mA to 1.0 A,

AUTO-PSM2 = 0

V_PVIN2= 5 V to 15 V, I_LOAD2= 500 mA

Line Regulation

SW2 Pins

0.004

%/V

High-Side Power FET On Resistance R_{DSON_2H}

Low-Side Power FET On Resistance R_{DSON_2L}

235

165

1.8

100

0

mΩ

A

ns

%

I_D= 100 mA

Valley current, −25°C ≤ T_J≤ +85°C

Switch Current Limit

Minimum Off Time

Minimum Duty Cycle

I_CL2

1.2

t_{OFF2 (MIN)}

D_MIN2

t_SS2

Soft Start Time

4

125

ms

Ω

SS2 = 10

V_FB2= 1 V

C_OUTDischarge Switch On Resistance

CHANNEL 3 SYNC BUCK REGULATOR

Channel 3 Output Voltage (FB3 Pin)

Fixed Voltage Range, 3 Bits

Minimum Adjustable Voltage

R_DIS2

V_FB3

1.2

1.8

V

0.8

VID3 = 111

Feedback Voltage Accuracy

at Default VID Code

V_{FB3 (DEFAULT)}

−0.8

−1.3

+0.8

+1.3

%

−25°C ≤ T_J≤ +85°C

Load Regulation

Line Regulation

∆V_FB3/I_LOAD3

∆V_FB3/V_PVIN3

0.17

%/A

I_LOAD3= 15 mA to 1.5 A,

AUTO-PSM3 = 0

V_PVIN3= 5 V to 15 V, I_LOAD3= 700 mA

0.003

%/V

Rev. A | Page 5 of 64

ADP5080

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SW3 Pins

High-Side Power FET On Resistance R_{DSON_3H}

Low-Side Power FET On Resistance R_{DSON_3L}

155

100

2.8

90

0

4

mΩ

A

ns

%

I_D= 100 mA

Valley current, −25°C ≤ T_J≤ +85°C

Switch Current Limit

Minimum Off Time

Minimum Duty Cycle

I_CL3

2.05

t_{OFF3 (MIN)}

D_MIN3

t_SS3

Soft Start Time

ms

Ω

SS3 = 10

V_FB3= 1 V

C_OUTDischarge Switch On Resistance

CHANNEL 4 SYNC BUCK REGULATOR

Channel 4 Output Voltage (FB4 Pin)

Fixed Voltage Range, 3 Bits

Minimum Adjustable Voltage

R_DIS3

125

V_FB4

1.8

3.55

V

0.8

VID4 = 111

Feedback Voltage Accuracy

at Default VID Code

V_{FB4 (DEFAULT)}

−1

−2

+1

+2

%

−25°C ≤ T_J≤ +85°C

Load Regulation

∆V_FB4/I_LOAD4

∆V_FB4/V_PVIN4

0.10

%/A

I_LOAD4= 10 mA to 800 mA,

AUTO-PSM4 = 0

V_PVIN4= 5 V to 15 V, I_LOAD4= 400 mA

Line Regulation

SW4 Pin

0.003

%/V

High-Side Power FET On Resistance R_{DSON_4H}

Low-Side Power FET On Resistance R_{DSON_4L}

350

345

1.4

75

100

4

mΩ

A

ns

%

I_D= 100 mA

Peak current, −25°C ≤ T_J≤ +85°C

Switch Current Limit

Minimum On Time

Maximum Duty Cycle

I_CL4

0.96

t_{ON4 (MIN)}

D_MAX4

t_SS4

Soft Start Time

ms

Ω

SS4 = 10

V_FB4= 1 V

C_OUTDischarge Switch On Resistance

CHANNEL 5 SYNC BUCK REGULATOR

Channel 5 Output Voltage (FB5 Pin)

Fixed Voltage Range, 3 Bits

R_DIS4

125

V_FB5

3.0

−1

5.0

+1

V

%

Feedback Voltage Accuracy

at Default VID Code

V_{FB5 (DEFAULT)}

−2

+2

%

−25°C ≤ T_J≤ +85°C

Load Regulation

∆V_FB5/I_LOAD5

∆V_FB5/V_PVIN5

0.05

%/A

I_LOAD5= 20 mA to 2 A,

AUTO-PSM5 = 0

V_PVIN5= 5 V to 15 V, I_LOAD5= 1 A

Line Regulation

SW5 Pins

0.001

%/V

High-Side Power FET On Resistance R_{DSON_5H}

Low-Side Power FET On Resistance R_{DSON_5L}

200

120

3

75

100

4

mΩ

A

ns

%

I_D= 100 mA

Peak current, −25°C ≤ T_J≤ +85°C

Switch Current Limit

Minimum On Time

Maximum Duty Cycle

I_CL5

2.4

t_{ON5 (MIN)}

D_MAX5

t_SS5

Soft Start Time

ms

Ω

SS5 = 10

V_FB5= 1 V

C_OUTDischarge Switch On Resistance

CHANNEL 6 BUCK BOOST REGULATOR

Channel 6 Output Voltage (FB6 Pin)

Fixed Voltage Range, 4 Bits

Minimum Adjustable Voltage

Accuracy at Default VID Code

R_DIS5

125

V_FB6

3.5

5.5

V

%

0.8

VID6 = 1111

V_{VOUT6 (DEFAULT )}−1

−2

+1

+2

−25°C ≤ T_J≤ +85°C

Load Regulation

Line Regulation

∆V_VOUT6/I_LOAD6

0.05

%/A

Buck boost configuration, I_LOAD6

15 mA to 1.5 A, AUTO-PSM6 = 0

V_PVIN6= 5 V to 15 V, I_LOAD6= 700 mA

=

∆V_VOUT6

/

0.001

%/V

V_PVIN6

Rev. A | Page 6 of 64

Data Sheet

ADP5080

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SW6A Pins

Low-Side Power FET On Resistance R_{DSON_6AL}

High-Side Power FET On Resistance R_{DSON_6AH}

95

60

4.4

80

mΩ

A

I_D= 100 mA, V_VDR6= 5 V

Peak current, −25°C ≤ T_J≤ +85°C

SW6A high-side on time

High-Side Switch Current Limit

Minimum On Time

I_CL6A

t_{ON6 (MIN)}

3.2

ns

SW6B Pins

Low-Side Power FET On Resistance R_{DSON_6BL}

High-Side Power FET On Resistance R_{DSON_6BH}

50

55

0

4

110

mΩ

%

ms

Ω

I_D= 100 mA

SW6B low-side duty cycle

SS6 = 10

V_VOUT6= 1 V

Boost Minimum Duty Cycle

Soft Start Time

D_MIN6B

t_SS6

C_OUTDischarge Switch On Resistance

R_DIS6

LINEAR REGULATOR BLOCK SPECIFICATIONS

T_J= 25°C, V_VBATT= 7.2 V, V_VREG1= V_VDRx= 5 V, V _VREG2= V_VDDIO= 3.3 V, unless otherwise noted.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

CHANNEL 7 LDO REGULATOR

Channel 7 Output Voltage

Voltage Accuracy

V_VOLDO7

V_{VOLDO7 (DEFAULT)}

5

−1.5

−2.5

12

+1.5

+2.5

V

%

V_VILDO7= V_VOLDO7+ 0.5 V

V_VILDO7= V_VOLDO7+ 0.5 V, I_LOAD7= 1 mA

V_VILDO7= V_VOLDO7+ 0.5 V, I_LOAD7= 1 mA,

−25°C ≤ T_J≤ +85°C

Load Regulation

Line Regulation

Dropout Voltage¹

∆V_VOLDO7/I_LOAD7

∆V_VOLDO7/V_VILDO7

V_DROP

0.005

0.007

75

%/mA

%/V

V_VILDO7= V_VOLDO7+ 0.5 V, I_LOAD7= 1 mA

to 20 mA

V_VILDO7= (V_VOLDO7+ 0.5 V) to 25 V,

I

_LOAD7= 1 mA

mV

V_VOLDO7programmed to 12 V,

I_VOLDO7= 10 mA

Current Limit

Soft Start Time

C_OUTDischarge Switch

On Resistance

I_CL7

t_SS7

R_DIS7

30

50

4

1

mA

ms

kΩ

V_VOLDO7= 95% of nominal

SS7 = 1

V_VOLDO7= 1 V

¹Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage.

Rev. A | Page 7 of 64

ADP5080

Data Sheet

I²C INTERFACE TIMING SPECIFICATIONS

T_J= 25°C, V_VBATT= 7.2 V, V_VDRx= 5 V, V_VREG2= V_VDDIO= 3.3 V, unless otherwise noted.

Table 5.

Parameter

Min

Typ

Max

Unit

kHz

µs

Description

f_SCL

t_HIGH

t_LOW

400

SCL clock frequency

SCL high time

SCL low time

0.6

1.3

µs

t_SU,DAT

t_HD,DAT

t_SU,STA

t_HD,STA

t_BUF

t_SU,STO

t_R

t_F

100

0

0.6

1.3

0.6

20 + 0.1 × C_B

0

ns

µs

ns

Data setup time

0.9

Data hold time¹

Setup time for repeated start

Hold time for start or repeated start

Bus free time between a stop condition and a start condition

Setup time for a stop condition

Rise time of SCL and SDA

Fall time of SCL and SDA

2

300

50

t_SP

C_B

ns

pF

Pulse width of suppressed spike

Capacitive load for each bus line

2

400

¹A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHminimum of the SCL signal) to bridge the undefined region of the

SCL falling edge.

²C_Bis the total capacitance of one bus line in picofarads (pF).

Timing Diagram

SDA

t_BUF

t_F

t_LOW

t_R

t_F

t_R

t_SP

t_HD,STA

t_SU,DAT

SCL

t_SU,STA

t_SU,STO

S

Sr

P

S

t_HD,DAT

t_HIGH

S = START CONDITION

Sr = REPEATED START CONDITION

P = STOP CONDITION

Figure 2. I²C Interface Timing Diagram

Rev. A | Page 8 of 64

Data Sheet

ADP5080

ABSOLUTE MAXIMUM RATINGS

Table 6.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

VBATT to GND

VDDIO to GND

VISW1 to GND

−0.3 V to +18 V

−0.3 V to +4.0 V

−0.3 V to +6.5 V

−0.3 V to +4.0 V

−0.3 V to +6.5 V

−0.3 V to +4.0 V

−0.3 V to +18 V

−0.3 V to +6.5 V

−0.3 V to +4.0 V

−0.3 V to +6.5 V

−0.3 V to +23 V

−0.3 V to (V_VDR5+ 0.3 V)

−0.3 V to +18 V

−0.3 V to +6.5 V

−0.3 V to +4.0 V

−0.3 V to +6.5 V

−2.0 V to +18 V

VISW2 to GND

VREG1 to GND

VREG2 to GND

EN to GND

EN34 to GND

FAULT to GND

THERMAL RESISTANCE

θ_JAis specified for worst-case conditions; that is, a device

soldered in a circuit board for surface-mount packages. Note

that actual θ_JAdepends on the application environment.

BSTCP to PVINCP

BSTCP to GND

C+ to PVINCP

Table 7. Thermal Resistance

PCB Type¹

1S0P

θ_JA

θ_JB

Unit

°C/W

2

C− to PGND5

60.6

26.9

7.3

4.5

PVINx to PGNDx

VDRx to PGNDx

BST16, BST23, BST45 to PVINx

FB1, FB2, FB3 to GND

FB4, FB5, FB6 to GND

VOUT6 to PGND6

SW1A, SW1B to PGND1

SW2 to PGND2

SW3 to PGND3

SW4 to PGND4

SW5 to PGND5

SW6A to PGND6

SW6B to PGND6

2S2P

¹PCB type conforms to JEDEC JESD51-9 standard.

²1.25 W power dissipation with zero airflow.

ESD CAUTION

−0.5 V to (V_VOUT6+ 2.0 V) or

+6.5 V, whichever is lower

PGNDx to GND

VILDO7 to GND

VOLDO7 to GND

FREQ to GND

−0.3 V to +0.3 V

−0.3 V to +28 V

−0.3 V to +18 V

−0.3 V to (V_VREG2+ 0.3 V)

−0.3 V to +4.0 V

SYNC to GND

CLKO to GND

SCL to GND

−0.3 V to (V_VREG2+ 0.3 V)

−0.3 V to +4.0 V

SDA to GND

−0.3 V to +4.0 V

Storage Temperature Range

Operating Ambient

Temperature Range

−65°C to +150°C

−25°C to +85°C

Operating Junction

Temperature Range

−25°C to +125°C

Rev. A | Page 9 of 64

ADP5080

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALL A1

CORNER

1

2

3

4

5

6

7

8

9

VOUT6

VISW1

VISW2

PVINCP

C+

PGND5

SW5

PVIN5

A

SW6B

PGND6

SW6A

PVIN6

PVIN1

SW1A

PGND1

SW6B

PGND6

SW6A

PVIN6

PVIN1

SW1B

PGND1

VREG1 VREG2 VOLDO7

C–

PGND5

VDR5

FB5

SW5

BST45

FB4

PVIN5

PVIN4

SW4

B

C

D

E

F

VBATT

VDR6

EN34

FB6

SDA

EN

VILDO7

GND

BSTCP

SYNC

GND

BST16

FB1

SCL

CLKO

FB3

VDR34

PGND3

SW3

PGND4

PGND3

SW3

VDDIO

GND

FREQ

FAULT

PVIN2

VDR12

PGND2

FB2

SW2

GND

G

H

SW2

BST23

PVIN3

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1A

2A

VOUT6

Output Voltage for Channel 6.

3A

VISW1

Input for an External Regulator Output. A 5.0 V to 5.5 V regulator connected to the VISW1 pin can take over from

LDO1 to supply the internal circuit of the ADP5080 and the VREG1 load. If this pin is not used, connect it to GND.

4A

VISW2

Input for an External Regulator Output. A 3.0 V to 3.3 V regulator connected to the VISW2 pin can take over from

LDO2 to supply the internal circuit of the ADP5080 and the VREG2 load. If this pin is not used, connect it to GND.

5A

6A

7A

8A

9A

1B

2B

3B

4B

5B

6B

7B

8B

9B

1C

2C

3C

4C

5C

6C

7C

8C

PVINCP

C+

PGND5

SW5

PVIN5

SW6B

VREG1

VREG2

VOLDO7

C−

Input Power Supply for the Charge Pump.

Flying Capacitor Terminal for the Charge Pump.

Power Ground for Channel 5.

Switching Node for Channel 5.

Input Power Supply for Channel 5.

Secondary Side Boost Switching Node for Channel 6.

Output Voltage for LDO1.

Output Voltage for LDO2.

Output Voltage for Channel 7. Leave this pin open if not used.

Flying Capacitor Terminal for the Charge Pump.

Power Ground for Channel 5.

Switching Node for Channel 5.

Input Power Supply for Channel 5.

PGND5

SW5

PVIN5

PGND6

VBATT

EN34

VILDO7

BSTCP

VDR5

Power Ground for Channel 6.

Power Supply Input for the Internal Circuits. Connect this pin to the battery.

Independent Enable Input for Channel 3 and Channel 4. If this pin is not used, connect it to GND.

Input Power Supply for Channel 7. If this pin is not used, connect it to VBATT.

Output Voltage for Charge Pump.

Low-Side FET Driver Power Supply for Channel 5. Connect this pin to VREG1.

High-Side FET Driver Power Supply for Channel 4 and Channel 5.

BST45

Rev. A | Page 10 of 64

Data Sheet

ADP5080

Pin No.

9C

Mnemonic

Description

PVIN4

SW6A

VDR6

FB6

GND

SYNC

FB5

FB4

SW4

PVIN6

BST16

SDA

Input Power Supply for Channel 4.

1D

2D

3D

4D

5D

6D

7D

8D

9D

1E

2E

3E

4E

5E

6E

7E

Primary Side Switching Node for Channel 6.

Low-Side FET Driver Power Supply for Channel 6. Connect this pin to VREG1.

Feedback Node for Channel 6.

Ground. All GND pins must be connected.

External Clock Input (CMOS Input Port). If this pin is not used, connect it to GND.

Feedback Node for Channel 5.

Feedback Node for Channel 4.

Switching Node for Channel 4.

Input Power Supply for Channel 6.

High-Side FET Driver Power Supply for Channel 1 and Channel 6.

Data Input/Output for I²C Interface. Open-drain I/O port.

Clock Input for I²C Interface. For start-up requirements, see the I²C Interface section.

Ground. All GND pins must be connected.

Clock Output (CMOS Output Port). CLKO replicates the Channel 1 switching clock. This output is not available

when the SYNC pin is driven by an external clock. If this pin is not used, leave it open.

SCL

GND

CLKO

8E

9E

1F

2F

3F

4F

5F

6F

VDR34

PGND4

PVIN1

FB1

EN

VDDIO

FREQ

Low-Side FET Driver Power Supply for Channel 3 and Channel 4. Connect this pin to VREG1.

Power Ground for Channel 4.

Input Power Supply for Channel 1.

Feedback Node for Channel 1.

Enable Control Input.

Supply Voltage for I²C Interface. Typically, this pin is connected externally to VREG2 or to the host I/O voltage.

Frequency Pin for the Internal Oscillator. To select the internal clock source oscillator, connect an external

100 kΩ resistor from the FREQ pin to GND.

7F

FB3

Feedback Node for Channel 3.

8F

9F

PGND3

SW1A

SW1B

VDR12

FB2

GND

FAULT

GND

SW3

PGND1

PGND2

SW2

Power Ground for Channel 3.

Switching Node for Channel 1.

Low-Side FET Driver Power Supply for Channel 1 and Channel 2. Connect this pin to VREG1.

Feedback Node for Channel 2.

Ground. All GND pins must be connected.

Fault Status Output Pin. This open-drain output port goes low when a fault occurs. Leave open if not used.

Ground. All GND pins must be connected.

Switching Node for Channel 3.

Power Ground for Channel 1.

Power Ground for Channel 2.

Switching Node for Channel 2.

Input Power Supply for Channel 2.

High-Side FET Driver Power Supply for Channel 2 and Channel 3.

Input Power Supply for Channel 3.

1G

2G

3G

4G

5G

6G

7G

8G

9G

1H

2H

3H

4H

5H

6H

7H

8H

9H

SW2

PVIN2

BST23

PVIN3

Input Power Supply for Channel 3.

Rev. A | Page 11 of 64

ADP5080

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

100

90

80

70

60

50

40

30

20

10

0

AUTO PSM

FPWM

90

80

AUTO PSM

70

60

V

= 4.5V

= 7.2V

= 12.6V

V

= 4.5V

= 7.2V

= 12.6V

IN

50

40

30

20

10

0

FPWM

10

100

1000

10

100

1000

OUTPUT CURRENT (mA)

Figure 4. Channel 1 Efficiency, V_OUT= 1.1 V

Figure 7. Channel 4 Efficiency, V_OUT= 3.3 V

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

AUTO PSM

FPWM

V

= 4.5V

= 7.2V

= 12.6V

V

= 4.5V

= 7.2V

= 12.6V

IN

FPWM

10

100

1000

10

100

1000

OUTPUT CURRENT (mA)

Figure 8. Channel 5 Efficiency, V_OUT= 3.3 V

Figure 5. Channel 2 Efficiency, V_OUT= 1.2 V

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

AUTO PSM

FPWM

V

= 4.5V

= 7.2V

= 12.6V

V

= 4.5V

= 7.2V

= 12.6V

IN

10

100

1000

10

100

1000

OUTPUT CURRENT (mA)

Figure 9. Channel 6 Efficiency, V_OUT= 5 V

Figure 6. Channel 3 Efficiency, V_OUT= 1.8 V

Rev. A | Page 12 of 64

Data Sheet

ADP5080

1.110

3.315

3.310

3.305

3.300

3.295

3.290

3.285

V

= 4.5V

= 7.2V

= 12.6V

IN

V

= 4.5V

= 7.2V

= 12.6V

IN

1.105

1.100

1.095

1.090

0.1

1

10

100

1000

0.1

1

10

OUTPUT CURRENT (mA)

100

1000

OUTPUT CURRENT (mA)

Figure 13. Channel 4 Load Regulation

Figure 10. Channel 1 Load Regulation

3.320

3.315

3.310

3.305

3.300

3.295

3.290

3.285

3.280

1.210

1.208

1.206

1.204

1.202

1.200

1.198

1.196

1.194

1.192

1.190

V

= 4.5V

= 7.2V

= 12.6V

IN

V

= 4.5V

= 7.2V

= 12.6V

IN

0.1

1

10

100

1000

0.1

1

10

OUTPUT CURRENT (mA)

100

1000

OUTPUT CURRENT (mA)

Figure 11. Channel 2 Load Regulation

Figure 14. Channel 5 Load Regulation

1.810

1.805

1.800

1.795

1.790

5.020

5.015

5.010

5.005

5.000

4.995

4.990

4.985

4.980

V

= 4.5V

= 7.2V

= 12.6V

V

= 4.5V

= 7.2V

= 12.6V

IN

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

Figure 12. Channel 3 Load Regulation

Figure 15. Channel 6 Load Regulation

Rev. A | Page 13 of 64

ADP5080

Data Sheet

12.05

12.04

12.03

12.02

12.01

12.00

11.99

11.98

11.97

11.96

2

4

11.95

0.1

B

CH2 20.0mV

CH4 500mA 50Ω

20.0M

250M

200µs/DIV

20.0MS/s

W

1

10

W

OUTPUT CURRENT (mA)

Figure 19. Channel 1 Load Transient, V_OUT= 1.1 V, FPWM Mode

Figure 16. Channel 7 Load Regulation, VILDO7 = 16 V

5.100

5.075

5.050

5.025

5.000

4.975

4.950

4.925

4.900

2

4

B

CH2 20.0mV

CH4 300mA 50Ω

20.0M

200µs/DIV

10.0MS/s

W

0.1

1

10

100

W

OUTPUT CURRENT (mA)

Figure 20. Channel 1 Load Transient, V_OUT= 1.1 V, Auto PSM Mode

Figure 17. VREG1 Load Regulation

3.400

3.375

3.350

3.325

3.300

3.275

3.250

3.225

3.200

2

4

B

CH2 20.0mV

CH4 300mA 50Ω

20.0M

250M

200µs/DIV

20.0MS/s

W

0.1

1

10

100

B

OUTPUT CURRENT (mA)

Figure 21. Channel 2 Load Transient, V_OUT= 1.2 V, FPWM Mode

Figure 18. VREG2 Load Regulation

Rev. A | Page 14 of 64

Data Sheet

ADP5080

2

4

B

CH2 20.0mV

CH4 200mA 50Ω

20.0M

200µs/DIV

20.0MS/s

CH2 20mV

CH4 200mA 50Ω

20.0M

250M

200µs/DIV

5.0MS/s

W

Figure 22. Channel 2 Load Transient, V_OUT= 1.2 V, Auto PSM Mode

Figure 25. Channel 4 Load Transient, V_OUT= 3.3 V, FPWM Mode

2

4

B

CH2 50.0mV

CH4 100mA 50Ω

20.0M

200µs/DIV

20.0MS/s

CH2 40.0mV

CH4 400mA 50Ω

20.0M

250M

200µs/DIV

20.0MS/s

W

B

Figure 23. Channel 3 Load Transient, V_OUT= 1.8 V, FPWM Mode

Figure 26. Channel 4 Load Transient, V_OUT= 3.3 V, Auto PSM Mode

2

4

B

CH2 50.0mV

CH4 200mA 50Ω

20.0M

200µs/DIV

20.0MS/s

CH2 50.0mV

CH4 500mA 50Ω

20.0M

250M

200µs/DIV

20.0MS/s

W

B

Figure 24. Channel 3 Load Transient, V_OUT= 1.8 V, Auto PSM Mode

Figure 27. Channel 5 Load Transient, V_OUT= 3.3 V, FPWM Mode

Rev. A | Page 15 of 64

ADP5080

Data Sheet

2

4

B

W

CH2 50.0mV

CH4 300mA 50Ω

20.0M

200µs/DIV

20.0MS/s

CH2 100mV

CH4 100mA 50Ω

20.0M

250M

W

200µs/DIV

20.0MS/s

W

B

W

Figure 28. Channel 5 Load Transient, V_OUT= 3.3 V, Auto PSM Mode

Figure 31. VREG1 Load Transient, VREG1 = 5 V

2

4

B

CH2 70.0mV

CH4 400mA 50Ω

20.0M

1.0G

200µs/DIV

20.0MS/s

CH2 20mV

CH4 100mA 50Ω

20.0M

250M

W

200µs/DIV

20.0MS/s

W

B

Figure 29. Channel 6 Load Transient, V_OUT= 5 V, FPWM Mode

Figure 32. VREG2 Load Transient, VREG2 = 3.3 V

2

4

B

CH2 100mV

CH4 300mA 50Ω

20.0M

200µs/DIV

20.0MS/s

W

B

W

Figure 30. Channel 6 Load Transient, V_OUT= 5 V, Auto PSM Mode

Rev. A | Page 16 of 64

Data Sheet

ADP5080

CH7

R3

CH5

R4

CH5

CH6

R1

R4

CH6

3

CH4

CH3

CH4

2

1

2

CH1

CH2

R2

3

CH3

1

CH2

EN

R3

CH1

R1

R2

4

EN

4

CH1 1.0V 1MΩ

CH2 2.0V 1MΩ

CH3 5.0V 1MΩ

CH4 5.0V 1MΩ

R1 1.0V 1.0ms

R2 1.0V

R3 5.0V

CH1 5.0V 1MΩ

CH2 3.0V 1MΩ

CH3 1.0V 1MΩ

CH4 5.0V 1MΩ

R1 5.0V

R2 1.0V

R3 700mV

R4 3.0V

2.0ms

R4 2.0V

Figure 33. Startup

Figure 34. Shutdown

Rev. A | Page 17 of 64

ADP5080

Data Sheet

APPLICATION CIRCUIT

VREG2

TO VDRx

5.0V

3.3V

POWER

SWITCH

VDDIO

KEY

CONTROLLER/

SUB-CPU

VBATT

10µF

4.7µF

1µF

VDDIO

EN34

SCL

SDA

2

I C

INTERFACE

OUTPUT

ENABLE

LOGIC

VREG2

LDO1

(KEEP-ALIVE)

LDO2

(KEEP-ALIVE)

UVLO

FAULT

POR

FAULT

PVIN1

VBATT

BSTCP

PVIN2

BST23

BST16

VBATT

PGND1

POWER FAULT

DETECTION

BSTCP

SW1A

SW1B

PGND2

V

1

CHANNEL 1

BUCK

CHANNEL 2

BUCK

REGULATOR

OUT

SW2

V

2

REGULATOR

OUT

PGND1

GATE

SCALING

PGND2

FB2

DISCHARGE

SWITCH

DISCHARGE

SWITCH

FB1

(VDR12)

SOFT

COMP

DAC

COMP

DAC

VDR12

START

VREG1

VBATT

PVIN3

PVIN4

VBATT

BSTCP

POWER

SEQUENCE

PGND3

SW3

PGND4

BST45

SW4

V

3

OUT

CHANNEL 3

BUCK

CHANNEL 4

BUCK

V

4

OUT

REGULATOR

PGND3

REGULATOR

DISCHARGE

SWITCH

PGND4

FB4

(BST23)

(BST16)

DISCHARGE

SWITCH

FB3

(VDR34)

SOFT

START

COMP

DAC

SOFT

START

VDR34

COMP

DAC

VREG1

VBATT

PVIN5

PVIN6

VBATT

VREG1

(BST45)

PGND5

VDR5

PGND6

SW6A

CHANNEL 5

BUCK

REGULATOR

SW5

V

5

OUT

PGND6

CHANNEL 6

BUCK/

BUCK BOOST

REGULATOR

VOUT6

PGND5

FB5

DISCHARGE

SWITCH

V

6

OUT

SOFT

START

COMP

DAC

PGND6

SW6B

FREQ

CLKO

SYNC

PGND6

100kΩ

OPTIONAL

OSCILLATOR

DISCHARGE

SWITCH

VDR6

FB6

VREG1

SOFT

COMP

DAC

START

BSTCP

C+

VILDO7

BSTCP

PVINCP

BSTx

CHANNEL 7

HV LDO

PVINCP

VBATT

VOLDO7

12V

CHARGE

PUMP

C+

C–

GND

Figure 35. Typical Application Circuit

Rev. A | Page 18 of 64

Data Sheet

ADP5080

THEORY OF OPERATION

The ADP5080 is a fully integrated, high efficiency power solu-

tion for multicell lithium ion battery applications. The device

can connect directly to the battery, which eliminates the need

for preregulators and increases the battery life of the system.

The VDRx pins provide the gate drive voltage to the internal

power FETs. If the VDR12 voltage falls below 2.9 V (typical),

all channels except LDO1 and LDO2 shut down to prevent

malfunction of the power FETs. As with a PVIN UVLO event,

EN must be toggled to restart channel operation.

The ADP5080 integrates two keep-alive LDO regulators, five

synchronous buck regulators, one configurable buck boost regu-

lator, and one high voltage LDO regulator. An integrated charge

pump provides the switch driver power supply. Along with the

integrated power FETs and drivers, integrated compensation,

soft start, and FB dividers contribute to minimize the number

of external components and the PCB layout space, providing

significant advantages for portable applications.

Power-On Reset (POR)

If the VBATT voltage falls below its UVLO threshold (V_{UVLO (BATT)}),

all channels, including LDO1 and LDO2, are shut down. This

event forces a power-on reset.

VREG2 is the voltage supply for the internal digital circuit blocks.

If the VREG2 voltage falls below the power-on reset threshold

(V_{UVLO (POR)}) of 2.4 V typical, the ADP5080 shuts down, and all

registers are reset to their default values.

Factory programming sets the default values for the output

voltages, fault behavior, switching frequency, start-up time, and

other functions. These values can also be programmed via the

I²C interface. The ADP5080 features a built-in sequencer that

provides automatic startup and shutdown timing based on these

settings.

DISCHARGE SWITCH

The ADP5080 integrates discharge switches for Channel 1 to

Channel 7. These switches help to discharge the output capacitors

quickly when a channel is turned off. The discharge switches are

turned on when the EN signal goes low or when a channel is

manually turned off via I²C control, provided that the discharge

function was enabled by setting the DSCGx_ON bit (x is 1 to 7)

in Register 1. The default values for the discharge switches are

factory fuse programmed.

UVLO AND POR

The undervoltage lockout (UVLO) and power-on reset (POR)

functions prevent abnormal behavior and force a smooth shut-

down when input voltages fall below the minimum required

levels. The ADP5080 incorporates UVLO on VBATT, PVIN1,

and VDR12; it incorporates POR on VREG2. The thresholds

are low enough to ensure normal operation down to 4 V at

VBATT with ample hysteresis to avoid chattering.

KEEP-ALIVE LDO REGULATORS

The keep-alive LDO linear regulators (LDO1 and LDO2) are kept

alive as long as a valid supply voltage is applied to the VBATT

pin. The LDO regulators are used to power the internal control

block of the ADP5080 so that the device is ready for the enable

(EN) signal. The outputs of LDO1 and LDO2 are also available

via the VREG1 and VREG2 pins for external circuits that are

also kept alive during system standby.

Undervoltage Lockout (UVLO)

If the PVIN1 voltage of Channel 1 falls below the UVLO threshold

(V_{UVLO (F)}), all channels, as well as the charge pump, are turned

off. However, LDO1 and LDO2 remain operational.

As the input voltage rises, the regulator channels do not restart

automatically. EN must be toggled after a UVLO event to restart

channels in sequencer mode or manual mode. For more informa-

tion about enabling channels using sequencer mode and manual

mode, see the Enabling and Disabling the Output Channels

section.

When VBATT initially rises above the UVLO threshold, LDO1

begins operation, followed by LDO2. When all UVLO thresholds

are cleared, the ADP5080 is in standby mode and ready to be

enabled. If an external voltage is used to drive VDDIO, VDDIO

can be on before VBATT; otherwise, LDO2 provides power to

VDDIO via the VREG2 output.

Rev. A | Page 19 of 64

ADP5080

Data Sheet

LDO1

The use of an external regulator connected to the VISW1 pin is

intended to achieve better system power efficiency by allowing a

switching power supply to take over the LDO1 linear regulator

when the system is powered up to operation. If the VISW1 input

is not used, tie it to GND. The VISW1 input is not active until

EN is high.

LDO1 regulates the supply voltage applied to the VBATT pin to

either 5.0 V or 5.5 V and is capable of providing up to 400 mA.

LDO1 internally supplies LDO2, as well as external circuits, includ-

ing the VDRx pins supplied through the VREG1 pin.

The LDO1 output is enabled when the VBATT pin voltage rises

above the UVLO threshold and is disabled when the VBATT pin

voltage falls below the UVLO threshold.

Current Limit for LDO1

LDO1 is rated to a maximum load current of 400 mA. Above

this level, the current-limit feature limits the current to protect

the device.

VISW1 Input

A 5.0 V to 5.5 V regulator connected to the VISW1 pin can take

over from LDO1 to supply the internal circuit of the ADP5080 and

the VREG1 load. To enable this feature, set the SEL_INP_LDO1

bit (Bit 0 in Register 33) high after the VISW1 pin voltage settles

above 4.7 V.

The VISW1 input has an independent current-limit circuit with

a typical threshold of 500 mA. If this overcurrent threshold is

exceeded, the VISW1 input is immediately disconnected and

LDO1 takes over to supply the VREG1 current. After the VISW1

input is turned off due to a current-limit event, it can be reset

only by toggling the EN pin.

If the VISW1 pin voltage falls below 4.5 V, LDO1 resumes

control automatically. However, if the VISW1 source is disabled,

it is recommended that the SEL_INP_LDO1 bit be reset to 0

before turning off the VISW1 pin source.

Discharge Switch for LDO1

A discharge switch at the VREG1 pin turns on during low

VBATT pin voltage (3.5 V 0.1 V hysteresis), removing the

charge of the external capacitor via a 1 kΩ resistor.

VOLTAGE

DETECTION

VISW1

OVERCURRENT

5.0V TO 5.5V

PROTECTION

CURRENT

DETECTION

OVERCURRENT

PROTECTION

VREG1

VBATT

5.0V OR 5.5V

AGND

DISCHARGE

SWITCH

TO

INTERNAL

CIRCUITS

VREF

LDO1

Figure 36. VREG1, LDO1, and VISW1

Rev. A | Page 20 of 64

Data Sheet

ADP5080

LDO2

is not used, tie it to GND. The VISW2 input is not active until

EN is high.

LDO2 regulates the internally routed VREG2 pin voltage to 3 V,

3.15 V, 3.2 V, or 3.3 V and is capable of providing up to

300 mA. LDO2 internally supplies the control block of the

ADP5080, as well as external circuits supplied through the

VREG2 pin.

Because the VISW2 input supplies VREG2 with no regulation,

the maximum voltage that can be applied to VISW2 is 3.3 V. The

VISW2 input has a relatively high resistance compared to the

LDO2 path. As a result, VISW2 regulation may not be sufficient

when used to supply heavier loads.

The LDO2 output is enabled when the VBATT pin voltage rises

above the UVLO threshold and is disabled when the VBATT

pin voltage falls below the UVLO threshold.

Current Limit for LDO2

LDO2 is rated to a maximum load current of 300 mA. Above

this level, the current-limit feature limits the current to protect

the device.

VISW2 Input

A 3.0 V to 3.3 V regulator connected to the VISW2 pin can take

over from LDO2 to supply the internal circuit of the ADP5080 and

the VREG2 load. To enable this feature, set the SEL_INP_LDO2

bit (Bit 4 in Register 33) high after the VISW2 pin voltage settles

above 2.7 V.

The VISW2 input has an independent current-limit circuit with

a typical threshold of 300 mA. If this overcurrent threshold is

exceeded, the VISW2 input is immediately disconnected and

LDO2 takes over to supply the VREG2 current. After the VISW2

input is turned off due to a current-limit event, it can be reset

only by toggling the EN pin.

If the VISW2 pin voltage falls below 2.55 V, LDO2 resumes

control automatically. However, if the VISW2 source is disabled,

it is recommended that the SEL_INP_LDO2 bit be reset to 0

before turning off the VISW2 pin source.

Discharge Switch for LDO2

A discharge switch at the VREG2 pin turns on during low

VBATT pin voltage (3.5 V 0.1 V hysteresis), removing the

residual charge of the external capacitor via a 12 Ω resistor.

The use of an external regulator connected to the VISW2 pin is

intended to achieve better system power efficiency by allowing

a switching power supply to take over the LDO2 linear regulator

when the system is powered up to operation. If the VISW2 input

VOLTAGE

DETECTION

VISW2

OVERCURRENT

3.0V TO 3.3V

PROTECTION

CURRENT

DETECTION

OVERCURRENT

PROTECTION

VREG2

3.0V TO 3.3V

AGND

DISCHARGE

SWITCH

FROM VREG1

OUTPUT

5.0V TO 5.5V

TO

INTERNAL

CIRCUITS

VREF

LDO2

Figure 37. VREG2, LDO2, and VISW2

Rev. A | Page 21 of 64

ADP5080

Data Sheet

If the input voltage falls below this level, the output voltage

droops below its nominal value.

DC-TO-DC CONVERTER CHANNELS

The ADP5080 integrates five buck regulators and a configurable

buck only/buck boost regulator. These regulators can be configured

for various functions including auto PSM, auto DCM, DVS, and

gate scaling. Each function is included only in the channels where

it is most effective (see Table 9).

Current-Limit Protection, Channel 1 to Channel 3

Channel 1, Channel 2, and Channel 3 use valley mode current

limit (see Figure 38). In valley mode current-limit protection,

inductor current is sensed during the low-side on cycle, imme-

diately before the high-side FET turns on. If the inductor current is

above the current-limit threshold at this point, the next switching

pulse is skipped.

Channel 1, Channel 2, and Channel 3: Buck Regulators

with Flex-Mode Architecture

Channel 1, Channel 2, and Channel 3 feature Flex-Mode™ current

mode control, which eliminates minimum on time requirements

and allows duty cycles as low as 0%. Flex-Mode uses a unique

adaptive control architecture that maintains stable operation over

a wide range of application conditions. With Flex-Mode control,

very high step-down ratios can be achieved while maintaining

high efficiency and excellent transient performance.

CURRENT

SENSING

POINT

INDUCTOR CURRENT

VALLEY CURRENT-

LIMIT THRESHOLD

Selecting the Output Voltage, Channel 1 to Channel 3

SKIPPED

CYCLE

The output voltage of Channel 1, Channel 2, or Channel 3 is

selected from one of the preset values available in the VIDx bits,

where x is 1, 2, or 3 (see Table 39 and Table 41). The default

output voltage value is factory fuse programmed.

SW NODE

Figure 38. Valley Mode Current Limit

Switching does not resume until the current falls below the limit

threshold. This behavior creates an inherent frequency foldback

feature, which makes valley mode current-limit protection very

robust against runaway inductor current. Because this type of

current limit senses current before switching, it is also relatively

immune to switching noise.

Channel 3 has an adjustable mode option that can be selected

using the VID3 bits. When the adjustable output voltage mode is

selected, the output voltage is set by an external feedback resistor

divider. Select resistor values such that the desired output voltage

is divided down to 0.8 V and the paralleled resistance seen from

the dividing node does not exceed 25 kΩ (see the Setting the

Output Voltage (Adjustable Mode Channels) section). Channel 1

can also be used in adjustable output mode by setting the VID1

bits to 0.8 V and using external feedback resistors with values less

than 1 kΩ. When using the adjustable mode for Channel 1 or

Channel 3, be aware of the minimum off time restriction, which

may limit the range of available output voltages.

Table 3 provides the valley current threshold specifications. The

actual load current-limit threshold varies with inductor value,

frequency, and input and output voltage.

When the current-limit threshold is exceeded, load current is not

allowed to increase further. Therefore, as the load impedance is

reduced, the current limit forces the output voltage to fall. The

falling output voltage in turn toggles the PWRGx, UVx,

Channel 1, Channel 2, and Channel 3 are designed for very low

duty cycle operation. However, at very high duty cycle, these chan-

nels have a limited range due to the minimum off time restriction

(see Table 3). The minimum input voltage capability for a given

output voltage can be determined using the following equation:

FAULT

and

error flags.

In the extreme event of an output voltage short circuit, the UVP

function protects the device against excessive current during the

on cycle (see the Undervoltage Protection (UVP) section).

V

_{IN_MIN}= V_OUT/(1 − t_{OFF_MIN}× f_SW)

Table 9. DC-to-DC Converter Specifications and Functions

Regulator

Adjustable

Mode (V)

Auto

PSM

Auto

DCM

Gate

Scaling

Channel

Type

Buck

V_INRange (V)

4 to 15

V_OUTRange (V)

0.8 to 1.2¹

1.0 to 3.3

1.2 to 1.8

1.8 to 3.55

3.0 to 5.0

I_OUT(A)

3

1.15

1.5

0.8

2

2 (buck)

1.5 (buck

boost)

DVS

Yes

N/A

1

2

3

4

5

6

0.8 to 1.2

N/A

0.8 to 3.6

1.0 to 5.0

N/A

Yes

N/A

Yes

N/A

4 to 15

Buck or

buck boost

3.5 to 5.5

1.0 to 5.0

Yes

¹Channel 1 has two available voltage ranges.

Rev. A | Page 22 of 64

Data Sheet

ADP5080

DVSx_INTVAL

Discharge Switch, Channel 1 to Channel 3

VID (NEW)

Each channel incorporates a discharge switch. For Channel 1

and Channel 2, the discharge switch is located at the FB1 and

FB2 pins, respectively; for Channel 3, the discharge switch is

located at the SW3 pin. The discharge switch can be turned on

when the corresponding channel output is turned off, removing

the residual charge of the external capacitor via a 125 Ω resistor.

The discharge switch can be enabled by setting the appropriate

DSCGx_ON bit in Register 1.

VID (PREV – 1)

VID (PREV)

OUTPUT VOLTAGE

Figure 39. DVS Operation

The output voltage for Channel 1 is programmed using the VID1

bits in Register 12; the output voltage for Channel 2 is programmed

using the VID2 bits in Register 13. When the DVS function is

enabled, the voltage transition takes place according to the steps

set by the VID1 or VID2 bits (see Table 39 and Table 41). The

transition time from one step to the next is specified by the

interval programmed in Register 17 using the DVSx_INTVAL

bits (where x is 1 or 2). The DVS function is enabled by setting

the EN_DVSx bit in Register 17.

Gate Scaling (Channel 1 Only)

Channel 1 features a gate scaling function, which improves

efficiency in light load conditions. When enabled by setting

the GATE_SCAL1 bit in Register 32, gate scaling halves the size

of the Channel 1 switching FETs, reducing the gate charge-up

current—which is a non-negligible loss element in light load

conditions—while allowing increased R_DSON, whose effect is less

significant in these conditions. When gate scaling is enabled,

only SW1A is used for the Channel 1 switch node because it is

assumed that the load current is light.

For Channel 2, DVS operation is limited to an output voltage

range of 1.0 V to 1.25 V.

When Channel 1 or Channel 2 is configured for DVS operation,

toggling EN low does not immediately reset the VID code to its

initial state. Instead Channel 1 or Channel 2 returns to its config-

ured output voltage according to the steps set by the VID1 or

VID2 bits (see Table 39 and Table 41, respectively).

Dynamic Voltage Scaling (DVS) Function

Channel 1 and Channel 2 incorporate a dynamic voltage scaling

(DVS) function. DVS provides a stair-step transition in output volt-

age when the preset value for the output voltage is reprogrammed

on the fly (see Figure 39).

BSTx

BSTCP

ADP5080

SEQUENCER

SOFT START

VDRx

VREG1

PWM

COMPARATOR

PGNDx

PVINx

4V TO 15V

PGNDx

R

RS

LATCH

SWx

OUTPUT

VOLTAGE

S

CLOCK

OVP

UVP

OCP

PGNDx

ZERO CROSS

COMPARATOR

PSM LOGIC

PGND

ON PERIOD

SLOPE

GENERATION

OUTPUT

VOLTAGE

CURRENT

SENSE AMP

CURRENT

LIMIT

OCP

ERROR AMP

FBx

0.8V

FB3

FB1

FB2

SW3

POWER-GOOD

COMPARATOR

VREF

EXTERNAL

VOLTAGE DIVIDER

(CH3 ADJ MODE ONLY)

DISCHARGE

SWITCH

Figure 40. Buck Regulator Block Diagram: Channel 1, Channel 2, and Channel 3

Rev. A | Page 23 of 64

ADP5080

Data Sheet

Channel 4 and Channel 5: Current Mode Buck Regulators

seen from the dividing node does not exceed 25 kΩ (see the

Setting the Output Voltage (Adjustable Mode Channels) section).

When using the adjustable mode for Channel 4, be aware of the

minimum on time restriction, which may limit the range of

available output voltages.

Channel 4 and Channel 5 are internally compensated current

mode control buck regulators (see Figure 41). Combined with

the integrated charge pump, these channels are designed to

operate at high duty cycles up to 100%.

Channel 4 and Channel 5 are designed for very high duty cycle

operation. However, at very low duty cycle, these channels have

a limited range due to the minimum on time restriction (75 ns

typical) inherent in current mode control. The maximum input

voltage capability for a given output voltage can be determined

using the following equation:

Selecting the Output Voltage, Channel 4 and Channel 5

The output voltage of Channel 4 or Channel 5 is selected from

one of the preset values available in the VIDx bits, where x is 4

or 5 (see Table 43). The default output voltage value is factory

fuse programmed.

Channel 4 has an adjustable mode option that can be selected

using the VID4 bits. When the adjustable output voltage mode

is selected, the output voltage is set by an external feedback

resistor divider. Select resistor values such that the desired output

voltage is divided down to 0.8 V and the paralleled resistance

V

_{IN_MAX}= V_OUT/(t_{ON_MIN}× f_SW)

If the input voltage rises above this level, the output voltage

continues to be regulated; however, switching pulses are skipped,

which may increase output voltage ripple.

BSTx

BSTCP

ADP5080

VDRx

VREG1

CURRENT

LIMIT

PGNDx

OCP

SEQUENCER

SOFT START

PWM

COMPARATOR

CURRENT

PVINx

SENSE AMP

4V TO 15V

PGNDx

R

SLOPE

RS

LATCH

COMPENSATION

SWx

OUTPUT

VOLTAGE

S

CLOCK

OVP

UVP

OCP

PGNDx

ZERO CROSS

COMPARATOR

PSM LOGIC

PGND

ERROR AMP

OUTPUT

VOLTAGE

FBx

SW4

FB5

0.8V

FB4

POWER-GOOD

COMPARATOR

VREF

EXTERNAL

DISCHARGE

SWITCH

VOLTAGE DIVIDER

(CH4 ADJ MODE ONLY)

Figure 41. Buck Regulator Block Diagram: Channel 4 and Channel 5

Rev. A | Page 24 of 64

Data Sheet

ADP5080

Current-Limit Protection, Channel 4 and Channel 5

Buck Boost Configuration

Channel 4 and Channel 5 have integrated cycle-by-cycle current-

limit protection. In this type of current-limit protection, inductor

current is sensed throughout the high-side on cycle. If the

inductor current rises above the current-limit threshold during

this time, the switching pulse is immediately terminated until

the next cycle. This behavior causes the duty cycle to decrease,

which in turn causes the output voltage to fall. The falling output

For the buck boost configuration, set the BUCK6_ONLY bit

(Bit 4 in Register 30) to 0. The default value of this bit is factory

fuse programmed. For the buck boost configuration, connect

the inductor between the SW6A and SW6B pins (see Figure 42).

Make sure that no capacitor is connected to the SW6B pin.

In buck boost operation, Channel 6 automatically switches

between the buck and boost modes as the input voltage varies.

FAULT

voltage then toggles the PWRGx, UVx, and

error flags.



In buck mode, the primary FETs (SW6A) switch with the

SW6B high-side FET operating at 100% duty cycle.

Because there is substantial parasitic noise at the rising edge of

the high-side switch, some blanking time is required to prevent

false current-limit triggering. This required blanking time

determines the minimum on time of the channel.



In boost mode, all four FETs are typically switching, although

the primary high-side FET is capable of a 100% duty cycle.

When the input voltage is close to the output voltage, Channel 6

operates in buck boost mode with all four power FETs switching.

This four-switch mode of operation ensures a smooth transition

and excellent regulation, regardless of input voltage conditions.

Unlike valley mode current-limit protection, peak mode current-

limit protection has no inherent frequency foldback. In extreme

conditions such as a short circuit or inductor saturation, peak

mode current limit is susceptible to runaway inductor current.

To prevent this, the ADP5080 provides frequency foldback on

Channel 4, Channel 5, and Channel 6. When the output voltage

falls below approximately 80% of its nominal value, the switch-

ing frequency is halved. The frequency is halved again if the output

voltage falls below approximately 40% of its nominal value. The

frequency foldback feature allows more time for inductor current

to decay, eliminating the possibility of current runaway.

The BOOST6_VTH bits (Bits[1:0] in Register 30) set the input

voltage threshold for the boost FETs to start switching. A lower

threshold provides higher efficiency because the region where

all four switches are in operation is smaller. The lowest setting

for these bits (11) sets an input voltage threshold that is still high

enough to prevent dropout in most cases. However, under heavy

load current at the lowest threshold setting, the buck side may

reach a 100% duty cycle and some output droop may occur. The

second lowest setting for these bits (00) is recommended for heavy

load applications. The default value of these bits is factory fuse

programmed.

Table 3 provides the peak current-limit threshold specifications.

The actual load current-limit threshold varies with inductor

value, frequency, and input and output voltage.

Discharge Switch, Channel 4 and Channel 5

Selecting the Output Voltage, Channel 6

Each channel incorporates a discharge switch. For Channel 4, the

discharge switch is located at the SW4 pin; for Channel 5, the

discharge switch is located at the FB5 pin. The discharge switch

can be turned on when the corresponding channel output is turned

off, removing the residual charge of the external capacitor via a

125 Ω resistor. The discharge switch can be enabled by setting the

appropriate DSCGx_ON bit in Register 1.

The output voltage of Channel 6 is selected from one of the

preset values available in the VID6 bits (see Table 45). The

default output voltage value is factory fuse programmed.

Channel 6 has an adjustable mode option that can be selected

using the VID6 bits. When the adjustable output voltage mode

is selected, the output voltage is set by an external feedback

resistor divider. Select resistor values such that the desired output

voltage is divided down to 0.8 V while the paralleled resistance seen

from the dividing node does not exceed 25 kΩ (see the Setting

the Output Voltage (Adjustable Mode Channels) section).

Channel 6: Buck or Buck Boost Regulator

Channel 6 is a current mode control, four-switch buck boost

regulator that can be configured as a buck only regulator. In a

system in which the input voltage never falls below the Channel 6

output, using the buck only configuration reduces the losses

caused by the switching FETs of the boost side. The buck only

configuration yields better power efficiency, as well as lower

output ripple and noise.

Because Channel 6 can operate in boost mode, there is no practical

output voltage limitation other than the maximum rating. When

using the adjustable output voltage in buck only mode, be aware

of the minimum on time restriction, which may limit the range

of available output voltages. The minimum on time limitation is

essentially the same as for Channel 4 and Channel 5 (see the

Selecting the Output Voltage, Channel 4 and Channel 5 section).

Buck Only Configuration

For the buck only configuration, set the BUCK6_ONLY bit (Bit 4

in Register 30) to 1. The default value of this bit is factory fuse

programmed. When Channel 6 is configured for buck only mode,

connect the inductor between the SW6A and VOUT6 pins, leaving

the SW6B pin open (see Figure 42). This configuration bypasses

the boost side switching FET.

Rev. A | Page 25 of 64

ADP5080

Data Sheet

Current-Limit Protection, Channel 6

Discharge Switch, Channel 6

Like Channel 4 and Channel 5, Channel 6 has integrated cycle-

by-cycle current-limit protection. In this type of current-limit

protection, inductor current is sensed throughout the high-side

on cycle. The Channel 6 current limit is sensed on the primary

high-side FET (SW6A). For more information, see the Current-

Limit Protection, Channel 4 and Channel 5 section.

Each channel incorporates a discharge switch. For Channel 6,

the discharge switch is located at the VOUT6 pin. The discharge

switch can be turned on when the Channel 6 output is turned

off, removing the residual charge of the external capacitor via a

110 Ω resistor. The discharge switch can be enabled by setting

the DSCG6_ON bit in Register 1.

BUCK BOOST CONFIGURATION

VREG1

PGND6

VDR6

SW6A

SW6B

CURRENT SENSE

AND LIMIT

ADP5080

PVIN6

4V TO 15V

OCP

VOUT6

3.5V TO 5.5V

PGND6

BSTCP

PGND6

VOUT6

BST16

CONTROL

LOGIC

CONTROL

LOGIC

PGND6

PSM LOGIC

ZERO CROSS

COMPARATOR

DISCHARGE

SWITCH

CLOCK

S

Q

RS

FB6

LATCH

OVP

UVP

OCP

R

VOUT6

PWM

COMPARATOR

SLOPE

COMPENSATION

SEQUENCER

0.8V

FB6

POWER-GOOD

COMPARATOR

ERROR AMP

VREF

CLOCK

SOFT START

EXTERNAL

PGND6

VOLTAGE DIVIDER

(ADJ MODE ONLY)

BUCK ONLY CONFIGURATION

OPEN

SW6A

SW6B

VOUT6

ADP5080

3.5V TO 5.5V

PGND6

VOUT6

0.8V

FB6

EXTERNAL

VOLTAGE DIVIDER

(ADJ MODE ONLY)

Figure 42. Channel 6 Buck or Buck Boost Regulator Block Diagram

Rev. A | Page 26 of 64

Data Sheet

ADP5080

LIGHT LOAD AND OTHER MODES OF OPERATION

FOR THE DC-TO-DC CONVERTER CHANNELS

AUTO PSM

Each dc-to-dc converter channel in the ADP5080 has two or

three options to handle light load conditions, whereas asyn-

chronous dc-to-dc converters simply transition to discontinuous

conduction mode (DCM). Although light load modes provide

higher efficiency and longer battery life, they are also associated

with increased ripple and noise. This trade-off requires the user

to select the option that best suits the application, usually on a

channel by channel basis (see Table 9). The modes of operation

are illustrated in Figure 43, which shows the inductor current and

the switch node in auto PSM, auto DCM, and FPWM modes.

AUTO DCM

FPWM

Figure 43. Auto PSM, Auto DCM, and FPWM Operation (Switch Node and

Inductor Current Shown, Dashed Line Indicates 0 A)

Slew Rate Adjustment

Each channel has a slew rate adjustment option, which is set

using the ADJ_SRx bit (where x is 1 to 6) in the OPT_SR_ADJ

register (Register 31). When the ADJ_SRx bit is set, the switch

node slew rate for the channel is reduced, which in turn reduces

high frequency spike noise. Enabling this feature reduces the

efficiency of the channel, however, due to increased switching

losses. For this reason, use the slew rate adjustment feature only

when low output noise is critical.

100

90

80

70

60

50

AUTO PSM

AUTO DCM

FPWM

40

30

20

10

0

Forced PWM (FPWM) Mode

Forced pulse-width modulation (FPWM) mode maintains PWM

operation despite light load conditions, allowing negative current

to flow from the inductor through the low-side switching FET.

This mode is also referred to as continuous conduction mode

(CCM). The FPWM option has the lowest efficiency, but may

be selected when constant frequency and low ripple are absolutely

required, regardless of load.

0.01

0.1

OUTPUT CURRENT (A)

1

Figure 44. Efficiency of Auto PSM, Auto DCM, and FPWM Operation

Selecting Light Load Switching Modes

Auto DCM

Each dc-to-dc converter channel can be configured with its

own light load switching mode using the AUTO-PSMx bits

in Register 28 and, for Channel 5 and Channel 6, the DCM56

bit in Register 32 (see Table 10 and Table 11).

Automatic discontinuous conduction mode (auto DCM) is

available on Channel 5 and Channel 6. Auto DCM turns off the

low-side switching FET when the inductor current falls to zero

during the t_OFFperiod, preventing negative current from flowing

through the low-side FET. This operation is equivalent to that of

traditional flywheel diode-based PWM regulators. Auto DCM has

higher efficiency than FPWM mode because negative inductor

current is not allowed, but rather is recirculated to the input side.

At very light loads in auto DCM, some pulse skipping occurs and,

therefore, switching is not at a constant frequency.

Table 10. Light Load Switching Modes, Channel 1 to

Channel 4

AUTO-PSMx Bit Light Load Switching Mode

0

1

FPWM

Auto PSM

Table 11. Light Load Switching Modes, Channel 5 and

Channel 6

Auto PSM

Automatic power save mode (auto PSM) is similar to auto DCM,

except that it intentionally turns on the high-side FET with a fixed

period (approximately 80% of nominal t_ON). This operation forces

the regulator to skip a number of PWM cycles. Compared to auto

DCM, auto PSM skips a larger number of cycles and begins skip-

ping cycles at a higher load current. Auto PSM reduces switching

losses dramatically and improves efficiency, as shown in Figure 44.

However, in light load conditions, larger output voltage ripple

can be expected.

AUTO-PSMx Bit DCM56 Bit

Light Load Switching Mode

0

1

X¹

FPWM

Auto PSM

Auto DCM

0

1

¹X = don’t care.

Rev. A | Page 27 of 64

ADP5080

Data Sheet

Selecting the External Resistor

SWITCHING CLOCK

An external 100 kΩ resistor from the FREQ pin to GND is

required for the internal clock source oscillator. To obtain an

accurate clock frequency, select a high precision resistor with

a low temperature coefficient. A 1 nF bypass capacitor is also

recommended at the FREQ pin.

The ADP5080 integrates a highly accurate switching clock for the

dc-to-dc converters and the charge pump. As shown in Figure 45,

the internal clock can also be bypassed and the system synchro-

nized to an external clock. When the internal clock source is

used, the switching frequency for each dc-to-dc converter and

the charge pump can be configured.

Phase Shifting

PHASEx

EN_CLKO

Each dc-to-dc converter can be configured to use the inverted

phase of the master clock by setting the PHASEx bit (where x is

1 to 6) in Register 20. Setting channels out of phase with each

other helps reduce rms current stress on the input capacitors and

spreads switching energy over two cycles. Phase shifting reduces

possible interference in a system due to propagated switching

noise on the input rail.

FREQx

SYNC

DETECTOR

CLKO

1/2

CH1

SYNC

CH2

SEL_FSW

CH3

CH4

CH5

When any channel is operated at 1/2 × f_SW, the higher frequency

channel must be set out of phase to have any effect on the

apparent phase of the lower frequency channel (see Figure 46).

CLOCK

SOURCE

2.0MHz (0)

OR

1

2

1

2

1.5MHz (1)

FREQ

CH6

MASTER CLOCK

R

OSC

100kΩ

1/2

1/8

CHARGE

PUMP

IN PHASE

2MHz

FREQ_CP[1]

FREQ_CP[0]

3

SYNC

DETECTOR

OUT OF PHASE

Figure 45. Switching Clock Distribution

External Synchronization Mode

IN PHASE

1MHz

When an external clock is present at the SYNC pin, all dc-to-dc

converters and the charge pump automatically use it as their

master switching clock; the FREQx bit settings in Register 18 are

ignored. When using external synchronization mode, ensure

that the external clock is already stable before the EN signal is

asserted to avoid unexpected behavior in the converters. When

an external clock is used, the clock must operate within the

specifications listed in Table 1.

OUT OF PHASE

Figure 46. Switching Phase Relationships

Any channel at 1 × f_SWhas the expected, set phase relationship to

the master clock. However, when a channel operates at 1/2 × f_SW

it always appears to be in phase with the master clock and with

any in-phase channel at 1 × f_SW. This relationship is illustrated

by the lines labeled 1 and 2 in Figure 46; regardless of the phase

setting, Line 1 or Line 2 is always aligned to the rising edge.

,

Selecting the Internal Clock Frequency

If the SYNC pin is tied high or low, the device uses the internal

clock. The internal oscillator generates a master clock at either

2.0 MHz or 1.5 MHz, as specified by the SEL_FSW bit in

Register 18. The internal clock is active when EN is high.

To set a channel operating at 1/2 × f_SWout of phase, the highest

frequency channel must be set out of phase. Referring to the lines

labeled 3 in Figure 46, the channel operating at 1/2 × f_SWis now

out of phase with the channel operating at 1 × f_SW, regardless of

the phase setting.

The master clock is divided down by half so that each dc-to-dc

converter can select 1× or 1/2× the master clock frequency. The

frequency of each channel is set using the FREQx bit (where x is

1 to 6) in Register 18. For example, if the master clock is set to

1.5 MHz, Channel 1 through Channel 6 can be configured to

operate at 750 kHz or 1.5 MHz, but not at 1 MHz or 2 MHz.

CLKO Pin

The clock output (CLKO) pin can output the internal switching

clock used for Channel 1. The output is enabled by setting the

EN_CLKO bit in Register 19 to 1. The CLKO output stays low

when external clocking is used or when the EN_CLKO bit is set

to 0.

For the charge pump, the FREQ_CP bits set the switching

frequency (see the Charge Pump Switching Frequency section).

Rev. A | Page 28 of 64

Data Sheet

ADP5080

OUTPUT

+ V

SOFT START FUNCTION

V

VBATT

VDR5

BSTCP

PVINCP

To provide controlled output voltage ramping on startup, the

ADP5080 incorporates soft start control for each dc-to-dc con-

verter. The ramp-up period to reach the target voltage can be

set to 1 ms, 2 ms, 4 ms, or 8 ms using the SSx bit (where x is 1

to 6) in Register 2 or Register 3. The default soft start values

are factory fuse programmed. It is not recommended that the

ADP5080 be started up into a full load condition.

BSTx

C

OUT

1µF

VBATT

C+

C–

C

1µF

FLY

CHANNEL 7: HIGH VOLTAGE LDO REGULATOR

The ADP5080 integrates a high voltage LDO linear regulator,

which allows input voltages up to 25 V (see Figure 47). The

LDO regulator outputs one of four preset regulated voltages

and is capable of providing up to 30 mA.

VDR5

CLOCK

PGND5

ADP5080

SEQUENCER

Figure 48. Charge Pump for BSTx Supply

POWER-GOOD

COMPARATOR

The charge pump requires a minimum VBATT voltage to start

up. In some cases, the start-up threshold, which is 4 V typical,

may be higher than the rising UVLO threshold.

PROGRAMMABLE

SOFT START

UP TO

25V

5V TO 12V

AGND

VILDO7

VOLDO7

If the BSTCP voltage drops approximately 2.5 V below the

nominal value, the ADP5080 shuts down to prevent abnormal

switching. An OVP or UVP fault is not indicated in this case.

CURRENT

DETECTION

AGND

Charge Pump Switching Frequency

CURRENT

LIMIT

DISCHARGE

SWITCH

The internal clock source generates either 2.0 MHz or 1.5 MHz,

as set by the SEL_FSW bit in Register 18. This master frequency

is further divided by 1/2, 1/4, 1/8, or 1/16 by the FREQ_CP bits

in Register 19 (see Table 53). If the master clock frequency is set

to 2.0 MHz, the charge pump switching clock frequency can be

1.0 MHz, 500 kHz, 250 kHz, or 125 kHz. If the master frequency

is set to 1.5 MHz, the charge pump switching clock frequency can

be 750 kHz, 375 kHz, 188 kHz, or 94 kHz. Typically, a setting of

1/4 in 1.5 MHz operation or 1/8 in 2 MHz operation is recom-

mended for the best efficiency. Lower settings may not provide

enough boost voltage when all channels are operating at load.

VREF

UVP

Figure 47. High Voltage LDO (Channel 7)

Selecting the Output Voltage, Channel 7

The output voltage of Channel 7 is selected from one of the

preset values (12 V, 9 V, 6 V, or 5 V) using the VID7 bits in

Register 16. The default value is factory fuse programmed.

Discharge Switch, Channel 7

If an external clock is used, the charge pump frequency can be set

to 1/4 or 1/8 of the external frequency using the FREQ_CP bits.

Charge pump efficiency is slightly affected by the duty cycle of the

external clock; a 50% duty cycle is the optimal point of operation.

Each channel incorporates a discharge switch. For Channel 7,

the discharge switch is located at the VOLDO7 pin. The dis-

charge switch can be turned on when Channel 7 is turned off,

removing the residual charge of the external capacitor via an

internal 1 kΩ resistor. The discharge switch can be enabled by

setting the DSCG7_ON bit in Register 1.

Capacitor Selection

A 1 µF capacitor is used for each charge pump capacitor (C_FLY

and C_OUT; see Figure 48). The voltage rating of these capacitors

must be adequate for the charge-up voltage, that is, the PVINCP

CHARGE PUMP

The ADP5080 includes an integrated charge pump, which

provides power to the high-side switching NMOS FET driver

(see Figure 48). The charge pump raises the voltage applied to

the PVINCP pin by the VDR5 pin voltage, making the voltage

available at the BSTCP pin. In a typical application, the PVINCP

pin is supplied by the battery (VBATT), and the VDR5 pin is

supplied by VREG1 (5 V or 5.5 V). Thus, the output voltage at

the BSTCP pin is VBATT + 5 V or 5.5 V, which is ideal for driving

the high-side FET driver supply pin for each channel, BSTx.

pin voltage across C_FLYand the VDR5 pin voltage across C_OUT

.

Protection Diode

It is strongly recommended that a protection diode be mounted

as shown in Figure 48 to avoid problems during power-up while

the BSTCP voltage is charging. Use a Schottky diode that can

withstand a 1 A peak current.

Rev. A | Page 29 of 64

ADP5080

Data Sheet

Using the Charge Pump as the Channel 7 Input Supply

Note that Figure 50 shows the logical states of each channel; it

does not show soft start and discharge ramps. The disable delay

time for all channels can be increased to four times its configured

value by setting the DIS_DLY_EXTEND bit in Register 35.

The charge pump can also be used to generate a high voltage for

the Channel 7 input. This configuration is enabled by adding the

circuit shown in Figure 49 in parallel with the BSTx generating

circuit shown in Figure 48.

When all channels controlled by the sequencer are turned

on, each channel can be manually turned off or on using the

CHx_ON bit (x is 1 to 7) in Register 48. When the CHx_ON

bit is used to turn a channel on or off, the enable state of the

channel changes immediately, regardless of the settings of the

EN_DLYx and DIS_DLYx bits.

BSTCP

VILDO7

V

+ 2V

PVINCP

VDR5

1µF

C+

PVINCP

When using the sequencer mode, note the following:

Figure 49. Charge Pump Used as a High Voltage Supply for Channel 7

•

A channel that is controlled by the sequencer cannot be

turned off manually until after the sequencer turns on all the

channels that it controls and the soft start period has ended.

This ready state can be identified by reading the PWRGx

bits (x is 1 to 7) in Register 24.

After the EN pin is asserted, writing to the VIDx bits is

forbidden while the internal sequencer is in operation to

prevent unexpected behavior. The internal sequencer is in

operation from the assertion of the EN pin until the PWRGx

bits in Register 24 go high.

The circuit shown in Figure 49 generates VILDO7 with the

voltage V_PVINCP+ 2 × V_VDR5. In a typical application, this voltage

is equivalent to V_VBATT+ 10 V to 11 V (PVINCP = VBATT;

VDR5 = VREG1 = 5.5 V or 5 V).

ENABLING AND DISABLING THE OUTPUT

CHANNELS

•

Each channel (Channel 1 to Channel 7) can be turned on and

off using the sequencer mode or the manual mode. A channel

configured for sequencer mode is automatically turned on and

off by assertion and deassertion of the EN pin, with individually

programmed delay times. A channel configured for manual mode

does not automatically start when EN goes high, but can be turned

on or off via I²C control, as required.

Manual Mode

When the MODE_ENx bit (x is 1 to 7) is cleared in Register 29,

the specified channel turns on and off under I²C control. All

channels that are not configured for sequencer mode can be

manually turned on or off using the CHx_ON bits (x is 1 to 7)

in the PCTRL register (Register 48). Writing 1 to the CHx_ON

bit enables the channel only when the EN pin is logic high.

Sequencer Mode

When the MODE_ENx bit (x is 1 to 7) is set in Register 29, the

specified channel turns on and off under the control of the internal

sequencer, which is triggered by the EN pin (see Figure 50).

When the EN pin is taken low, all channels configured for

manual mode turn off immediately, and all the CHx_ON bits

are reset to 0. While the EN pin is low, any data written to or

read from the CHx_ON bits is not valid.

When the EN pin goes high, each channel controlled by the

sequencer begins a soft start after the delay time specified by the

EN_DLYx bits (see Table 23, Table 25, Table 27, and Table 29).

Similarly, when the EN pin goes low, the channel turns off after

the delay time specified by the DIS_DLYx bits (see Table 31,

Table 33, Table 35, and Table 37).

EN

t_{DIS_DLY1}

t_{DIS_DLY2}

t_{DIS_DLY3}

t_{DIS_DLY4}

t_{EN_DLY1}

ON

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

OFF

t_{EN_DLY2}

t_{EN_DLY3}

t_{EN_DLY4}

t_{EN_DLY5}

t_{DIS_DLY5}

t_{DIS_DLY6}

t_{EN_DLY6}

t_{EN_DLY7}

t_{DIS_DLY7}

Figure 50. Example Power-Up/Power-Down Sequence Using Sequencer Mode

Rev. A | Page 30 of 64

Data Sheet

ADP5080

EN Function

POWER-GOOD FUNCTION

The EN pin has an internal pull-down resistor that holds the

ADP5080 in standby mode until the pin is actively pulled high.

The EN function does not take effect until the device is ready

for operation, that is, until all the following conditions are met:

The power-good status of each channel (PWRGx bit) can be

read back from the PWRG register (Register 24). A value of 1

for the PWRGx bit indicates that the regulated output voltage of

Channel x is within 85% to 125% of its nominal value. When

the regulated output voltage of a channel falls below this level,

the PWRGx bit is set to 0. As shown in Figure 51, hysteresis is

applied to both the upper and lower boundaries to minimize

power-good chattering.



VBATT pin voltage (V_{UVLO (BATT)}) is above 3.3 V.

VREG1 pin voltage is within the specified range.

VREG2 pin voltage (V_{UVLO (POR)}) is within the specified

range.

V

OUT



Device is not in thermal shutdown.

125%

123%

Internal oscillator is stable (typically 250 μs).

PVIN1 pin voltage (V_{UVLO (R)}) is above 3.7 V.

VDR12 pin voltage is above 2.95 V.

CHx OUTPUT

85%

82%

If any of these conditions are not met during operation, the

ADP5080 shuts down, as described in the UVLO and POR

section.

PWRGx

(x = 1 TO 7)

Figure 51. Power-Good Status Bit

EN34 Function

The EN34 pin allows Channel 3, Channel 4, or both channels

to be independently enabled and disabled using the EN34 pin.

This functionality can be enabled on either or both channels

using the DIS_EN34_CHx bits (x is 3 or 4) in Register 35.

FAULT FUNCTION

FAULT

The

pin is an open-drain output that indicates the

logical OR status of the PWRGx bits for all channels. When any

FAULT

PWRGx bit = 0, the

pin goes low. As shown in Figure 52,

has approximately 70 ms of blanking time after EN is

asserted to allow for the enable delay and soft start times. After

FAULT

When the DIS_EN34_CHx bit is set low, the channel is not

turned on until both the EN and EN34 pins are high. If Channel 3

or Channel 4 is in sequencer mode, EN34 must be high before EN

goes high to maintain the enable delay timing on the channels

(see the Sequencer Mode section). If EN is high when the EN34

pin is taken high, Channel 3 or Channel 4 is immediately enabled

or disabled, regardless of whether the channel is configured for

manual mode or sequencer mode.

FAULT

the blanking period, a PWRGx low bit causes

to go low

remains low until the EN pin is toggled or

power is cycled. If an OVP or UVP condition at startup forces a

FAULT

immediately.

FAULT

shutdown before the

not go low.

blanking period ends,

does

VBATT

When the DIS_EN34_CHx bit is set high, Channel 3 or

Channel 4 is enabled and disabled in the same way as all the

other channels in the device, and the EN34 pin has no effect

on the operation of the channel.

EN

Σ

PWRGx

Regardless of the state of the DIS_EN34_CHx bits, disabling

TIMEOUT

COUNTER

FAULT

Channel 3 and Channel 4 does not cause

to go low (see

70ms

RESET

the Fault Function section). This means that the power-good

flags for Channel 3 and Channel 4 do not need to be masked.

FAULT

Figure 52.

Function

FAULT

goes low only when Channel 3 or Channel 4 is enabled

If a channel is not enabled manually or via the sequencer, the

FAULT

using the CH3_ON or CH4_ON bit and the PWRG3 or PWRG4

bit subsequently goes low.

PWRGx bit remains low. This forces

low unless the

channel is masked by the MASK_PWRGx bit in Register 25.

This does not apply to Channel 3 and Channel 4, as described

in the EN34 Function section.

Rev. A | Page 31 of 64

ADP5080

Data Sheet

EN

MASK_PWRG1

PWRG1

PWRG2

MASK_PWRG2

MASK_PWRG3

MASK_PWRG4

PWRG3

TIMEOUT

LOGIC

CH3_ON

FAULT

1

0

PWRG4

CH4_ON

1

0

D

Q

MASK_PWRG5

MASK_PWRG6

0

PWRG5

PWRG6

R

VBATT_UVLO

MASK_PWRG7

PWRG7

Figure 53. Fault Function Logic Diagram

Table 12. Channel 5 Standalone Undervoltage Detection Option

Undervoltage Detected

Any Channel Other

SEL_IND_UV5 Bit Than Channel 5

Channel 5

Yes

No

Yes

No

Output

0

Yes

No

Yes

No

All channels shut down

All channels are operational

All channels shut down

1

Yes

No

Yes

No

Channel 5 shuts down; all other channels are operational

All channels are operational

V

OUT

UNDERVOLTAGE PROTECTION (UVP)

65%

The ADP5080 incorporates undervoltage protection (UVP) on

Channel 1 to Channel 7. When the output of any channel falls

below 65% of the specified voltage, UVP shuts down all seven

channels by internally resetting the CHx_ON bits in Register 48.

Channel 5 can be configured for standalone undervoltage pro-

tection (see the Channel 5 Standalone Undervoltage Detection

Option section).

SHUTDOWN

TIME

Δt

< UV_DLY

Δt = UV_DLY

CHx_ON

(x = 1 TO 7)

UVP Detection Delay

Undervoltage detection includes a debounce delay, which is

configured in Register 23 (see Table 57). The undervoltage

condition is recognized only after it continues for the period

specified by the UV_DLY bits in Register 23 (see Figure 54).

Setting the UV_DLY bits to 11 disables UVP.

UVx

(x = 1 TO 7)

Figure 54. Undervoltage Detection Delay

Channel 5 Standalone Undervoltage Detection Option

If desired, undervoltage protection on Channel 5 can be isolated

from UVP on all the other channels. When the SEL_IND_UV5

bit is set high in Register 34, an undervoltage condition on

Channel 5 causes only Channel 5 to be shut down (see Table 12).

If this option is selected, the UV_DLY5 bits in Register 34 can

be used to set a UVP detection delay for Channel 5 only.

Rev. A | Page 32 of 64

Data Sheet

ADP5080

Recovering from UVP

Recovering from OVP

After the cause of the undervoltage condition is removed, the

outputs can be recovered by toggling EN from low to high. If

standalone Channel 5 undervoltage shutdown is enabled (by

setting the SEL_IND_UV5 bit in Register 34), Channel 5 can

be recovered by setting the CH5_ON bit in Register 48 to 1.

After the cause of the overvoltage condition is removed, the

outputs can be recovered by toggling EN from low to high.

The overvoltage status of a channel is stored in the OVPST

register (Register 27) after shutdown and can be read back

from the OVx bit in Register 27. The OVx bit is cleared by

writing a 1 to it.

The undervoltage status of a channel is stored in the UVPST

register (Register 26) after shutdown and can be read back from

the UVx bit in Register 26. The UVx bit is cleared by writing a

1 to it.

SHUTDOWN

V

OUT

125%

OVERVOLTAGE PROTECTION (OVP)

TIME

The ADP5080 incorporates overvoltage protection (OVP)

on Channel 1 to Channel 6. When the output of any of these

channels rises above 125% of the specified voltage, OVP shuts

down all six channels by internally resetting the CHx_ON bits

in Register 48.

Δ

t

< OV_DLY

Δt = OV_DLY

CHx_ON

(x = 1 TO 6)

OVP Detection Delay

Overvoltage detection includes a debounce delay, which is

configured in Register 23 (see Table 57). The overvoltage

condition is recognized only after it continues for the period

specified by the OV_DLY bits in Register 23 (see Figure 55).

Setting the OV_DLY bits to 11 disables OVP.

OVx

(x = 1 TO 6)

Figure 55. Overvoltage Detection Delay

Rev. A | Page 33 of 64

ADP5080

Data Sheet

APPLICATIONS INFORMATION

This section provides component and PCB layout guidelines

to ensure optimal device performance, efficiency, stability, and

minimal switching noise and crosstalk.

Note that ripple current varies with input voltage. The typical

input voltage can be used to determine the inductor value.

However, to avoid inductor saturation and current limit, also

calculate the inductor value with the worst-case input voltage

(V_INmax).

COMPONENT SELECTION FOR THE BUCK AND

BUCK BOOST REGULATORS

The maximum rated current of the selected inductor (both rms

current and saturation current) must be greater than the peak

inductor current (I_PEAK) at the maximum load current. If the rating

of the inductor is not sufficient, the inductor may saturate due to

inductor value degradation, causing it to reach the current limit,

even in a lower load condition than expected.

Setting the Output Voltage (Adjustable Mode Channels)

Channel 3, Channel 4, and Channel 6 can be configured for an

adjustable output voltage. Table 9 provides the adjustable output

voltage range for these channels. When any of these channels is

configured for adjustable mode, connect a resistor divider to the

FBx pin between V_OUTand GND, as shown in Figure 56.

The peak current can be estimated using Equation 3.

V

OUT

I

_PEAK= I_LOAD+ (I_RIPPLE/2)

(3)

(4)

R

FB_TOP

FB_BOT

If the 30% ripple guideline is followed, typical peak current is

simplified as follows:

FBx

R

I

_PEAK= (I_LOAD+ 0.15) × I_LOAD= 1.15 × I_LOAD

Another important specification to consider is the parasitic

Figure 56. Feedback Resistors for Adjustable Output

series resistance in the inductor: dc resistance (DCR). A larger

DCR decreases efficiency, but a larger size inductor typically has

lower DCR. Therefore, the trade-off between available space on

the PCB and device performance must be considered carefully.

The resistor values can be calculated as follows, where 0.8 V

is the typical FB voltage, and 20 kΩ is a good typical value for

R_{FB_BOT}

.

Equation 1 to Equation 4 apply to the buck regulators. Although

Channel 6 is a buck boost regulator, the inductor value can be

determined using the buck regulator mode of operation given

that the available step-up ratio in boost mode is relatively small

(4 V at the PVIN6 pin to 5.5 V at the VOUT6 pin) compared to

the available step-down ratio. Therefore, an inductor value selected

for buck regulator mode typically works equally well in boost

regulator mode.

(

V_OUT− 0.8V × R_{FB _ BOT}

)

R_{FB _TOP}

=

0.8V

Note that changing the output voltage often requires a change

to the inductor (L) and output capacitor (C_OUT) values. After the

_OUTvalue is selected, calculate and test the L and C_OUTvalues

(see the Selecting the Inductor section and the Selecting the

Output Capacitor section).

V

Selecting the Inductor

Table 13 lists recommended inductor values for a range of volt-

ages and frequencies. The values provided are based on a wide

operating range and assume the maximum load current for each

channel. In the actual application, larger or smaller values may be

more appropriate. In general, the inductor value can be increased

or decreased by one standard value from the recommended 30%

ripple guideline. A larger inductance provides higher efficiency,

whereas smaller values results in better transient response and

a smaller footprint. Note that inductor values much smaller or

larger than the ones recommended in Table 13 may cause control

loop instability.

The required inductor value can be determined by the input and

output voltages, the switching frequency, and the ripple current,

as shown in Equation 1.

V_IN− V_OUT

V_OUT

V_IN

1

L =

×

(1)

I_RIPPLE

f_SW

where:

L is the inductor value.

f

I

_SWis the switching frequency.

_RIPPLEis a peak-to-peak value for the ripple current.

It is also important to note that because the current-limit pro-

tection monitors peak or valley current, the selected inductance

affects the load current level at which current limit is triggered.

In general, the recommended ripple current is 30% of the maxi-

mum load current. Therefore, Equation 1 can be rewritten as

follows:

V_IN− V_OUT

0.3 × I_LOAD

V_OUT

V_IN

1

L =

×

(2)

f_SW

Rev. A | Page 34 of 64

Data Sheet

ADP5080

Table 13. Suggested Inductors

Channel

V_OUT(V)

Frequency (kHz)

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

750 or 1000

1500 or 2000

Inductance (µH)

Part Number

1

<1.0

1

Toko FDSD0420-H-1R0

Toko FDSD0420-H-R47

Toko FDSD0420-H-1R5

Toko FDSD0420-H-R68

Toko FDSD0420-H-4R7

Toko FDSD0420-H-2R2

Taiyo Yuden NRS4018T6R8M

Toko FDSD0420-H-3R3

Toko FDSD0420-H-1R5

Toko FDSD0420-H-3R3

Toko FDSD0420-H-1R5

Taiyo Yuden NRS4018T6R8M

Toko FDSD0420-H-3R3

Taiyo Yuden NRS4018T100M

Toko FDSD0420-H-4R7

Toko FDSD0420-H-3R3

Toko FDSD0420-H-2R2

Toko FDSD0420-H-3R3

Toko FDSD0420-H-1R5

Toko FDSD0420-H-4R7

Toko FDSD0420-H-2R2

Toko FDSD0420-H-4R7

Toko FDSD0420-H-3R3

0.47

1.5

0.68

4.7

2.2

6.8

3.3

1.5

3.3

1.5

6.8

3.3

10

4.7

3.3

2.2

3.3

1.5

4.7

2.2

4.7

3.3

1.0 to 1.2

<1.8

2

3

4

5

6

1.8 to 3.3

<1.5

1.5 to 1.8

<2.5

2.5 to 3.55

<4

4 to 5

<4.5

4.5 to 5.5

Selecting the Input Capacitor

Selecting the Output Capacitor

Step-down switching regulators draw current from the input

supply in pulses that have very fast rise and fall times. Low ESR

ceramic input capacitors are required to reduce the input voltage

ripple and provide bypass for high frequency switching noise. If

not well bypassed, the input noise can cause poor device perfor-

mance, instability, and increased conducted and radiated emissions

(EMI).

The output capacitor is important for regulator operation

because it affects the loop stability, output voltage ripple, and

load transient response.

The ADP5080 is designed to operate with low ESR ceramic

output capacitors. Higher output capacitor values reduce the

output voltage ripple and improve load transient step response.

When choosing an output capacitor value, it is also important to

account for the loss of capacitance due to output voltage dc bias.

Each switching channel should have approximately 10 µF of

input bypass capacitance. Place the input capacitors as close

as possible to the PVINx and PGNDx pins. Place an additional

ceramic input capacitor at VBATT. It is usually beneficial to use

multiple capacitors in parallel instead of a single high value

capacitor.

Table 14 lists the minimum recommended capacitor values for

each channel. Note that the capacitor values shown in Table 14

are nominal values, not derated values. The capacitors listed

work for the full range of operating frequency and load.

Lower values can be used at higher frequency or lighter load

currents. However, exercise caution when using values smaller

than the minimum recommended values; too small an output

capacitor can result in unstable operation. Output capacitance

can typically be increased with no practical limit without causing

stability problems. Greater capacitance improves ripple and

transient performance.

Note that ceramic capacitors have very strong dc bias character-

istics and lose as much as 80% of their capacitance value at the

rated voltage. Also, note that the rise in case temperature due to

rms current in the input capacitor can be quite high on the input

of a buck regulator. For these reasons, capacitors of X5R and X7R

type or better are recommended. A good estimate for the rms

current in the input capacitor of a single channel is

I_LOAD

×

V_OUT× (V_IN− V_OUT)

I_RMS

=

V_IN

Rev. A | Page 35 of 64

ADP5080

Data Sheet

Table 14. Minimum Recommended Output Capacitors

PCB LAYOUT RECOMMENDATIONS

Channel

Output Capacitor (µF)

Proper printed circuit board (PCB) layout is essential for optimal

device performance and thermal dissipation, and to minimize

switching noise and electromagnetic interference (EMI). A few

key layout guidelines are provided in the following sections.

1

2

3

4

5

6

44

33

44

Sensitive Signal Treatment

It is important to isolate sensitive signal traces from noisy

switching traces. The FBx pins and the FREQ pin are sensitive

to noise coupling and should be routed away from noise sources.

Any node with high dV/dt—such as SWx, BSTx, and SCL—is

considered a noise source.

Ceramic capacitors are manufactured with a variety of dielectrics,

each with different behavior over temperature and applied voltage.

Capacitors must have a dielectric that is adequate to ensure the

minimum capacitance over the necessary temperature range and

dc bias conditions. X5R or X7R dielectrics with a voltage rating

of at least 2 × V_OUTare recommended for best performance.

Additional noisy circuit areas to avoid are the main areas of high

switching current: primarily the input capacitors and PGNDx

connections. Finally, do not route sensitive nodes below or near

the inductors. If a sensitive signal trace must cross a noisy source,

it is recommended that at least one PCB ground layer be placed

between these signal traces as a shield.

The peak-to-peak output voltage ripple for the selected output

capacitor and inductor values is calculated using Equation 5.

V_IN

I_RIPPLE

V_RIPPLE

=

(5)

(2π × f_SW) × 2 ×L × C_OUT

8 × f_SW× C_OUT

Grounding

It is recommended that the analog ground (AGND) and power

ground (PGND) planes be separated. The AGND plane is used

for the device reference voltage; therefore, it should be as quiet as

possible and not used as a current path. The PGND plane serves

as the current return path for the regulators. PGND can be very

noisy due to the flow of current, as well as the presence of switch-

ing noise. Therefore, care must be taken with the connection

of the AGND and PGND planes so that currents flowing in the

PGND plane do not intrude on the AGND region. Connect the

AGND and PGND planes at a single point, preferably at the device.

High ESR capacitors are not recommended because they increase

output ripple and can cause loop instability. Equation 5 assumes

ceramic capacitors and does not include ESR.

For optimal performance, place output capacitors to minimize

PCB parasitics. Connect capacitor pads directly to the output

and GND power paths, not via separate traces. For purposes of

high frequency noise reduction, it can be beneficial to use multiple

capacitors in parallel instead of a single high value capacitor.

Because Channel 6 operates in buck boost mode, the output

capacitors see large switching currents. Therefore, placement of

the output capacitors requires additional attention. Make sure

to place the output capacitors as close as possible to the VOUT6

and PGND6 pins of Channel 6.

The PGNDx nodes are part of the regulation loop for each

switching regulator and carry fast switching currents. Therefore,

it is critical that the PGNDx regions for each switching regulator

be separated and connected to the PGND plane at the output

capacitor ground. This prevents interference from adjacent

channels and helps contain switching noise. Multiple vias are

recommended for the connection between the PGNDx regions

and the PGND plane.

COMPONENT SELECTION FOR THE LDO

REGULATORS

Selecting the Capacitors

Use low ESR capacitors for all LDO input and output capacitors.

Lower ESR reduces the output impedance and ripple voltage.

High ESR capacitors are not recommended due to ripple and

stability of the LDO control loop. Therefore, it is recommended

that surface-mount ceramic capacitors be used. The X5R and

X7R type of capacitor is preferable for adequate performance.

To improve thermal performance and noise immunity, each

AGND or PGND layer should have as much copper coverage

as possible.

Use an output capacitor with a value from 2.2 µF to 10 µF

for VREG2. Values of 4.7 µF to 10 µF are recommended for

VREG1; 4.7 µF is the minimum requirement for stability.

For the Channel 7 high voltage LDO regulator, the minimum

required output capacitor value for the VOLDO7 pin is 1 µF.

Because Channel 7 is a high voltage output, make sure to account

for capacitor bias voltage derating. If the charge pump doubler

circuit is used as the input supply to Channel 7, the maximum

recommended value for the Channel 7 output capacitor is 3.3 µF.

This is to prevent overloading the charge pump during startup.

Rev. A | Page 36 of 64

Data Sheet

ADP5080

External Component Placement and Signal Routing

The rise in junction temperature is directly proportional to the

power dissipation in the device, as shown in Equation 7.

The majority of the critical switching regulator pins are located

on the outer bumps of the device, making it easier to lay out and

connect to the external components. In general, make traces that

handle large current as wide and short as possible. This consid-

eration applies to the traces for PVINx, SWxA, SWxB, SWx,

PGNDx, and VOUT6.

T_R= PD_LOSS× θ_JA

where:

PD_LOSSis the power dissipation in the ADP5080.

_JAis the junction-to-ambient thermal resistance of the package

mounted on a PCB.

(7)

θ

Make traces that handle switching currents as short as possible.

These critical areas are PVINx, SW6B, VOUT6, and PGNDx.

Reducing the trace length on these nodes helps mitigate noise

coupling. For these connections, avoid using vias because they

add parasitic inductance in the current path. If vias are required

due to routing restrictions, place multiple vias in parallel.

The θ_JAvalue provided in Table 7 is for a JEDEC standard board.

However, this value is only a benchmark and does not necessarily

correlate to the thermal performance of a real-world PCB.

The thermal performance of the WLCSP package itself is given

by the θ_JBvalue (see Table 7). This value is the thermal resistance

from junction to solder ball and varies little with PCB design.

For the buck regulators, the input capacitor has placement

priority. Place the input capacitor as close as possible to the PVINx

and PGNDx pins with wide trace connections. For Channel 6, the

critical component connections are the input capacitor and the

output capacitor. Connect these components as close as possible

to the PVIN6, VOUT6, and PGND6 pins.

To determine the junction temperature, it is recommended that

the ADP5080 case temperature be measured under worst-case

conditions. The case temperature (T_C) is defined as the temper-

ature on the top surface of the device and can be calculated using

Equation 8.

T_C= T_A+ PD_LOSS× (θ_JA− θ_JC)

where:

_JCis the junction-to-case thermal resistance of the package,

which is 0.2°C/ W.

(8)

For all channels, keep the SWx pin to inductor connection as

short as possible to minimize capacitive coupling. Because the

SWx nodes carry high current, the traces must be wide enough

to handle it.

θ

Because θ_JCis very low, it can be seen from Equation 9 that the

measured value of T_Cis a good approximation of T_J.

THERMAL CONSIDERATIONS

The ADP5080 is a high efficiency power converter. However, in

applications with heavy loads at high ambient temperature (T_A),

the heat dissipated on the device may exceed the maximum

junction temperature of 125°C. If the junction temperature (T_J)

exceeds 165°C, the ADP5080 enters thermal shutdown (TSD),

and all outputs are disabled. When the junction temperature

falls below approximately 150°C, TSD is cleared. After a TSD

event, the ADP5080 does not restart automatically, but must be

reenabled with the EN pin.

T_J= T_C+ T_R= T_C+ PD_LOSS× θ_JC≈ T_C

(9)

The estimated junction temperature or measured case tempera-

ture in worst-case conditions must be less than the maximum

junction temperature of 125°C.

The junction temperature can be calculated using Equation 6.

T_J= T_A+ T_R

(6)

where T_Ris the rise in junction temperature of the device due

to power dissipation.

Rev. A | Page 37 of 64

ADP5080

Data Sheet

I²C INTERFACE

The ADP5080 includes an I²C-compatible serial interface to

control the power management blocks and to read back system

status. The I²C serial interface provides access to the internal

registers of the ADP5080. For detailed information about the

registers, see the Control Register Information section.

Note that the SCL pin must be pulled high to VDDIO during

power-up so that the programmed fuse settings are properly

loaded into the I²C registers at power-on reset (POR). This

restriction does not apply as long as VDDIO is low. If VDDIO is

supplied by VREG2, SCL must be high impedance until VREG2

rises above the POR threshold. If VDDIO is supplied by an external

I²C host, either SCL must be held high or the VDDIO supply must

be off until the VREG2 voltage rises above the POR threshold.

I²C ADDRESS

The 7-bit I²C chip address for the ADP5080 is 0x30 (011 0000);

the subaddress is used to select one of the user registers, through

which the I²C master communicates with the ADP5080.

All registers programmed by the I²C interface are cleared and reset

to their default values by a power-on reset (see the Power-On

Reset (POR) section). The CHx_ON bits in the PCTRL register

(Register 48) are cleared by a power-on reset or by taking the

EN pin low.

The I²C interface operates at clock frequencies of up to 400 kHz.

The ADP5080 does not respond to general calls. The ADP5080

accepts multiple masters, but if the device is in read mode, access

is limited to one master until the data transmission is completed.

SELF-CLEARING REGISTER BITS

Register 26 and Register 27 are status registers that contain

self-clearing register bits. These bit are cleared automatically

when a 1 is written to the status bit. Therefore, it is not necessary

to write a 0 to the status bit to clear it.

SDA AND SCL PINS

The ADP5080 has two dedicated I²C pins: SDA and SCL. SDA

is an open-drain line for receiving and transmitting data. SCL is

an input line for receiving the clock signal. These buses must be

externally pulled up to the VDDIO supply.

I²C INTERFACE TIMING DIAGRAMS

Figure 57 is a timing diagram for the I²C write operation.

Figure 58 and Figure 59 are timing diagrams for the I²C read

operation. Register 48 (PCTRL register) has a special status flag

in Bit 7 that indicates the presence of valid data in this register (see

Figure 59). If Bit 7 = 0, the data is not yet valid, and the read

operation must be repeated until the status bit changes to 1.

Serial data is transferred by the SCL rising edge. The read data

is generated at the SDA pin in read mode. If the V_VDDIOvoltage

level is below the undervoltage threshold (typically 950 mV), the

EN signal goes low, and the SDA and SCL pins are left high-Z.

The internal level shifter is disabled to prevent corrupt data from

being received.

SCL

R/W

0

A6 A5 A4 A3 A2 A1 A0

A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

SDA

0

1

0

CHIP ADDRESS

SUBADDRESS

WRITE DATA

OUTPUT BY PROCESSOR

OUTPUT BY ADP5080

NOTES

1. MAXIMUM SCL FREQUENCY IS 400kHz.

2. NO RESPONSE TO GENERAL CALL.

Figure 57. I²C Write to Registers

SCL

SDA

R/W

0

R/W

1

A6 A5 A4 A3 A2 A1 A0

A7 A6 A5 A4 A3 A2 A1 A0

SUBADDRESS

A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

CHIP ADDRESS

READ DATA

OUTPUT BY PROCESSOR

OUTPUT BY ADP5080

NOTES

1. MAXIMUM SCL FREQUENCY IS 400kHz.

2. NO RESPONSE TO GENERAL CALL.

Figure 58. I²C Read from Registers with No Read Status Bit (All Registers Except PCTRL)

Rev. A | Page 38 of 64

Data Sheet

ADP5080

SCL

R/W

0

R/W

1

A6 A5 A4 A3 A2 A1 A0

A7 A6 A5 A4 A3 A2 A1 A0

SUBADDRESS

A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1 D0

SDA

0

1

0

1

0

1

CHIP ADDRESS

READ DATA

OUTPUT BY PROCESSOR

OUTPUT BY ADP5080

NOTES

1. MAXIMUM SCL FREQUENCY IS 400kHz.

2. NO RESPONSE TO GENERAL CALL.

Figure 59. I²C Read from Register with Read Status Bit (PCTRL Register)

Rev. A | Page 39 of 64

ADP5080

Data Sheet

CONTROL REGISTER INFORMATION

CONTROL REGISTER MAP

Table 15 lists all control registers for the ADP5080. Any bits shown as blank are reserved.

Table 15. Control Register Map

Register Register

Reg. Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x17

0x18

0x19

Reserved

DSCG

Reserved

1

DSCG7_ON DSCG6_ON DSCG5_ON DSCG4_ON DSCG3_ON DSCG2_ON DSCG1_ON

2

SFTTIM1234

SFTTIM567

EN_DLY12

EN_DLY34

EN_DLY56

EN_DLY7

DIS_DLY12

DIS_DLY34

DIS_DLY56

DIS_DLY7

VID1

SS4[1:0]

SS3[1:0]

SS7

SS2[1:0]

SS6[1:0]

SS1[1:0]

SS5[1:0]

3

4

EN_DLY2[2:0]

EN_DLY1[2:0]

5

EN_DLY4[2:0]

EN_DLY6[2:0]

EN_DLY3[2:0]

EN_DLY5[2:0]

EN_DLY7[2:0]

DIS_DLY1[2:0]

DIS_DLY3[2:0]

DIS_DLY5[2:0]

DIS_DLY7[2:0]

6

7

8

DIS_DLY2[2:0]

DIS_DLY4[2:0]

DIS_DLY6[2:0]

9

10

11

12

13

14

15

16

17

18

19

20

23

24

25

VID1[4:0]

VID2[3:0]

VID4[2:0]

VID6[3:0]

VID23

VID3[2:0]

VID5[2:0]

VID45

VID6

VID7_LDO12

DVS12

VID_LDO2[1:0]

VID_LDO1

VID7[1:0]

DVS2_INTVL DVS1_INTVL

EN_DVS2

FREQ2

EN_DVS1

FREQ1

SEL_FREQ

SEL_FREQ_CP

SEL_PHASE

PROT_DLY

PWRG

SEL_FSW

EN

FREQ6

FREQ5

FREQ4

FREQ3

EN_CLKO

PHASE5

FREQ_CP[1:0]

PHASE6

PHASE4

PHASE3

PHASE2

PHASE1

UV_DLY[1:0]

OV_DLY[1:0]

PWRG7

PWRG6

PWRG5

PWRG4

PWRG3

PWRG2

PWRG1

MASK_PWRG

MASK_

PWRG7

MASK_

PWRG6

MASK_

PWRG5

MASK_

PWRG4

MASK_

PWRG3

MASK_

PWRG2

MASK_

PWRG1

26

27

28

29

30

31

32

33

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

UVPST

UV7

UV6

OV6

UV5

OV5

UV4

OV4

UV3

OV3

UV2

OV2

UV1

OV1

OVPST

AUTO-PSM

SEQ_MODE

ADJ_BST_VTH6

OPT_SR_ADJ

DCM56_GSCAL1

SEL_INP_LDO12

AUTO-PSM6 AUTO-PSM5 AUTO-PSM4 AUTO-PSM3 AUTO-PSM2 AUTO-PSM1

MODE_EN7 MODE_EN6 MODE_EN5 MODE_EN4 MODE_EN3 MODE_EN2 MODE_EN1

BUCK6_ONLY

ADJ_SR5

BOOST6_VTH[1:0]

ADJ_SR6

ADJ_SR4

ADJ_SR3

ADJ_SR2

ADJ_SR1

DCM56

GATE_SCAL1

SEL_INP_

LDO2

SEL_INP_

LDO1

34

35

48

0x22

0x23

0x30

SEL_IND_UV5

OPTION_SEL

PCTRL

UV_DLY5[1:0]

SEL_IND_

UV5

REDUCE_

VOUT1

DIS_DLY_

EXTEND

DIS_EN34_ DIS_EN34_

CH4

CH3

RDST_PCTRL CH7_ON

CH6_ON

CH5_ON

CH4_ON

CH3_ON

CH2_ON

CH1_ON

Rev. A | Page 40 of 64

Data Sheet

ADP5080

CONTROL REGISTER DETAILS

This section describes the bit functions of each register used by the ADP5080.

Register 1: DSCG (Discharge Switch Control), Address 0x01

Register 1 disables and enables the discharge switch for Channel 1 to Channel 7. The default values are defined by the fuse option.

Table 16. Register 1 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DSCG7_ON

DSCG6_ON

DSCG5_ON

DSCG4_ON

DSCG3_ON

DSCG2_ON

DSCG1_ON

Table 17. DSCG Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

6

DSCG7_ON

R/W

0 = disable output discharge switch for Channel 7.

1 = enable output discharge switch for Channel 7.

5

4

3

2

1

0

DSCG6_ON

DSCG5_ON

DSCG4_ON

DSCG3_ON

DSCG2_ON

DSCG1_ON

R/W

0 = disable output discharge switch for Channel 6.

1 = enable output discharge switch for Channel 6.

0 = disable output discharge switch for Channel 5.

1 = enable output discharge switch for Channel 5.

0 = disable output discharge switch for Channel 4.

1 = enable output discharge switch for Channel 4.

0 = disable output discharge switch for Channel 3.

1 = enable output discharge switch for Channel 3.

0 = disable output discharge switch for Channel 2.

1 = enable output discharge switch for Channel 2.

0 = disable output discharge switch for Channel 1.

1 = enable output discharge switch for Channel 1.

Register 2: SFTTIM1234 (Soft Start Time for Channel 1, Channel 2, Channel 3, and Channel 4), Address 0x02

Register 2 sets the soft start time for Channel 1 to Channel 4. The default values are defined by the fuse option.

Table 18. Register 2 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

SS3

Bit 3

Bit 2

SS2

Bit 1

Bit 0

SS4

SS1

Table 19. SFTTIM1234 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[7:6]

SS4

R/W

Soft start time for Channel 4.

00 = 1 ms.

01 = 2 ms.

10 = 4 ms.

11 = 8 ms.

[5:4]

[3:2]

[1:0]

SS3

SS2

SS1

R/W

Soft start time for Channel 3.

00 = 1 ms.

01 = 2 ms.

10 = 4 ms.

11 = 8 ms.

Soft start time for Channel 2.

00 = 1 ms.

01 = 2 ms.

10 = 4 ms.

11 = 8 ms.

Soft start time for Channel 1.

00 = 1 ms.

01 = 2 ms.

10 = 4 ms.

11 = 8 ms.

Rev. A | Page 41 of 64

ADP5080

Data Sheet

Register 3: SFTTIM567 (Soft Start Time for Channel 5, Channel 6, and Channel 7), Address 0x03

Register 3 sets the soft start time for Channel 5 to Channel 7. The default values are defined by the fuse option.

Table 20. Register 3 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SS6

Bit 1

Bit 0

SS7

SS5

Table 21. SFTTIM567 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

4

SS7

R/W

Soft start time for Channel 7.

0 = 2 ms.

1 = 4 ms.

[3:2]

[1:0]

SS6

SS5

R/W

Soft start time for Channel 6.

00 = 1 ms.

01 = 2 ms.

10 = 4 ms.

11 = 8 ms.

Soft start time for Channel 5.

00 = 1 ms.

01 = 2 ms.

10 = 4 ms.

11 = 8 ms.

Register 4: EN_DLY12 (Enable Delay Time for Channel 1 and Channel 2), Address 0x04

Register 4 sets the enable delay time for Channel 1 and Channel 2. The default values are defined by the fuse option.

Table 22. Register 4 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

EN_DLY1

Bit 0

EN_DLY2

Table 23. EN_DLY12 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[6:4]

EN_DLY2

R/W

Enable delay time for Channel 2.

000 = 0 ms.

001 = 2 ms.

010 = 4 ms.

011 = 6 ms.

100 = 8 ms.

101 = 10 ms.

110 = 12 ms.

111 = 14 ms.

[2:0]

EN_DLY1

R/W

Enable delay time for Channel 1.

000 = 0 ms.

001 = 2 ms.

010 = 4 ms.

011 = 6 ms.

100 = 8 ms.

101 = 10 ms.

110 = 12 ms.

111 = 14 ms.

Rev. A | Page 42 of 64

Data Sheet

ADP5080

Register 5: EN_DLY34 (Enable Delay Time for Channel 3 and Channel 4), Address 0x05

Register 5 sets the enable delay time for Channel 3 and Channel 4. The default values are defined by the fuse option.

Table 24. Register 5 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

EN_DLY3

Bit 0

EN_DLY4

Table 25. EN_DLY34 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[6:4]

EN_DLY4

R/W

Enable delay time for Channel 4.

000 = 0 ms.

001 = 2 ms.

010 = 4 ms.

011 = 6 ms.

100 = 8 ms.

101 = 10 ms.

110 = 12 ms.

111 = 14 ms.

[2:0]

EN_DLY3

R/W

Enable delay time for Channel 3.

000 = 0 ms.

001 = 2 ms.

010 = 4 ms.

011 = 6 ms.

100 = 8 ms.

101 = 10 ms.

110 = 12 ms.

111 = 14 ms.

Register 6: EN_DLY56 (Enable Delay Time for Channel 5 and Channel 6), Address 0x06

Register 6 sets the enable delay time for Channel 5 and Channel 6. The default values are defined by the fuse option.

Table 26. Register 6 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

EN_DLY5

Bit 0

EN_DLY6

Table 27. EN_DLY56 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[6:4]

EN_DLY6

R/W

Enable delay time for Channel 6.

000 = 0 ms.

001 = 2 ms.

010 = 4 ms.

011 = 6 ms.

100 = 8 ms.

101 = 10 ms.

110 = 12 ms.

111 = 14 ms.

[2:0]

EN_DLY5

R/W

Enable delay time for Channel 5.

000 = 0 ms.

001 = 2 ms.

010 = 4 ms.

011 = 6 ms.

100 = 8 ms.

101 = 10 ms.

110 = 12 ms.

111 = 14 ms.

Rev. A | Page 43 of 64

ADP5080

Data Sheet

Register 7: EN_DLY7 (Enable Delay Time for Channel 7), Address 0x07

Register 7 sets the enable delay time for Channel 7. The default value is defined by the fuse option.

Table 28. Register 7 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

EN_DLY7

Bit 0

Table 29. EN_DLY7 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[2:0]

EN_DLY7

R/W

Enable delay time for Channel 7.

000 = 0 ms.

001 = 2 ms.

010 = 4 ms.

011 = 6 ms.

100 = 8 ms.

101 = 10 ms.

110 = 12 ms.

111 = 14 ms.

Register 8: DIS_DLY12 (Disable Delay Time for Channel 1 and Channel 2), Address 0x08

Register 8 sets the disable delay time for Channel 1 and Channel 2. The disable delay depends on the setting of the DIS_DLY_EXTEND

bit in Register 35 (Bit 2 in Address 0x23). The default values are defined by the fuse option.

Table 30. Register 8 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

DIS_DLY1

Bit 0

DIS_DLY2

Table 31. DIS_DLY12 Register, Bit Function Descriptions

Bits

Bit Name

R/W

Description

[6:4]

DIS_DLY2

R/W

These bits set the disable delay time for Channel 2.

Bits[6:4]

000

DIS_DLY_EXTEND = 0

DIS_DLY_EXTEND = 1

0 ms

001

010

011

100

101

110

111

4 ms

8 ms

16 ms

32 ms

48 ms

64 ms

80 ms

96 ms

112 ms

12 ms

16 ms

20 ms

24 ms

28 ms

[2:0]

DIS_DLY1

R/W

These bits set the disable delay time for Channel 1.

Bits[2:0]

000

DIS_DLY_EXTEND = 0

DIS_DLY_EXTEND = 1

0 ms

001

010

011

100

101

110

111

4 ms

8 ms

16 ms

32 ms

48 ms

64 ms

80 ms

96 ms

112 ms

12 ms

16 ms

20 ms

24 ms

28 ms

Rev. A | Page 44 of 64

Data Sheet

ADP5080

Register 9: DIS_DLY34 (Disable Delay Time for Channel 3 and Channel 4), Address 0x09

Register 9 sets the disable delay time for Channel 3 and Channel 4. The disable delay depends on the setting of the DIS_DLY_EXTEND

bit in Register 35 (Bit 2 in Address 0x23). The default values are defined by the fuse option.

Table 32. Register 9 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

DIS_DLY3

Bit 0

DIS_DLY4

Table 33. DIS_DLY34 Register, Bit Function Descriptions

Bits

Bit Name

R/W

Description

[6:4]

DIS_DLY4

R/W

These bits set the disable delay time for Channel 4.

Bits[6:4]

000

DIS_DLY_EXTEND = 0

DIS_DLY_EXTEND = 1

0 ms

001

010

011

100

101

110

111

4 ms

8 ms

16 ms

32 ms

48 ms

64 ms

80 ms

96 ms

112 ms

12 ms

16 ms

20 ms

24 ms

28 ms

[2:0]

DIS_DLY3

R/W

These bits set the disable delay time for Channel 3.

Bits[2:0]

000

DIS_DLY_EXTEND = 0

DIS_DLY_EXTEND = 1

0 ms

001

010

011

100

101

110

111

4 ms

8 ms

16 ms

32 ms

48 ms

64 ms

80 ms

96 ms

112 ms

12 ms

16 ms

20 ms

24 ms

28 ms

Rev. A | Page 45 of 64

ADP5080

Data Sheet

Register 10: DIS_DLY56 (Disable Delay Time for Channel 5 and Channel 6), Address 0x0A

Register 10 sets the disable delay time for Channel 5 and Channel 6. The disable delay depends on the setting of the DIS_DLY_EXTEND

bit in Register 35 (Bit 2 in Address 0x23). The default values are defined by the fuse option.

Table 34. Register 10 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

DIS_DLY5

Bit 0

DIS_DLY6

Table 35. DIS_DLY56 Register, Bit Function Descriptions

Bits

Bit Name

R/W

Description

[6:4]

DIS_DLY6

R/W

These bits set the disable delay time for Channel 6.

Bits[6:4]

000

DIS_DLY_EXTEND = 0

DIS_DLY_EXTEND = 1

0 ms

001

010

011

100

101

110

111

4 ms

8 ms

16 ms

32 ms

48 ms

64 ms

80 ms

96 ms

112 ms

12 ms

16 ms

20 ms

24 ms

28 ms

[2:0]

DIS_DLY5

R/W

These bits set the disable delay time for Channel 5.

Bits[2:0]

000

DIS_DLY_EXTEND = 0

DIS_DLY_EXTEND = 1

0 ms

001

010

011

100

101

110

111

4 ms

8 ms

16 ms

32 ms

48 ms

64 ms

80 ms

96 ms

112 ms

12 ms

16 ms

20 ms

24 ms

28 ms

Register 11: DIS_DLY7 (Disable Delay Time for Channel 7), Address 0x0B

Register 11 sets the disable delay time for Channel 7. The disable delay depends on the setting of the DIS_DLY_EXTEND bit in Register 35

(Bit 2 in Address 0x23). The default value is defined by the fuse option.

Table 36. Register 11 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

DIS_DLY7

Bit 0

Table 37. DIS_DLY7 Register, Bit Function Descriptions

Bits

Bit Name

R/W

Description

[2:0]

DIS_DLY7

R/W

These bits set the disable delay time for Channel 7.

Bits[2:0]

000

DIS_DLY_EXTEND = 0

DIS_DLY_EXTEND = 1

0 ms

001

010

011

100

101

110

111

4 ms

8 ms

16 ms

32 ms

48 ms

64 ms

80 ms

96 ms

112 ms

12 ms

16 ms

20 ms

24 ms

28 ms

Rev. A | Page 46 of 64

Data Sheet

ADP5080

Register 12: VID1 (Output Voltage for Channel 1), Address 0x0C

Register 12 sets the output voltage for Channel 1. The output voltage depends on the setting of the REDUCE_VOUT1 bit in Register 35

(Bit 3 in Address 0x23). The default value is defined by the fuse option.

Table 38. Register 12 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VID1

Table 39. VID1 Register, Bit Function Descriptions

Bits

Bit Name

R/W

Description

[4:0]

VID1

R/W

These bits set the output voltage for Channel 1.

Bits[4:0]

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

REDUCE_VOUT1 = 0

1.20 V

1.19 V

1.18 V

1.17 V

1.16 V

1.15 V

1.14 V

1.13 V

1.12 V

1.11 V

1.10 V

1.09 V

1.08 V

1.07 V

1.06 V

1.05 V

1.04 V

1.03 V

1.02 V

1.01 V

1.00 V

0.99 V

0.98 V

0.97 V

0.96 V

0.95 V

0.94 V

0.93 V

0.92 V

0.91 V

0.90 V

0.89 V

REDUCE_VOUT1 = 1

1.11 V

1.10 V

1.09 V

1.08 V

1.07 V

1.06 V

1.05 V

1.04 V

1.03 V

1.02 V

1.01 V

1.00 V

0.99 V

0.98 V

0.97 V

0.96 V

0.95 V

0.94 V

0.93 V

0.92 V

0.91 V

0.90 V

0.89 V

0.88 V

0.87 V

0.86 V

0.85 V

0.84 V

0.83 V

0.82 V

0.81 V

0.80 V

Rev. A | Page 47 of 64

ADP5080

Data Sheet

Register 13: VID23 (Output Voltage for Channel 2 and Channel 3), Address 0x0D

Register 13 sets the output voltage for Channel 2 and Channel 3. The default values are defined by the fuse option.

Table 40. Register 13 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

VID2

Bit 0

VID3

Table 41. VID23 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[6:4]

VID3

R/W

These bits set the output voltage for Channel 3.

000 = 1.8 V.

001 = 1.5 V.

010 = 1.35 V.

011 = 1.3 V.

100 = 1.25 V.

101 = 1.225 V.

110 = 1.2 V.

111 = adjustable mode.

[3:0]

VID2

R/W

These bits set the output voltage for Channel 2.

0000 = 3.3 V.

0001 = 3.2 V.

0010 = 3.15 V.

0011 = 3.00 V.

0100 = 1.8 V.

0101 = 1.25 V.

0110 = 1.225 V.

0111 = 1.2 V.

1000 = 1.175 V.

1001 = 1.15 V.

1010 = 1.125 V.

1011 = 1.1 V.

1100 = 1.075 V.

1101 = 1.05 V.

1110 = 1.025 V.

1111 = 1.0 V.

Rev. A | Page 48 of 64

Data Sheet

ADP5080

Register 14: VID45 (Output Voltage for Channel 4 and Channel 5), Address 0x0E

Register 14 sets the output voltage for Channel 4 and Channel 5. The default values are defined by the fuse option.

Table 42. Register 14 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VID5

VID4

Table 43. VID45 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[6:4]

VID5

R/W

These bits set the output voltage for Channel 5.

000 = 5.00 V.

001 = 4.30 V.

010 = 4.25 V.

011 = 3.30 V.

100 = 3.20 V.

101 = 3.15 V.

110 = 3.10 V.

111 = 3.00 V.

[2:0]

VID4

R/W

These bits set the output voltage for Channel 4.

000 = 3.55 V.

001 = 3.30 V.

010 = 3.20 V.

011 = 3.15 V.

100 = 3.10 V.

101 = 2.80 V.

110 = 1.80 V.

111 = adjustable mode.

Register 15: VID6 (Output Voltage for Channel 6), Address 0x0F

Register 15 sets the output voltage for Channel 6. The default value is defined by the fuse option.

Table 44. Register 15 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

VID6

Bit 0

Table 45. VID6 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[3:0]

VID6

R/W

These bits set the output voltage for Channel 6.

0000 = 5.5 V.

0001 = 5.4 V.

0010 = 5.3 V.

0011 = 5.2 V.

0100 = 5.15 V.

0101 = 5.1 V.

0110 = 5.0 V.

0111 = 4.9 V.

1000 = 4.8 V.

1001 = 4.7 V.

1010 = 4.6 V.

1011 = 4.5 V.

1100 = 4.4 V.

1101 = 3.8 V.

1110 = 3.5 V.

1111 = adjustable mode.

Rev. A | Page 49 of 64

ADP5080

Data Sheet

Register 16: VID7_LDO12 (Output Voltage for Channel 7, LDO1, and LDO2), Address 0x10

Register 16 sets the output voltage for Channel 7, LDO1, and LDO2. The default values are defined by the fuse option.

Table 46. Register 16 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VID_LDO2

VID_LDO1

VID7

Table 47. VID7_LDO12 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[6:5]

VID_LDO2

R/W

These bits set the output voltage for LDO2.

00 = 3.3 V.

01 = 3.2 V.

10 = 3.15 V.

11 = 3.0 V.

4

VID_LDO1

VID7

R/W

These bits set the output voltage for LDO1.

0 = 5.5 V.

1 = 5.0 V.

[1:0]

These bits set the output voltage for Channel 7.

00 = 12 V.

01 = 9 V.

10 = 6 V.

11 = 5 V.

Register 17: DVS12 (DVS Control for Channel 1 and Channel 2), Address 0x11

Register 17 configures the dynamic voltage scaling (DVS) function for Channel 1 and Channel 2. For more information, see the Dynamic

Voltage Scaling (DVS) Function section.

Table 48. Register 17 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DVS2_INTVAL

DVS1_INTVAL

EN_DVS2

EN_DVS1

Table 49. DVS12 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

5

DVS2_INTVAL R/W

This bit configures the DVS interval for Channel 2.

0 = 32 µs (default).

1 = 64 µs.

4

1

0

DVS1_INTVAL R/W

This bit configures the DVS interval for Channel 1.

0 = 16 µs (default).

1 = 32 µs.

EN_DVS2

EN_DVS1

R/W

This bit enables or disables the DVS function for Channel 2.

0 = disable DVS function for Channel 2 (default).

1 = enable DVS function for Channel 2.

This bit enables or disables the DVS function for Channel 1.

0 = disable DVS function for Channel 1 (default).

1 = enable DVS function for Channel 1.

Rev. A | Page 50 of 64

Data Sheet

ADP5080

Register 18: SEL_FREQ (Switching Frequency for Channel 1 to Channel 6), Address 0x12

Register 18 sets the master switching frequency (f_SW) and the switching frequency for each channel. The default values are defined by the

fuse option.

Table 50. Register 18 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SEL_FSW

FREQ6

FREQ5

FREQ4

FREQ3

FREQ2

FREQ1

Table 51. SEL_FREQ Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

7

SEL_FSW

R/W

This bit selects the master switching frequency (f_SW).

0 = f_SWis 2 MHz.

1 = f_SWis 1.5 MHz.

5

4

3

2

1

0

FREQ6

FREQ5

FREQ4

FREQ3

FREQ2

FREQ1

R/W

This bit sets the switching frequency for Channel 6.

0 = 1 × f_SW

1 = 1/2 × f_SW

This bit sets the switching frequency for Channel 5.

0 = 1 × f_SW

1 = 1/2 × f_SW

This bit sets the switching frequency for Channel 4.

0 = 1 × f_SW

1 = 1/2 × f_SW

This bit sets the switching frequency for Channel 3.

0 = 1 × f_SW

1 = 1/2 × f_SW

This bit sets the switching frequency for Channel 2.

0 = 1 × f_SW

1 = 1/2 × f_SW

This bit sets the switching frequency for Channel 1.

0 = 1 × f_SW

1 = 1/2 × f_SW

.

Register 19: SEL_FREQ_CP (Charge Pump Frequency), Address 0x13

Register 19 sets the switching frequency for the charge pump and configures the CLKO output. The switching frequency for the charge pump

depends on whether the device is synchronized to the internal clock or to an external clock. The default values are defined by the fuse option.

Table 52. Register 19 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FREQ_CP

EN_CLKO

Table 53. SEL_FREQ_CP Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

4

EN_CLKO

R/W

This bit configures the clock output (CLKO) pin. The CLKO pin can output the internal switching

clock used for Channel 1 when the device is configured to use the internal oscillator.

0 = no output from CLKO pin.

1 = output from CLKO pin.

[1:0]

FREQ_CP

R/W

These bits set the charge pump switching frequency.

Bits[1:0]

Internal Clock

1/2 × f_SW

1/4 × f_SW

1/8 × f_SW

1/16 × f_SW

External Clock

1/4 × f_SW

1/8 × f_SW

1/4 × f_SW

1/8 × f_SW

00

01

10

11

Rev. A | Page 51 of 64

ADP5080

Data Sheet

Register 20: SEL_PHASE (Switching Phase for Channel 1 to Channel 6), Address 0x14

Register 20 is used to reverse the phase of the switching clock to spread switching energy over time. The default values for Channel 2 to

Channel 6 are defined by the fuse option.

Table 54. Register 20 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PHASE6

PHASE5

PHASE4

PHASE3

PHASE2

PHASE1

Table 55. SEL_PHASE Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

5

PHASE6

R/W

This bit sets the phase for Channel 6.

0 = switching pulse in phase.

1 = switching pulse reversed.

4

3

2

1

0

PHASE5

PHASE4

PHASE3

PHASE2

PHASE1

R/W

This bit sets the phase for Channel 5.

0 = switching pulse in phase.

1 = switching pulse reversed.

This bit sets the phase for Channel 4.

0 = switching pulse in phase.

1 = switching pulse reversed.

This bit sets the phase for Channel 3.

0 = switching pulse in phase.

1 = switching pulse reversed.

This bit sets the phase for Channel 2.

0 = switching pulse in phase.

1 = switching pulse reversed.

This bit sets the phase for Channel 1.

0 = switching pulse in phase (default).

1 = switching pulse reversed.

Register 23: PROT_DLY (Undervoltage/Overvoltage Protection Delay Times), Address 0x17

Register 23 sets the delay times to start undervoltage and overvoltage protection. The default values are defined by the fuse option.

Table 56. Register 23 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

UV_DLY

Bit 3

Bit 2

Bit 1

Bit 0

OV_DLY

Table 57. PROT_DLY Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[5:4]

UV_DLY

R/W

Undervoltage protection delay time.

00 = 0 ms.

01 = 21 ms.

10 = 45 ms.

11 = disable undervoltage protection.

[1:0]

OV_DLY

R/W

Overvoltage protection delay time.

00 = 0 ms.

01 = 1.3 ms.

10 = 3.4 ms.

11 = disable overvoltage protection.

Rev. A | Page 52 of 64

Data Sheet

ADP5080

Register 24: PWRG (Power-Good Status), Address 0x18

Register 24 is the read-only register for the power-good status of Channel 1 to Channel 7. A value of 1 for any PWRGx bit indicates that

the power for that channel is good. The EN signal logic level can be monitored using Bit 7 of this register.

Table 58. Register 24 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EN

PWRG7

PWRG6

PWRG5

PWRG4

PWRG3

PWRG2

PWRG1

Table 59. PWRG Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

7

EN

R

This bit displays the state of the EN pin.

0 = EN pin low (default).

1 = EN pin high.

6

5

4

3

2

1

0

PWRG7

PWRG6

PWRG5

PWRG4

PWRG3

PWRG2

PWRG1

R

This bit displays the power-good status of Channel 7.