ADP5092_技术文档

Ultralow Power Energy Harvester PMUs

with MPPT and Charge Management

Data Sheet

ADP5091/ADP5092

FEATURES

TYPICAL APPLICATION CIRCUIT

Boost regulator with maximum power point tracking (MPPT)

with dynamic sensing or no sensing mode

ADP5091

LLD

TO MCU

REG_D0

REG_D1

VID

REG_OUT

FROM MCU

Hysteresis mode for best ultralight load efficiency

Operating quiescent current of SYS pin (V_IN> V_CBP≥V_MINOP): 510 nA

Sleeping quiescent current of SYS pin (V_CBP<V_MINOP): 390 nA

Input voltage operating range: 0.08 V to 3.3 V

Fast cold start from 380 mV (typical) with charge pump

Programmable shutdown point on MINOP pin based on the

input open circuit voltage (OCV)

150 mA regulated output from 1.5 V to 3.6 V

Battery terminal charging threshold (2.2 V to 5.2 V) to

support charging storage elements

HYSTERESIS

REGULATOR

AND LDO

REG_FB

P

PGOOD

SYS

TO MCU

IN

SW

VIN

COLD START

CHARGE PUMP

SYSTEM

LOAD

MPPT

CBP

BAT

REF

RECHARGEABLE

BATTERY OR

SUPERCAP

+

–

MPPT

BOOST

CONTROL REGULATOR

MINOP

CHARGE CONTROL

AND

POWER PATH

MANAGEMENT

SETSD

SETPG

Optional BACK_UP power path management

Radio frequency (RF) transmission conducive to shutting

down the switcher temporarily via microcontroller unit

(MCU) communication

SETHYST

SETBK

TERM

DIS_SW

FROM MCU

BACK_UP

OPTIONAL

PRIMARY

BATTERY

+

–

AGND PGND

APPLICATIONS

Photovoltaic (PV) cell energy harvesting

Thermoelectric generators (TEGs) energy harvesting

Industrial monitoring

Figure 1.

Self powered wireless sensor devices

Portable and wearable devices with energy harvesting

GENERAL DESCRIPTION

The ADP5091/ADP5092 are intelligent, integrated energy

harvesting, ultralow power management unit (PMU) solutions

that convert dc power from PV cells or TEGs. These devices charge

storage elements such as rechargeable Li-Ion batteries, thin film

batteries, super capacitors, or conventional capacitors, and

power up small electronic devices and battery free systems.

As a low light indicator for a microprocessor, the LLD pin of the

ADP5091 is the MINOP comparator output. However, the

REG_GOOD flag of the ADP5092 monitors the REG_OUT

voltage. In addition, the DIS_SW pin can temporarily shut down

the boost regulator and is RF transmission friendly.

The charging control function of the ADP5091/ADP5092 protects

the rechargeable energy storage, which is achieved by monitoring

the battery voltage with the programmable charging termination

voltage and the shutdown discharging voltage. In addition, a

programmable PGOOD flag monitors the SYS voltage.

The ADP5091/ADP5092 provide efficient conversion of the

harvested limited power from a 6 µW to 600 mW range with

submicrowatt operation losses. With the internal cold start circuit,

the regulator can start operating at an input voltage as low as

380 m V. After cold startup, the regulator is functional at an

input voltage range of 0.08 V to 3.3 V. An additional 150 mA

regulated output can be programmed by an external resistor

divider or the VID pin.

An optional primary cell battery can be connected and managed

by an integrated power path management control block that is

programmable to switch the power source from the energy

harvester, rechargeable battery, and primary cell battery.

The MPPT control keeps the input voltage ripple in a fixed range to

maintain stable dc-to-dc boost conversion. The dynamic sensing

mode and no sensing mode, both programming regulation points

of the input voltage, allow extraction of the highest possible energy

from the harvester. A programmable minimum operation

The ADP5091/ADP5092 are available in a 24-lead LFCSP and

are rated for a −40°C to +125°C temperature range.

threshold enables boost shutdown during a low input condition.

Rev. A

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Technical Support

www.analog.com

ADP5091/ADP5092

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Regulated Output Configuration ............................................. 17

REG_GOOD (ADP5092 Only)................................................ 18

Energy Storage Charge Management ...................................... 18

Backup Storage Path................................................................... 18

Backup and BAT Selection Threshold..................................... 19

Battery Overcharging Protection ............................................. 19

Battery Discharging Protection................................................ 19

Power Good (PGOOD)............................................................. 20

Power Path Working Flow......................................................... 20

Current-Limit and Short-Circuit Protection.............................. 20

Thermal Shutdown .................................................................... 21

Applications Information .............................................................. 23

Energy Harvester Selection....................................................... 23

Energy Storage Element Selection ........................................... 23

Inductor Selection...................................................................... 23

Capacitor Selection .................................................................... 24

Layout and Assembly Considerations ..................................... 24

Typical Application Circuits ..................................................... 25

Factory Programmable Options................................................... 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Applications....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Detailed Functional Block Diagram .............................................. 3

Specifications..................................................................................... 4

Regulated Output Specifications ................................................ 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 16

Fast Cold Start-Up Circuit (V_SYS< V_{SYS_TH}, V_IN> V_{IN_COLD})... 16

Main Boost Regulator (V_{BAT_TERM}> V_SYS> V_{SYS_TH})..................... 16

VIN Open Circuit and MPPT .................................................. 16

Minimum Operation Threshold Function ............................. 17

Disabling Boost........................................................................... 17

Regulated Output Working Mode............................................ 17

REG_D0 and REG_D1 .............................................................. 17

REVISION HISTORY

5/2017—Rev. 0 to Rev. A

Changes to Figure 2.......................................................................... 3

Changes to Figure 7, Figure 10, Figure 7 Caption, and Figure 10

Caption ............................................................................................. 10

Changes to Figure 11 and Figure 11 Caption ............................. 11

Changed CP-24-10 to CP-24-14.................................. Throughout

Updated Outline Dimensions....................................................... 28

Changes to Ordering Guide .......................................................... 28

7/2016—Revision 0: Initial Version

Rev. A | Page 2 of 28

Data Sheet

ADP5091/ADP5092

DETAILED FUNCTIONAL BLOCK DIAGRAM

ADP5091/ADP5092

SYS

LDO

C

R

SYS

REG_SWITCHES

REG_OUT

BACK_UP

+

–

REG_FB

BACK_UP

BK

BACK_UP

CONTROL

SWITCHES

REG_D0

HYSTERESIS

REGULATOR

AND LDO

SYS SWITCH

REG_D1

VID

BAT SWITCHES

PHOTOVOLTAIC

CELL

L

BAT

+

SW

SD

+

–

HS

–

C

IN

BAT

SYS

VIN

COLD START

CHARGE PUMP

LS

BK

REF

R

OC2

MPPT

CONTROLLER

MPPT

TERM_REF

SD

SETSD

R

OC1

EN_BST

CHARGE

CONTROL

AND

POWER PATH

MANAGEMENT

CBP

BOOST

CONTROLLER

PGOOD

PG

MINOP

SETPG

PG

BK

SETHYST

DIS_SW

PG

V

SETBK

TERM

INT_REF

LLD (ADP5091)

REG_GOOD (ADP5092)

TERM_REF

2R

TERM

CONTROL

V

BIAS REFERENCE

AND OSCILLATOR

REF

CLK

R

PGND

BAT

AGND

Figure 2. Detailed Functional Block Diagram

Rev. A | Page 3 of 28

ADP5091/ADP5092

SPECIFICATIONS

Data Sheet

Voltage input (V_IN) = 1.2 V, V_SYS= V_BAT= 3 V, T_J= −40°C to +125°C for minimum/maximum specifications, and T_A= 25°C for typical

specifications, unless otherwise noted. External components include the following: inductance (L) = 22 µH, input capacitance (C_IN) = 4.7 µF,

and C_SYS= 4.7 µF.

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

QUIESCENT CURRENT

Operating Quiescent Current of SYS Pin

I_{Q_SYS}

REG_D0 = low, REG_D1 = low

510

1000

nA

(V_IN> V_CBP≥ V_MINOP

)

REG_D0 = high, REG_D1 = low

REG_D0 = low, REG_D1 = high

REG_D0 = high, REG_D1 = high

REG_D0 = low, REG_D1 = low

650

750

760

390

1150

1290

1300

880

nA

Sleeping Quiescent Current of SYS Pin

(V_CBP< V_MINOP

COLD START CIRCUIT

Minimum Input Voltage for Cold Start V_{IN_COLD}

I_{IQ_SLEEP_SYS}

)

V_SYS= 0 V, 0°C < T_A< 85°C

380

6

500

mV

µW

Minimum Input Power for Cold Start

End of Cold Start Operation

Threshold

P_{IN_COLD}

V_{SYS_TH}

1.73

1.87

95

2.00

V

mV

Hysteresis

V_{SYS_HYS}

BOOST REGULATOR

Input Voltage Operating Range

Input Power Operating Range

Start Charging BAT Threshold on SYS

Start Charging BAT Hysteresis on SYS

Input Peak Current

V_IN

P_IN

V_{SYS_CHG}

V_{SYS_CHG_HYS}

I_{IN_PEAK}

Cold start completed

Cold start completed, V_IN= 3 V

0.08

2.00

3.3

600

2.35

V

mW

V

mV

mA

Ω

2.19

150

200

300

0.44

0.85

0.32

Factory trim, 1 bit, Option 0

Option 1

Pin to pin measurement

250

Low-Side Switch On Resistance

High-Side Switch On Resistance

SYS Switch On Resistance

DIS_SW Voltage

R_{LS_DS_ON}

R_{HS_DS_ON}

R_{SYS_DS_ON}

0.6

1.2

0.70

Ω

High

Low

DIS_SW Delay

V_{DIS_SW_HIGH}

V_{DIS_SW_LOW}

t_{DIS_SW_DELAY}

1

V

µs

0.5

1

VIN CONTROL AND MINOP

VIN Open Circuit Voltage

Default Sampling Cycle

t_{OCV_CYCLE}

Factory trim, 2 bit (4 sec, 8 sec, 16 sec,

32 sec)

16

sec

Sampling Time

MINOP Bias Current

MINOP Operation Voltage Threshold

of Dynamic MPPT Sensing Mode

MPPT Bias Current of MPPT No

Sensing Mode

t_{OCV_SAMPL}

I_MINOP

V_{MINOP_DSM}

256

2.00

ms

µA

V

1.58

1.7

2.45

1.5

I_MPPT

2.0

2.3

µA

LLD (ADP5091 Only)

Pull-Up Resistor

Pull-Down Resistor

High Voltage

12

V_{REG_OUT}

10

17

kΩ

V

V_{LLD_IH}

I_{CBP_LEAK}

Leakage Current at CBP Pin

2000

pA

Rev. A | Page 4 of 28

Data Sheet

ADP5091/ADP5092

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

ENERGY STORAGE MANAGEMENT

Internal Reference Voltage

Battery Stop Discharging

Threshold

Hysteresis Resistor

Battery Terminal Charging

Threshold

V_{INT_REF}

0.955

1.011

1.067

V

V_SETSD

R_{SETSD_HYS}

2.0

80

V_{BAT_TERM}

160

V

kΩ

115

3

V_{BAT_TERM}

V_{BAT_TERM_HYS}

V_{SYS_PG}

2.2

5.2

3.1

V_{BAT_TERM}

17.0

V

%

V

kΩ

V

Ω

A

nA

Hysteresis

PGOOD Rising Threshold at SYS Pin

PGOOD Pull-Up Resistor

PGOOD Pull-Down Resistor

PGOOD High Voltage

Battery Switches On Resistance

Battery Source Current

Leakage Current at BAT Pin

V_SETSD

11.6

V_SYS

V_{PGOOD_HIGH}

R_{BAT_SW_ON}

I_BAT

Pin to pin measurement

0.59

0.85

1

50

35

I_{BAT_LEAK}

V_BAT= 2 V, V_SETSD= 2.2 V, V_SYS= 2 V

V_BAT= 3.3 V, V_SETSD= 2.2 V, V_SYS= 0 V

22

3.5

BACK_UP POWER PATH

Turning Off BACK_UP Switch

Threshold on BAT

V_SETBK

R_{SETBK_HYS}

2.0

80

V_{BAT_TERM}

160

1.20

V

kΩ

Ω

Hysteresis Resistor

115

0.85

BACK_UP Switches On Resistance

BACK_UP and BAT Comparator

Offset

V_SYS≥ V_{SYS_TH}

V_{BKP_OFFSET}

V_{BAT_HYS}

I_BKP

158

68

190

75

250

16

271

108

mV

µA

Hysteresis

BACK_UP Current Capability

Leakage Current at BACK_UP Pin

THERMAL SHUTDOWN

Threshold

V_SYS< V_{SYS_TH}

V_{BACK_UP}= V_SYS= V_BAT= 3 V

I_{BKP_LEAK}

40

nA

T_SHDN

T_HYS

V_SYS≥ V_{SYS_TH}

142

15

°C

Hysteresis

Rev. A | Page 5 of 28

ADP5091/ADP5092

Data Sheet

REGULATED OUTPUT SPECIFICATIONS

V_IN= 1.2 V, V_SYS= V_BAT= 3 V, V_{REG_OUT}= 2 V, L = 22 µH, C_IN= 4.7 µF, C_SYS= 4.7 µF, C_{REG_OUT}= 4.7 µF, T_J= −40°C to +125°C for

minimum/maximum specifications, and T_A= 25°C for typical specifications, unless otherwise noted.

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

REGULATED OUTPUT

Output Options by VID Control

Rating Current

REG_OUT Pull-Down Resistance

REG_OUT IN BOOST MODE

REG_OUT Wake Threshold

V_{REG_OUT}

I_{REG_OUT}

R_{REG_OUT}

1.5

3.6

V

mA

Ω

V_{REG_OUT}= 1.5 V to 3.6 V

150

235

V_{REG_WAKE}

1.008 × 1.027 ×

V_{REG_OUT}V_{REG_OUT}

1.048 ×

V_{REG_OUT}

V

REG_OUT Wake Threshold

Hysteresis

Adjustable REG_OUT Wake

Threshold

Adjustable REG_OUT Sleep

Threshold

V_{REG_WAKE_HYS}

V_{ADJ_REG_WAKE}

V_{ADJ_REG_SLEEP}

1

%

V

1.008

1.018

1.028

1.038

1.048

1.058

V

High-Side Switches On Resistance

Current-Limit Threshold of Boost

Mode

R_{BST_DS_ON}

I_{REG_BST_LIM}

1.63

100

2.15

155

Ω

mA

REG_OUT IN LOW DROPOUT (LDO)

MODE

REG_OUT Accuracy

Adjustable REG_OUT Accuracy

V_{REG_LDO}

V_{REG_LDO_ADJ}

0 µA < I_OUT< 150 mA, V_SYS= (V_{REG_OUT}+ 0.5 V) −3.5

I_OUT= 1 mA 0.999

0 µA < I_OUT< 150 mA, V_SYS= (V_{REG_OUT}+ 0.5 V) 0.985

I_OUT= 150 mA

+3.5

1.028

1.045

%

V

mV

mA

1.015

200

REG_OUT Dropout

Current-Limit Threshold of LDO

Mode

V_{REG_DROP}

I_{REG_LIM}

V_SYS≥ V_{SYS_TH}

200

260

Output Noise

Power Supply Rejection Ratio

OUT_NOISE

PSRR

10 Hz to 100 kHz

100 Hz

700

60

µV rms

dB

1 kHz

40

dB

REG_D0 and REG_D1

Input Logic

High

Low

V_{REG_DX_IH}

V_{REG_DX_IL}

I_{REG_DX_LEAK}

1.2

V

nA

0.4

Input Leakage Current

REG_GOOD (ADP5092 ONLY )

Rising Threshold

Hysteresis

20

V_{REG_GOOD}

V_{REG_GOOD_HYS}

89.5

92.5

2

95.7

%

Pull-Up Resistor

Pull-Down Resistor

High Voltage

11.6

V_{REG_OUT}

17

kΩ

V

V_{REG_GOOD_IH}

Rev. A | Page 6 of 28

Data Sheet

ADP5091/ADP5092

ABSOLUTE MAXIMUM RATINGS

Table 3.

THERMAL RESISTANCE

θ_JAis specified for the worst case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Parameter

Rating

VIN, MPPT, CBP, MINOP

−0.3 V to +3.6 V

−0.3 V to +6.0 V

DIS_SW, TERM, SETPG, SETSD, SETBK,

PGOOD, SETHYST, REF, REG_D0, VID,

REG_D1, LLD, REG_GOOD to AGND

SW, SYS, BAT, BACK_UP, REG_OUT, REG_FB

to PGND

Table 4.

Package Type

θ_JA

θ_JC

Unit

24-Lead LFCSP

58.7

36

°C/W

−0.3 V to +6.0 V

−0.3 V to +0.3 V

PGND to AGND

ESD CAUTION

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. A | Page 7 of 28

ADP5091/ADP5092

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

18

17

16

15

14

13

18

17

16

15

14

13

REF

SETSD

SETBK

BACK_UP

1

2

3

REF

SETSD

SETBK

BACK_UP

BAT

SYS

ADP5092

TOP VIEW

(Not to Scale)

ADP5091

TOP VIEW

(Not to Scale)

REG_FB

REG_OUT

SW

TERM 4

REG_FB

REG_OUT

SW

TERM 4

5

6

SETPG

5

6

SETPG

SETHYST

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

Figure 4. ADP5092 Pin Configuration

Figure 3. ADP5091 Pin Configuration

Table 5. Pin Function Descriptions

Pin No.¹

ADP5091 ADP5092 Mnemonic Description

1

2

1

2

REF

SETSD

Internal Voltage Reference Monitoring Node for the SETSD, SETPG, SETBK, and TERM Pins.

Shutdown Setting. The SETSD pin sets the shutdown discharging voltage based on the BAT pin

voltage level.

3

4

3

4

SETBK

TERM

BACK_UP Disabled Threshold Monitoring BAT Voltage Setting. Connect the SETBK pin to the AGND

pin without the BACK_UP storage element.

Termination Charging Voltage. This pin sets the termination charging voltage based on the BAT pin

voltage level.

5

6

5

6

SETPG

SETHYST

Power-Good Rising Threshold Monitoring SYS Node Voltage Level Setting.

PGOOD Falling Hysteresis Setting. Connect a resistor between SETPG and SETHYST to program the

PGOOD falling hysteresis.

7

8

7

8

AGND

CBP

Analog Ground.

Capacitor Bypass. This pin samples and holds the maximum power point level. Connect a 10 nF

capacitor from the CBP pin to the AGND pin. When the MPPT pin is disabled, tie the CBP pin to an

external reference that is lower than the VIN pin.

9

MPPT

Maximum Power Point Tracking. This pin sets the maximum power point ratio for the different

energy harvesters with a resistor divider. In no sensing mode, place a resistor through AGND to set

the MPPT voltage. The typical current value is 2.0 µA.

10

11

10

VIN

LLD

Input Supply from Energy Harvester Source. Connect at least a 10 µF capacitor as close as possible

between VIN and PGND.

Low Light Density Indicator to Microcontroller for the ADP5091. LLD pulls high at the MINOP voltage

higher than the CBP voltage.

N/A

12

13

11

12

13

REG_GOOD Regulated Output Power Good for the ADP5092.

PGND

SW

Power Ground.

Switching Node for the Inductive Boost Regulator with a Connection to an External Inductor.

Connect a 22 µH inductor between SW and VIN.

14

15

14

15

REG_OUT

REG_FB

Regulated Output. Connect at least a 4.7 µF capacitor as close as possible between REG_OUT and PGND.

Regulated Output Feedback Voltage Sense Input. The fixed output connects this pin to REG_OUT.

The adjustable output connects this pin to a resistor divider from REG_OUT.

16

17

18

16

17

18

SYS

Output Supply to System Load. Connect at least a 4.7 µF capacitor as close as possible between SYS

and PGND.

SYS Output Supply Storage. This pin places the rechargeable battery or super capacitor as a storage

for the SYS output supply.

BAT

BACK_UP

Optional Input Supply from the Backup Primary Battery Cell.

Rev. A | Page 8 of 28

Data Sheet

ADP5091/ADP5092

Pin No.¹

ADP5091 ADP5092 Mnemonic Description

19

20

21

19

20

21

PGOOD

Output Signal to Microcontroller. This pin maintains a pulled high level when SYS is higher than the

SETPG threshold.

Voltage Configuration Pin for REG_OUT. This pin sets up to eight different regulated outputs tied

low through a resistor to AGND. The output configuration details are in Table 7.

Minimum Operating Power. Place a resistor on MINOP to set the minimum operating input voltage

level. The boost regulator starts switching when the CBP voltage exceeds the MINOP voltage. When

the MINOP pin is floating, the IC operates in no sensing mode with a fixed MPPT level. Connect this

pin through AGND to disable the MINOP function.

VID

MINOP

22

23

24

22

23

24

DIS_SW

REG_D1

REG_D0

EPAD

Control Signal from Microcontroller or RF Transceiver to Stop Switching Boost Charger.

Regulated Output Working Mode Set D1. Enable LDO mode by pulling this pin high.

Regulated Output Working Mode Set D0. Enable boost mode by pulling this pin high.

Exposed Pad. The exposed pad must be connected to AGND.

¹N/A means not applicable.

Rev. A | Page 9 of 28

ADP5091/ADP5092

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

V_{BAT_TERM}= 3.5 V, V_{SYS_PG}= 2.8 V, V_SETSD= 2.4 V, MPPT (OCV) = 80%, L = 22 μH, C_IN= 10 μF, C_SYS= 4.7 μF, C_{REG_OUT}= 10 μF, C_CBP= 10 nF.

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

SYS = 2V

SYS = 3V

SYS = 5V

SYS = 2V

SYS = 3V

SYS = 5V

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

INPUT VOLTAGE (V)

Figure 5. Efficiency vs. Input Voltage, I_IN= 10 μA

Figure 8. Efficiency vs. Input Voltage, I_IN= 100 μA

100

90

80

70

60

50

40

30

20

90

80

70

60

50

40

30

20

10

0

SYS = 2V

SYS = 3V

SYS = 5V

SYS = 2V

SYS = 3V

SYS = 5V

0

0.5

1.0

1.5

2.0

2.5

3.0

0.01

0.10

1

10

INPUT VOLTAGE (V)

INPUT CURRENT (mA)

Figure 6. Efficiency vs. Input Voltage, I_IN= 10 mA

Figure 9. Efficiency vs. Input Current, V_IN= 0.2 V

90

80

70

60

50

40

30

20

90

80

70

60

50

40

30

20

SYS = 2V

SYS = 3V

SYS = 5V

SYS = 2V

SYS = 3V

SYS = 5V

0.01

0.1

1

10

100

0.01

0.1

1

10

100

INPUT VOLTAGE (V)

Figure 7. Efficiency vs. Input Voltage, V_IN= 0.5 V

Figure 10. Efficiency vs. Input Voltage, V_IN= 1 V

Rev. A | Page 10 of 28

Data Sheet

ADP5091/ADP5092

100

90

80

70

60

50

40

30

20

10

0

100

95

90

85

80

75

70

65

SYS = 3V

SYS = 5V

SYS = 3V

SYS = 5V

60

0.01

.05

0.5

5

50

0.1

1

10

100

INPUT CURRENT (mA)

INPUT VOLTAGE (V)

Figure 14. Efficiency vs. Input Current, V_IN= 0.5 V, V_{REG_OUT}= 2 V,

_{REG_OUT}= 10 µA

Figure 11. Efficiency vs. Input Voltage, V_IN= 2 V

I

1400

1200

1000

800

600

400

200

0

100

90

80

70

60

50

40

30

20

10

0

T

= –40°C

= +25°C

= +85°C

= +125°C

A

SYS = 3V

SYS = 5V

2.0

2.5

3.0

3.5

4.0

4.5

5.0

.02

0.2

2

20

SYS VOLTAGE (V)

INPUT CURRENT (mA)

Figure 12. Efficiency vs. Input Current, V_IN= 1 V, V_{REG_OUT}= 2 V, I_{REG_OUT}= 10 µA

Figure 15. Quiescent Current vs. SYS Voltage, V_MINOP≤ V_CBP

1600

1400

1200

1000

800

1200

1000

800

600

400

200

0

T

= –40°C

= +25°C

= +85°C

= +125°C

A

600

T

= –40°C

= +25°C

= +85°C

= +125°C

400

200

0

A

2.0

2.5

3.0

3.5

4.0

4.5

5.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

SYS VOLTAGE (V)

Figure 13. Quiescent Current vs. SYS Voltage, V_{REG_D0}= V_{REG_D1}= V_SYS, V_MINOP≤ V_CBP

Figure 16. Quiescent Current vs. SYS Voltage, V_MINOP> V_CBP

Rev. A | Page 11 of 28

ADP5091/ADP5092

Data Sheet

120

60

50

40

30

20

10

0

T

= –40°C

= +25°C

= +85°C

= +125°C

T

= –40°C

= +25°C

= +85°C

= +125°C

A

100

80

60

40

20

0

2.0

2.4

2.8

3.2

3.6

4.0

4.4

4.8

5.2

2.0

2.4

2.8

3.2

3.6

4.0

4.4

4.8

5.2

BACK_UP VOLTAGE (V)

BAT VOLTAGE (V)

Figure 17. BACK_UP Leakage Current vs. BACK_UP Voltage

Figure 20. BAT Leakage Current vs. BAT Voltage

VIN

1

BAT

SYS

BAT

SYS

2

4

2

4

SW

B

CH1 1.00V

CH3 1.00V

CH2 1.00V

CH4 2.00V

M40.0ms

A

CH2

1.00V

CH1 1.00V

CH3 1.00V

CH2 1.00V

CH4 2.00V

M100ms

A

CH2

1.00V

W

Figure 18. Startup with 100 µF Battery, V_BAT> V_SETSD

Figure 21. Startup with Empty 100 µF Capacitor

VIN

CH3: BAT (AC)

CH2: SYS (AC)

VIN

1

3

1

SYS

BAT

3

4

SW

PGOOD

4

B

CH1 1.00V

CH3 50.0mV

CH2 50.0mV

CH4 2.00V

M20.0ms A CH3

5.00mV

CH1 500mV

B

CH3 1.00V

CH2 1.00V

CH4 2.00V

W

M40.0ms

A

CH4

1.00V

W

B

T

80.0000µs

W

Figure 19. Output Ripple of TERM Function with 100 µA Load

Figure 22. PGOOD Function Waveform

Rev. A | Page 12 of 28

Data Sheet

ADP5091/ADP5092

VIN

1

BAT

SYS

VIN

1

BACK_UP

BAT

3

4

SW

SYS

3

B

CH1 500mV

CH3 1.00V

CH2 1.00V

CH4 2.00V

M10.0ms

A

CH2

2.00V

CH1 500mV

B

CH3 1.00V

CH2 1.00V

CH4 1.00V

W

M2.00s

A

CH2

2.12V

W

B

T

–80.0000µs

W

Figure 23. Battery Protection Function Waveform

Figure 26. BACK_UP Function, V_BAT< V_SETBK, V_{BACK_UP}< V_BAT

VIN

1

43

1

BAT

BACK_UP

BAT

CH2: SYS

SYS

3

B

CH1 500mV

CH3 1.00V

CH2 1.00V

CH4 2.00V

M2.00s

A

CH2

2.12V

CH1 500mV

B

CH3 1.00V

CH2 1.00V

CH4 1.00V

W

M2.00s

A

CH2

2.12V

W

B

W

Figure 24. Backup Function, V_BAT< V_SETBK, V_{BACK_UP}> V_BAT

Figure 27. BACK_UP Function, V_BAT> V_SETBK, V_{BACK_UP}> V_BAT

VIN

SYS

BAT

1

3

4

1

DIS_SW

3

2

4

SW

B

CH1 500mV

CH3 2.00V

CH2 2.00V

CH4 2.00V

M40.0µs

996.400µs

A

CH4

2.00V

W

CH1 500mV

CH3 2.00V

CH2 1.00V

CH4 1.00V

M100ms

A

CH1

880mV

B

T

W

Figure 25. Main Boost Pulse Frequency Modulation (PFM) Waveform with

200 µA Load

Figure 28. DIS_SW Function Waveform

Rev. A | Page 13 of 28

ADP5091/ADP5092

Data Sheet

VIN

SYS

1

BAT

SW

2

3

4

SW

2

3

B

CH1 500mV

B

CH1 500mV

CH3 1.00V

CH2 1.00V

CH4 2.00V

M4.00s

A

CH2

2.12V

W

CH2 2.00V

CH4 5.00V

W

M4.00s

A

CH2

2.04V

780mV

2.00V

W

B

CH3 2.00V

W

Figure 29. MPPT No Sensing Mode, R_MPPT= 400 kΩ

Figure 32. MPPT Dynamic Sensing Mode

VIN

SYS

LLD

1

2

4

MINOP

3

2

4

SW

B

CH1 500mV

CH3 500mV

B

CH1 500mV

CH3 500mV

B

W

CH2 1.00V

CH4 2.00V

M100ms

A

CH1

780mV

W

CH2 1.00V

CH4 2.00V

W

M400ms

A CH1

W

B

W

Figure 30. MINOP Function

Figure 33. LLD Function

VIN

SYS

VIN

1

3

1

REG_OUT (AC)

SYS

REG_OUT

BAT

3

4

2

4

SW

B

CH1 500mV

B

W

CH2 1.00V

CH4 2.00V

M400ms

A

CH4

220mV

CH1 500mV

CH3 20.0mV

CH2 1.00V

CH4 2.00V

W

M400µs

T 0.0000s

A CH3

W

B

CH3 1.00V

W

Figure 31. REG_OUT Start (Hybrid Mode)

Figure 34. REG_OUT Ripple (Boost Mode)

Rev. A | Page 14 of 28

Data Sheet

ADP5091/ADP5092

SYS

REG_OUT (AC)

1

VIN

3

1

4

2

REG_OUT

2

REG_GOOD

LOAD CURRENT

B

CH1 50.0mV

CH2 10.0mAΩ

A

CH2 –129mA

CH1 500mV

CH3 1.00V

CH2 2.00V

CH4 2.00V

M200ms

A

CH2

1.68V

W

T 0.0000s

M1.00ms

Figure 35. REG_GOOD Function

Figure 38. REG_OUT Load Transient (Hybrid), I_{REG_OUT}from 10 µA to 10 mA

1200

1000

800

REG_OUT (AC)

1

600

I

= 0mA

= 1mA

= 10mA

= 150mA

LOAD

400

200

0

2

LOAD CURRENT

B

10

100

1k

10k

100k

1M

10M

CH1 50.0mV

CH2 50.0mAΩ

M1.00µs

A

CH1 –36.0mV

W

T 0.0000s

FREQUENCY (Hz)

Figure 36. REG_OUT Load Transient (LDO), I_{REG_OUT}from 10 µA to 50 mA

Figure 39. REG_OUT RMS Noise vs. Frequency

1

0

–10

–20

–30

–40

–50

–60

–70

–80

I

= 0mA

= 1mA

= 10mA

= 150mA

LOAD

100m

10m

1m

I

= 0mA

= 1mA

= 10mA

= 150mA

LOAD

100µ

10µ

1µ

100n

10n

1n

100p

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 37. REG_OUT Noise Density vs. Frequency at Various Current Loads (I_LOAD

)

Figure 40. Power Supply Rejection Ratio (PSRR) vs. Frequency

Rev. A | Page 15 of 28

ADP5091/ADP5092

Data Sheet

THEORY OF OPERATION

The ADP5091/ADP5092 are intelligent, integrated energy

harvesting, ultralow power management solutions that include

a cold start-up circuit, one synchronous main boost controller,

and one regulated output hybrid controller with integrated

switches, a charging controller with integrated switches, and

backup power path switches. The main boost controller converts

maximum power from low voltage, high impedance dc sources,

such as PV cells, TEGs, and piezoelectric modules, to store energy

in a rechargeable battery or capacitor with storage protection

and provides power to the load. Another regulated output with

automatic hysteresis boost/LDO mode, or pure LDO mode, is

optimized to provide high efficiency across low output currents

(10 μA), see Figure 14) to high currents of 200 mA. The ADP5091/

ADP5092 can also control an additional power path from a

primary battery cell to the system. An external signal can

temporarily stop the two boost circuits to prevent interference

with RF transmission.

MAIN BOOST REGULATOR (V_{BAT_TERM}> V_SYS> V_{SYS_TH}

)

The switching mode synchronous boost regulator, with an external

inductor connected between the VIN and the SW pins, operates

in pulse frequency modulation (PFM) mode, transferring energy

stored in the input capacitor to the energy storage connected to

the BAT pin. The MPPT control loop regulates the VIN voltage

at the level sampled at the MPPT pin and stored at the capacitor

through the CBP and the AGND pins. To maintain the high

efficiency of the regulator across a wide input power range, the

current sense circuitry employs an internal dither peak current

limit to control the inductor current.

The main boost regulator operation reaches an asynchronous

mode via the energy storage controller if the BAT pin voltage is

less than the battery terminal charging threshold programmed at

the SETSD pin, or stops switching if the BAT pin voltage is

more than the battery overcharging threshold programmed at

the TERM pin. The boost regulator disables when the voltage

on the CBP pin decreases to the threshold set by the resistor at

the MINOP pin. In addition, the boost is periodically stopped

by an open voltage sampling circuit and can also be temporary

disabled by driving the DIS_SW pin high.

FAST COLD START-UP CIRCUIT (V_SYS< V_{SYS_TH}

,

V_IN> V_{IN_COLD}

)

The fast cold start-up circuit extracts energy available at the

VIN pin and charges only the capacitors at the SYS pin up to

V

_{SYS_TH}above which the main boost regulator and charge controller

VIN OPEN CIRCUIT AND MPPT

start working. The efficient boost regulator charges storage

elements on the BAT pin when the SYS voltage is more than

the internal BAT charging threshold (V_{SYS_CHG}). When the SYS

voltage is less than the internal BAT charging threshold with a

hysteresis, it stops charging the BAT pin and restarts charging

the SYS pin to ensure that it does not enter cold startup. Figure 41

shows the fast cold start-up sequence.

By floating the MINOP pin, the MPPT no sensing mode can

operate on a fixed MPPT voltage. The MPPT pin, with a 2.0 μA

(typical) bias current through a resistor, sets the MPPT voltage,

which is the boost input regulation reference.

When the MINOP pin voltage is set lower than V_{MINOP_DSM}

through a resistor to AGND, the ADP5091/ADP5092 operate in

MPPT dynamic sensing mode. The boost input regulation

reference is the open circuit voltage at the VIN pin scaled to a ratio

programmed by the resistor divider at the MPPT pin. To keep

the VIN voltage operating at the maximum power points available

from the energy harvester at the input of the ADP5091/ADP5092,

periodically sample the MPPT voltage and store it in the capacitor

connected to the CBP pin. The reference voltage refreshes every

16 sec (default value) by periodically disabling the boost regulator

for 256 ms (default value) and by sampling the ratio of the open

circuit voltage when the BAT voltage level exceeds the SETSD

rising threshold. The factory bit can program the sampling

cycle. Set the reference voltage by

The cold start-up circuit is required when the VIN pin is more

than the minimum input voltage for the cold start (V_{IN_COLD}),

and the energy storage voltage at the SYS pin is less than the end

of the cold start operation threshold (V_{SYS_TH}). To complete the

cold startup, the energy harvester must supply sufficient power

(see the Energy Harvester Selection section). The cold startup,

with much lower efficiency compared to the main boost regulator,

achieves a short start-up time, creating a low shutdown current

from the system load enabled by the PGOOD signal. To bypass

the cold startup, place a primary battery at the BACK_UP pin

(see the Backup Storage Path section).

V

SETSD









R_OC1

_OC1 R_OC2





V_MPPTV_IN

where:



Open Circuit

(1)

V



SYS_CHG

R



V

SYS_CHG_HYS

V

SYS_TH

V_IN(Open Circuit) is the input open circuit voltage (V_IN__OCV) of

FAST

COLD

START

the input voltage.

See Figure 2 for R_OC1and R_OC2

.

SYS

BAT

0V

LOW

EFFICIENCY

HIGH EFFICIENCY

Figure 41. Fast Cold Start-Up Sequence

Rev. A | Page 16 of 28

Data Sheet

ADP5091/ADP5092

The typical MPPT ratio depends on the type of harvester. For

example, it is 0.7 to 0.85 for PV cells, and 0.5 for TEGs. The

sampling OCV rate is adjustable depending on the previously

sampled OCV level. To disable the MPPT function, leave the

MPPT pin floating and set the CBP pin to an external voltage

reference lower than the VIN voltage.

In LDO mode, the output generates power from the SYS pin

with at least a small 4.7 µF ceramic output capacitor. Using new

innovative design techniques, the LDO provides ultralow quiescent

current and superior transient performance for digital and RF

applications, and supports noise sensitive applications.

In hybrid mode, the VIN and SYS pins both extract energy to

the REG_OUT pin. When the load power is lower than the input

power, the regulator exits LDO mode and obtains the energy

only from the input side.

MINIMUM OPERATION THRESHOLD FUNCTION

By setting the MINOP pin voltage lower than the MINOP

operation voltage range of the dynamic MPPT sensing mode

(V_{MINOP_DSM}) through a resistor to AGND, the minimum operation

threshold function can disable the main boost regulator to prevent

discharging the storage element when the energy generated by the

harvester is less than the system consumption. When the voltage

of the CBP pin decreases to the threshold set by the resistor at

the MINOP pin, the boost regulator stops switching. The

typical MINOP bias current is 2.00 µA. The minimum operation

threshold function disables the MPPT function to achieve the

sleeping quiescent current of 390 nA (typical). Disable this

function by connecting the MINOP pin to the AGND pin.

REG_D0 AND REG_D1

The REG_D0 and REG_D1 pins allow flexible configuration of

the working mode of the regulated output. Table 6 details the

working mode configuration set by these two pins.

Table 6. Regulated Output Working Mode Configuration

Working Mode

Boost Disable

Boost Enable

LDO Disable

LDO Enable

REG_D0

REG_D1

Not applicable

Low

High

Not applicable

High

The low light density (LLD) indicator (ADP5091 only) is the

MINOP comparator output that signals the microprocessor to

calculate the cycle with insufficient input energy in a certain

period.

REGULATED OUTPUT CONFIGURATION

The 150 mA regulated output of the ADP5091/ADP5092 is

available in eight fixed output voltage options ranging from

1.5 V to 3.6 V by connecting one resistor through the VID pin

to the AGND pin. Table 7 shows the output voltage options set by

the VID pin.

DISABLING BOOST

For noise or electromagnetic interference (EMI) sensitive

applications, pull the DIS_SW pin high to stop the boost

switcher temporarily to prevent interference with RF circuits.

Pull the DIS_SW pin low to resume the boost switching. The

transition delay is 1 µs (typical).

Table 7. Output Voltage Options Set by the VID Pin

VID Configuration

Short to Ground

Floating

Output Voltage Set by the VID Pin

Programmed with external resistors

V_OUT= 2.5 V

REGULATED OUTPUT WORKING MODE

The 150 mA regulated output of the ADP5091/ADP5092 not

only operates in the hysteresis boost mode or the LDO mode

but also operates in the hybrid mode in which the regulator can

smoothly transition between these two modes automatically.

After the BAT voltage exceeds the SETSD threshold or the SYS

voltage is greater than SETPG threshold, the regulator can be

enabled.

R_VID= 7 kΩ

R_VID= 14 kΩ

V_OUT= 1.5 V

V_OUT= 1.8 V

V_OUT= 3.6 V

V_OUT= 3.3 V

V_OUT= 2.0 V

V_OUT= 3.0 V

V_OUT= 2.8 V

R_VID= 27.7 kΩ

R_VID= 55.6 kΩ

R_VID= 111 kΩ

R_VID= 221 kΩ

R_VID= 442 kΩ

In hysteresis boost mode, the boost regulator in the ADP5091/

ADP5092 charges the output voltage slightly higher than its

preset output voltage. When the output voltage increases until

the output sense signal exceeds the hysteresis comparator upper

threshold (the sleep threshold), the regulator enters sleep mode. In

sleep mode, to allow a low quiescent current as well as high

efficiency performance, the low-side and high-side switches

and a majority of the circuitry are disabled.

The external resistor divider or the VID pin can program the

regulated output. The ratio of the two external resistors sets the

adjustable output voltage range of 1.5 V to 3.6 V, as shown in

Figure 47. The device acts as a servo to the output to maintain

the voltage at the REG_FB pin at 1.0 V referenced to ground.

The current in R1 is then equal to 1.0 V/R2, and the current in

R1 is the current in R2 plus the REG_FB pin bias current.

Calculate the output voltage by

During sleep mode, the output capacitor supplies the energy into

the load, the output voltage decreases until it falls below the

hysteresis comparator lower threshold (the wake threshold),

and the boost regulator wakes up and generates the pulse-width

modulation (PWM) pulses to charge the output again. The

hysteresis mode allows the regulator to act as the keep alive

power supply.

V

_OUT= 1.02 V × (1 + R1/R2)

(2)

where:

_OUT= V_{REG_OUT}

See Figure 47 for R1 and R2.

V

.

To minimize quiescent current, it is recommended to use large

resistance values for R1 and R2.

Rev. A | Page 17 of 28

ADP5091/ADP5092

Data Sheet

REG_GOOD (ADP5092 ONLY)

BACKUP STORAGE PATH

A logic high on the REG_GOOD pin indicates that the REG_OUT

voltage is above 92.5% (typical) of its nominal output for a delay

time greater than approximately 2 ms. The logic high level on

REG_GOOD is equal to the REG_OUT voltage, and the logic low

level is ground. When the REG_OUT voltage falls below a 2%

hysteresis (typical) of the rising threshold, the REG_GOOD pin

goes low. The logic high level has about 11.6 kΩ internally in

series to limit the available current.

The ADP5091/ADP5092 provide an optional backup storage

energy path, an integrated backup controller, and two back to

back power switches between the BACK_UP pin and the SYS

pin. When the system operates at a condition where the harvested

and stored energy is periodically insufficient, attach a backup

energy storage element to the BACK_UP pin.

The backup controller enables when the SYS voltage exceeds the

end of the cold start operation threshold (V_{SYS_TH}). Before the BAT

voltage lowers the SETBK threshold, the backup switches turn

off. While the BAT voltage is less than the SETBK threshold, the

switches status depends on the voltage level of the BACK_UP pin

and the BAT pin. The internal BACK_UP_Mx and BACK_UP

control circuit automatically determine the BACK_UP switches

(BACK_UP_M1 and BACK_UP_M2) on/off status and selects

the high voltage terminal as the power source of SYS. The 190 mV

(typical) comparator input offset of the BAT pin prevents the

input source and the BAT pin from charging the BACK_UP pin

(see Figure 44).

ENERGY STORAGE CHARGE MANAGEMENT

Energy storage is connected to the BAT pin. The storage can be

a rechargeable battery, super capacitor, or 100 µF or larger

capacitor. The energy storage controller manages the charging

and discharging operations, monitors the SYS pin voltage, and

asserts the PGOOD signal high when it is above the threshold

programmed at the SETPG pin.

When the BAT pin voltage exceeds the battery terminal charging

threshold programmed at the TERM pin, the boost operation

terminates to prevent battery overcharging. The battery terminal

charging threshold is programmable from 2.2 V to 5.2 V. When

the BAT voltage drops below the battery stop charging threshold

level programmed at the SETSD pin, the switches between the

BAT pin and the SYS pin are turned off to prevent a deep, destruc-

tive battery discharge, and the boost operates in asynchronous

mode. Although there is no current limit at the SYS and the

BAT pins, it is recommended to limit the system load current

to lower than 1000 mA. The large system load current generates a

droop between the SYS pin and the rechargeable battery at the

BAT pin, with consideration given to the resistance of the SYS

switch, the BAT switch, and the rechargeable battery internal

resistance.

In addition, the backup storage element can bypass the cold

startup with inrush current protection circuitry. Nevertheless,

the current capability is only 250 µA (typical) when plugging in

the backup battery before completing the cold start. It is recom-

mended to restrict the system load current from the SYS pin to

ensure that the power path can enter normal operation status.

Table 9 explains the power path working state. For long-term

store mode, disconnect the backup storage element and then

discharge SYS to ground.

When no input source is attached, discharge the SYS pin to

ground before attaching a storage element to the BAT pin.

After hot plugging a charged storage element, release the SYS pin

because a SYS voltage that is less than the end of the cold start

operation threshold (V_{SYS_TH}) results in the BAT switch remaining

off to protect the storage element until the SYS voltage reaches

V

_{SYS_TH}. The BAT switches remaining off can also be described

as store mode, a state with the lowest leakage (3.5 nA typical)

that allows a long store period without discharging the storage

element on BAT.

Rev. A | Page 18 of 28

Data Sheet

ADP5091/ADP5092

BACKUP AND BAT SELECTION THRESHOLD

BATTERY OVERCHARGING PROTECTION

To determine when to enable the BACK_UP function, the switch

threshold on the BAT pin must be set by using external resistors at

SETBK pin. When the BAT voltage is lower than the SETBK

threshold, the internal BACK_UP_Mx control circuit automatically

selects the high voltage terminal as the SYS power source. Figure 42

shows the V_SETBKfalling threshold voltage given by Equation 3.

To prevent rechargeable batteries from being overcharged and

damaged, the battery terminal charging threshold (V_{BAT_TERM}) must

be set by using external resistors. Figure 42 shows the V_{BAT_TERM}

rising threshold voltage given by Equation 6.





R

3

2



^TERM1

V

_{BAT_TERM} V_{INT_REF} 1

(6)





R_TERM2











R

(3)

^BK1

V_SETBK V

1

^{INT _ REF}



R_BK2

Considering the quiescent current consumption, the sum of the

resistors must be more than 6 MΩ, that is,

The ADP5091/ADP5092 have an internal resistor, R_{SETBK_HYS}

115 kΩ (typical), to program the hysteresis, given by

Equation 4.

=

R

_TERM1+ R_TERM2≥ 6 Mꢀ

The battery terminal charging threshold is given by V_{BAT_TERM_HYS}

which is internally set to the battery terminal charging threshold

minus an internal hysteresis voltage denoted by V_{BAT_TERM_HYS}

(7)

,

R_{SETBK_HYS}

(4)

V_{SETBK_HYS}V_SETBK



.

R_E

When the voltage at the battery exceeds the V_{BAT_TERM}threshold,

the main boost regulator disables. The main boost starts again

when the battery voltage falls below the V_{BAT_TERM_HYS}level. When

input energy is excessive, the VBAT pin voltage ripples between

the V_{BAT_TERM}and the V_{BAT_TERM_HYS}levels.

where R_Eis the equivalent resistor of the four external

configuration resistor dividers.

Considering the quiescent current consumption, the sum of the

resistors that comprise the resistor divider (R_{SETBK_HYS}, R_BK1, and

R_BK2) must be greater than 6 MΩ, that is,

BATTERY DISCHARGING PROTECTION

R

_{SETBK_HYS}+ R_BK1+ R_BK2> 6 Mꢀ

(5)

To prevent rechargeable batteries from being deeply discharged

and damaged, the battery stop discharging threshold (V_SETSD

must be set by using external resistors. Figure 42 shows the

V_SETSDfalling threshold voltage given by Equation 8.

)

The equivalent resistor of the four external configuration resistor

dividers (R_E) is equivalent to the paralleling value of the three

resistor dividers.







R

(8)

^SD1

V_SETSD V

1

TERM_REF

^{INT _ REF}



R_SD2

BK

The ADP5091/ADP5092 have an internal resistor, R_{SETSD_HYS}

=

BAT

115 kΩ (typical), to program the hysteresis, given by Equation 9.

R

SETBK_HYS

REF

R_{SETSD_HYS}

SD

(9)

V_{SETSD_HYS} V_SETSD



BAT

R_E

R

TERM1

SD1

PG1

BK1

SETSD_HYS

Considering the quiescent current consumption, the sum of the

resistors that comprise the resistor divider (R_{SETSD_HYS}, R_SD1, and

SETSD

SD

R

_SD2) must be more than 6 MΩ, that is,

_{SETSD_HYS}+ R_SD1+ R_SD2≥ 6 Mꢀ

The equivalent resistor of the three external configuration

resistor dividers (R_E) is equivalent to the paralleling value of the

three resistor dividers.

PG

PGOOD

SETPG

R

(10)

PG

BK

R

PG_HYST

SETHYST

PG

V

INT_REF

SETBK

TERM

TERM_REF

2R

TERM

CONTROL

TRM

R

TERM2

SD2

PG2

BK2

R

BAT

Figure 42. ADP5091/ADP5092 Program Paramater Setting

Rev. A | Page 19 of 28

ADP5091/ADP5092

Data Sheet

POWER GOOD (PGOOD)

POWER PATH WORKING FLOW

The ADP5091/ADP5092 allow users to set a programmable

PGOOD voltage threshold, which indicates that the SYS voltage

is at an acceptable level. It must be set by using external resistors.

Figure 42 shows the V_SETPGfalling threshold voltage given by

Equation 11.

Figure 44 shows the power switches structure when the backup

primary battery is used. During the cold start, when a primary

battery connects to the BACK_UP pin, the S1 switch turns on.

The primary battery with the Diode D1 forward voltage drop

can be the SYS power source.

After completing the cold start, if the BAT voltage is above the

SETBK falling threshold, the BACK_UP switches remain off.

When the BAT voltage is lower than the SETBK falling threshold,

the backup control automatically selects the high voltage terminal

as the SYS power source as long as the SYS voltage is more than









R_PG1

V_{SETPG_FALLING}=V

1 +

(11)

^{INT _REF}





R_PG2+ R_{PG_HYST}



The SETHYST pin can program the hysteresis with an external

resistor (R_{PG_HYST}) given by Equation 12.

V

_{SYS_CHG}. The backup control also prevents the BACK_UP









R

_PG1+ R_{PG_HYST}

primary battery from charging the BAT pin. Meanwhile, the BAT

offset of the comparator prevents the input source from

charging the BACK_UP primary battery. Table 9 shows the

power path of the working state.

(12)



^{INT _REF}



V_{SETPG _RISING}= V

1 +

R_PG2

Considering the quiescent current consumption, the sum of the

resistors that comprise the power-good resistor divider

(R_{PG_HYST}, R_PG1, and R_PG2) must be more than 6 MΩ, that is,

S1

D1

R

_{PG_HYST}+ R_PG1+ R_PG2≥ 6 MΩ

BACK_UP

+

BACK_UP_M1

The logic high level on PGOOD is equal to the SYS voltage and

the logic low level is ground. The logic high level has approximately

11.6 kΩ (typical) internally in series to limit the available current.

The V_{SETPG_FALLING}threshold must be greater than the V_SETSD

threshold.

–

BACK_UP_M2

SYS SWITCH

HS

SYS

SW

For the best operation of the system, use PGOOD to enable the

system load or to turn on an ultralow power load switch or to

drive an external positive channel field effect transistor (PFET)

between SYS and the system load via an inverter to determine

when the system load can be connected or removed (see Figure 48).

BAT_M1 BAT_M2

BAT

+

BSTO

–

LS

GATE

DRIVER

GATE DRIVER

Figure 44. ADP5091/ADP5092 Power Switches Structure

Table 8 shows programming threshold resistor examples

corresponding to various voltages with a 10 MΩ resistor divider.

Figure 43 shows various threshold voltages states.

MAXIMUM DEVICE

CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION

The boost regulator and regulated output in hysteresis boost mode

in the ADP5091/ADP5092 includes current-limit protection

circuitry to limit the amount of positive current flowing through

the low-side boost switch. The boost regulator current-limit

protection circuitry is a cycle-by-cycle, three-level peak current-

limit protection with a third level of 200 mA (typical), and the

regulated output current-limit protection circuitry is 100 mA

(typical). In LDO mode, the current-limit protection is designed

to limit the current when the output load reaches 260 mA

(typical). When the output load exceeds 260 mA, the output

voltage reduces to maintain a constant current limit.

RATING VOLTAGE

MAIN BOOST

CHARGER OFF

TURN OFF MAIN BOOST

V

BAT_TERM

BAT_TERM_HYS

PGOOD BECOMES HIGH

V

SETPG_RISING

SETPG_FALLING

MAIN BOOST

CHARGER ON

MAIN BOOST IN

SYNCHRONOUS MODE

TURN ON SWITCH BETWEEN

BSTO AND BAT

V

SETSD_HYS

Although there is no current limit at the SYS and the BAT pins,

it is recommended to limit the system load current to lower

than 1000 mA. The total resistance of the SYS switch and the

BAT switch (1.03 Ω, typical) generates a voltage drop when the

system load sinks a large current from BAT. It is also necessary

to consider the internal resistance of the storage elements

connected to the BAT pin.

SETSD

V

SYS_CHG

CHARGING BATTERY

V

SYS_CHG_HYS

TURN ON MAIN BOOST IN

ASYNCHRONOUS MODE

V

SYS_TH

COLD STARTUP

ENABLE CHIP

0V

Figure 43. ADP5091/ADP5092 Various Threshold Voltages States (See

Equation 8 and Equation 9)

Rev. A | Page 20 of 28

Data Sheet

ADP5091/ADP5092

included, allowing the ADP5091/ADP5092 to return to operation

when the on-chip temperature drops to less than 127°C. When

exiting thermal shutdown, the boost and the energy storage

controller resume their functions.

THERMAL SHUTDOWN

In the event that the ADP5091/ADP5092 junction temperature

rises above 142°C, the thermal shutdown circuit turns off the

switch between the BAT pin and the SYS pin to prevent the

damage of the energy storage at a high ambient temperature. In

addition, the boost operation terminates. A 15°C hysteresis is

Table 8. Programming Threshold Resistors (See Figure 42)

Voltage Threshold (V)

R_BK1, R_SD1, and R_PG1(MΩ)

R_BK2, R_SD2, and R_PG2(MΩ)

R_TERM1(MΩ)

Not applicable

3.2

3.48

3.74

4

4.22

4.42

4.64

4.87

5

5.11

5.36

5.49

5.6

R_TERM2(MΩ)

Not applicable

6.81

6.49

6.2

6.04

5.76

5.6

5.36

5.23

5

4.87

4.7

4.53

4.42

4.3

4.12

2

5

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4

5.23

5.49

5.62

5.9

6.04

6.19

6.34

6.49

6.6

4.75

4.53

4.32

4.12

4

3.83

3.74

3.57

3.48

3.32

3.24

3.09

3.01

2.94

2.87

2.8

6.65

6.8

6.81

6.98

7.15

7.32

7.5

5.76

5.9

6.04

6.19

6.2

2.7

4.02

3.92

3.83

3.74

2.61

2.55

2.5

7.5

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5

7.5

2.43

2.37

2.32

2.26

2.21

2.15

2.1

2.05

2

1.96

1.91

6.34

6.49

6.6

6.65

6.8

6.81

6.98

7.15

3.65

3.57

3.48

3.4

3.32

3.24

3.2

3.09

3

2.94

2.87

7.68

7.87

8.06

5.1

5.2

Rev. A | Page 21 of 28

ADP5091/ADP5092

Data Sheet

Table 9. Power Path Working State (See Figure 44)

Backup Battery Power Condition¹

Main Boost

BAT_M1

BAT_M2 SYS Switch BACK_UP_M1

BACK_UP_M2

Without

V_{SYS_CHG}> V_SYS> V_{SYS_TH}

_SETSD> V_BAT

V_SYS> V_{SYS_CHG}, V_SETSD> V_BAT

,

Asynchronous

Off

On

Off

V

Asynchronous

On

Off

On

Off

On

Off

V_{BAT_TERM}> V_BAT= V_SYS> V_SETSDSynchronous

V_SYS> V_{SYS_TH}, V_BAT> V_{BAT_TERM}

V_{SYS_CHG}> V_SYS> V_{SYS_TH}

_SETSD> V_BAT

V_SYS> V_{SYS_CHG}, V_SETSD> V_BAT

_{BACK_UP}> V_BAT

V_SYS> V_{SYS_TH}, V_BAT> V_SETSD

_BAT> V_SETBK

V_SYS> V_{SYS_TH}, V_BAT> V_SETSD

Disabled

With

,

Asynchronous

V

,

Asynchronous

Synchronous

Disabled

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

V

,

V

_BAT< V_SETBK, V_{BACK_UP}> V_BAT

V_SYS< V_{SYS_TH}

¹V_{BACK_UP}is the voltage on the BACK_UP pin, and V_SETBKis the threshold of the SETBK pin.

Rev. A | Page 22 of 28

Data Sheet

ADP5091/ADP5092

APPLICATIONS INFORMATION

The ADP5091/ADP5092 extract the energy from the VIN pin

to charge the SYS and the BAT pins. This process occurs in

three stages: cold start, asynchronous boost, and synchronous

boost. This section describes the procedures for selecting the

external components to maintain the energy transmission

system with the layout and assembly considerations.

Table 10. Recommended Solar Cells

Vendor

Device Type

Alta Devices

Fujikura

Gcell

GaAs

Dye sensitized solar cell

ElectricFilm

ENERGY HARVESTER SELECTION

ENERGY STORAGE ELEMENT SELECTION

The energy harvester input source must provide a minimum level

of power for cold start, asynchronous boost, and synchronous

boost. To estimate the minimum input power required to

complete the cold start using the following equation:

To protect the storage element from overcharging or overdis-

charging, the storage element must be connected to the BAT pin

and the system load tied to the SYS pin. The ADP5091/ADP5092

support many types of storage elements, such as rechargeable

batteries, super capacitors, and conventional capacitors. A

storage element with a 100 µF equivalent capacitance is required

to filter the pulse currents of the PFM switching converter. The

storage element capacity must provide the entire system load

when the input source is no longer generating power.

V_IN× I_IN× η_COLD> V_{SYS_TH}× I_{SYS_LOAD}

(13)

where:

V

_INis clamped to V_{IN_COLD}= 380 mV (typical), which indicates

the minimum input voltage for cold start.

_INis the input current.

_COLDis the cold start efficiency, which is about 5% to 7%.

(V_{SYS_TH}is the end of cold start operation.

_{SYS_LOAD}is the system load current of the SYS pin. Minimizing

I

η

If there is a high pulse current or the storage element has

significant impedance, it may be necessary to increase the SYS

capacitor from the 4.7 µF minimum, or add additional capacitance

to the BAT pin to prevent a droop in the SYS voltage. Note that

increasing the SYS capacitor causes the boost regulator to operate

in the less efficient cold start stage for a longer period at startup.

If the application is unable to accept the longer cold start time,

place the additional capacitor parallel to the storage element. See

the Capacitor Selection section for more information.

I

the system load accelerates the cold start. Programming the

PGOOD threshold to enable the system load current is

recommended.

After the ADP5091/ADP5092 complete the cold start, the MPPT

function enables. To meet the average system load current, the

input source must provide the boost regulator with enough power

to fully charge the storage element while the system is in low

power or sleep mode. To estimate the power required by the

system, use the following equation:

INDUCTOR SELECTION

The boost regulator needs an appropriate inductor for proper

operation. The inductor saturation current must be at least 30%

higher than the expected peak inductor currents, as well as a

low series resistance (DCR) to maintain high efficiency. The

boost regulator internal control circuitry is designed to optimize

the efficiency and control the switching behavior with a nominal

inductance of 22 µH 20%. Table 11 lists some of the

recommended inductors.

V

_IN× I_IN× η_BOOST> V_{BAT_TERM}× (I_{STR_LEAK}+ I_{SYS_LOAD}

)

(14)

where:

V

I

η

_INis regulated to the MPPT pin voltage (MPPT ratio × OCV).

_INis the input current.

_BOOSTis the boost regulator efficiency. See Figure 5 through

Figure 12 in the Typical Performance Characteristics section for

more information.

V_{BAT_TERM}is the battery terminal charging threshold (see Table 1).

I_{STR_LEAK}is the storage element leakage current at the BAT pin.

I_{SYS_LOAD}is the average system load current of the SYS pin.

Table 11. Recommended Inductors

Vendor

Device No.

L (µH)

22

I_SAT(A)¹

2

I_RMS(A)²

1

0.88

0.65

DCR (mΩ)

470

255

Würth Elektronik

74437324220

744042220

0.6

Coilcraft

LPS4018-223M

22

0.8

360

¹I_SATis the dc current that causes the 20% inductance drop from its value without current.

²I_RMSis the current that causes a 20°C rise from a 25°C ambient temperature.

Rev. A | Page 23 of 28

ADP5091/ADP5092

Data Sheet

influences the effectiveness of MPPT. When the IC junction

CAPACITOR SELECTION

temperature exceeds 85°C, a larger capacitance is beneficial to

the effectiveness of MPPT, and for a higher CPB pin leakage

current. It is recommended to keep the same RC time constant

of the MPPT resistors and CBP capacitor (up to 22 µF) as shown

in the typical application circuit in Figure 45. Considering the

time constant of the MPPT resistor divide and the CBP capacitor, a

low leakage X7R or C0G 10 nF ceramic capacitor is recommended.

Low leakage capacitors are required for ultralow power

applications that are sensitive to the leakage current. Any

leakage from the capacitors reduces efficiency, increases the

quiescent current, and degrades the MPPT effectiveness.

Input Capacitor

A capacitor (C_IN) connected to the VIN pin and the PGND pin

stores energy from the input source. For the energy harvester,

capacitive behavior dominates the source impedance. Scale the

input capacitor according to the value of the output capacitance

of the energy harvester; a minimum of 10 µF is recommended.

LAYOUT AND ASSEMBLY CONSIDERATIONS

Carefully consider the printed circuit board (PCB) layout

during the design of the switching power supply, especially at

high peak currents and high switching frequency. Therefore, it

is recommended to use wide and short traces for the main power

path and the power ground paths. Place the input capacitors,

output capacitors, inductor, and storage elements as close as

possible to the IC. It is most important for the boost regulator to

minimize the power path from output to ground. Therefore,

place the output capacitor as close as possible between the SYS

pin and the PGND pin. Keep a minimum power path from the

input capacitor to the inductor from the VIN pin to the PGND

pin. Place the input capacitor as close as possible between the

VIN pin and the PGND pin, and place the inductor close to the

VIN pin and the SW pin. It is best to use vias and bottom traces

for connecting the inductors to their respective pins. To minimize

noise pickup by the high impedance threshold setting nodes

(REF, TERM, SETBK, SETSD, and SETPG), place the external

resistors close to the IC with short traces.

For the primary battery application, a larger capacitance helps

to reduce the input voltage ripple and keeps the source current

stable to extend the battery life.

SYS Capacitor

The ADP5091/ADP5092 require two capacitors to be connected

between the SYS pin and the PGND pin. Connect a low ESR

ceramic capacitor of at least 4.7 µF parallel to a high frequency,

0.1 µF bypass capacitor. Connect the bypass capacitor as close as

possible between SYS and PGND.

REG_OUT Capacitor

The ADP5091/ADP5092 regulated output is designed for

operation with small, space-saving ceramic capacitors but

functions with the most commonly used capacitors as long as

care is taken with regard to the effective series resistance (ESR)

value. The ESR of the output capacitor affects stability of the

LDO control loop. A minimum capacitance of 4.7 µF with an

ESR of 1 Ω or less is recommended to ensure stability of the

regulated output. Transient response to changes in load current

is also affected by output capacitance. Using a larger value of

output capacitance improves the transient response of the

regulated output to large changes in load current.

The CBP capacitor must hold the MPPT voltage for 16 sec,

because any leakage can degrade the MPPT effectiveness. During

board assembly and cleaning, contaminants such as solder flux

and residue may form parasitic resistance to ground, especially

in humid environments with fast airflow. Contamination can

significantly degrade the voltage regulation and change threshold

levels set by the external resistors. Therefore, it is recommended

that no ground planes be poured near the CBP capacitor or the

threshold setting resistors. In addition, carefully clean the boards. If

possible, clean ionic contamination with deionized water for the

CBP capacitor and the threshold setting resistors.

CBP Capacitor

The operation of the MPPT pin depends on the sampled value

of the OCV. The voltage stored on the CBP capacitor regulates

to the VIN pin. This capacitor is sensitive to leakage because the

holding period is around 16 sec. As the capacitor voltage drops

due to leakage, the VIN regulation voltage also drops and

Rev. A | Page 24 of 28

Data Sheet

ADP5091/ADP5092

TYPICAL APPLICATION CIRCUITS

VID

LLD

REG_OUT

REG_FB

TO MCU

111kΩ

2V

SENSOR

10µF

REG_D0

REG_D1

FROM MCU

22µH

PGOOD

SYS

SOLAR

HARVESTER

SW

VIN

4.7µF

10µF

4.7MΩ

BAT

+

MPPT

CBP

–

18MΩ

PA-5R0H224

0.22F

MCU

(ALWAYS ON)

10nF

ADP5091

REF

SETSD

SETPG

BACK_UP

CR2032

+

–

3V

DIS_SW

MINOP

225mAh

ADF7024

(Rx/Tx)

SETHYST

SETBK

150kΩ

TERM

AGND PGND

Figure 45. ADP5091-Based Energy Harvester Wireless Sensor Application with PV Cell as the Harvesting Energy Source (Trony 0.7 V, 60 μA, Alta Devices 0.72 V, 42 ꢀA,

Gcell 1.1 V, 100 μA), Cooper Bussmann Super Capacitor PA-5R0H224 as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup

Battery

VID

LLD

REG_OUT

REG_FB

TO MCU

111kΩ

2V

10µF

FROM MCU

22µH

REG_D0

REG_D1

THERMOELECTRIC

GENERATOR

PGOOD

SYS

SW

VIN

4.7µF

+

10µF

BAT

+

MPPT

CBP

–

250kΩ

PA-5R0H224

0.22F

10nF

ADP5091

REF

SETSD

SETPG

BACK_UP

CR2032

3V

225mAh

+

–

DIS_SW

MINOP

SETHYST

SETBK

TERM

AGND PGND

Figure 46. ADP5091-Based Energy Harvester Circuit with a Thermoelectric Generator as the Harvesting Energy Source, Cooper Bussmann Super Capacitor

PA-5R0H224 as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup Battery

Rev. A | Page 25 of 28

ADP5091/ADP5092

Data Sheet

VID

LLD

REG_OUT

REG_FB

TO MCU

2V

R1 10MΩ

R2 10MΩ

10µF

REG_D0

REG_D1

FROM MCU

22µH

PIEZOELECTRIC

HARVESTER

PGOOD

SYS

SW

VIN

4.7µF

10MΩ

BAT

+

–

10µF

MPPT

CBP

PA-5R0H224

0.22F

10nF

ADP5091

REF

SETSD

SETPG

BACK_UP

CR2032

+

–

3V

DIS_SW

MINOP

225mAh

SETHYST

SETBK

200kΩ

TERM

AGND PGND

Figure 47. ADP5091-Based Energy Harvester Circuit with a Piezoelectric Generator as the Harvesting Energy Source, Cooper Bussmann Super Capacitor PA-5R0H224

as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup Battery

VID

REG_GOOD

REG_OUT

111kΩ

2V

1µF

REG_D0

REG_D1

REG_FB

SYS

FROM MCU

22µH

SYSTEM

LOAD

4.7µF

SYS

SW

VIN

TRANSFORMER

PGOOD

BAT

6.34MΩ

AC

10µF

MPPT

CBP

+

–

14.7MΩ

PA-5R0H224

0.22F

10nF

ADP5092

REF

SETSD

SETPG

BACK_UP

CR2032

3V

225mAh

+

–

DIS_SW

MINOP

SETHYST

SETBK

20kΩ

TERM

AGND PGND

Figure 48. ADP5092 AC Input Source and PGOOD Function Determines the Time to Enable the System Load

Rev. A | Page 26 of 28

Data Sheet

ADP5091/ADP5092

FACTORY PROGRAMMABLE OPTIONS

To order a device with options other than the default options,

contact a local Analog Devices, Inc., sales or distribution

representative.

Table 13. VIN Open Circuit Voltage Sampling Cycle Options

Option

Description

Option 0

Option 1

Option 2

Option 3

4 sec

8 sec

16 sec (default)

32 sec

Table 12. Input Current-Limit Options

Option

Description

200 mA (default)

300 mA

Option 0

Option 1

Rev. A | Page 27 of 28

ADP5091/ADP5092

Data Sheet

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

4.10

4.00 SQ

3.90

0.30

0.25

0.20

PIN 1

INDICATOR

PIN 1

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

24

19

18

1

0.50

BSC

2.44

2.30 SQ

2.16

EXPOSED

PAD

13

12

6

7

0.50

0.40

0.30

0.20 MIN

TOP VIEW

BOTTOM VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8

Figure 49. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-24-14)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

ADP5091ACPZ-1-R7

−40°C to + 125°C

24-Lead Lead Frame Chip Scale Package [LFCSP], 200 mA Input

Peak Current

CP-24-14

ADP5091ACPZ-2-R7

ADP5092ACPZ-1-R7

−40°C to + 125°C

24-Lead Lead Frame Chip Scale Package [LFCSP], 300 mA Input

Peak Current

24-Lead Lead Frame Chip Scale Package [LFCSP], 200 mA Input

Peak Current

CP-24-14

ADP5091-1-EVALZ

ADP5091-2-EVALZ

ADP5092-1-EVALZ

Evaluation Board

Evaluation Board with Solar Harvester and Super Capacitor

Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D14145-0-5/17(A)

Rev. A | Page 28 of 28


型号：	ADP5092
厂家：	ADI
描述：	Ultralow Power Energy Harvester PMUs with MPPT and Charge Management
文件：	总28页 (文件大小：916K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP5092 [ADI]

相关型号：

ADP5092-1-EVALZ

ADP5092ACPZ-1-R7

ADP5100

ADP5101

ADP5110

ADP5111

ADP5120

ADP5121

ADP5130

ADP5131

ADP5133ACBZ-R7

ADP5134ACPZ-R7