ADP5042ACPZ-2-R7 [ADI]
Micro PMU with 0.8 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset;
| 型号： | ADP5042ACPZ-2-R7 |
| 厂家： | 
ADI |
| 描述： | Micro PMU with 0.8 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset |
| 文件： | 总33页 (文件大小：1425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Micro PMU with 0.8 A Buck, Two 300 mA LDOs
Supervisory, Watchdog and Manual Reset
Data Sheet
ADP5042
FEATURES
HIGH LEVEL BLOCK DIAGRAM
Input voltage range: 2.3 V to 5.5 V
One 0.8 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Initial regulator accuracy: 1%
Overcurrent and thermal protection
Soft start
R
= 30Ω
FILT
AVIN
L1
1µH
AVIN
VIN1
SW
V
AT
OUT1
800mA
VOUT1
PGND
VIN1 = 2.3V
TO 5.5V
C6
BUCK
EN_BK
10µF
C5
4.7µF
ON
FPWM
MODE
EN1
OFF
OFF
PSM/PWM
VOUT2
V
AT
OUT2
300mA
LDO1
(DIGITAL)
VIN2
VIN2 = 1.7V
TO 5.5V
C1
1µF
C2
1µF
EN_LDO1
ON
ON
WSTAT
nRSTO
EN2
AVIN
Undervoltage lockout
WDI1
WDI2
MR
Open drain processor reset with threshold monitoring
1.5% threshold accuracy over the full temperate range
Guaranteed reset output valid to VCC = 1 V
Dual watchdog for secure systems
Watchdog 1 controls reset
EN3
OFF
EN_LDO2
VOUT3
VIN3
V
AT
VIN3 = 1.7V
TO 5.5V
OUT3
300mA
LDO2
(ANALOG)
C3
1µF
C4
1µF
AGND
Watchdog 2 controls reset and regulators power cycle
Buck key specifications
Figure 1.
Current mode topology for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PFM/PSM modes
100% duty cycle low dropout mode
LDOs key specifications
Low VIN from 1.7 V to 5.5 V
Stable with1 µF ceramic output capacitors
High PSRR, 60 dB PSRR up to 1 kHz/10 kHz
Low output noise
110 µV rms typical output noise at VOUT = 2.8 V
Low dropout voltage: 150 mV at 300 mA load
−40°C to +125°C junction temperature range
GENERAL DESCRIPTION
The ADP5042 combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
requirements.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5042 LDOs extend the battery life of
portable devices. The two LDOs maintain power supply
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.
The high switching frequency of the buck regulator enables
use of tiny multilayer external components and minimizes the
board space.
Each regulator is activated by a high level on the respective
enable pin. The ADP5042 is available with factory programmable
default output voltages and can be set to a wide range of options.
The MODE pin selects the buck mode of operation. When set
to logic high, the buck regulators operate in forced PWM mode.
When the MODE pin is set to logic low, the buck regulators
operate in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold
the regulator operates in power save mode (PSM) improving
the light-load efficiency.
The ADP5042 contains supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. They also provide power-on
reset signals. An on-chip dual watchdog timer can reset the
microprocessor or power cycle the system (Watchdog 2) if it
fails to strobe within a preset timeout period.
Rev. A
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ADP5042* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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Supervisory, Watchdog and Manual Reset
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ADP5042
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power Management Unit........................................................... 18
Buck Section................................................................................ 19
LDO Section ............................................................................... 20
Supervisory Section ................................................................... 20
Applications Information.............................................................. 23
Buck External Component Selection....................................... 23
LDO Capacitor Selection .......................................................... 24
Supervisory Section ................................................................... 25
PCB Layout Guidelines.............................................................. 26
Evaluation Board Schematics and Artwork............................ 27
Suggested Layout........................................................................ 27
Bill of Materials........................................................................... 28
Application Diagram ................................................................. 28
Factory Programmable Options................................................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
High Level Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
General Specification................................................................... 3
Supervisory Specification............................................................ 3
Buck Specifications....................................................................... 5
LDO1, LDO2 Specifications ....................................................... 5
Input and Output Capacitor, Recommended Specifications.. 6
Absolute Maximum Ratings............................................................ 7
Thermal Data................................................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Theory of Operation ...................................................................... 18
REVISION HISTORY
10/11—Rev. 0 to Rev. A
Updated Outline Dimensions....................................................... 30
Changes to Ordering Guide .......................................................... 30
12/10—Revision 0: Initial Version
Rev. A | Page 2 of 32
Data Sheet
ADP5042
SPECIFICATIONS
GENERAL SPECIFICATION
AVIN, VIN1 = (VOUT1+ 0.5 V) or 2.3 V, whichever is greater, AVIN, VIN1 ≥ VIN2, VIN3, TA = 25°C, unless otherwise noted. Regulators
are enabled.
Table 1.
Parameter
Symbol
Description
Min Typ Max Unit
AVIN UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
SHUTDOWN CURRENT
UVLOAVIN
UVLOAVINRISE
UVLOAVINFALL
IGND-SD
TJ = −40°C to +125°C
2.25
2
V
V
1.95
1.2
ENx = GND
ENx = GND, TJ = −40°C to +125°C
TJ rising
0.1
µA
µA
°C
°C
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSSD
TSSD-HYS
150
20
MR
ENx, WDIx, MODE, WMOD,
Input Logic High
INPUTS
VIH
VIL
VI-LEAKAGE
2.5 V ≤ AVIN ≤ 5.5 V
2.5 V ≤ AVIN ≤ 5.5 V
ENx = AVIN or GND
V
V
µA
Input Logic Low
Input Leakage Current (WMOD
Excluded)
0.4
0.05
30
ENx = AVIN or GND, TJ = −40°C to +125°C
VWMOD = 3.6 V, TJ = −40°C to +125°C
1
50
µA
µA
WMOD Input Leakage Current
OPEN-DRAIN OUTPUTS
nRSTO, WSTAT Output Voltage
VI-LKG-WMOD
VOL
AVIN = 2.3 V to 5.5 V, InRSTO/WSTAT = 3 mA
mV
Open-Drain Reset Output Leakage
Current
1
µA
SUPERVISORY SPECIFICATION
AVIN, VIN1 = full operating range, TJ = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY
Supply Current (Supervisory Circuit Only)
45
43
55
52
µA
µA
V
AVIN = 5.5 V, EN1 = EN2 = EN3 = VIN
AVIN = 3.6 V, EN1 = EN2 = EN3 = VIN
TA = 25°C, sensed on VOUTx
TJ = −40°C to +125°C, sensed on
VOUTx
RESET THRESHOLD ACCURACY
VTH − 0.8%
VTH − 1.5%
VTH
VTH
VTH + 0.8%
VTH + 1.5%
V
RESET THRESHOLD TO OUTPUT DELAY
50
125
400
µs
VTH = VUOT − 50 mV
GLITCH IMMUNITY (tUOD
)
RESET TIMEOUT PERIOD WATCHDOG1 (tRP1
Option A
Option B
)
)
24
160
30
200
36
240
ms
ms
RESET TIMEOUT PERIOD WATCHDOG2 (tRP2
3.5
5
7
ms
µs
VCC TO RESET DELAY (tRD)
150
2
VIN1 falling at 1 mV/µs
REGULATORS SEQUENCING DELAY (tD1, tD2)
WATCHDOG INPUTS
ms
Watchdog 1 Timeout Period (tWD1
)
Option A
Option B
81.6
1.28
102
1.6
122.4
1.92
ms
sec
Rev. A | Page 3 of 32
ADP5042
Data Sheet
Parameter
Watchdog 2 Timeout Period (tWD2
Option A
Min
Typ
Max
Unit
Test Conditions/Comments
)
6
7.5
9
sec
Option B
Watchdog 2 disabled
Option C
Option D
Option E
Option F
Option G
Option H
3.2
6.4
11.2
25.6
51.2
102.4
4
8
16
32
64
128
4.8
9.6
19.2
38.4
76.8
153.8
min
min
min
min
min
min
Watchdog 2 Power Off Period (tPOFF
Option A
Option B
WDI1 Pulse Width
WDI2 Pulse Width
)
210
400
ms
ms
ns
80
8
VIL = 0.4 V, VIH = 1.2 V
VIL = 0.4 V, VIH = 1.2 V
µs
Watchdog Status Timeout Period (tWDCLEAR
WDI1 Input Current (Source)
WDI1 Input Current (Sink)
WDI2 Internal Pull-Down
MANUAL RESET INPUT
)
11.2
15
−25
45
sec
µA
µA
kΩ
8
−30
20
−14
VWDI1 = VCC, time average
VWDI1 = 0, time average
MR Input Pulse Width
1
µs
ns
kΩ
ns
MR Glitch Rejection
220
52
MR Pull-Up Resistance
25
80
MR to Reset Delay
280
VCC = 5 V
Rev. A | Page 4 of 32
Data Sheet
ADP5042
BUCK SPECIFICATIONS
AVIN, VIN1 = 3.6 V, VOUT1 = 1.8 V, TJ= −40°C to +125°C for minimum/maximum specifications, L = 1 µH, COUT = 10 µF, and TA = 25°C
for typical specifications, unless otherwise noted.1
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Voltage Range (VIN1)
OUTPUT CHARACTERISTICS
Output Voltage Accuracy
2.3
5.5
V
PWM mode, TA= 25 °C , ILOAD = 100 mA
PWM mode
VIN1 = 2.3 V to 5.5 V, PWM mode,
ILOAD = 1 to 800 mA
−1
−2
−3
+1
+2
+3
%
%
%
PWM TO POWER SAVE MODE CURRENT THRESHOLD
INPUT CURRENT CHARACTERISTICS
DC Operating Current
100
mA
ILOAD = 0 mA, device not switching
ENx = 0 V, TA = TJ = −40°C to +125°C
21
0.2
35
1.0
μA
μA
Shutdown Current
SW CHARACTERISTICS
SW On Resistance
PFET
180
140
170
150
1360
75
240
190
235
210
1600
mΩ
mΩ
mΩ
mΩ
mA
Ω
PFET, AVIN = VIN1 = 5 V
NFET
NFET, AVIN = VIN1 = 5 V
PFET switch peak current limit
EN1 = 0 V
Current Limit
1100
2.5
ACTIVE PULL-DOWN
OSCILLATOR FREQUENCY
START-UP TIME
3.0
3.5
MHz
μs
250
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
LDO1, LDO2 SPECIFICATIONS
AVIN = 3.6 V, VIN2, VIN3 = (VOUT3 + 0.2 V) or 2.3 V, whichever is greater; AVIN, VIN1 ≥ VIN2, VIN3; IOUT = 10 mA; CIN = COUT = 1 µF;
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Symbol
VIN2, VIN3
IGND
Conditions
Min
Typ
Max
Unit
V
INPUT VOLTAGE RANGE
TJ = −40°C to +125°C
IOUT = 0 µA, VOUT = 3.3 V
1.7
5.5
OPERATING SUPPLY CURRENT (per
LDO)
15
µA
IOUT = 0 µA, VOUT = 3.3 V, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 200 mA
IOUT = 200 mA, TJ = −40°C to +125°C
IOUT = 10 mA
100 µA < IOUT < 300 mA
50
µA
µA
µA
µA
µA
%
67
105
100
245
+1
+2
FIXED OUTPUT VOLTAGE ACCURACY
VOUT2, VOUT3
−1
−2
%
VIN2, VIN3 = (VOUT2, VOUT3 + 0.5 V) to 5.5 V
100 µA < IOUT < 300 mA
−3
+3
%
VIN2, VIN3 = (VOUT2, VOUT3 + 0.5 V) to 5.5 V
TJ = −40°C to +125°C
REGULATION
Line Regulation
∆VOUT2/∆VIN2
∆VOUT3/∆VIN3
V
IN2, VIN3 = (VOUT2, VOUT3 + 0.5 V) to 5.5 V
−0.03
+0.03
%/V
IOUT3 = 1 mA
TJ = −40°C to +125°C
Rev. A | Page 5 of 32
ADP5042
Data Sheet
Parameter
Load Regulation1
Symbol
Conditions
OUT2, VOUT3 = 1 mA to 200 mA
Min
Typ
Max
Unit
∆VOUT2/∆IOUT2
∆VOUT3/∆IOUT3
I
0.002
%/mA
IOUT2, VOUT3 = 1 mA to 200 mA
TJ = −40°C to +125°C
0.0075
%/mA
DROPOUT VOLTAGE2
VDROPOUT
VOUT2, VOUT3 = 3.3 V
IOUT2, IOUT3 = 10 mA
IOUT2, IOUT3 = 10 mA, TJ = −40°C to +125°C
IOUT2, IOUT3 = 200 mA
IOUT2, IOUT3 = 200 mA, TJ = −40°C to +125°C
EN2/EN3 = 0 V
4
mV
mV
mV
mV
Ω
5
60
100
ACTIVE PULL-DOWN
START-UP TIME
CURRENT-LIMIT THRESHOLD3
RPDLDO
600
85
TSTART-UP
ILIMIT
VOUT2, VOUT3 = 3.3 V
µs
TJ = −40°C to +125°C
335
470
123
110
59
140
129
66
mA
OUTPUT NOISE
OUTLDO2NOISE
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
OUTLDO1NOISE
POWER SUPPLY REJECTION RATIO
PSRR
1 kHz, VIN2, VIN3 = 3.3 V, VOUT2, OUT3 = 2.8 V,
IOUT = 100 mA
100 kHz, VIN2,VIN3 = 3.3 V, VOUT2,VOUT3 = 2.8 V,
IOUT = 100 mA
1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,
IOUT = 100 mA
66
dB
dB
dB
57
60
1 Based on an end-point calculation using 1 mA and 100 mA loads.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
3 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 5.
Parameter
Symbol
CMIN1
Conditions
Min
7
Typ
Max
Unit
µF
MINIMUM OUTPUT CAPACITANCE (BUCK)1
MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO1, LDO2)
CAPACITOR ESR
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TJ = −40°C to +125°C
40
CMIN23
RESR
0.70
0.001
µF
1
Ω
1 The minimum output capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met.
2 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with LDOs or the buck.
Rev. A | Page 6 of 32
Data Sheet
ADP5042
ABSOLUTE MAXIMUM RATINGS
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The specified
value of θJA is based on a four-layer, 4” × 3”, 2.5 oz copper board,
as per JEDEC standard. For additional information, see the
AN-772 Application Note, A Design and Manufacturing Guide
for the Lead Frame Chip Scale (LFCSP).
Table 6.
Parameter
Rating
AVIN, VINx, VOUTx, ENx, MODE, MR, WDIx,
WMOD, WSTAT, nRSTO to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
−0.3 V to +6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
3000 V
ESD Human Body Model
ESD Charged Device Model
ESD Machine Model
1500 V
100 V
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type
20-Lead, 0.5 mm pitch LFCSP
θJA
θJC
Unit
38
4.2
°C/W
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
ESD CAUTION
The ADP5042 can be damaged when the junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient
temperature may have to be derated. In applications with
moderate power dissipation and low PCB thermal resistance,
the maximum ambient temperature can exceed the maximum
limit as long as the junction temperature is within specification
limits. The junction temperature of the device is dependent on
the ambient temperature, the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package. Maximum junction temperature is calculated from the
ambient temperature and power dissipation using the formula
TJ = TA + (PD × θJA)
Rev. A | Page 7 of 32
ADP5042
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 WSTAT
14 VOUT2
13 VIN2
NC
VOUT3
VIN3
1
2
3
4
5
ADP5042
TOP VIEW
(Not to Scale)
EN3
12 WDI2
nRSTO
11 VOUT1
NOTES
1. EXPOSED PAD SHOULD BE CONNECTED TO AGND.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 2. Pin Configuration—View from Top of the Die
Table 8. Preliminary Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
NC
VOUT3
VIN3
Do not connect to this pin.
LDO2 Output Voltage and Sensing Input.
LDO2 Input Supply (1.7 V to 5.5 V).
4
5
6
7
EN3
Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2.
Open-Drain Reset Output, Active Low.
Regulators Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V).
Buck Input Supply (2.3 V to 5.5 V).
nRSTO
AVIN
VIN1
8
SW
Buck Switching Node.
9
PGND
EN1
VOUT1
WDI2
VIN2
Dedicated Power Ground for Buck Regulator.
Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck.
Buck Sensing Node.
Watchdog 2 (Long Timeout) Refresh Input from Processor. Can be disabled only by factory option.
LDO1 Input Supply (1.7 V to 5.5 V).
LDO1 Output Voltage and Sensing Input.
Open-Drain Watchdog Timeout Status. WSTAT = high: Watchdog 1 timeout or power-on reset; WSTAT = low:
Watchdog 2 timeout. Auto cleared after one second.
10
11
12
13
14
15
VOUT2
WSTAT
16
17
EN2
MODE
Enable LDO1. EN2 = high: turn on LDO1. EN2 = low: turn off LDO1.
Buck Mode. MODE = high: buck regulator operates in fixed PWM mode; MODE = low: buck regulator operates
in pulse skipping mode (PSM) at light load and in constant PWM at higher load.
18
WMOD
Watchdog Mode. WMOD = low: Watchdog 1 normal mode; WMOD = high: Watchdog 1 cannot be disabled by
a three-state condition applied on WDI1.
19
20
TP
WDI1
MR
Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled.
Manual Reset Input, Active Low.
AGND
Analog Ground (TP = Thermal Pad). Exposed pad should be connected to AGND.
Rev. A | Page 8 of 32
Data Sheet
ADP5042
TYPICAL PERFORMANCE CHARACTERISTICS
VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted.
SW
4
2
VOUT1
1
VOUT1
VOUT2
2
VOUT3
3
EN
1
3
LOAD
B
B
B
B
CH1 4.0V/DIV
CH2 3.0V/DIV
CH3 200mA/DIV 1MΩ
CH4 5.0V/DIV 1MΩ
1MΩ
1MΩ
20.0M
500M
20.0M
500M
A
CH1
2.24V
50µs/DIV
20.0MS/s
50.0ns/pt
W
W
W
W
B
CH1 2.0V/DIV 1MΩ
CH2 2.0V/DIV 1MΩ
CH3 2.0V/DIV 1MΩ
20.0M
500M
20.0M
A
CH1
1.76V
200µs/DIV
50.0MS/s
20.0ns/pt
W
W
W
B
B
Figure 3. 3-Channel Start-Up Waveforms
Figure 6. Buck Startup, VOUT1 = 1.8 V, IOUT2 = 20 mA
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.34
3.32
3.30
3.28
3.26
3.24
3.22
–40°C
+25°C
+85°C
VOUT1 = 1.8V,
VOUT2 = VOUT = 3.3V
2.3
2.8
3.3
3.8
4.3
4.8
5.3
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Figure 4. System Quiescent Current (Sum of All the Input Currents) vs. Input Voltage,
VOUT1 = 1.8 V, VOUT2 = VOUT3 = 3.3 V
Figure 7. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode
1.830
SW
4
–40°C
+25°C
+85°C
1.825
1.820
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
1.775
VOUT1
2
EN
1
IIN
3
B
CH1 2.0V/DIV
CH2 2.0V/DIV
CH3 100mA/DIV 1MΩ
1MΩ
1MΩ
20.0M
500M
20.0M
500M
A
CH1
2.92V
50µs/DIV
50.0MS/s
20.0ns/pt
W
W
B
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
B
B
W
CH4 5.0V/DIV
1MΩ
W
OUTPUT CURRENT (A)
Figure 8. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, Auto Mode
Figure 5. Buck Startup, VOUT1 = 1.8 V, IOUT1 = 20 mA
Rev. A | Page 9 of 32
ADP5042
Data Sheet
100
90
80
70
60
50
40
30
20
10
0
1.795
1.794
1.793
1.792
1.791
1.790
1.789
1.788
1.787
1.786
1.785
3.6V
4.5V
5.5V
+85°C
+25°C
–40°C
0.3
1.784
0
0.001
0.01
0.1
1
0.1
0.2
0.4
0.5
0.6
0.7
0.8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 12. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V,
PWM Mode
Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode
1.797
1.796
100
90
80
70
60
50
40
30
1.795
VIN = 5.5V
1.794
VIN = 4.5V
1.793
VIN = 3.6V
1.792
20
2.4V
1.791
1.790
3.6V
4.5V
5.5V
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 10. Buck Load Regulation Across Input Voltage, VOUT1 = 1.8 V, PWM Mode
Figure 13. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.8 V,
Auto Mode
100
90
80
70
60
50
40
30
100
2.4V
3.6V
4.5V
5.5V
90
80
70
60
50
40
30
20
10
0
20
3.6V
10
4.5V
5.5V
0
0.0001
0.001
0.01
0.1
1
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
I
(A)
OUT
Figure 11. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V,
Auto Mode
Figure 14. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V,
PWM Mode
Rev. A | Page 10 of 32
Data Sheet
ADP5042
100
90
80
70
60
50
40
30
20
10
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
–40ºC
+25ºC
+85ºC
0
0.001
0.01
0.1
1
2.6
3.6
4.6
5.6
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
Figure 15. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V,
PWM Mode
Figure 18. Buck DC Current Capability vs. Input Voltage, VOUT1 = 1.8 V
3.10
100
–40°C
+25°C
+85°C
80
90
–40°C
3.05
+25°C
70
60
50
40
30
20
10
0
3.00
2.95
+85°C
2.90
2.85
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 19. Buck Switching Frequency vs. Output Current, Across Temperature,
VOUT1 = 1.8 V, PWM Mode
Figure 16. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 3.3 V,
Auto Mode
VOUT
100
–40°C
+25°C
+85°C
80
90
1
70
60
50
40
30
20
10
0
I
SW
2
SW
3
B
B
B
CH1 20.0mV/DIV
CH2 200mA/DIV 1MΩ
CH3 2.0V/DIV
20.0M
20.0M
20.0M
A
CH1 2.4mV 5.0µs/DIV
20.0MS/s
W
W
0.0001
0.001
0.01
0.1
1
50.0ns/pt
1MΩ
W
OUTPUT CURRENT (A)
Figure 20. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode
Figure 17. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V,
Auto Mode
Rev. A | Page 11 of 32
ADP5042
Data Sheet
VOUT
2
VIN
I
SW
3
VOUT
SW
2
SW
1
3
1
B
B
B
CH1 2.0V/DIV 1MΩ
CH2 50.0mV/DIV
CH3 500mA/DIV
20.0M
20.0M
20.0M
A
CH1 1.56mV 5.0µs/DIV
200MS/s
CH1 3V/DIV
CH2 50mV/DIV
CH3 900mV/DIV 1MΩ
20.0M A CH3 4.79V
20.0M
20.0M
100µs/DIV
10.0MS/s
100ns/pt
W
W
W
B
B
W
5.0ns/pt
B
W
W
Figure 21. Typical Waveforms, VOUT1 = 1.8 V, IOUT2 = 30 mA, Auto Mode
Figure 24. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V,
VOUT1 = 3.3 V, PWM Mode
VOUT
2
I
SW
3
VOUT
2
SW
SW
3
4
1
B
B
CH1 2.0V/DIV 1MΩ
CH2 50.0mV/DIV
CH3 500mA/DIV
20.0M
20.0M
20.0M
A
CH1 1.56mV 500ns/DIV
200MS/s
B
W
W
CH2 50mV/DIV
CH3 1V/DIV
CH4 2V/DIV
20.0M
20.0M
20.0M
A
CH3 4.96mV 100µs/DIV
20MS/s
W
W
W
B
B
1MΩ
1MΩ
5.0ns/pt
B
100ns/pt
W
Figure 22. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode
Figure 25. Buck Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT1 = 1.8 V,
PWM Mode
VOUT
1
1
I
SW
2
VOUT
2
SW
3
3
B
B
B
CH1 20.0mV/DIV
CH2 200mA/DIV 1MΩ
CH3 2.0V/DIV
20.0M
20.0M
20.0M
A
CH1 2.4mV
200ns/DIV
500MS/s
2.0ns/pt
B
W
W
CH1 4V/DIV
CH2 50mV/DIV 1MΩ
CH3 50mA/DIV 1MΩ
20.0M
20.0M
20.0M
A
CH3 44mA 200µs/DIV
10MS/s
W
W
B
100ns/pt
1MΩ
B
W
W
Figure 23. Typical Waveforms, VOUT1 = 3.3 V, IOUT2 = 30 mA, PWM Mode
Figure 26. Buck Response to Load Transient, IOUT1 from 1 mA to 50 mA,
VOUT1 = 3.3 V, Auto Mode
Rev. A | Page 12 of 32
Data Sheet
ADP5042
SW
1
3
VOUT
2
1
2
LOAD
3
B
B
B
CH1 4V/DIV
CH2 50mV/DIV
CH3 50mA/DIV 1MΩ
20.0M
20.0M
20.0M
A
CH3 28mA 200µs/DIV
5MS/s
CH1 1V/DIV
CH2 3V/DIV
CH3 50mA/DIV 1MΩ
1MΩ
1MΩ
500M A CH2
500M
20.0M
1.14V
50µs/DIV
2MS/s
500ns/pt
W
W
W
B
B
W
W
200ns/pt
B
W
Figure 27. Buck Response to Load Transient, IOUT2 from 1 mA to 50 mA,
VOUT2 = 1.8 V, Auto Mode
Figure 30. LDO1 Startup, VOUT3=1.5 V, IOUT3 = 5 mA
1
3
2
1
2
3
B
B
CH1 4V/DIV
CH2 50mV/DIV
CH3 50mA/DIV 1MΩ
20.0M A CH3
20.0M
20.0M
86mA
200µs/DIV
10MS/s
100ns/pt
CH1 1V/DIV
CH2 3V/DIV
CH3 50mA/DIV 1MΩ
1MΩ
1MΩ
500M A CH2
500M
20.0M
1.14V
100µs/DIV
1MS/s
1.0µs/pt
W
W
W
B
B
W
W
B
B
W
Figure 28. Buck Response to Load Transient, IOUT1 from 20 mA to 140 mA,
VOUT1 = 3.3 V, Auto Mode
Figure 31. LDO2 Startup, VOUT3=3.3 V, IOUT3 = 5 mA
1.510
1.508
1.506
1.504
1.502
1.500
2
3
4
3.3V
4.5V
5.0V
5.5V
B
A CH3
145mA 200µs/DIV
50MS/s
CH2 4V/DIV
CH3 50mV/DIV 1MΩ
CH4 50mA/DIV 1MΩ
1MΩ
20.0M
20.0M
20.0M
W
0.0001
0.001
0.01
0.1
B
W
20ns/pt
B
W
OUTPUT CURRENT (A)
Figure 29. Buck Response to Load Transient, IOUT2 from 20 mA to 180 mA,
VOUT1 = 1.8 V, PWM Mode
Figure 32. LDO1 Load Regulation Across Input Voltage, VOUT2 = 1.5 V
Rev. A | Page 13 of 32
ADP5042
Data Sheet
1.53
1.52
1.51
1.5
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
1.49
1.48
1.47
0.0001
0.001
0.01
0.1
0.0001
0.001
0.01
0.1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 33. LDO1 Load Regulation Across Temperature, VIN2 = 3.3 V, VOUT2 = 1.5 V
Figure 36. LDO2 Load Regulation Across Temperature, VIN3 = 3.6 V, VOUT3 = 3.3 V
1.520
100µA
1mA
3.325
100µA
1mA
3.320
10mA
10mA
1.515
1.510
1.505
1.500
1.495
1.490
1.485
1.480
100mA
150mA
100mA
150mA
3.315
3.310
3.305
3.300
3.295
3.290
3.285
3.280
3.6
4.5
5.0
5.5
3.6
4.5
5.0
5.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 37. LDO2 Line Regulation Across Output Load, VOUT3 = 3.3 V
Figure 34. LDO1 Line Regulation Across Output Load, VOUT2 = 1.5 V
3.35
3.6V
250
4.5V
3.34
5.0V
5.5V
3.33
200
150
100
50
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
0
0.0001
0.001
0.01
0.1
0
0.05
0.10
0.15
OUTPUT CURRENT (A)
LOAD (A)
Figure 35. LDO2 Load Regulation Across Input Voltage, VOUT3 = 3.3 V
Figure 38. LDO2 Ground Current vs. Output Load, VOUT3 = 2.8 V
Rev. A | Page 14 of 32
Data Sheet
ADP5042
0.50
1µA
100µA
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
1mA
10mA
100mA
150mA
VIN
VOUT
1
2
2.3
2.8
3.3
3.8
4.3
4.8
5.3
5.8
B
B
20.0M
20.0M
CH1 10.0mV/DIV
CH2 800mV/DIV
A CH2
5.33V
W
W
INPUT VOLTAGE (V)
1MΩ
Figure 39. LDO2 Ground Current vs. Input Voltage, Across Output Load,
VOUT3 = 2.8 V
Figure 42. LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V,
VOUT3 = 3.3 V
VIN
IOUT
3
VOUT
1
VOUT
1
2
B
B
B
A CH3
28mA 200µs/DIV
500kS/s
CH1 50mV/DIV 1MΩ
CH3 50mA/DIV 1MΩ
500M
20.0M
20.0M
20.0M
CH1 10.0mV/Div
CH2 800mV/Div
A CH2
5.33V
W
W
W
B
1MΩ
W
2.0µs/pt
Figure 40. LDO2 Response to Load Transient, IOUT3 from 1 mA to 80 mA,
VOUT3 = 3.3 V
Figure 43. LDO1 Line Transient VIN = 4.5 V to 5.5 V, VOUT2 = 1.5 V
3.0
2.5
2.0
1.5
1.0
IOUT
3
VOUT
1
0.5
5.5V
4.5V
3.6V
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
B
A CH3
50mA
200µs/DIV
500kS/s
2.0µs/pt
CH1 50mV/DIV 1MΩ
CH3 50mA/DIV 1MΩ
500M
20.0M
LOAD CURRENT (A)
W
B
W
Figure 41. LDO1 Response to Load Transient, IOUT3 from 1 mA to 80 mA,
VOUT2 = 1.5 V
Figure 44. LDO1, LDO2 Output Current Capability vs. Input Voltage
Rev. A | Page 15 of 32
ADP5042
Data Sheet
100
10
VOUT3 = 3.3V, VIN3 = 3.6V, I
VOUT3 = 1.5V, VIN3 = 1.8V, I
VOUT3 = 2.8V, VIN3 = 3.1V, I
= 300mA
= 300mA
= 300mA
LOAD
LOAD
LOAD
100
1
CH2; V
CH2; V
CH2; V
CH2; V
CH2; V
= 3.3V; VIN = 5V
= 3.3V; VIN = 3.6V
= 2.8V; VIN = 3.1V
= 1.5V; VIN = 5V
= 1.5V; VIN = 1.8V
OUT
OUT
OUT
OUT
OUT
0.1
0.01
10
0.0001 0.001
0.01
0.1
1
10
100
1k
1
10
100
1k
10k
100k
1M
LOAD (mA)
FREQUENCY (Hz)
Figure 45. LDO1 Output Noise vs. Load Current, Across Input and Output Voltage
Figure 48. LDO2 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.3 V
100
VOUT2 = 3.3V, VIN2 = 3.6V, I
VOUT3 = 3.3V, VIN3 = 3.6V, I
VOUT2 = 1.5V, VIN2 = 1.8V, I
= 300mA
= 300mA
= 300mA
LOAD
LOAD
LOAD
10
100
1.0
0.1
CH3; VOUT = 3.3V; VIN = 5V
CH3; VOUT = 3.3V; VIN = 3.6V
CH3; VOUT = 2.8V; VIN = 3.1V
CH3; VOUT = 1.5V; VIN = 5V
CH3; VOUT = 1.5V; VIN = 1.8V
10
VOUT3 = 1.5V, VIN3 = 1.8V, I
VOUT2 = 2.8V, VIN2 = 3.1V, I
VOUT3 = 2.8V, VIN3 = 3.1V, I
= 300mA
= 300mA
= 300mA
LOAD
LOAD
LOAD
0.01
10
100
1k
10k
100k
1M
10M
0.0001 0.001
0.01
0.1
1
10
100
1k
FREQUENCY (Hz)
LOAD (mA)
Figure 49. LDO1 vs. LDO2 Noise spectrum
Figure 46. LDO2 Output Noise vs. Load Current, Across Input and Output Voltage
100
VOUT2 = 3.3V, VIN2 = 3.6V, I
VOUT2 = 1.5V, VIN2 = 1.8V, I
VOUT2 = 2.8V, VIN2 = 3.1V, I
= 300mA
= 300mA
= 300mA
LOAD
LOAD
LOAD
–10
–20
1mA
10mA
100mA
200mA
300mA
10
1.0
–30
–40
–50
–60
–70
–80
0.1
–90
0.01
10
100
1k
10k
100k
1M
10M
–100
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 50. LDO2 PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V
Figure 47. LDO1 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.3 V
Rev. A | Page 16 of 32
Data Sheet
ADP5042
–10
–20
–10
–20
1mA
1mA
10mA
100mA
200mA
300mA
10mA
100mA
200mA
300mA
–30
–40
–30
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
10
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 54. LDO1 PSRR Across Output Load, VIN2 = 5.0 V, VOUT2 = 1.5 V
Figure 51. LDO2 PSRR Across Output Load, VIN3 = 3.1 V, VOUT3 = 2.8 V
–10
–10
1mA
10mA
100mA
200mA
1mA
10mA
100mA
–20
–20
200mA
–30
–30
–40
300mA
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 52. LDO2 PSRR Across Output Load, VIN3 = 5 V, VOUT3 = 3.3 V
Figure 55. LDO1 PSRR Across Output Load, VIN2 = 1.8 V, VOUT2 = 1.5 V
–10
1mA
10mA
100mA
–20
200mA
300mA
–30
–40
–50
–60
–70
–80
–90
–100
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 53. LDO2 PSRR Across Output Load, VIN3 = 3.6 V, VOUT3 = 3.3 V
Rev. A | Page 17 of 32
ADP5042
Data Sheet
THEORY OF OPERATION
VOUT1
WMOD
WDI1
WDI2
MR
40kΩ
60Ω
ENWD1
ENWD2
ENBK
VDDA
52kΩ
WATCHDOG
DETECTOR1
WATCHDOG
DETECTOR2
VDDA
AVIN
VIN1
GM ERROR
AMP
POFF
200kΩ
PWM
COMP
WATCHDOG
WSTAT
STATUS
MONITOR
SOFT START
I
LIMIT
DEBOUNCE
R1
PSM
COMP
R0
PWM/
PSM
CONTROL
BUCK1
LOW
CURRENT
VDDA
A
nRSTO
SW
B
C
Y
RESET
GENERATOR
D
OSCILLATOR
DRIVER
AND
ANTISHOOT
THROUGH
V
REF
SYSTEM
UNDERVOLTAGE
LOCK OUT
500Ω
PGND
ENLDO2
THERMAL
SHUTDOWN
POFF
MODE
MODE
EN1
ENABLE
AND MODE
CONTROL
ENBK
ENLDO1
ENLDO2
EN2
R1
R2
R3
R4
EN3
SEL
LDO1
CONTROL
LDO2
CONTROL
VDDA
VDDA
OPMODE_FUSES
ADP5042
500Ω
ENLDO1
VIN2
AGND VOUT2 VIN3
VOUT3
Figure 56. Functional Block Diagram
The buck regulator can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
switching frequency of the buck is always constant and does not
change with the load current. If the MODE pin is at logic low
level, the switching regulator operates in auto PWM/PSM mode.
In this mode, the regulator operates at fixed PWM frequency
when the load current is above the power saving current threshold.
When the load current falls below the power saving current
threshold, the regulator enters power saving mode, where the
switching occurs in bursts. The burst repetition is a function of
the current load and the output capacitor value. This operating
mode reduces the switching and quiescent current losses.
POWER MANAGEMENT UNIT
The ADP5042 is a micro power management unit (micro PMU)
combing one step-down (buck) dc-to-dc convertor, two low
dropout linear regulators (LDOs), and a supervisory circuit, with
dual watchdog, for processor control. The regulators are activated
by a logic level high applied to the respective EN pin. The EN1
controls the buck regulator, the EN2 controls LDO1, and the
EN3 controls LDO2. The ADP5042 has factory programmed
output voltages and reset voltage threshold. Other features
available in this device are the mode pin to control the buck
switching operation, a status pin informing the external processor
which watchdog caused a reset and push-button reset input.
When a regulator is turned on, the output voltage is controlled
through a soft start circuit to avoid a large inrush current due to
the discharged output capacitors.
Rev. A | Page 18 of 32
Data Sheet
ADP5042
Thermal Protection
PWM Mode
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off the buck and the LDOs.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included so that when thermal shutdown
occurs, the buck and LDOs do not return to operation until the
on-chip temperature drops below 130°C. When coming out of
thermal shutdown, soft start is initiated.
In PWM mode, the buck operates at a fixed frequency of 3 MHz,
set by an internal oscillator. At the start of each oscillator cycle,
the PFET switch is turned on, sending a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the PFET switch and turns on the NFET synchronous
rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulates the
output voltage by adjusting the peak inductor current threshold.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated in the system. If the input
voltage on AVIN drops below a typical 2.15 V UVLO threshold,
all channels shut down. In the buck channel, both the power
switch and the synchronous rectifier turn off. When the voltage
on AVIN rises above the UVLO threshold, the part is enabled
once more.
Power Save Mode (PSM)
The buck smoothly transitions to PSM operation when the load
current decreases below the PSM current threshold. When the
buck enters power save mode, an offset is induced in the PWM
regulation level, which makes the output voltage rise. When the
output voltage reaches a level that is approximately 1.5% above
the PWM regulation level, PWM operation is turned off. At this
point, both power switches are off, and the buck enters an idle
mode. The output capacitor discharges until the output voltage
falls to the PWM regulation voltage, at which point the device
drives the inductor to make the output voltage rise again to the
upper threshold. This process is repeated while the load current
is below the PSM current threshold.
Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for 5 V applications. For these
models, the device hits the turn-off threshold when the input
supply drops to 3.65 V typical.
Enable/Shutdown
The ADP5042 has individual control pins for each regulator. A
logic level high applied to the ENx pin activates a regulator, a
logic level low turns off a regulator.
PSM Current Threshold
The PSM current threshold is set to 100 mA. The buck employs
a scheme that enables this current to remain accurately con-
trolled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to and exit from the PSM.
The PSM current threshold is optimized for excellent efficiency
over all load currents.
When regulators are turned off after a Watchdog 2 event (see
the Watchdog 2 Input section), the reactivation of the regulator
occurs with a factory programmed order (see Table 9). The
delay between the regulator activation (tD1, tD2) is 2 ms.
Table 9. ADP5042 Regulators Sequencing
REGSEQ[1:0] Regulators Sequence (First to Last)
Short-Circuit Protection
0
0
1
1
0
1
0
1
LDO1 LDO2 Buck
Buck LDO1 LDO2
LDO1 Buck LDO2
No sequence, all regulators start at same time
The buck includes frequency foldback to prevent output current
runaway on a hard short. When the voltage at the feedback pin
falls below half the target output voltage, indicating the possi-
bility of a hard short at the output, the switching frequency is
reduced to half the internal oscillator frequency. The reduction
in the switching frequency allows more time for the inductor to
discharge, preventing a runaway of output current.
BUCK SECTION
The buck uses a fixed frequency and high speed current mode
architecture. The buck operates with an input voltage of 2.3 V
to 5.5 V.
Soft Start
Control Scheme
The buck has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the converter.
The buck operates with a fixed frequency, current mode PWM
control architecture at medium to high loads for high efficiency
but shift to a power save mode (PSM) control scheme at light
loads to lower the regulation power losses. When operating in
fixed frequency PWM mode, the duty cycle of the integrated
switches is adjusted and regulates the output voltage. When
operating in PSM at light loads, the output voltage is controlled
in a hysteretic manner, with higher output voltage ripple. During
part of this time, the converter is able to stop switching and
enters an idle mode, which improves conversion efficiency.
Current Limit
The buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
Rev. A | Page 19 of 32
ADP5042
Data Sheet
the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.
Reset Output
The ADP5042 has an active-low, open-drain reset output. This
output structure requires an external pull-up resistor to connect
the reset output to a voltage rail that is no higher than 6 V. The
resistor should comply with the logic low and logic high voltage
level requirements of the microprocessor while supplying input
current and leakage paths on the nRSTO pin. A 10 kΩ resistor is
adequate in most situations.
100% Duty Operation
With a dropping input voltage or with an increase in load
current, the buck may reach a limit where, even with the PFET
switch on 100% of the time, the output voltage drops below the
desired output voltage. At this limit, the buck transitions to a
mode where the PFET switch stays on 100% of the time. When
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.
The reset output is asserted when the monitored rail is below
the reset threshold (VTH), when WDI1 or WDI2 is not serviced
within the watchdog timeout period (tWD1 and tWD12). Reset remains
asserted for the duration of the reset active timeout period (tRP)
after VCC rises above the reset threshold or after the watchdog
timer times out. Figure 57 illustrates the behavior of the reset
output, nRSTO, and it assumes that VOUT2 is selected as the
rail to be monitored and supplies the external pull-up connected
to the nRSTO output.
LDO SECTION
The ADP5042 contains two LDOs with low quiescent current,
low dropout linear regulator, and provides up to 300 mA of
output current. Drawing a low 15 μA quiescent current (typical)
at no load makes the LDO ideal for battery-operated portable
equipment.
VOUT2
V
V
TH
TH
1V
0V
VOUT2
nRSTO
The LDO operates with an input voltage range of 1.7 V to 5.5 V.
The wide operating range makes these LDOs suitable for
cascading configurations where the LDO supply voltage is
provided from the buck regulator.
VOUT2
tRP1
tRD
0V
RSTO
tRP1
1V
0V
tRD
The LDOs also provide high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with just a small 1 µF ceramic input and output capacitor.
Figure 57. Reset Timing Diagram
The reset threshold voltage and the sensed rail (VOUT1,
LDO2 is optimized to supply analog circuits because it offers
better noise performance compared to LDO1. LDO1 should be
used in applications where noise performance is not critical.
VOUT2, VOUT3, or AVIN) are factory programmed. Refer to
Table 16 for a complete list of the reset thresholds available for
the ADP5042.
Internally, one LDO consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is con-
trolled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower
than the reference voltage, the gate of the PMOS device is
pulled lower, allowing more current to flow and increasing
the output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
reducing the current flowing to the output.
When monitoring the input supply voltage, AVIN, if the
selected reset threshold is below the UVLO level (factory
programmable to 2.25 V or 3.6 V) the reset output, nRSTO, is
asserted low as soon as the input voltage falls below the UVLO
threshold. Below the UVLO threshold, the reset output is
maintained low down to ~1 V VIN. This it to ensure that the reset
output is not released when there is sufficient voltage on the rail
supplying a processor to restart the processor operations.
Manual Reset Input
MR
The ADP5042 features a manual reset input ( ) which, when
MR
transitions from
SUPERVISORY SECTION
driven low, asserts the reset output. When
low to high, reset remains asserted for the duration of the reset
MR
The ADP5042 provides microprocessor supply voltage super-
vision by controlling the reset input of the microprocessor.
Code execution errors are avoided during power-up, power-
down, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold and by allowing
supply voltage stabilization with a fixed timeout reset pulse
after the supply voltage rises above the threshold. In addition,
problems with microprocessor code execution can be monitored
and corrected with a dual-watchdog timer.
active timeout period before deasserting. The
input has a
52 kΩ, internal pull-up, connected to AVIN, so that the input is
always high when unconnected. An external push-button
MR
switch can be connected between
user can generate a reset. Debounce circuitry for this purpose is
MR
and ground so that the
integrated on chip. Noise immunity is provided on the
input,
and fast, negative-going transients of up to 100 ns (typical) are
MR
ignored. A 0.1 µF capacitor between
additional noise immunity.
and ground provides
Rev. A | Page 20 of 32
Data Sheet
ADP5042
Watchdog 1 Input
V
V
SENSED
TH
1V
0V
The ADP5042 features a watchdog timer that monitors micro-
processor activity. A timer circuit is cleared with every low-to-
high or high-to-low logic transition on the watchdog input pin
(WDI1), which detects pulses as short as 80 ns. If the timer
counts through the preset watchdog timeout period (tWD1), reset
is asserted. The microprocessor is required to toggle the WDI1
pin to avoid being reset. Failure of the microprocessor to toggle
WDI1 within the timeout period, therefore, indicates a code
execution error, and the reset pulse generated restarts the
microprocessor in a known state.
nRSTO
tRP1
tWD1
tRP1
0V
0V
WDI1
Figure 58. Watchdog 1 Timing Diagram
Watchdog 2 Input
The ADP5042 features an additional watchdog timer that
monitors microprocessor activity in parallel to the first watchdog
with a much longer timeout. This provides additional security
and safety in case Watchdog 1 is incorrectly strobed. A timer
circuit is cleared with every low-to-high or high-to-low logic
transition on the watchdog input pin (WDI2), which detects pulses
as short as 8 µs. If the timer counts through the preset watchdog
timeout period (tWD2), reset is asserted, followed by a power
cycle of all regulators . The microprocessor is required to toggle
the WDI2 pin to avoid being reset and powered down. Failure
of the microprocessor to toggle WDI2 within the timeout period,
therefore, indicates a code execution error, and the reset output
nRSTO is forced low for tRP2. Then, all the regulators are turned
off for the tPOFF time. After the tPOFF period, the regulators are re-
activated according to a predefined sequence (see Table 9). Finally,
the reset line (nRSTO) is asserted for tRP1. This guarantees a
clean power-up of the system and proper reset.
As well as logic transitions on WDI1, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
the monitored rail. When reset is asserted, the watchdog timer
is cleared and does not begin counting again until reset deasserts.
Watchdog 1 timer can be disabled by leaving WDI1 floating or
by three-stating the WDI1 driver. The pin WMOD controls the
Watchdog 1 operating mode. If WMOD is set to logic level low,
Watchdog 1 is enabled as long as WDI1 is not in three-state. If
WMOD is set to logic level high, Watchdog 1 is always active
and cannot be disabled by a three-state condition. WMOD
input has an internal 200 kΩ pull-down resistor.
Watchdog 1 timeout is factory set to two possible values as
indicated in Table 18.
As well as logic transitions on WDI2, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
the VTH monitored rail which can be factory programmable
between VOUT1, VOUT2, VOUT3, and AVIN (see Table 21).
When reset is asserted, the watchdog timer is cleared and does
not begin counting again until reset deasserts.
Watchdog 2 timeout is factory set to seven possible values as
indicated in Table 19. One additional option allows Watchdog 2
to be factory disabled.
AVIN/VINx/ENx
tPOFF
VOUT1
VOUT3
VOUT2
0V
tD1
tD1
tD2
0V
0V
tD2
VTH
tRP1
tWD2
tRP2
tRP1
n
RSTO
0V
0V
WDI2
tWDCLEAR
WSTAT
Figure 59. Watchdog 2 Timing Diagram (Assuming That VOUT2 Is the Monitored Rail)
Rev. A | Page 21 of 32
ADP5042
Data Sheet
Watchdog Status Indicator
situation, WSTAT maintains the previous state (see state flow in
Figure 60).
In addition to the dual watchdog function, the ADP5042
features a watchdog status monitor available on the WSTAT pin.
This pin can be queried by the external processor to determine
the origin of a reset. WSTAT is an open-drain output.
The external processor can further distinguish a reset caused by
a Watchdog 1 timeout from a power failure, status monitor
WSTAT indicating a high level, by implementing a RAM check
or signature verification after reset. A RAM check or signature
failure indicates that a power failure has occurred, whereas a
RAM check or signature validation indicates that a Watchdog 1
timeout has occurred.
WSTAT outputs a logic level depending on the condition that
has generated a reset. WSTAT is forced low if the reset was
generated because of a Watchdog 2 timeout. WSTAT is pulled
high, through external pull-up, for any other reset cause (Watchdog
1 timeout, power failure or monitored voltage below threshold).
The status monitor is automatically cleared (set to logic level
high) 10 seconds after the nRSTO low to high transition (tWDCLEAR),
processor firmware must be designed being able to read the
WSTAT flag before tWDCLEAR expiration after a Watchdog 2 reset.
Table 10 shows the possible watchdog decoded statuses.
Table 10. Watchdog Status Decoding
WSTAT
High
High
Low
RAM CHECKSUM
RESET ORIGIN
Power failure
Watchdog 1
Watchdog 2
Failed
Ok
Don't care
The WSTAT flag is not updated in the event of a reset due to a
low voltage threshold detection or Watchdog 1 event occurring
within 10 seconds after nRSTO low to high transition. In this
NO POWER APPLIED TO AVIN.
ALL REGULATORS AND SUPERVISORY
TURNED OFF
NO POWER
AVIN > VUVLO
AVIN < VUVLO
AVIN < VUVLO
TRANSITION
STATE
POR
INTERNAL CIRCUIT BIASED
REGULATORS AND
SUPERVISORY NOT ACTIVATED
END OF POR
STANDBY
AVIN < VUVLO
ALL ENx = HIGH
ALL ENx = LOW
AVIN < VUVLO
TRANSITION
WSTAT
TIMEOUT
(t
WDOG2
STATE
TIMEOUT
TRANSITION
STATE
WSTAT = HIGH
WSTAT = 1
)
(t
)
WSTAT = 0
WDCLEAR
WD2
WSTAT = LOW
ALL REGULATORS AND
SUPERVISOR ACTIVATED
ACTIVE
RESET SHORT
END OF RESET
WDOG1 TIMEOUT
(t ) AND
WD1
WSTAT TIMEOUT
PULSE (t
)
RP2
WDOG1 TIMEOUT
(t
END OF RESET
PULSE (t
)
)
RP1
WD1
TRANSITION
STATE
WSTAT = HIGH
POWER OFF
VMON < VTH
WSTAT = 1
END OF (t
POFF
)
PULSE
RESET
NORMAL
Figure 60. ADP5042 State Flow
Rev. A | Page 22 of 32
Data Sheet
ADP5042
APPLICATIONS INFORMATION
BUCK EXTERNAL COMPONENT SELECTION
Output Capacitor
Trade-offs between performance parameters such as efficiency
and transient response can be made by varying the choice of
external components in the applications circuit, as shown in
Figure 66.
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.
Inductor
Ceramic capacitors are manufactured with a variety of dielec-
trics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R
dielectrics with a voltage rating of 6.3 V or 10 V are recom-
mended for best performance. Y5V and Z5U dielectrics are
not recommended for use with any dc-to-dc converter because
of their poor temperature and dc bias characteristics.
The high switching frequency of the ADP5042 buck allows for
the selection of small chip inductors. For best performance, use
inductor values between 0.7 μH and 3 μH. Suggested inductors
are shown in Table 11.
The peak-to-peak inductor current ripple is calculated using
the following equation:
VOUT ×(VIN −VOUT
)
IRIPPLE
=
V
IN × fSW ×L
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calcu-
lated using the following equation:
where:
SW is the switching frequency.
L is the inductor value.
f
C
EFF = COUT × (1 − TEMPCO) × (1 − TOL)
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
where:
C
EFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
IRIPPLE
2
IPEAK = ILOAD(MAX)
+
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the buck is high switching frequency dc-to-dc converters,
shielded ferrite core material is recommended for its low core
losses and low EMI.
C
OUT is 9.2481 μF at 1.8 V, as shown in Figure 61.
Substituting these values in the equation yields
EFF = 9.2481 μF × (1 − 0.15) × (1 − 0.1) = 7.0747 μF
C
To guarantee the performance of the buck, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
12
Table 11. Suggested 1.0 μH Inductors
Dimensions
(mm)
ISAT
(mA)
DCR
(mΩ)
Vendor
Murata
Murata
Model
10
8
LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9
LQM18FN1R0M00B 1.6 × 0.8 × 0.8
1.6 × 0.8 × 0.8
2.0 × 2.0 × 1.4
GLFR1608T1R0M-LR 1.6 × 0.8 × 0.8
1400
150
290
900
230
85
26
90
59
80
81
85
Taiyo Yuden CBMF1608T1R0M
Coilcraft
TDK
Coilcraft
Toko
EPL2014-102ML
6
0603LS-102
MDT2520-CN
1.8 × 1.69 × 1.1 400
2.5 × 2.0 × 1.2
4
1350
2
0
0
1
2
3
4
5
6
DC BIAS VOLTAGE (V)
Figure 61. Typical Capacitor Performance
Rev. A | Page 23 of 32
ADP5042
Data Sheet
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
VIN
×2×L×COUT
IRIPPLE
8× fSW ×COUT
VRIPPLE
=
=
(
2π × fSW
)
VOUT (VIN −VOUT
)
ICIN ≥ ILOAD(MAX)
Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
VIN
To minimize supply noise, place the input capacitor as close
to the VIN pin of the buck as possible. As with the output
capacitor, a low ESR capacitor is recommended.
VRIPPLE
IRIPPLE
ESRCOUT
≤
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 µF and a
maximum of 10 µF. A list of suggested capacitors is shown in
Table 13.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 µF and a
maximum of 40 µF.
Table 13. Suggested 4.7 μF Capacitors
Table 12. Suggested 10 μF Capacitors
Voltage
Case Rating
Size (V)
GRM188R60J475ME19D 0603 6.3
Case
Size
Voltage
Rating (V)
Vendor
Murata
Taiyo Yuden
TDK
Type
X5R
X5R
X5R
X5R
Model
Vendor
Type Model
X5R
GRM188R60J106
JMK107BJ475
C1608JB0J106K
ECJ1VB0J106M
0603
0603
0603
0603
6.3
6.3
6.3
6.3
Murata
Taiyo Yuden X5R
Panasonic X5R
JMK107BJ475
0603 6.3
0402 6.3
ECJ-0EB0J475M
Panasonic
LDO CAPACITOR SELECTION
Output Capacitor
The buck regulator requires 10 µF output capacitors to guaran-
tee stability and response to rapid load variations and to transition
in and out the PWM/PSM modes. In certain applications, where
the buck regulator powers a processor, the operating state is
known because it is controlled by software. In this condition,
the processor can drive the MODE pin according to the operating
state; consequently, it is possible to reduce the output capacitor
from 10 µF to 4.7 µF because the regulator does not expect a
large load variation when working in PSM mode (see Figure 62).
The ADP5042 LDOs are designed for operation with small,
space-saving ceramic capacitors, but they function with most
commonly used capacitors as long as care is taken with the ESR
value. The ESR of the output capacitor affects stability of the
LDO control loop. A minimum of 0.70 µF capacitance with an
ESR of 1 Ω or less is recommended to ensure stability of the
ADP5042. Transient response to changes in load current is also
affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP5042 to
large changes in load current.
ADP5042
R
FLT
30Ω
MICRO PMU
L1
1µH
AVIN
PROCESSOR
VCORE
SW
Input Bypass Capacitor
VOUT1
PGND
C6
4.7µF
VIN1
Connecting a 1 µF capacitor from VIN2 and VIN3 to GND
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source
impedance is encountered. If greater than 1 µF of output
capacitance is required, increase the input capacitor to match it.
V
IN
2.3V TO 5.5V
C2
4.7µF
VOUT2
VDDIO
RESET
VIN2
C4
R1
100kΩ
1µF
C1
1µF
nRSTO
VIN3
WDI
GPIO1
C3
1µF
Table 14. Suggested 1.0 μF Capacitors
MODE
ENx
GPIO2
3
Voltage
Case Rating
GPIO[x:y]
Vendor
Murata
TDK
Panasonic
Taiyo Yuden X5R
Type Model
Size
(V)
VOUT3
VANA
0402 10.0
0402 6.3
0402 6.3
0402 10.0
X5R
X5R
X5R
GRM155R61A105ME15
C1005JB0J105KT
ECJ0EB0J105K
C5
1µF
ANALOG
SUB-SYSTEM
Figure 62. Processor System Power Management with PSM/PWM Control
LMK105BJ105MV-F
Rev. A | Page 24 of 32
Data Sheet
ADP5042
Input and Output Capacitor Properties
To guarantee the performance of the ADP5042, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Use any good quality ceramic capacitors with the ADP5042 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary tempe-
rature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or 10 V are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any LDO because of their poor temperature and dc
bias characteristics.
SUPERVISORY SECTION
Watchdog 1 Input Current
To minimize watchdog input current (and minimize overall
power consumption), leave WDI1 low for the majority of the
watchdog timeout period. When driven high, WDI1 can draw
as much as 25 µA. Pulsing WDI1 low-to-high-to-low at a low
duty cycle reduces the effect of the large input current. When
WDI1 is unconnected and WMOD is set to logic level low, a
window comparator disconnects the watchdog timer from the
reset output circuitry so that reset is not asserted when the
watchdog timer times out.
Figure 63 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about 15% over the −40°C to +85°C tempera-
ture range and is not a function of package or voltage rating.
1.2
Negative-Going VCC Transients
To avoid unnecessary resets caused by fast power supply transients,
the ADP5042 is equipped with glitch rejection circuitry. The typical
performance characteristic in Figure 64 plots the monitored rail
voltage, VTH , transient duration vs. the transient magnitude.
The curve shows combinations of transient magnitude and
duration for which a reset is not generated for a 2.93 V reset
threshold part. For example, with the 2.93 V threshold, a
transient that goes 100 mV below the threshold and lasts 8 µs
typically does not cause a reset, but if the transient is any larger
in magnitude or duration, a reset is generated.
1.0
0.8
0.6
1000
0.4
0.2
0
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
DC BIAS VOLTAGE (V)
Figure 63. Capacitance vs. Voltage Characteristic
Use the following equation to determine the worst-case capa-
citance accounting for capacitor variation over temperature,
component tolerance, and voltage.
C
EFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
0.1
1
10
100
COMPARATOR OVERDRIVE (% OF V
)
TH
where:
Figure 64. Maximum VTH Transient Duration vs. Reset
Threshold Overdrive
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
Watchdog Software Considerations
In implementing the watchdog strobe code of the micro-
processor, quickly switching WDI1 low to high and then high
to low (minimizing WDI1 high time) is desirable for current
consumption reasons. However, a more effective way of using
the watchdog function can be considered.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and CBIAS is 0.94 μF at 1.8 V as shown in Figure 63.
Substituting these values into the following equation yields:
A low-to-high-to-low WDI1 pulse within a given subroutine
prevents the watchdog from timing out. However, if the sub-
routine becomes stuck in an infinite loop, the watchdog cannot
detect this because the subroutine continues to toggle WDI1. A
more effective coding scheme for detecting this error involves
C
EFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
Rev. A | Page 25 of 32
ADP5042
Data Sheet
V
CC
using a slightly longer watchdog timeout. In the program that
calls the subroutine, WDI1 is set high. The subroutine sets
WDI1 low when it is called. If the program executes without error,
WDI1 is toggled high and low with every loop of the program.
If the subroutine enters an infinite loop, WDI1 is kept low, the
watchdog times out, and the microprocessor is reset (see
Figure 65).
VIN1
VOUT1
VCORE
VDDIO
VOUT2
nRSTO
WDI1
RESET
I/O
WDI2
I/O
MICROPROCESSOR
ADP5042
START
Figure 66. Typical Applications Circuit
SET WDI
HIGH
RESET
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5042 performance, causing electro-
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:
PROGRAM
CODE
INFINITE LOOP:
WATCHDOG
TIMES OUT
SUBROUTINE
SET WDI
LOW
•
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
Maximize the size of ground metal on the component side
to help with thermal dissipation.
RETURN
•
•
•
Figure 65. Watchdog Flow Diagram
The second watchdog, refreshed through the WDI2 pin, is
useful in applications where safety is a very critical factor and
the system must recover from unwanted operations, for example, a
processor stuck in a continuous loop where Watchdog 1 is kept
refreshed or environmental conditions that may unset or damage
the processor port controlling the WDI1 pin. In the event of a
Watchdog 2 timeout, the ADP5042 power cycles all the supplied
rails to guarantee a clean processor start.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
Rev. A | Page 26 of 32
Data Sheet
ADP5042
EVALUATION BOARD SCHEMATICS AND ARTWORK
R
FILT
30Ω
AVIN
AVIN
L1
1µH
TP4
TP1
SW
VOUT1 AT
800mA
VOUT1
PGND
C6
10µF
TP5
BUCK
EN_BK
VIN1 = 2.3V
TO 5.5V
VIN1
C5
4.7µF
TP12
MODE
EN1
TP2
VOUT2
TP6
VOUT2 AT
300mA
LDO1
VIN2
VIN2 = 1.7V
C2
1µF
TO 5.5V
EN_LDO1
TP11
C1
1µF
WSTAT
nRSTO
WDI1
TP9
EN2
AVIN
TP10
TP7
WDI2
EN3
TP8
EN_LDO2
LDO2
TP3
VOUT3
VIN3
VOUT3 AT
300mA
VIN3 = 1.7V
TO 5.5V
C3
1µF
C4
1µF
AGND
Figure 67. Evaluation Board Schematic
SUGGESTED LAYOUT
5.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
PPL
6.0
6.5
7.0
mm
3.3V
GPL
C3 – 1µF
6.3V/XR5
0402
C4 – 1µF
6.3V/XR5
0402
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
GPL
PIN 1
PPL PPL PPL
MODE
MR
VIN1
SW
WDI1
GPL
GPL
GPL
AGND
WMOD
GPL
PGND
EN1
NC
ADP5042
EN2
GPL GPL
GPL
GPL
VIAs LEGEND
PPL = POWER PLANE (+4V)
GPL = GROUND PLANE
C6 - 10µF
6.3V/XR5 0603
C1 – 1µF
10V/XR5
0402
C2 – 1µF
10V/XR5
0402
TOP LAYER
SECOND LAYER
1.8V
6.0
mm
1.5V
Figure 68. Layout
Rev. A | Page 27 of 32
ADP5042
Data Sheet
BILL OF MATERIALS
Table 15.
Reference
Value
Part Number
Vendor
Package
C1, C2, C3, C4
1 µF, X5R, 6.3 V
LMK105BJ105MV-F
LMK107BJ475MA-T
JMK107BJ106MA-T
Taiyo Yuden
Taiyo Yuden
Taiyo Yuden
0402
0603
0603
0201/0402
0603
C5
C6
RFILT
L1
4.7 µF, X5R, 10 V
10 µF, X5R, 6.3 V
30 Ω
1 µH, 0.09 Ω, 290 mA
1 µH, 0.08 Ω, 230 mA
3-regulator micro PMU
BRC1608T1R0M
GLFR1608T1R0M-LR
ADP5042
Taiyo Yuden
TDK
Analog Devices
0603
20-Lead LFCSP
IC1
APPLICATION DIAGRAM
AVIN
L1
1µH
R
30Ω
FILT
AVIN
VIN1
SW
VOUT1 AT
6
7
8
800mA
VOUT1
PGND
C6
10µF
11
9
BUCK
EN_BK
V
IN1 = 2.3V
TO 5.5V
C5
4.7µF
FPWM
MODE
ON
17
14
PWM/PSM
EN1
10
13
OFF
VOUT2
VOUT2 AT
300mA
LDO1
VIN2
VIN2 = 1.7V
TO 5.5V
(DIGITAL)
C2
1µF
C1
1µF
EN_LDO1
V
DD
ON
AVIN
EN2
MR
SUPERVISOR
16
20
OFF
R1 R2
WSTAT
15
5
nRSTO
RESET
POFF
PUSH-BUTTON
RESET
WDI2
WDI1
12
19
WDOG2
WDOG1
V
DD
ON
EN3
ON
WMOD
4
3
OFF
17
OFF
EN2
NC
16
1
EN_LDO2
VIN3
VOUT3
VOUT3 AT
300mA
VIN3 = 1.7V
TO 5.5V
LDO2
(ANALOG)
2
C3
1µF
C4
1µF
AGND
Figure 69. Application Diagram
Rev. A | Page 28 of 32
Data Sheet
ADP5042
FACTORY PROGRAMMABLE OPTIONS
Table 16. Reset Voltage Threshold Options1
TA = +25°C
Typ
TA = −40°C to +85°C
Selection
Min
Max
Min
Max
Unit
V
V
V
V
V
V
V
V
111 (For VIN = 5 V − 6%)
110 (For VOUT = 3.3 V)
101 (For VOUT = 3.3 V)
100 (For VOUT = 2.8 V)
011 (For VOUT = 2.8 V)
010 (For VOUT = 2.5 V − 6%)
001 (For VOUT = 2.2 V − 6%)
000 (For VOUT = 1.8 V − 6%)
4.630
3.080
2.930
2.630
2.500
2.350
2.068
1.692
4.700
3.157
3.000
2.696
2.563
2.385
2.099
1.717
3.034
2.886
2.591
2.463
3.126
2.974
2.669
2.538
3.003
2.857
2.564
2.438
Table 17. Reset Timeout Options
Selection
Min
Typ
Max
Unit
0
1
24
160
30
200
36
240
ms
ms
Table 18. Watchdog 1 Timer Options
Selection
Min
81.6
1.12
Typ
102
1.6
Max
122.4
1.92
Unit
ms
sec
0
1
Table 19. Watchdog 2 Timer Options
Selection
Min
Typ
Max
Unit
000
6
7.5
9
sec
001
Watchdog 2 disabled
010
011
100
101
110
111
3.2
6.4
12.8
25.6
51.2
102.4
4
8
16
32
64
128
4.8
9.6
19.2
38.4
76.8
153.6
min
min
min
min
min
min
Table 20. Power-Off Timing Options
Selection
Min
140
280
Typ
200
400
Max
280
560
Unit
ms
ms
0
1
Table 21. Reset Sensing Options
Selection
Monitored Rail
VOUT1 pin
VOUT2 pin
VOUT3 pin
AVIN1 pin
00
01
10
11
1 When monitoring AVIN, the reset threshold selected, by fuse option or by the external resistor divided, must be higher than the UVLO threshold (2.25 V or 3.6 V).
Rev. A | Page 29 of 32
ADP5042
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.65
2.50 SQ
2.35
5
11
6
10
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 70. 20-Lead, Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-10)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model1, 2
Regulator Settings
Supervisory Settings Temperature Range
Package Description
ADP5042ACPZ-1-R7
VOUT1 = 1.8 V
WD1 tOUT = 1.6 sec
TJ = −40°C to +125°C
20-Lead, Lead Frame
Scale Package
CP-20-10
[LFCSP_WQ]
VOUT2 = 1.5 V
VOUT3 = 3.3 V
UVLO = 2.2 V
WD2 tOUT = 128 min
Reset tOUT = 200 ms
POFF = 200 ms
Sequencing: LDO1,
LDO2, buck
VTH Sensing =
VOUT3, 2.93 V
ADP5042ACPZ-2-R7
VOUT1 = 1.5 V
WD1 tOUT = 1.6 sec
TJ = −40°C to +125°C
20-Lead, Lead Frame
Scale Package
CP-20-10
[LFCSP_WQ]
VOUT2 = 1.8 V
VOUT3 = 3.3 V
UVLO = 2.2 V
WD2 tOUT = 128 min
Reset tOUT = 200 ms
POFF = 200 ms
Sequencing: LDO1,
LDO2, buck
VTH Sensing =
VOUT3, 2.93 V
ADP5042CP-1-EVALZ
ADP5042CP-2-EVALZ
Evaluation Board
Evaluation Board
1 Z = RoHS Compliant Part.
2 Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits.
Rev. A | Page 30 of 32
Data Sheet
NOTES
ADP5042
Rev. A | Page 31 of 32
ADP5042
NOTES
Data Sheet
©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08811-0-11/11(A)
Rev. A | Page 32 of 32
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