ADP5043 [ADI]
Micro PMU with 800 mA Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset;
| 型号： | ADP5043 |
| 厂家： | 
ADI |
| 描述： | Micro PMU with 800 mA Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset |
| 文件： | 总30页 (文件大小：1816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Micro PMU with 800 mA Buck, 300 mA LDO,
Supervisory, Watchdog, and Manual Reset
Data Sheet
ADP5043
FEATURES
GENERAL DESCRIPTION
Input voltage range: 2.3 V to 5.5 V
One 800 mA buck regulator
One 300 mA LDO
The ADP5043 combines one high performance buck regulator
and one low dropout (LDO) regulator in a small 20-lead LFCSP
to meet demanding performance and board space requirements.
20-lead, 4 mm × 4 mm LFCSP package
Initial regulator accuracy: 1ꢀ
Overcurrent and thermal protection
Soft start
The high switching frequency of the buck regulator enables use of
tiny multilayer external components and minimizes board space.
The MODE pin selects the buck’s mode of operation. When set
to logic high, the buck regulator operates in forced PWM mode.
When the MODE pin is set to logic low, the buck regulator
operates in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold,
the regulator operates in power save mode (PSM) improving the
light-load efficiency.
Undervoltage lockout
Open-drain processor reset with threshold monitoring
1.5ꢀ threshold accuracy over the full temperate range
Guaranteed reset output valid to VCC = 1 V
Dual watchdog for secure systems
Watchdog 1 controls reset
Watchdog 2 controls reset and regulators power cycle
Buck regulator key specifications
Current-mode topology for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PFM/PSM modes
100ꢀ duty cycle low dropout mode
LDO key specifications
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5043 LDO extend the battery life of
portable devices. The LDO maintains a power supply rejection
of greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage.
Each regulator is activated by a high level on the respective
enable pin. The ADP5043 is available with factory programmable
default output voltages and can be set to a wide range of options.
Low VIN from 1.7 V to 5.5 V
The ADP5043 contains supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. The ADP5043 also provides
power-on reset signals. An on-chip dual watchdog timer can
reset the microprocessor or power cycle the system (Watchdog 2)
if it fails to strobe within a preset timeout period.
Stable with1 μF ceramic output capacitors
High PSRR, 60 dB up to 1 kHz/10 kHz
Low output noise
Low dropout voltage: 150 mV at 300 mA load
−40°C to +125°C junction temperature range
HIGH LEVEL BLOCK DIAGRAM
ADP5043
AVIN
L1
1µH
R
FILT
30Ω
AVIN
VIN1
SW
V
@
OUT1
800mA
VOUT1
PGND
VIN1 = 2.3V
TO 5.5V
C6
10µF
BUCK
EN_BK
C5
4.7µF
ON
ON
FPWM
MODE
EN1
OFF
PSM/PWM
VOUT2
V
@
OUT2
300mA
VIN2
VIN2 = 1.7V
TO 5.5V
LDO
C2
1µF
C1
1µF
EN_LDO
EN2
OFF
AVIN
WSTAT
nRSTO
MR
NC
WDI1
WDI2
NC
VIN
WMOD
WD1 MODE
SELECTION
GND
AGND
GND
Figure 1.
Rev. C
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ADP5043
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power Management Unit........................................................... 16
Buck Section................................................................................ 17
LDO Section ............................................................................... 18
Supervisory Section ................................................................... 18
Applications Information.............................................................. 21
Buck External Component Selection....................................... 21
LDO Capacitor Selection .......................................................... 22
Supervisory Section ................................................................... 23
PCB Layout Guidelines.............................................................. 24
Power Dissipation/Thermal Considerations ............................. 25
Evaluation Board Schematics and Artwork............................ 27
Suggested Layout........................................................................ 27
Bill of Materials........................................................................... 28
Application Diagram ................................................................. 28
Factory Programmable Options................................................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
General Description......................................................................... 1
High Level Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
General Specifications ................................................................. 3
Supervisory Specifications .......................................................... 3
Buck Specifications....................................................................... 5
LDO Specifications ...................................................................... 5
Input and Output Capacitor, Recommended Specifications.. 6
Absolute Maximum Ratings............................................................ 7
Thermal Data................................................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 16
REVISION HISTORY
9/2019—Rev. B to Rev. C
10/2011—Rev. 0 to Rev. A
Changes to Output Capacitor Section ......................................... 22
Updated Outline Dimensions....................................................... 30
Updated Outline Dimensions....................................................... 30
Changes to Ordering Guide.......................................................... 30
5/2018—Rev. A to Rev. B
4/2011—Revision 0: Initial Version
Updated Outline Dimensions....................................................... 30
Changes to Ordering Guide .......................................................... 30
Rev. C | Page 2 of 30
Data Sheet
ADP5043
SPECIFICATIONS
GENERAL SPECIFICATIONS
AVIN, VIN1 = (VOUT1 + 0.5 V) or 2.3 V, whichever is greater, AVIN, VIN1 ≥ VIN2, TA = 25°C, unless otherwise noted. Regulators
are enabled.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min Typ Max Unit
AVIN UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Option A
UVLOAVIN
UVLOAVINRISE
TJ = −40°C to +125°C
2.25
3.9
V
V
Option B
Input Voltage Falling
Option A
Option B
UVLOAVINFALL
1.95
3.1
V
V
SHUTDOWN CURRENT
IGND-SD
ENx = GND
ENx = GND, TJ = −40°C to +125°C
TJ rising
0.1
μA
μA
°C
°C
2
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSSD
TSSD-HYS
150
20
ENx, WDIx, MODE, WMOD, MR INPUTS
Input Logic High
Input Logic Low
VIH
VIL
2.5 V ≤ AVIN ≤ 5.5 V
2.5 V ≤ AVIN ≤ 5.5 V
1.2
V
V
0.4
Input Leakage Current (WMOD Excluded) VI-LEAKAGE
ENx = AVIN or GND
ENx = AVIN or GND, TJ = −40°C to +125°C
VWMOD = 3.6 V, TJ = −40°C to +125°C
0.05
30
μA
μA
μA
1
50
WMOD Input Leakage Current
OPEN-DRAIN OUTPUTS
VI-LKG-WMOD
VOL
nRSTO, WSTAT Output Voltage
Open-Drain Reset Output Leakage Current
AVIN = 2.3 V to 5.5 V, InRSTO/WSTAT = 3 mA
mV
μA
1
SUPERVISORY SPECIFICATIONS
AVIN, VIN1 = full operating range, TJ = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ Max
Unit Test Conditions/Comments
SUPPLY
Supply Current (Supervisory Circuit Only)
45
43
55
52
μA
μA
V
AVIN = 5.5 V, EN1 = EN2 = VIN1
AVIN = 3.6 V, EN1 = EN2 = VIN1
TA = 25°C, sensed on VOUTx
RESET THRESHOLD ACCURACY
VTH − 0.8%
VTH − 1.5%
50
VTH
VTH
VTH + 0.8%
VTH + 1.5%
V
TJ = −40°C to +125°C, sensed on VOUTx
TH = VOUT − 50 mV
RESET THRESHOLD TO OUTPUT DELAY
125 400
μs
V
GLITCH IMMUNITY (tUOD
)
RESET TIMEOUT PERIOD WATCHDOG1 (tRP1
Option A
Option B
)
)
24
160
3.5
30
36
ms
ms
ms
μs
200 240
RESET TIMEOUT PERIOD WATCHDOG2 (tRP2
5
7
VCC TO RESET DELAY (tRD
)
150
2
VIN1 falling at 1 mV/μs
REGULATORS SEQUENCING DELAY (tD1, tD2
)
ms
WATCHDOG INPUTS
Watchdog 1 Timeout Period (tWD1
)
Option A
Option B
81.6
1.28
102 122.4
1.6 1.92
ms
sec
Rev. C | Page 3 of 30
ADP5043
Data Sheet
Parameter
Watchdog 2 Timeout Period (tWD2
Option A
Min
Typ Max
Unit Test Conditions/Comments
)
6
7.5
9
sec
Option B
Watchdog 2 disabled
Option C
Option D
Option E
Option F
Option G
Option H
3.2
6.4
11.2
25.6
51.2
102.4
4
8
16
32
64
4.8
9.6
19.2
38.4
76.8
min
min
min
min
min
min
128 153.8
Watchdog 2 Power Off Period (tPOFF
Option A
Option B
WDI1 Pulse Width
WDI2 Pulse Width
)
210
400
ms
ms
ns
80
8
VIL = 0.4 V, VIH = 1.2 V
VIL = 0.4 V, VIH = 1.2 V
μs
Watchdog Status Timeout Period (tWDCLEAR
WDI1 Input Current (Source)
WDI1 Input Current (Sink)
WDI2 Internal Pull-Down
MANUAL RESET INPUT
)
11.2
15
−25 −14
45
sec
μA
μA
kΩ
8
−30
20
VWDI1 = VCC, time average
VWDI1 = 0, time average
MR Input Pulse Width
1
μs
ns
kΩ
ns
MR Glitch Rejection
220
MR Pull-Up Resistance
25
52
80
MR to Reset Delay
280
VCC = 5 V
Rev. C | Page 4 of 30
Data Sheet
ADP5043
BUCK SPECIFICATIONS
AVIN, VIN1 = 3.6 V, VOUT1 = 1.8 V, TJ = −40°C to +125°C for minimum/maximum specifications, L = 1 μH, COUT = 10 μF, and TA = 25°C
for typical specifications, unless otherwise noted.1
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Voltage Range (VIN1)
OUTPUT CHARACTERISTICS
Output Voltage Accuracy
2.3
5.5
V
PWM mode, ILOAD = 100 mA
PSM mode
VIN1 = 2.3 V to 5.5 V, PWM mode,
−1
−2
−3
+1
+2
+3
%
%
%
I
LOAD = 1 mA to 800 mA
PWM TO POWER SAVE MODE CURRENT THRESHOLD
INPUT CURRENT CHARACTERISTICS
DC Operating Current
100
mA
ILOAD = 0 mA, device not switching
ENx = 0 V, TA = TJ = −40°C to +125°C
21
0.2
35
1.0
μA
μA
Shutdown Current
SW CHARACTERISTICS
SW On Resistance
PFET
180
140
170
150
1360
75
240
190
235
210
1600
mΩ
mΩ
mΩ
mΩ
mA
Ω
PFET, AVIN = VIN1 = 5 V
NFET
NFET, AVIN = VIN1 = 5 V
PFET switch peak current limit
EN1 = 0 V
Current Limit
1100
2.5
ACTIVE PULL-DOWN
OSCILLATOR FREQUENCY
START-UP TIME
3.0
3.5
MHz
μs
250
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
LDO SPECIFICATIONS
AVIN = 3.6 V, VIN2 = (VOUT2 + 0.2 V) or 2.3 V, whichever is greater; AVIN, VIN1 ≥ VIN2; IOUT = 10 mA; CIN = COUT = 1 μF;
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Symbol
VIN2
Test Conditions/Comments
TJ = −40°C to +125°C
Min
Typ
Max
Unit
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT (per LDO)
1.7
5.5
V
IGND
IOUT = 0 ꢀA, VOUT = 3.3 V
15
ꢀA
ꢀA
IOUT = 0 ꢀA, VOUT = 3.3 V,
50
TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 200 mA
IOUT = 200 mA, TJ = −40°C to +125°C
IOUT = 10 mA
100 ꢀA < IOUT < 300 mA
VIN2 = (VOUT2 + 0.5 V) to 5.5 V
100 ꢀA < IOUT < 300 mA
VIN2 = (VOUT2 + 0.5 V) to 5.5 V
TJ = −40°C to +125°C
67
ꢀA
ꢀA
ꢀA
ꢀA
%
105
100
245
+1
+2
FIXED OUTPUT VOLTAGE ACCURACY
VOUT2
−1
−2
%
−3
+3
%
Rev. C | Page 5 of 30
ADP5043
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
REGULATION
Line Regulation
∆VOUT2/∆VIN2
VIN2= (VOUT2 + 0.5 V) to 5.5 V
IOUT2 = 1 mA
−0.03
+0.03
%/V
TJ = −40°C to +125°C
IOUT2 = 1 mA to 200 mA
IOUT2 = 1 mA to 200 mA
TJ = −40°C to +125°C
VOUT2 = 3.3 V
Load Regulation1
∆VOUT2/∆IOUT2
0.002
%/mA
%/mA
0.0075
DROPOUT VOLTAGE2
VDROPOUT
IOUT2 = 10 mA
IOUT2 = 10 mA, TJ = −40°C to +125°C
IOUT2 = 200 mA
IOUT2 = 200 mA, TJ = −40°C to +125°C
EN2 = 0 V
4
mV
mV
mV
mV
Ω
5
60
100
ACTIVE PULL-DOWN
START-UP TIME
CURRENT-LIMIT THRESHOLD3
RPDLDO
600
85
TSTART-UP
ILIMIT
VOUT2 = 3.3 V
μs
TJ = −40°C to +125°C
335
470
123
mA
μV rms
OUTPUT NOISE
OUTLDONOISE
10 Hz to 100 kHz, VIN2 = 5 V,
VOUT2 = 3.3 V
10 Hz to 100 kHz, VIN2 = 5 V,
VOUT2 = 2.8 V
10 Hz to 100 kHz, VIN2 = 5 V,
VOUT2 = 1.5 V
110
59
μV rms
μV rms
dB
POWER SUPPLY REJECTION RATIO
PSRR
1 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V,
66
I
OUT = 100 mA
100 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V,
OUT = 100 mA
1 MHz, VIN2 = 3.3 V, VOUT2 = 2.8 V,
OUT = 100 mA
57
dB
I
60
dB
I
1 Based on an end-point calculation using 1 mA and 100 mA loads.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
3 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 5.
Parameter
Symbol
CMIN1
Test Conditions/Comments Min
Typ
Max
Unit
μF
OUTPUT CAPACITANCE (BUCK)1
MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO)
CAPACITOR ESR
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TJ = −40°C to +125°C
7
40
CMIN2
0.70
0.001
μF
RESR
1
Ω
1 The minimum output capacitance should be greater than 4.7 μF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met.
2 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with LDOs or the buck.
Rev. C | Page 6 of 30
Data Sheet
ADP5043
ABSOLUTE MAXIMUM RATINGS
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The specified
value of θJA is based on a four-layer, 4 inch × 3 inch, 2.5 oz
copper board, as per JEDEC standard. For additional
Table 6.
Parameter
Rating
AVIN, VINx, VOUTx, ENx, MODE, MR, WDIx,
WMOD, WSTAT, nRSTO to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
−0.3 V to +6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
3000 V
ESD Human Body Model
ESD Charged Device Model
ESD Machine Model
1500 V
100 V
information, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale (LFCSP).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 7. Thermal Resistance
Package Type
θJA
θJC
Unit
THERMAL DATA
20-Lead, 0.5 mm pitch LFCSP
38
4.2
°C/W
Absolute maximum ratings apply individually only, not in
combination.
ESD CAUTION
The ADP5043 can be damaged when the junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temper-
ature may have to be derated. In applications with moderate
power dissipation and low PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits. The
junction temperature of the device is dependent on the ambient
temperature, the power dissipation of the device (PD), and the
junction-to-ambient thermal resistance of the package. Maxi-
mum junction temperature is calculated from the ambient
temperature and power dissipation using the formula
TJ = TA + (PD × θJA)
Rev. C | Page 7 of 30
ADP5043
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 WSTAT
14 NC
NC
VOUT2
VIN2
1
2
3
4
5
ADP5043
TOP VIEW
(Not to Scale)
13 GND
EN2
12 WDI2
11 VOUT1
nRSTO
NOTES
1. EXPOSED PAD SHOULD BE CONNECTED TO AGND.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
THE PIN SHOULD BE LEFT FLOATING.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 14
2
3
4
5
6
7
8
NC
No Connect. Do not connect to this pin. The pin should be left floating.
LDO Output Voltage and Sensing Input.
LDO Input Supply (1.7 V to 5.5 V).
Enable LDO. EN2 = high: turn on the LDO; EN2 = low: turn off the LDO.
Open-Drain Reset Output, Active Low.
Regulators Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V).
Buck Input Supply (2.3 V to 5.5 V).
VOUT2
VIN2
EN2
nRSTO
AVIN
VIN1
SW
Buck Switching Node.
9
PGND
EN1
VOUT1
WDI2
GND
WSTAT
Dedicated Power Ground for Buck Regulator.
Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck.
Buck Sensing Node.
Watchdog 2 (Long Timeout) Refresh Input from Processor. This pin can be disabled only by a factory option.
Connect to the ground plane.
10
11
12
13, 16
15
Open-Drain Watchdog Timeout Status. WSTAT = high: Watchdog 1 timeout or power-on reset; WSTAT = low:
Watchdog 2 timeout. Auto cleared after one second.
17
18
MODE
Buck Mode. MODE = high: buck regulator operates in fixed PWM mode; MODE = low: (auto mode) buck
regulator operates in power save mode (PSM) at light load and in constant PWM at higher load.
Watchdog Mode. WMOD = low: Watchdog 1 normal mode; WMOD = high: Watchdog 1 cannot be disabled by a
three-state condition applied on WDI1. WMOD has an internal 200 kΩ pull-down resistor connected to AGND.
WMOD
19
20
WDI1
MR
Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled.
Manual Reset Input, Active Low.
EPAD
Exposed Pad. The exposed pad should be connected to analog ground (AGND).
Rev. C | Page 8 of 30
Data Sheet
ADP5043
TYPICAL PERFORMANCE CHARACTERISTICS
VIN1 = VIN2 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted.
3.34
3.32
3.30
3.28
3.26
3.24
3.22
–40°C
+25°C
+85°C
VOUT1
1
VOUT2
2
B
CH1 2.0V/DIV 1MΩ
CH2 2.0V/DIV 1MΩ
20.0M
20.0M
A
CH1
1.76V
200µs/DIV
20.0ns/pt
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
W
W
B
OUTPUT CURRENT (A)
Figure 6. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode
Figure 3. 3-Channel Start-Up Waveforms
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.830
–40°C
+25°C
+85°C
1.825
1.820
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
1.775
V
V
= 1.5V,
= 3.3V
OUT1
OUT2
2.3
2.8
3.3
3.8
4.3
4.8
5.3
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Figure 7. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, Auto Mode
Figure 4. System Quiescent Current (Sum of All the Input Currents) vs. Input
Voltage, VOUT1 = 1.5 V, VOUT2 = 3.3 V
1.795
1.794
SW
4
+85°C
1.793
1.792
VOUT1
2
+25°C
1.791
1.790
1.789
1.788
1.787
1.786
EN
1
IIN
3
–40°C
1.785
1.784
B
CH1 2.0V/DIV
CH2 2.0V/DIV
CH3 100mA/DIV 1MΩ
1MΩ
1MΩ
20.0M
500M
20.0M
500M
A
CH1
2.92V
50µs/DIV
50.0MS/s
20.0ns/pt
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
W
W
B
OUTPUT CURRENT (A)
B
B
W
CH4 5.0V/DIV
1MΩ
W
Figure 8. Buck Load Regulation Across Temperature,
VOUT1 = 1.8 V, PWM Mode
Figure 5. Buck Startup, VOUT1 = 1.8 V, IOUT1 = 20 mA
Rev. C | Page 9 of 30
ADP5043
Data Sheet
1.797
1.796
1.795
1.794
1.793
1.792
1.791
100
90
80
70
60
50
40
30
20
10
0
V
V
= 5.5V
= 4.5V
IN
IN
V
= 3.6V
IN
2.4V
3.6V
4.5V
5.5V
1.790
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 12. Buck Efficiency vs. Load Current, Across Input Voltage,
OUT1 = 1.8 V, Auto Mode
Figure 9. Buck Load Regulation Across Input Voltage,
OUT1 = 1.8 V, PWM Mode
V
V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
2.4V
3.6V
4.5V
5.5V
3.6V
4.5V
5.5V
0.0001
0.001
0.01
0.1
1
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 13. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1= 1.8 V, PWM Mode
Figure 10. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, Auto Mode
100
100
–40°C
+25°C
3.6V
4.5V
5.5V
90
90
80
70
60
50
40
30
20
10
0
+85°C
80
70
60
50
40
30
20
10
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 14. Buck Efficiency vs. Load Current, Across Temperature,
VOUT1 = 1.8 V, PWM Mode
Figure 11. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, PWM Mode
Rev. C | Page 10 of 30
Data Sheet
ADP5043
100
3.10
3.05
3.00
2.95
2.90
2.85
–40°C
+25°C
90
+85°C
80
–40°C
+25°C
70
60
50
40
30
20
10
+85°C
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 15. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 3.3 V,
Auto Mode
Figure 18. Buck Switching Frequency vs. Output Current, Across
Temperature, VOUT1 = 1.8 V, PWM Mode
100
–40°C
VOUT
+25°C
+85°C
80
90
1
70
60
50
40
30
20
10
0
I
SW
2
SW
3
0.0001
0.001
0.01
0.1
1
B
B
B
CH1 20.0mV/DIV
20.0M
20.0M
20.0M
A
CH1 2.4mV 5.0µs/DIV
20.0MS/s
W
W
CH2 200mA/DIV 1MΩ
OUTPUT CURRENT (A)
50.0ns/pt
CH3 2.0V/DIV
1MΩ
W
Figure 16. Buck Efficiency vs. Load Current, Across Temperature,
VOUT1 = 1.8 V, Auto Mode
Figure 19. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
VOUTx
2
I
SW
3
SW
1
B
2.6
3.6
4.6
5.6
CH1 2.0V/DIV 1MΩ
CH2 50.0mV/DIV
CH3 500mA/DIV
20.0M
20.0M
20.0M
A
CH1 1.56mV 5.0µs/DIV
200MS/s
W
W
B
INPUT VOLTAGE (V)
5.0ns/pt
B
W
Figure 17. Buck DC Current Capability vs. Input Voltage, VOUT1 = 1.8 V
Figure 20. Typical Waveforms, VOUT1 = 1.8 V, IOUT1= 30 mA, Auto Mode
Rev. C | Page 11 of 30
ADP5043
Data Sheet
VOUTx
2
VN
SW
I
SW
VOUTx
3
2
SW
3
4
1
B
B
B
B
CH1 2.0V/DIV 1MΩ
CH2 50.0mV/DIV
CH3 500mA/DIV
20.0M
20.0M
20.0M
A
CH1 1.56mV 500ns/DIV
200MS/s
CH2 50mV/DIV
CH3 1V/DIV
CH4 2V/DIV
20.0M
20.0M
20.0M
A CH3 4.96mV 100µs/DIV
W
W
W
20MS/s
1MΩ
1MΩ
W
W
5.0ns/pt
100ns/pt
B
B
W
Figure 21. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode
Figure 24. Buck Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT1 = 1.8 V,
PWM Mode
VOUTx
1
1
I
SW
2
VOUTx
2
SW
3
3
B
B
B
CH1 20.0mV/DIV
CH2 200mA/DIV 1MΩ
CH3 2.0V/DIV
20.0M
20.0M
20.0M
A
CH1 2.4mV
200ns/DIV
500MS/s
2.0ns/pt
B
B
W
W
CH1 4V/DIV
CH2 50mV/DIV 1MΩ
CH3 50mA/DIV 1MΩ
20.0M
20.0M
20.0M
A
CH3 44mA 200µs/DIV
10MS/s
W
W
100ns/pt
1MΩ
B
W
W
Figure 22. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode
Figure 25. Buck Response to Load Transient, IOUT1 from 1 mA to 50 mA,
VOUT1 = 3.3 V, Auto Mode
SW
1
VINx
VOUTx
VOUTx
2
2
SW
1
3
LOAD
3
B
CH1 3V/DIV
CH2 50mV/DIV
CH3 900mV/DIV 1MΩ
20.0M
20.0M
20.0M
A
CH3 4.79V
100µs/DIV
10.0MS/s
100ns/pt
B
W
CH1 4V/DIV
CH2 50mV/DIV
CH3 50mA/DIV 1MΩ
20.0M
20.0M
20.0M
A
CH3 28mA 200µs/DIV
5MS/s
W
B
B
B
W
W
W
W
B
200ns/pt
Figure 23. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V,
VOUT1 = 3.3 V, PWM Mode
Figure 26. Buck Response to Load Transient, IOUT2 from 1 mA to 50 mA,
VOUT1 = 1.8 V, Auto Mode
Rev. C | Page 12 of 30
Data Sheet
ADP5043
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.6V
4.5V
5.0V
5.5V
SW
1
VOUTx
2
3
B
0.0001
0.001
0.01
0.1
CH1 4V/DIV
CH2 50mV/DIV
CH3 50mA/DIV 1MΩ
20.0M A CH3
20.0M
20.0M
86mA
200µs/DIV
10MS/s
100ns/pt
W
B
W
W
OUTPUT CURRENT (A)
B
Figure 27. Buck Response to Load Transient, IOUT1 from 20 mA to 140 mA,
VOUT1 = 3.3 V, Auto Mode
Figure 30. LDO Load Regulation Across Input Voltage, VOUT2 = 3.3 V
3.35
+85°C
SW
+25°C
3.34
–40°C
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
2
3
4
0.0001
0.001
0.01
0.1
B
A
CH3
145mA 200µs/DIV
50MS/s
CH2 4V/DIV
CH3 50mV/DIV 1MΩ
CH4 50mA/DIV 1MΩ
1MΩ
20.0M
20.0M
20.0M
W
B
OUTPUT CURRENT (A)
W
20ns/pt
B
W
Figure 28. Buck Response to Load Transient, IOUT1 = 20 mA to 180 mA,
VOUT1 = 1.8 V, PWM Mode
Figure 31. LDO Load Regulation Across Temperature, VIN2 = 3.6 V,
VOUT2 = 3.3 V
3.325
100µA
1mA
3.320
10mA
100mA
150mA
3.315
I
IN
3
3.310
3.305
3.300
3.295
3.290
3.285
3.280
VOUTx
EN
1
2
3.5
4.5
5.0
5.5
B
B
CH1 1V/DIV
CH2 3V/DIV
CH3 50mA/DIV 1MΩ
1MΩ
1MΩ
500M
500M
20.0M
A
CH2
1.14V
100µs/DIV
1MS/s
1.0µs/pt
W
W
INPUT VOLTAGE (V)
B
W
Figure 32. LDO Line Regulation Across Output Load, VOUT2 = 3.3 V
Figure 29. LDO Startup, VOUT2 = 3.3 V, IOUT2 = 5 mA
Rev. C | Page 13 of 30
ADP5043
Data Sheet
250
200
150
100
50
VIN
VOUT
1
2
0
0
B
B
20.0M
20.0M
CH1 10.0mV/DIV
CH2 800mV/DIV
A
CH2
5.33V
W
W
0.05
0.10
0.15
1MΩ
LOAD (A)
Figure 33. LDO Ground Current vs. Output Load, VOUT2 = 2.8 V
Figure 36. LDO Response to Line Transient, VIN2 = 4.5 V to 5.5 V, VOUT2 = 3.3 V
0.50
3.0
2.5
2.0
1.5
1.0
1µA
100µA
1mA
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
10mA
100mA
150mA
0.5
5.5V
4.5V
3.6V
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
5.8
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
INPUT VOLTAGE (V)
LOAD CURRENT (A)
Figure 34. LDO Ground Current vs. Input Voltage, Across Output Load,
VOUT2 = 2.8 V
Figure 37. LDO Output Current Capability vs. Output Voltage
IOUT
3
100
VOUT
1
V
V
V
V
V
= 3.3V; V = 5V
IN
OUT
OUT
OUT
OUT
OUT
= 3.3V; V = 3.6V
IN
= 2.8V; V = 3.1V
IN
= 1.5V; V = 5V
IN
= 1.5V; V = 1.8V
IN
10
B
A
CH3
28mA 200µs/DIV
500kS/s
CH1 50mV/DIV 1MΩ
CH3 50mA/DIV 1MΩ
500M
20.0M
W
0.0001 0.001
0.01
0.1
1
10
100
1k
B
W
2.0µs/pt
LOAD (mA)
Figure 35. LDO Response to Load Transient, IOUT2 from 1 mA to 80 mA,
VOUT2 = 3.3 V
Figure 38. LDO Output Noise vs. Load Current, Across Input and
Output Voltage
Rev. C | Page 14 of 30
Data Sheet
ADP5043
–10
–20
100
V
V
V
= 3.3V, V
= 1.5V, V
= 2.8V, V
= 3.6V, I
= 1.8V, I
= 3.1V, I
= 300mA
= 300mA
= 300mA
1mA
OUT2
OUT2
OUT2
IN2
IN2
IN2
LOAD
LOAD
LOAD
10mA
100mA
200mA
300mA
–30
–40
10
1
–50
–60
–70
–80
0.1
0.01
–90
–100
1
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 41. LDO PSRR vs. Frequency, VIN2 = 3.1 V, VOUT2 = 2.8 V
Figure 39. LDO Output Noise Spectrum, Across Input and Output Voltage
–10
–10
1mA
1mA
10mA
100mA
200mA
10mA
100mA
200mA
–20
–20
–30
–40
–30
–40
300mA
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 42. LDO PSRR vs. Frequency, VIN2 = 5 V, VOUT2 = 3.3 V
Figure 40. LDO PSRR Across Output Load, VIN2 = 3.3 V, VOUT2 = 2.8 V
Rev. C | Page 15 of 30
ADP5043
Data Sheet
THEORY OF OPERATION
VOUT1
WMOD
WDI1
WDI2
MR
40kΩ
75Ω
ENWD1
ENWD2
ENBK
VDDA
52kΩ
WATCHDOG
DETECTOR1
WATCHDOG
DETECTOR2
VDDA
AVIN
VIN1
GM ERROR
AMP
POFF
200kΩ
PWM
COMP
WATCHDOG
WSTAT
STATUS
MONITOR
SOFT START
I
LIMIT
DEBOUNCE
R1
PSM
COMP
R0
PWM/PSM
CONTROL
BUCK1
LOW
CURRENT
VDDA
A
B
C
nRSTO
SW
Y
RESET
GENERATOR
OSCILLATOR
DRIVER
AND
ANTISHOOT
THROUGH
V
REF
SYSTEM
UNDERVOLTAGE
LOCK OUT
600Ω
PGND
ENLDO
THERMAL
SHUTDOWN
POFF
MODE
ENABLE
AND MODE
CONTROL
MODE
EN1
ENBK
R1
R2
ENLDO
EN2
SEL
LDO
CONTROL
VDDA
OPMODE_FUSES
ADP5043
AGND
VIN2
VOUT2
Figure 43. Functional Block Diagram
The buck regulator can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
switching frequency of the buck is always constant and does not
change with the load current. If the MODE pin is at a logic low
level, the switching regulator operates in auto PWM/PSM mode.
In this mode, the regulator operates at fixed PWM frequency
when the load current is above the power saving current threshold.
When the load current falls below the power saving current
threshold, the regulator enters power saving mode where the
switching occurs in bursts. The burst repetition rate is a
function of the current load and the output capacitor value.
This operating mode reduces the switching and quiescent
current losses.
POWER MANAGEMENT UNIT
The ADP5043 is a micro power management unit (micro PMU)
combing one step-down (buck) dc-to-dc regulator, one low
dropout linear regulator (LDO), and a supervisory circuit with dual
watchdog, for processor control. The regulators are activated by a
logic level high applied to the respective EN pins. EN1 controls
the buck regulator while EN2 controls the LDO. The ADP5043
has factory programmed output voltages and reset voltage
threshold. Other features available in this device are the MODE
pin to control the buck switching operation, a status pin (WSTAT)
informing the external processor of which watchdog caused a
reset, and a push-button reset input (nRSTO).
When a regulator is turned on, the output voltage is controlled
through a soft start circuit, which prevents a large inrush current
due to the discharged output capacitors.
Rev. C | Page 16 of 30
Data Sheet
ADP5043
part of this time, the converter is able to stop switching and
Thermal Protection
enters an idle mode, which improves conversion efficiency.
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off the buck and LDO.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included in the thermal shutdown circuit
so that if thermal shutdown occurs, the buck and LDO do not
return to normal operation until the on-chip temperature drops
below 130°C. When coming out of thermal shutdown, a soft
start is initiated.
PWM Mode
In PWM mode, the buck operates at a fixed frequency of 3 MHz,
set by an internal oscillator. At the start of each oscillator cycle,
the high-side PFET switch is turned on, sending a positive
voltage across the inductor. Current in the inductor increases
until the current sense signal crosses the peak inductor current
threshold that turns off the PFET switch and turns on the low-
side NFET synchronous rectifier. This sends a negative voltage
across the inductor, causing the inductor current to decrease.
The synchronous rectifier stays on for the rest of the cycle. The
buck regulates the output voltage by adjusting the peak inductor
current threshold.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated in the ADP5043. If the input
voltage on AVIN drops below a typical 2.15 V UVLO threshold,
all channels shut down. In the buck channel, both the power
switch and the synchronous rectifier turn off. When the voltage
on AVIN rises above the UVLO threshold, the part is enabled
once more.
Power Save Mode (PSM)
The buck smoothly transitions to PSM operation when the load
current decreases below the PSM current threshold. When the
buck enters power save mode, an offset is induced in the PWM
regulation level, which makes the output voltage rise. When the
output voltage reaches a level that is approximately 1.5% above
the PWM regulation level, PWM operation is turned off. At this
point, both power switches are off, and the buck enters an idle
state. The output capacitor discharges until the output voltage
falls to the PWM regulation voltage, at which point the device
drives the inductor to make the output voltage rise again to the
upper threshold. This process is repeated while the load current
stays below the PSM current threshold.
Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for 5 V applications. For these
models, the device hits the turn-off threshold when the input
supply drops to 3.65 V typical.
Enable/Shutdown
The ADP5043 has individual control pins for each regulator. A
logic level high applied to the ENx pin activates a regulator; a
logic level low turns off a regulator.
When regulators are turned off after a Watchdog 2 event (see
the Watchdog 2 Input section), the reactivation of the regulator
occurs with a factory programmed order (see Table 9). The
delay between the regulator activation (tD1, tD2) is 2 ms.
PSM Current Threshold
The PSM current threshold is set to 100 mA. The buck employs
a scheme that enables this current to remain accurately con-
trolled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to, and exit from, the PSM
mode. The PSM current threshold is optimized for high
efficiency over all load currents.
Table 9. ADP5043 Regulators Sequencing
REGSEQ[1:0] Regulators Sequence (First to Last)
0
0
1
1
0
1
0
1
LDO to buck
Buck to LDO
Buck to LDO
No sequence, all regulators start at same time
Short-Circuit Protection
The buck includes frequency foldback to prevent current
runaway with a hard short on the output. When the voltage
at the feedback pin falls below half the target output voltage,
indicating the possibility of a hard short at the output, the
switching frequency is reduced to half the internal oscillator
frequency. The reduction in the switching frequency allows
more time for the inductor to discharge, preventing a runaway
of output current.
BUCK SECTION
The buck uses a fixed frequency and high speed current-mode
architecture. The buck operates with an input voltage of 2.3 V
to 5.5 V.
Control Scheme
The buck operates with a fixed frequency current-mode PWM
control at medium to high loads for high efficiency; operation
shifts to a power save mode (PSM) control scheme at light loads
to lower the regulation power losses. When operating in fixed
frequency PWM mode, the duty cycle of the integrated switch is
adjusted to regulate the output voltage. When operating in PSM at
light loads, the output voltage is controlled in a hysteretic
manner that produces a higher output voltage ripple. During
Soft Start
The buck has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input
voltage drops when a battery or a high impedance power
source is connected to the input of the converter.
Rev. C | Page 17 of 30
ADP5043
Data Sheet
problems with microprocessor code execution can be monitored
and corrected with a dual-watchdog timer.
Current Limit
The buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.
Reset Output
The ADP5043 has an active-low, open-drain reset output. This
output structure requires an external pull-up resistor to connect the
reset output to a voltage rail that is no higher than 6 V. The resistor
should comply with the logic low and logic high voltage level
requirements of the microprocessor while supplying input current
and leakage paths on the nRSTO pin. A 10 kΩ pull-up resistor is
adequate in most situations.
100% Duty Operation
With a dropping input voltage or with an increase in load
current, the buck may reach a limit where, even with the PFET
switch on 100% of the time, the output voltage drops below the
desired output voltage. At this limit, the buck transitions to a
mode where the PFET switch stays on 100% of the time. When
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.
The reset output is asserted when the monitored rail is below
the reset threshold (VTH), when WDI1 or WDI2 is not serviced
within the watchdog timeout period (tWD1 and tWD2). Reset remains
asserted for the duration of the reset active timeout period (tRP)
after the monitored rail rises above the reset threshold or after
the watchdog timer times out. Figure 44 illustrates the behavior
of the reset output, nRSTO, and it assumes that VOUT2 is
selected as the rail to be monitored and supplies the external pull-
up connected to the nRSTO output.
LDO SECTION
The ADP5043 contains one LDO with a low quiescent current
that provides an output current up to 300 mA. The low, 15 μA
typical, quiescent current at no load makes the LDO ideal for
battery-operated portable equipment.
V
V
TH
TH
1V
0V
VOUT2
nRSTO
tRP1
tRD
The LDO operates with an input voltage range of 1.7 V to
5.5 V. The wide operating range makes this LDO suitable for
a cascade configuration where the LDO supply voltage is
provided from the buck regulator.
0V
RSTO
tRP1
1V
0V
tRD
Figure 44. Reset Timing Diagram
The LDO also provides high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with a small 1 ꢀF ceramic input and output capacitors.
The reset threshold voltage and the sensed rail (VOUT1, VOUT2,
or AVIN) are factory programmed. Refer to Table 16 for a
complete list of the reset thresholds available for the ADP5043.
The LDO is optimized to supply analog circuits by offering
better noise performance than the buck regulator.
When monitoring the input supply voltage, AVIN, if the
selected reset threshold is below the UVLO level (factory
programmable to 2.25 V or 3.6 V) the reset output, nRSTO,
is asserted low as soon as the input voltage falls below the
UVLO threshold. Below the UVLO threshold, the reset output
is maintained low down to ~1 V VIN. This is to ensure that the
reset output is not released when there is sufficient voltage on the
rail supplying a processor to restart the processor operations.
Internally, an LDO consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is con-
trolled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower
than the reference voltage, the gate of the PMOS device is
pulled lower, allowing more current to flow and increasing
the output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
reducing the current flowing to the output.
Manual Reset Input
MR
The ADP5043 features a manual reset input ( ) which, when
MR
driven low, asserts the reset output. When
low-to-high, reset remains asserted for the duration of the reset
MR
transitions from
SUPERVISORY SECTION
active timeout period before deasserting. The
input has a
The ADP5043 provides microprocessor supply voltage super-
vision by controlling the reset input of the microprocessor.
Code execution errors are avoided during power-up, power-
down, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold and by allowing
supply voltage stabilization with a fixed timeout reset pulse
after the supply voltage rises above the threshold. In addition,
52 kΩ, internal pull-up, connected to AVIN, so that the input
is always high when unconnected. An external push-button
MR
switch can be connected between
user can generate a reset. Debounce circuitry for this purpose is
MR
and ground so that the
integrated on chip. Noise immunity is provided on the
input,
and fast, negative-going transients of up to 100 ns (typical) are
MR
ignored. A 0.1 ꢀF capacitor between
additional noise immunity.
and ground provides
Rev. C | Page 18 of 30
Data Sheet
ADP5043
Watchdog 1 Input
Watchdog 2 Input
The ADP5043 features a watchdog timer that monitors
microprocessor activity. The watchdog timer circuit is cleared
with every low-to-high or high-to-low logic transition on the
watchdog input pin (WDI1), which detects pulses as short as
80 ns. If the timer counts through the preset watchdog timeout
period (tWD1), an output reset is asserted. The microprocessor is
required to toggle the WDI1 pin to avoid being reset. Failure of
the microprocessor to toggle WDI1 within the timeout period,
therefore, indicates a code execution error, and the reset pulse
generated restarts the microprocessor into a known state.
The ADP5043 features an additional watchdog timer that
monitors microprocessor activity in parallel with the first
watchdog but with a much longer timeout. This provides
additional security and safety in case Watchdog 1 is incorrectly
strobed. A timer circuit is cleared with every low-to-high or
high-to-low logic transition on the watchdog input pin (WDI2),
which detects pulses as short as 8 μs. If the timer counts through
the preset watchdog timeout period (tWD2), reset is asserted,
followed by a power cycle of all regulators. The microprocessor
is required to toggle the WDI2 pin to avoid being reset and
powered down. Failure of the microprocessor to toggle WDI2
within the timeout period, therefore, indicates a code execution
error, and the reset output nRSTO is forced low for tRP2. Then,
all the regulators are turned off for the tPOFF time. After the tPOFF
period, the regulators are reactivated according to a predefined
sequence (see Table 9). Finally, the reset line (nRSTO) is asserted
for tRP1. This guarantees a clean power-up of the system and
proper reset.
As well as logic transitions on WDI1, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
the monitored rail. When reset is asserted, the watchdog timer
is cleared and does not begin counting again until reset deasserts.
Watchdog 1 timer can be disabled by leaving WDI1 floating or
by three-stating the WDI1 driver. The pin WMOD controls the
Watchdog 1 operating mode. If WMOD is set to logic level low,
Watchdog 1 is enabled as long as WDI1 is not in three-state. If
WMOD is set to logic level high, Watchdog 1 is always active
and cannot be disabled by a three-state condition. WMOD
input has an internal 200 kΩ pull-down resistor.
As well as logic transitions on WDI2, the watchdog timer is
also cleared by a reset assertion due to an undervoltage condition
on the VTH monitored rail which can be factory programmable
between VOUT1, VOUT2, and AVIN (see Table 21). When
reset is asserted, the watchdog timer is cleared and does not
begin counting again until reset deasserts.
Watchdog 1 timeout is factory set to two possible values, as
indicated in Table 18.
V
V
SENSED
TH
Watchdog 2 timeout is factory set to seven possible values as
indicated in Table 19. One additional option allows Watchdog 2
to be factory disabled.
1V
0V
nRSTO
WDI1
tRP1
tWD1
tRP1
0V
0V
Figure 45. Watchdog 1 Timing Diagram
AVIN/VINx/ENx
VOUT1
tPOFF
0V
tD1
tD1
tD2
tD2
VOUT2
V
TH
0V
tRP2
tRP1
tRP1
nRSTO
WDI2
tWD2
0V
0V
tWDCLEAR
WSTAT
Figure 46. Watchdog 2 Timing Diagram (Assuming that VOUT2 is the Monitored Rail)
Rev. C | Page 19 of 30
ADP5043
Data Sheet
The external processor can further distinguish a reset caused
by a Watchdog 1 timeout from a power failure, status monitor
WSTAT indicating a high level, by implementing a RAM check
or signature verification after reset. A RAM check or signature
failure indicates that a power failure has occurred, whereas a
RAM check or signature validation indicates that a Watchdog 1
timeout has occurred.
Watchdog Status Indicator
In addition to the dual watchdog function, the ADP5043 features a
watchdog status monitor available on the WSTAT pin. This pin
can be queried by the external processor to determine the origin of
a reset. WSTAT is an open-drain output.
WSTAT outputs a logic level depending on the condition
that has generated a reset. WSTAT is forced low if the reset
was generated because of a Watchdog 2 timeout. WSTAT is
pulled high, through external pull-up, for any other reset cause
(Watchdog 1 timeout, power failure or monitored voltage be
low threshold). The status monitor is automatically cleared
(set to logic level high) 10 seconds after the nRSTO low-to-high
transition (tWDCLEAR). The processor firmware must be designed
to read the WSTAT flag before tWDCLEAR expiration after a
Watchdog 2 reset.
Table 10 shows the possible watchdog decoded statuses.
Table 10. Watchdog Status Decoding
WSTAT
High
High
Low
RAM Checksum
Reset Origin
Power failure
Watchdog 1
Watchdog 2
Failed
Ok
Don't care
The WSTAT flag is not updated in the event of a reset due to a
low voltage threshold detection or Watchdog 1 event occurring
within 10 seconds after an nRSTO low-to-high transition. In
this situation, WSTAT maintains the previous state (see the state
flow in Figure 47).
NO POWER APPLIED TO AVIN.
ALL REGULATORS AND SUPERVISORY
TURNED OFF
NO POWER
AVIN > VUVLO
AVIN < VUVLO
AVIN < VUVLO
TRANSITION
STATE
POR
INTERNAL CIRCUIT BIASED
REGULATORS AND
SUPERVISORY NOT ACTIVATED
END OF POR
STANDBY
AVIN < VUVLO
ALL ENx = HIGH
ALL ENx = LOW
AVIN < VUVLO
TRANSITION
WSTAT
TIMEOUT
(t
WDOG2
STATE
TIMEOUT
TRANSITION
STATE
WSTAT = HIGH
WSTAT = 1
)
(t
)
WSTAT = 0
WDCLEAR
WD2
WSTAT = LOW
ALL REGULATORS AND
SUPERVISOR ACTIVATED
ACTIVE
RESET SHORT
END OF RESET
WDOG1 TIMEOUT
(t ) AND
WD1
WSTAT TIMEOUT
PULSE (t
)
RP2
WDOG1 TIMEOUT
(t
END OF RESET
PULSE (t
)
)
RP1
WD1
TRANSITION
STATE
WSTAT = HIGH
POWER OFF
VMON < VTH
WSTAT = 1
END OF (t
POFF
)
PULSE
RESET
NORMAL
Figure 47. ADP5043 State Flow
Rev. C | Page 20 of 30
Data Sheet
ADP5043
APPLICATIONS INFORMATION
Because the buck is a high switching frequency dc-to-dc converter,
shielded ferrite core material is recommended for its low core
losses and low EMI.
BUCK EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency
and transient response are made by varying the choice of
external components in the applications circuit, as shown in
Figure 48.
Output Capacitor
Higher output capacitor values reduce the output voltage
ripple and improve load transient response. When choosing
the capacitor value, it is also important to account for the loss
of capacitance due to output voltage dc bias.
V
CC
VIN1
VOUT1
VCORE
VDDIO
VOUT2
Ceramic capacitors are manufactured with a variety of dielec-
trics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temper-
ature range and dc bias conditions. X5R or X7R dielectrics with
a voltage rating of 6.3 V or 10 V are highly recommended for
best performance. Y5V and Z5U dielectrics are not recommended
for use with any dc-to-dc converter because of their poor
temperature and dc bias characteristics.
nRSTO
WDI1
RESET
I/O
WDI2
I/O
MICROPROCESSOR
ADP5043
Figure 48. Typical Applications Circuit
Inductor
The high switching frequency of the buck regulator of the
ADP5043 allows for the selection of small chip inductors. For
best performance, use inductor values between 0.7 μH and
3 μH. Suggested inductors are shown in Table 11.
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calcu-
lated using the following equation:
C
EFF = COUT × (1 − TEMPCO) × (1 − TOL)
The peak-to-peak inductor current ripple is calculated using
the following equation:
where:
CEFF is the effective capacitance at the operating voltage.
VOUT (VIN VOUT
VIN fSW L
)
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
IRIPPLE
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%,
and COUT is 9.2481 μF at 1.8 V, as shown in Figure 49.
where:
SW is the switching frequency.
L is the inductor value.
f
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
Substituting these values in the equation yields
CEFF = 9.2481 μF × (1 − 0.15) × (1 − 0.1) = 7.0747 μF
I RIPPLE
2
To guarantee the performance of the buck regulator, it is
imperative that the effects of dc bias, temperature, and
tolerances on the behavior of the capacitors be evaluated
for each application.
I PEAK I LOAD ( MAX )
Table 11. Suggested 1.0 μH Inductors
Dimensions
(mm)
ISAT
(mA)
DCR
(mΩ)
Vendor
Murata
Murata
Model
12
LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9
LQM18FN1R0M00B 1.6 × 0.8 × 0.8
Taiyo Yuden CBMF1608T1R0M
1400
150
290
900
230
85
26
90
59
80
81
85
10
8
1.6 × 0.8 × 0.8
2.0 × 2.0 × 1.4
Coilcraft
TDK
EPL2014-102ML
GLFR1608T1R0M-LR 1.6 × 0.8 × 0.8
Coilcraft
Toko
0603LS-102
1.8 × 1.69 × 1.1 400
6
MDT2520-CN
2.5 × 2.0 × 1.2
1350
4
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
2
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
0
0
1
2
3
4
5
6
DC BIAS VOLTAGE (V)
Figure 49. Typical Capacitor Performance
Rev. C | Page 21 of 30
ADP5043
Data Sheet
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
VRIPPLE IRIPPLE ESR
1/ 8 f COUT
COUT
SW
VOUT (VIN VOUT
)
where:
ICIN ILOAD (MAX )
VIN
VRIPPLE is allowable peak-to-peak output voltage ripple in volts.
IRIPPLE is the inductor ripple current in Amperes.
ESRCOUT is the equivalent series resistance of the output
capacitor in Ω.
To minimize supply noise, place the input capacitor as close
to the VIN pin of the buck as possible. As with the output
capacitor, a low ESR input capacitor is recommended.
fSW is the converter switching frequency in Hertz.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 μF and a
maximum of 10 μF. Suggested capacitors are shown in Table 13.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 μF and a
maximum of 40 μF.
Table 13. Suggested 4.7 μF Capacitors
Table 12. Suggested 10 μF Capacitors
Voltage
Case Rating
Size (V)
GRM188R60J475ME19D 0603 6.3
JMK107BJ475
ECJ-0EB0J475M
Case
Size
Voltage
Rating (V)
Vendor
Type Model
X5R
Vendor
Murata
Taiyo Yuden
TDK
Type
X5R
X5R
X5R
X5R
Model
Murata
GRM188R60J106
JMK107BJ475
C1608JB0J106K
ECJ1VB0J106M
0603
0603
0603
0603
6.3
6.3
6.3
6.3
Taiyo Yuden X5R
Panasonic X5R
0603 6.3
0402 6.3
Panasonic
LDO CAPACITOR SELECTION
Output Capacitor
The buck regulator requires 10 μF output capacitors to guaran-
tee stability and response to rapid load variations and to transition
in and out the PWM/PSM modes. In certain applications, where
the buck regulator powers a processor, the operating state is
known because it is controlled by software. In this condition,
the processor can drive the MODE pin according to the operating
state; consequently, it is possible to reduce the output capacitor
from 10 μF to 4.7 μF because the regulator does not expect a
large load variation when working in PSM mode (see Figure 50).
The ADP5043 LDO is designed for operation with small, space-
saving ceramic capacitors but functions with most commonly
used capacitors as long as care is taken with the
ESR value. The ESR of the output capacitor affects stability of
the LDO control loop. A minimum of 0.70 μF capacitance
with an ESR of 1 ꢀ or less is recommended to ensure stability
of the LDO. Transient response to changes in load current is
also affected by output capacitance. Using a larger value of
output capacitance improves the transient response of the
LDO to large changes in load current.
ADP5043
R
FILT
30Ω
MICRO PMU
L1
1µH
AVIN
PROCESSOR
VCORE
SW
Input Bypass Capacitor
VOUT1
PGND
C6
Connecting a 1 μF capacitor from VIN2 to GND reduces
the circuit sensitivity to printed circuit board (PCB) layout,
especially when long input traces or high source impedance
is encountered. If greater than 1 μF of output capacitance is
required, increase the input capacitor to match it.
VIN1
4.7µF
V
IN
2.3V TO 5.5V
C2
4.7µF
VOUT2
VDDIO
RESET
C4
1µF
VIN2
R1
100kΩ
C3
1µF
nRSTO
Table 14. Suggested 1.0 μF Capacitors
WDIx
MODE
ENx
GPIO1
Voltage
Case Rating
GPIO2
2
GPIO[x:y]
Vendor
Murata
TDK
Type Model
Size
(V)
0402 10.0
0402 6.3
0402 6.3
0402 10.0
X5R
X5R
X5R
GRM155R61A105ME15
C1005JB0J105KT
ECJ0EB0J105K
Figure 50. Processor System Power Management with PSM/PWM Control
Panasonic
Taiyo Yuden X5R
LMK105BJ105MV-F
Rev. C | Page 22 of 30
Data Sheet
ADP5043
Substituting these values into the following equation yields:
EFF = 0.94 ꢁF × (1 − 0.15) × (1 − 0.1) = 0.719 ꢁF
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5043 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary tempe-
rature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or 10 V are highly recommended
for best performance. Y5V and Z5U dielectrics are not
recommended for use with any LDO because of their poor
temperature and dc bias characteristics.
C
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5043, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
SUPERVISORY SECTION
Watchdog 1 Input Current
To minimize watchdog input current (and minimize overall
power consumption), leave WDI1 low for the majority of the
watchdog timeout period. When driven high, WDI1 can draw
as much as 25 μA. Pulsing WDI1 low-to-high-to-low at a low
duty cycle reduces the effect of the large input current. When
WDI1 is unconnected and WMOD is set to logic level low, a
window comparator disconnects the watchdog timer from the
reset output circuitry so that reset is not asserted when the
watchdog timer times out.
Figure 51 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 μF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about 15ꢀ over the −40°C to +85°C tempera-
ture range and is not a function of package or voltage rating.
1.2
Negative-Going VCC Transients
1.0
0.8
0.6
To avoid unnecessary resets caused by fast power supply transients,
the ADP5043 is equipped with glitch rejection circuitry. The
typical performance characteristic in Figure 52 plots the monitored
rail voltage, VTH, transient duration vs. the transient magnitude.
The curve shows combinations of transient magnitude and
duration for which a reset is not generated for a 2.93 V reset
threshold part. For example, with the 2.93 V threshold, a transient
that goes 100 mV below the threshold and lasts 8 μs typically
does not cause a reset, but if the transient is any larger in
magnitude or duration, a reset is generated.
0.4
0.2
0
0
1
2
3
4
5
6
1000
DC BIAS VOLTAGE (V)
Figure 51. Capacitance vs. Voltage Characteristic
900
800
700
600
500
400
300
200
100
0
Use the following equation to determine the worst-case capa-
citance accounting for capacitor variation over temperature,
component tolerance, and voltage.
C
EFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
where:
C
BIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
0.1
1
10
100
(TEMPCO) over −40°C to +85°C is assumed to be 15ꢀ for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10ꢀ, and CBIAS is 0.94 ꢁF at 1.8 V as shown in Figure 51.
COMPARATOR OVERDRIVE (% OF V
)
TH
Figure 52. Maximum VTH Transient Duration vs. Reset
Threshold Overdrive
Rev. C | Page 23 of 30
ADP5043
Data Sheet
The second watchdog, refreshed through the WDI2 pin, is
Watchdog Software Considerations
useful in applications where safety is a very critical factor and
the system must recover from unexpected operations, for example,
a processor stuck in a continuous loop where Watchdog 1 is
kept refreshed or environmental conditions that may unset or
damage the processor port controlling the WDI1 pin. In the
event of a Watchdog 2 timeout, the ADP5043 power cycles all
the supplied rails to guarantee a clean processor start.
In implementing the watchdog strobe code of the
microprocessor, quickly switching WDI1 low-to-high and
then high-to-low (minimizing WDI1 high time) is desirable
for current consumption reasons. However, a more effective
way of using the watchdog function can be considered.
A low-to-high-to-low WDI1 pulse within a given subroutine
prevents the watchdog from timing out. However, if the sub-
routine becomes stuck in an infinite loop, the watchdog cannot
detect this because the subroutine continues to toggle WDI1. A
more effective coding scheme for detecting this error involves
using a slightly longer watchdog timeout. In the program that
calls the subroutine, WDI1 is set high. The subroutine sets
WDI1 low when it is called. If the program executes without error,
WDI1 is toggled high and low with every loop of the program.
If the subroutine enters an infinite loop, WDI1 is kept low, the
watchdog times out, and the microprocessor is reset (see
Figure 53).
PCB LAYOUT GUIDELINES
Poor layout can affect the ADP5043 performance, causing
electro-magnetic interference (EMI) and electromagnetic
compatibility (EMC) problems, ground bounce, and voltage
losses. Poor layout can also affect regulation and stability. A
good layout is implemented using the following guidelines:
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
Maximize the size of ground metal on the component side
to help with thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
START
SET WDI
HIGH
RESET
PROGRAM
CODE
INFINITE LOOP:
WATCHDOG
TIMES OUT
SUBROUTINE
SET WDI
LOW
RETURN
Figure 53. Watchdog Flow Diagram
Rev. C | Page 24 of 30
Data Sheet
ADP5043
necessary to include a safety margin when calculating the
power dissipated in the buck.
POWER DISSIPATION/THERMAL CONSIDERATIONS
The ADP5043 is a highly efficient micro PMU, and in most
cases the power dissipated in the device is not a concern.
However, if the device operates at high ambient temperatures
and with maximum loading conditions, the junction
temperature can reach the maximum allowable operating
limit (125°C).
A third way to estimate the power dissipation is analytical and
involves modeling the losses in the buck circuit provided by
Equation 8 to Equation 11 and the losses in the LDO provided
by Equation 12.
Buck Regulator Power Dissipation
When the junction temperature exceeds 150°C, the ADP5043
turns off all the regulators, allowing the device to cool down.
Once the die temperature falls below 135°C, the ADP5043
resumes normal operation.
The power loss of the buck regulator is approximated by
P
LOSS = PDBUCK + PL
where:
DBUCK is the power dissipation on the ADP5043 buck regulator.
(3)
P
This section provides guidelines to calculate the power dissi-
pated in the device and to make sure the ADP5043 operates
below the maximum allowable junction temperature.
PL is the inductor power losses.
The inductor losses are external to the device and they don’t
have any effect on the die temperature.
The efficiency for each regulator on the ADP5043 is given by
The inductor losses are estimated (without core losses) by
P
OUT
2
100%
(1)
(4)
(5)
PL
IOUT1 (RMS )
DCR
L
P
IN
where IOUT1(RMS) is the RMS load current of the buck regulator.
where:
η is efficiency.
PIN is the input power.
OUT is the output power.
Power loss is given by
LOSS = PIN − POUT
or
LOSS = POUT (1-η)/η
IOUT1 (RMS ) IOUT1
1 + r/12
where r is the inductor ripple current.
P
r ≈ VOUT1 × (1-D)/(IOUT1 × L × fSW)
D = VOUT1/VIN1
(6)
(7)
P
(2a)
(2b)
f
SW is switching frequency.
L is inductance.
DCRL is the inductor series resistance.
D is duty cycle.
P
The power dissipation of the supervisory function is small and
can be neglected.
The ADP5043 buck regulator power dissipation, PDBUCK
,
Power dissipation can be calculated in several ways. The most
intuitive and practical is to measure the power dissipated at
the input and all the outputs. The measurements should be
performed at the worst-case conditions (voltages, currents,
and temperature). The difference between input and output
power is dissipated in the device and the inductor. Use
Equation 4 to derive the power lost in the inductor, and from
this use Equation 3 to calculate the power dissipation in the
ADP5043 buck regulator.
includes the power switch conductive losses, the switch losses,
and the transition losses of each channel. There are other
sources of loss, but these are generally less significant at high
output load currents, where the thermal limit of the application
will be. Equation 8 shows the calculation made to estimate the
power dissipation in the buck regulator.
P
DBUCK = PCOND + PSW + PTRAN
The power switch conductive losses are due to the output current,
OUT1, flowing through the PMOSFET and the NMOSFET power
(8)
I
A second method to estimate the power dissipation uses the
efficiency curves provided for the buck regulator, while the
power lost on the LDO is calculated using Equation 12. Once
the buck efficiency is known, use Equation 2b to derive the total
power lost in the buck regulator and inductor, use Equation 4
to derive the power lost in the inductor, and thus calculate the
power dissipation in the buck converter using Equation 3. Add
the power dissipated in the buck and in the LDO to find the
total dissipated power.
switches that have internal resistance, RDSON-P and RDSON-N. The
amount of conductive power loss is found by:
2
P
COND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT1
(9)
For the ADP5043, at 125°C junction temperature and VIN =
3.6 V, RDSON-P is approximately 0.2 Ω, and RDSON-N is
approximately 0.16 Ω. At VIN = 2.3 V, these values change to
0.31 Ω and 0.21 Ω respectively, and at VIN = 5.5 V, the values
are 0.16 Ω and 0.14 Ω.
It should be noted that the buck efficiency curves are typical
values and may not be provided for all possible combinations
of VIN, VOUT, and IOUT. To account for these variations, it is
Rev. C | Page 25 of 30
ADP5043
Data Sheet
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by:
Junction Temperature
The total power dissipation in the ADP5043 simplifies to:
PD = {[PDBUCK + PDLDO1 + PDLDO2]}
(13)
P
SW = (CGATE-P + CGATE-N) × VIN12 × fSW
(10)
In cases where the board temperature (TA) is known, the
where:
thermal resistance parameter, θJA, can be used to estimate the
junction temperature rise. TJ is calculated from TA and PD using
the formula:
C
C
GATE-P is the PMOSFET gate capacitance.
GATE-N is the NMOSFET gate capacitance.
For the ADP5043, the total of (CGATE-P + CGATE-N) is ~150 pF.
TJ = TA + (PD × θJA)
(14)
The transition losses occur because the PMOSFET cannot be
turned on or off instantaneously, and the SW node takes some
time to slew from near ground to near VOUT1 (and from VOUT1 to
ground). The amount of transition loss is calculated by:
The typical θJA value for the 20-lead, 4 mm × 4 mm LFCSP is
38°C/W, see Table 7.
An important factor to consider is that θJA is based on a four-
layer 4 inch × 3 inch, 2.5 oz copper, as per JEDEC standard, and
real applications may use different sizes and layers. It is
important to maximize the copper used to remove the heat from
the device, and copper exposed to air dissipates heat better than
copper used in the inner layers. The thermal pad (TP) should
be connected to the ground plane with several vias as shown in
Figure 55.
P
TRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW
(11)
where tRISE and tFALL are the rise time and the fall time of the
switching node, SW. For the ADP5043, the rise and fall times of
SW are in the order of 5 ns.
If the equations and parameters previously given are used for
estimating the converter efficiency, it must be noted that the
equations do not describe all of the converter losses, and the
parameter values given are typical numbers. The converter
performance also depends on the choice of passive components
and board layout, so a sufficient safety margin should be
included in the estimate.
If the case temperature can be measured, the junction
temperature is calculated by:
TJ = TC + (PD × θJC)
where:
TC is the case temperature.
JC is the junction-to-case thermal resistance provided in
(15)
LDO Regulator Power Dissipation
θ
The power loss of a LDO regulator is given by:
Table 7.
P
DLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND
)
(12)
When designing an application for a particular ambient
temperature range, calculate the expected ADP5043 power
dissipation (PD) due to the losses of all channels by using
Equation 8 to Equation 13. From this power calculation, the
where:
I
V
LOAD is the load current of the LDO regulator.
IN and VOUT are input and output voltages of the LDO,
respectively.
junction temperature, TJ, can be estimated using Equation 14.
I
GND is the ground current of the LDO regulator.
The reliable operation of the buck regulator and the LDO
regulator can be achieved only if the estimated die junction
temperature of the ADP5043 (Equation 14) is less than 125°C.
Reliability and mean time between failures (MTBF) is highly
affected by increasing the junction temperature. Additional
information about product reliability can be found in the
Analog Devices, Inc., Reliability Handbook.
Power dissipation due to the ground current is small and it
can be ignored.
Rev. C | Page 26 of 30
Data Sheet
ADP5043
EVALUATION BOARD SCHEMATICS AND ARTWORK
AVIN
AVIN
L1
1µH
R
30Ω
TP4
TP1
FILT
SW
V
@
OUT1
800mA
VOUT1
PGND
C6
TP5
BUCK
EN_BK
10µF
VIN1 = 2.3V
TO 5.5V
VIN1
C5
4.7µF
TP12
MODE
EN1
TP2
VOUT2
TP6
V
@
OUT2
300mA
LDO
VIN2
VIN2 = 1.7V
C2
1µF
TO 5.5V
EN_LDO
C1
1µF
TP11
TP3
EN2
WSTAT
nRSTO
WDI1
AVIN
TP9
TP10
TP8
TP7
MR
WDI2
NC
NC
WMOD
GND
AGND
GND
Figure 54. Evaluation Board Schematic
SUGGESTED LAYOUT
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
mm
3.3V
C3 1uF
6.3V/XR5
0402
C4 - 1uF
10V/XR5
0402
0.5
1
1.5
2
AVIN
VIN 1
SW
MR
WDI 1
WMOD
2.5
3
AGND
3.5
4
PGND
EN1
MODE
GND
ADP5043
4.5
5
VIAs LEGEND:
PPL = POWER PLANE (+4V)
GPL = GROUND PLANE
C6 - 10uF
6.3V/XR5 0603
5.5
TOP LAYER
2ND LAYER
6
1.5V
mm
Figure 55. Layout
Rev. C | Page 27 of 30
ADP5043
Data Sheet
BILL OF MATERIALS
Table 15.
Reference
C1, C2
C5
C6
RFILT
Value
Part Number
Vendor
Package
1 μF, X5R, 6.3 V
LMK105BJ105MV-F
LMK107BJ475MA-T
JMK107BJ106MA-T
Taiyo Yuden
Taiyo Yuden
Taiyo Yuden
0402
0603
0603
0201/0402
0603
4.7 μF, X5R, 10 V
10 μF, X5R, 6.3 V
30 Ω
1 μH, 0.09 Ω, 290 mA
1 μH, 0.08 Ω, 230 mA
Dual regulator micro PMU
L1
BRC1608T1R0M
GLFR1608T1R0M-LR
ADP5043
Taiyo Yuden
TDK
Analog Devices
0603
20-Lead LFCSP
IC1
APPLICATION DIAGRAM
AVIN
R
30Ω
FILT
L1
1µH
AVIN
VIN1
6
SW
V
@
OUT1
BUCK
8
11
9
800mA
VOUT1
PGND
C6
10µF
VIN1 = 2.3V
TO 5.5V
7
EN_BK
C5
4.7µF
ON
FPWM
MODE
17
2
PWM/PSM
EN1
10
3
OFF
VOUT2
V
@
OUT2
LDO
VIN2
VIN2 = 1.7V
TO 5.5V
300mA
C2
1µF
C1
1µF
EN_LDO
V
DD
ON
EN2
MR
SUPERVISOR
4
OFF
R1 R2
AVIN
WSTAT
nRSTO
15
5
20
RESET
POFF
PUSH-BUTTON
RESET
WDI2
WDI1
12
19
WDOG2
WDOG1
V
DD
ON
WMOD
18
OFF
NC
NC
1
IC1
14
TP
13
16
AGND
GND
GND
Figure 56. Application Diagram
Rev. C | Page 28 of 30
Data Sheet
ADP5043
FACTORY PROGRAMMABLE OPTIONS
Table 16. Reset Voltage Threshold Options1
TA = +25°C
Typ
TA = −40°C to +85°C
Selection
Min
Max
Min
Max
Unit
V
V
V
V
V
V
V
V
111 (For VIN = 5 V − 6%)
110 (For VOUT = 3.3 V)
101 (For VOUT = 3.3 V)
100 (For VOUT = 2.8 V)
011 (For VOUT = 2.8 V)
010 (For VOUT = 2.5 V − 6%)
001 (For VOUT = 2.2 V − 6%)
000 (For VOUT = 1.8 V − 6%)
4.630
3.080
2.930
2.630
2.500
2.350
2.068
1.692
4.700
3.157
3.000
2.696
2.563
2.385
2.099
1.717
3.034
2.886
2.591
2.463
3.126
2.974
2.669
2.538
3.003
2.857
2.564
2.438
1 When monitoring AVIN, the reset threshold selected, by fuse option or by the external resistor divided, must be higher than the UVLO threshold (2.25 V or 3.6 V).
Table 17. Reset Timeout Options
Selection
Min
Typ
30
200
Max
36
240
Unit
ms
ms
0
1
24
160
Table 18. Watchdog 1 Timer Options
Selection
Min
81.6
1.12
Typ
102
1.6
Max
122.4
1.92
Unit
ms
sec
0
1
Table 19. Watchdog 2 Timer Options
Selection
Min
Typ
Max
Unit
000
6
7.5
9
sec
001
Watchdog 2 disabled
010
011
100
101
110
111
3.2
6.4
12.8
25.6
51.2
102.4
4
8
16
32
64
128
4.8
9.6
19.2
38.4
76.8
153.6
min
min
min
min
min
min
Table 20. Power-Off Timing Options
Selection
Min
140
280
Typ
200
400
Max
280
560
Unit
ms
ms
0
1
Table 21. Reset Sensing Options
Selection
Monitored Rail
VOUT1 pin
Reserved
VOUT2 pin
AVIN1 pin
00
01
10
11
1 When monitoring AVIN, the reset threshold selected, by fuse option or by the external resistor divided, must be higher than the UVLO threshold (2.25 V or 3.6 V).
Table 22. BUCK and LDO Output Voltage Options
Selection
Output Voltage
3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.82 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V
Buck
LDO
3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.25 V, 2.0 V, 1.8 V, 1.7 V, 1.6 V, 1.5 V, 1.2 V, 1.1 V, 1 V, 0.9 V, 0.8 V
Rev. C | Page 29 of 30
ADP5043
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
AREA
PIN 1
TIONS
INDICATOR AR EA OP
(SEE DETAIL A)
16
20
0.50
BSC
1
15
2.75
2.60 SQ
2.35
EXPOSED
PAD
5
11
10
6
0.50
0.40
0.30
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11.
Figure 57. 20-Lead, Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Regulator Settings
VOUT1 = 1.5 V
Supervisory Settings
WD1 tOUT = 1.6 sec
WD2 tOUT = 128 min
Reset tOUT = 200 ms
POFF = 200 ms
Temperature Range
Package Description
Package Option
ADP5043ACPZ-1-R7
TJ = −40°C to +125°C
20-Lead LFCSP
CP-20-8
VOUT2 = 3.3 V
UVLO = 2.25 V
Sequencing: LDO, buck
V
TH sensing = VOUT2, 2.93 V
ADP5043CP-1-EVALZ
Evaluation Board
1 Z = RoHS Compliant Part.
2 Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits. See the Power Dissipation/Thermal
Considerations section for more information.
©2011–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09682-0-9/19(C)
Rev. C | Page 30 of 30
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