ADP3192A_技术文档

8-Bit Programmable 2- to 4-Phase

Synchronous Buck Controller

ADP3192A

FUNCTIONAL BLOCK DIAGRAM

FEATURES

VCC

31

RT RAMPADJ

12 13

Selectable 2-, 3-, or 4-phase operation at up to

1 MHz per phase

7.7 mV worst-case differential sensing error over

temperature

Logic-level PWM outputs for interface to external high

power drivers

Fast enhanced PWM (FEPWM) flex mode for excellent load

transient performance

Active current balancing between all output phases

Built-in power-good/crowbar blanking supports on-the-fly

VID code changes

Digitally programmable 0.5 V to 1.6 V output supports both

VR10.x and VR11 specifications

SHUNT

REGULATOR

OSCILLATOR

19

OD

UVLO

SHUTDOWN

SET EN

RESET

+

18

1

GND

EN

30

29

28

CMP

PWM1

PWM2

PWM3

–

+

850mV

+

RESET

CMP

–

DAC

+ 150mV

+

–

+

RESET

CMP

–

2/3/4-PHASE

CSREF

DRIVER LOGIC

RESET

27 PWM4

+

–

+

CMP

–

DAC

– 350mV

CURRENT

LIMIT

DELAY

2

PWRGD

CROWBAR

25

24

23

22

SW1

SW2

SW3

Programmable short-circuit protection with programmable

latch-off delay

10

9

TTSENSE

VRHOT

THERMAL

THROTTLING

CONTROL

VRFAN

8

SW4

17

15

CSCOMP

CSREF

11

7

ILIMIT

CURRENT

+

–

APPLICATIONS

MEASUREMENT

AND LIMIT

DELAY

16

21

CSSUM

IMON

Desktop PC power supplies for next generation

Intel® processors

VRM modules

20

5

IREF

–

+

4

FB

COMP

+

PRECISION

14

LLSET

REFERENCE

–

BOOT

VOLTAGE

AND

SOFT START

CONTROL

3

FBRTN

VIDSEL

6

SS

VID DAC

40

ADP3192A

32

33

34

35

36

37

38

39

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Figure 1.

GENERAL DESCRIPTION

The ADP3192A¹is a highly efficient, multiphase, synchronous

buck-switching regulator controller optimized for converting a

12 V main supply into the core supply voltage required by high

performance Intel processors. It uses an internal 8-bit DAC to read

a voltage identification (VID) code directly from the processor,

which is used to set the output voltage between 0.5 V and 1.6 V.

The ADP3192A also includes programmable no load offset and

slope functions to adjust the output voltage as a function of the

load current, optimally positioning it for a system transient. In

addition, the ADP3192A provides accurate and reliable short-

circuit protection, adjustable current limiting, and a delayed

power-good output that accommodates on-the-fly output

voltage changes requested by the CPU.

This device uses a multimode PWM architecture to drive the

logic-level outputs at a programmable switching frequency that

can be optimized for VR size and efficiency. The phase relation-

ship of the output signals can be programmed to provide 2-, 3-,

or 4-phase operation, allowing for the construction of up to

four complementary buck-switching stages.

The ADP3192A has a built-in shunt regulator that allows the part

to be connected to the 12 V system supply through a series resistor.

The ADP3192A is specified over the extended commercial

temperature range of 0°C to 85°C and is available in a

40-lead LFCSP.

¹Protected by U.S. Patent Number 6,683,441; other patents pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADP3192A

TABLE OF CONTENTS

Features .............................................................................................. 1

Power-Good Monitoring........................................................... 14

Output Crowbar ......................................................................... 14

Output Enable and UVLO ........................................................ 14

Thermal Monitoring.................................................................. 14

Application Information................................................................ 19

Setting the Clock Frequency..................................................... 19

Soft Start Delay Time................................................................. 19

Current-Limit Latch-Off Delay Times .................................... 19

Inductor Selection...................................................................... 19

Current Sense Amplifier............................................................ 20

Inductor DCR Temperature Correction ................................. 21

Output Offset.............................................................................. 22

C_OUTSelection ............................................................................. 22

Power MOSFETs......................................................................... 23

Ramp Resistor Selection............................................................ 24

COMP Pin Ramp ....................................................................... 25

Current-Limit Setpoint.............................................................. 25

Feedback Loop Compensation Design.................................... 25

C_INSelection and Input Current di/dt Reduction.................. 27

Thermal Monitor Design .......................................................... 27

Shunt Resistor Design................................................................ 28

Tuning the ADP3192A .............................................................. 28

Layout and Component Placement ......................................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Test Circuits....................................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 10

Start-Up Sequence...................................................................... 10

Phase Detection Sequence......................................................... 10

Master Clock Frequency............................................................ 11

Output Voltage Differential Sensing........................................ 11

Output Current Sensing ............................................................ 11

Active Impedance Control Mode............................................. 11

Current Control Mode and Thermal Balance ........................ 11

Voltage Control Mode................................................................ 12

Current Reference ...................................................................... 12

Fast Enhanced PWM Mode...................................................... 12

Delay Timer................................................................................. 12

Soft Start ...................................................................................... 12

Current-Limit, Short-Circuit, and Latch-Off Protection...... 13

Dynamic VID.............................................................................. 13

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

ADP3192A

SPECIFICATIONS

VCC = 5 V, FBRTN = GND, T_A= 0°C to 85°C, unless otherwise noted.¹

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

REFERENCE CURRENT

Reference Bias Voltage

Reference Bias Current

ERROR AMPLIFIER

Output Voltage Range²

Accuracy

V_IREF

I_IREF

1.5

14.25 15

V

R_IREF= 100 kΩ

15.75 μA

V_COMP

V_FB

0

−7.7

4.4

+7.7

V

mV

Relative to nominal DAC output, referenced

to FBRTN, LLSET = CSREF (see Figure 2)

V_FB(BOOT)

In startup

CSREF − LLSET = 80 mV

1.092 1.1

1.108

−82

+1

16.5

200

V

Load Line Positioning Accuracy

Differential Nonlinearity

Input Bias Current

FBRTN Current

Output Current

−78

−1

−80

mV

LSB

μA

I_FB

I_FB= I_IREF

13.5

15

65

I_FBRTN

I_COMP

GBW_(ERR)

FB forced to V_OUT– 3%

COMP = FB

500

20

25

Gain Bandwidth Product

Slew Rate

MHz

V/μs

LLSET Input Voltage Range

LLSET Input Bias Current

Boot Voltage Hold Time

VID INPUTS

V_LLSET

I_LLSET

t_BOOT

Relative to CSREF

−250

−10

+250 mV

+10

nA

ms

C_DELAY= 10 nF

2

Input Low Voltage

Input High Voltage

Input Current

VID Transition Delay Time²

No CPU Detection Turn-Off Delay Time²

OSCILLATOR

Frequency Range²

Frequency Variation

V_IL(VID)

V_IH(VID)

I_IN(VID)

VID(X), VIDSEL

0.4

V

μA

ns

μs

0.8

−1

VID code change to FB change

VID code change to PWM going low

400

5

f_OSC

f_PHASE

0.25

180

4

220

MHz

kHz

V

T_A= 25°C, R_T= 205 kΩ, 4-phase

T_A= 25°C, R_T= 118 kΩ, 4-phase

T_A= 25°C, R_T= 55 kΩ, 4-phase

R_T= 205 kΩ to GND

200

400

800

2.0

Output Voltage

V_RT

V_RAMPADJ

I_RAMPADJ

1.9

−50

1

2.1

+50

50

RAMPADJ Output Voltage

RAMPADJ Input Current Range

CURRENT SENSE AMPLIFIER

Offset Voltage

Input Bias Current

Gain Bandwidth Product

Slew Rate

Input Common-Mode Range

Output Voltage Range

Output Current

Current Limit Latch-Off Delay Time

IMON Output

RAMPADJ − FB

mV

μA

V_OS(CSA)

I_BIAS(CSSUM)

GBW_(CSA)

CSSUM − CSREF (see Figure 3)

−1.0

−10

+1.0

+10

mV

nA

MHz

V/μs

V

CSSUM = CSCOMP

C_CSCOMP= 10 pF

CSSUM and CSREF

10

0

0.05

3.5

V

I_CSCOMP

t_OC(DELAY)

IMON

500

8

μA

ms

%

C_DELAY= 10 nF

10 × (CSREF − CSCOMP) > 50 mV

−6

+6

CURRENT BALANCE AMPLIFIER

Common-Mode Range

Input Resistance

Input Current

Input Current Matching

V_SW(X)CM

R_SW(X)

I_SW(X)

−600

10

8

+200 mV

SW(X) = 0 V

17

12

26

20

+4

kΩ

μA

%

−4

ΔI_SW(X)

CURRENT-LIMIT COMPARATOR

ILIMIT Bias Current

I_ILIMIT

I_ILIMIT= 2/3 × I_IREF

9

10

11

μA

Rev. 0 | Page 3 of 32

ADP3192A

Parameter

Symbol

Conditions

Min

1.09

3

Typ

Max

Unit

V

mV

mV/V

ILIMIT Voltage

V_ILIMIT

R_ILIMIT= 121 kΩ (V_ILIMIT= (I_ILIMIT× R_ILIMIT))

1.21

1.33

Maximum Output Voltage

Current-Limit Threshold Voltage

Current-Limit Setting Ratio

DELAY TIMER

V_CL

V_CSREF− V_CSCOMP, R_ILIMIT= 121 kΩ

V_CL/V_ILIMIT

80

100

82.6

125

Normal Mode Output Current

Output Current in Current Limit

Threshold Voltage

SOFT START

I_DELAY

I_DELAY(CL)

V_DELAY(TH)

I_DELAY= I_IREF

I_DELAY(CL)= 0.25 × I_IREF

12

3.0

1.6

15

3.75

1.7

18

4.5

1.8

μA

V

Output Current

I_SS

During startup, I_SS= I_IREF

12

15

18

μA

ENABLE INPUT

Threshold Voltage

Hysteresis

Input Current

V_TH(EN)

V_HYS(EN)

I_IN(EN)

800

80

850

100

−1

2

900

125

mV

μA

Delay Time

t_DELAY(EN)

EN > 950 mV, C_DELAY= 10 nF

ms

OD OUTPUT

Output Low Voltage

V_OL(

160

5

500

mV

V

)

OD

Output High Voltage

OD Pull-Down Resistor

V_OH(

4

0

)

OD

60

kΩ

THERMAL THROTTLING CONTROL

TTSENSE Voltage Range

TTSENSE Bias Current

TTSENSE VRFAN Threshold Voltage

TTSENSE VRHOT Threshold Voltage

TTSENSE Hysteresis

VRFAN Output Low Voltage

VRHOT Output Low Voltage

POWER-GOOD COMPARATOR

Undervoltage Threshold

Overvoltage Threshold

Output Low Voltage

Power-Good Delay Time

During Soft Start²

VID Code Changing

VID Code Static

Crowbar Trip Point

Crowbar Reset Point

Crowbar Delay Time

VID Code Changing

VID Code Static

Internally limited

5

V

−133 −123 −113 μA

1.06

765

1.105 1.15

810

50

150

V

855

mV

V_OL(VRFAN)

V_OL(VRHOT)

I_VRFAN(SINK)= −4 mA

I_VRHOT(SINK)= −4 mA

300

V_PWRGD(UV)Relative to nominal DAC output

V_PWRGD(OV)Relative to nominal DAC output

V_OL(PWRGD)

−400 −350 −300 mV

100

150

200

300

mV

I_PWRGD(SINK)= −4 mA

C_DELAY= 10 nF

2

ms

μs

ns

mV

100

250

200

150

375

V_CROWBAR

t_CROWBAR

Relative to nominal DAC output

Relative to FBRTN

Overvoltage to PWM going low

100

320

200

430

100

250

400

μs

ns

PWM OUTPUTS

Output Low Voltage

Output High Voltage

SUPPLY

V_OL(PWM)

V_OH(PWM)

I_PWM(SINK)= −400 μA

I_PWM(SOURCE)= 400 μA

160

5

500

mV

V

4.0

V_SYSTEM= 12 V, R_SHUNT= 340 Ω (see Figure 2)

VCC²

VCC

I_VCC

4.65

5

5.55

25

11

V

DC Supply Current

V_SYSTEM= 13.2 V, R_SHUNT= 340 Ω

mA

V

UVLO Turn-On Current

UVLO Threshold Voltage

UVLO Turn-Off Voltage

6.5

4.1

V_UVLO

VCC rising

VCC falling

9

V

¹All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

²Guaranteed by design or bench characterization, not tested in production.

Rev. 0 | Page 4 of 32

ADP3192A

TEST CIRCUITS

12V

ADP3192A

680Ω

8-BIT CODE

VCC

31

5

+

1µF

100nF

COMP

40

10kΩ

FB

1

1.25V

4

EN

PWM1

PWM2

PWM3

PWM4

NC

SW1

SW2

SW3

SW4

NC

PWRGD

FBRTN

FB

COMP

SS

DELAY

VRFAN

VRHOT

TTSENSE

LLSET

CSREF

GND

–

+

1kΩ

ADP3192A

14

15

18

10nF

ΔV

10nF

VID

DAC

1V

100kΩ

250kΩ

20kΩ

ΔV = FB = 80mV – FB = 0mV

FB ΔV ΔV

NC = NO CONNECT

Figure 4. Positioning Voltage

100nF

Figure 2. Closed-Loop Output Voltage Accuracy

12V

ADP3192A

680Ω

VCC

31

17

CSCOMP

CSSUM

CSREF

GND

100nF

39kΩ

1kΩ

1V

16

15

18

CSCOMP – 1V

V

=

OS

40

Figure 3. Current Sense Amplifier V_OS

Rev. 0 | Page 5 of 32

ADP3192A

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 2.

Parameter

Rating

VCC

FBRTN

−0.3 V to +6 V

−0.3 V to +0.3 V

−0.3 V to VCC + 0.3 V

−5 V to +25 V

−10 V to +25 V

−0.3 V to VCC + 0.3 V

−65°C to +150°C

0°C to 85°C

PWM3 to PWM4, RAMPADJ

SW1 to SW4

<200 ns

All Other Inputs and Outputs

Storage Temperature Range

Operating Ambient Temperature Range

Operating Junction Temperature

Thermal Impedance (θ_JA)

Lead Temperature

Soldering (10 sec)

Absolute maximum ratings apply individually only, not in

combination. Unless otherwise specified, all other voltages

referenced to GND.

125°C

39°C/W

ESD CAUTION

300°C

260°C

Infrared (15 sec)

Rev. 0 | Page 6 of 32

ADP3192A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

EN

PWRGD

FBRTN

FB

COMP

SS

DELAY

VRFAN

VRHOT

1

2

3

4

5

6

7

8

9

30 PWM1

29 PWM2

28 PWM3

27 PWM4

26 NC

25 SW1

24 SW2

23 SW3

22 SW4

21 IMON

INDICATOR

ADP3192A

TOP VIEW

(Not to Scale)

TTSENSE 10

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN

ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND.

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

EN

PWRGD

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.

Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper

operating range.

3

4

FBRTN

FB

Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between

this pin and the output voltage sets the no load offset point.

5

6

COMP

SS

Error Amplifier Output and Compensation Point.

Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start

ramp-up time.

7

DELAY

Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent

latch-off delay time, boot voltage hold time, EN delay time, and PWRGD delay time.

8

VRFAN

VRHOT

TTSENSE

VR Fan Activation Output. Open-drain output that signals when the temperature at the monitoring point

connected to TTSENSE exceeds the programmed VRFAN temperature threshold.

VR Hot Output. Open-drain output that signals when the temperature at the monitoring point connected to

TTSENSE exceeds the programmed VRHOT temperature threshold.

VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely sense

the temperature at the desired thermal monitoring point.

9

10

11

12

ILIMIT

RT

Current-Limit Setpoint. An external resistor from this pin to GND sets the current-limit threshold of the converter.

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device.

13

14

15

RAMPADJ

LLSET

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.

Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected to

the center point of a resistor divider between CSCOMP and CSREF. Connecting LLSET to CSREF disables positioning.

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense

amplifier and the power-good and crowbar functions. This pin should be connected to the common point of

the output inductors.

CSREF

16

17

18

CSSUM

CSCOMP

GND

Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor

currents together to measure the total output current.

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the

current sense amplifier and the positioning loop response time.

Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

Rev. 0 | Page 7 of 32

ADP3192A

Pin No. Mnemonic

Description

19

20

21

OD

Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when VCC is below its

UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.

Current Reference Input. An external resistor from this pin to ground sets the reference current for I_FB, I_DELAY, I_SS,

IREF

I

_ILIMIT, and I_TTSENSE.

IMON

Analog Output. Represents the total load current.

22 to 25 SW4 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases

should be left open.

26 NC

No Connection.

27 to 30 PWM4 to PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3120A. Connecting the PWM4 and PWM3 outputs to VCC causes that phase to turn off, allowing the

ADP3192A to operate as a 2-, 3-, or 4-phase controller.

31

32 to 39 VID7 to VID0

40 VIDSEL

VCC

Supply Voltage for the Device. A 340 Ω resistor should be placed between the 12 V system supply and the VCC

pin. The internal shunt regulator maintains VCC = 5 V.

Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a Logic 0 if left open. When

in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V (see Table 4).

VID DAC Selection Pin. The logic state of this pin determines whether the internal VID DAC decodes VID0 to

VID7 as extended VR10 or VR11 inputs.

Rev. 0 | Page 8 of 32

ADP3192A

TYPICAL PERFORMANCE CHARACTERISTICS

7000

6000

5000

4000

MASTER CLOCK

3000

2000

PHASE 1

IN 4 PHASE DESIGN

1000

0

13

20 30 43 68 75 82 130 180 270 395 430 680 850

RT (kΩ)

Figure 6. Master Clock Frequency vs. RT

Rev. 0 | Page 9 of 32

ADP3192A

THEORY OF OPERATION

The ADP3192A combines a multimode, fixed frequency,

PWM control with multiphase logic outputs for use in 2-, 3-,

and 4-phase synchronous buck CPU core supply power

converters. The internal VID DAC is designed to interface

with the Intel 8-bit VRD/VRM 11-compatible CPU and 7-bit

VRD/VRM 10×-compatible CPU. Multiphase operation is

important for producing the high currents and low voltages

demanded by today’s microprocessors. Handling the high

currents in a single-phase converter places high thermal

demands on the components in the system, such as the

inductors and MOSFETs.

5V

UVLO

THRESHOLD

SUPPLY

VTT I/O

(ADP3192A EN)

0.85V

V

DELAY(TH)

(1.7V)

DELAY

V

BOOT

V

VID

(1.1V)

1V

SS

TD3

V

BOOT

The multimode control of the ADP3192A ensures a stable,

high performance topology for the following:

(1.1V)

TD1

VCC_CORE

TD4

TD2

•

Balancing currents and thermals between phases

High speed response at the lowest possible switching

frequency and output decoupling

VR READY

(ADP3192A PWRGD)

TD5

50µs

•

Minimizing thermal switching losses by using lower

frequency operation

Tight load line regulation and accuracy

High current output due to 4-phase operation

Reduced output ripple due to multiphase cancellation

PC board layout noise immunity

Ease of use and design due to independent component

selection

Flexibility in operation for tailoring design to low cost or

high performance

CPU

VID INVALID

VID VALID

VID INPUTS

Figure 7. System Start-Up Sequence

•

PHASE DETECTION SEQUENCE

During startup, the number of operational phases and their

phase relationship is determined by the internal circuitry that

monitors the PWM outputs. Normally, the ADP3192A operates

as a 4-phase PWM controller. Connecting the PWM4 pin to

VCC programs 3-phase operation and connecting the PWM4

and PWM3 pins to VCC programs 2-phase operation.

•

Prior to soft start, while EN is low, the PWM3 and PWM4 pins

sink approximately 100 μA. An internal comparator checks each

pin’s voltage vs. a threshold of 3 V. If the pin is tied to VCC, it is

above the threshold. Otherwise, an internal current sink pulls

the pin to GND, which is below the threshold. PWM1 and

PWM2 are low during the phase detection interval that occurs

during the first four clock cycles of TD2. After this time, if the

remaining PWM outputs are not pulled to VCC, the 100 μA

current sink is removed, and they function as normal PWM

outputs. If they are pulled to VCC, the 100 μA current source is

removed, and the outputs are put into a high impedance state.

START-UP SEQUENCE

The ADP3192A follows the VR11 start-up sequence shown in

Figure 7. After both the EN and UVLO conditions are met,

the DELAY pin goes through one cycle (TD1). The first four

clock cycles of TD2 are blanked from the PWM outputs and

used for phase detection as explained in the Phase Detection

Sequence section. Then, the soft start ramp is enabled (TD2),

and the output comes up to the boot voltage of 1.1 V. The boot

hold time is determined by the DELAY pin as it goes through a

second cycle (TD3). During TD3, the processor VID pins settle

to the required VID code. When TD3 is over, the ADP3192A

soft starts either up or down to the final VID voltage (TD4).

After TD4 is complete and the PWRGD masking time (equal to

VID on-the-fly masking) is complete, a third ramp on the

DELAY pin sets the PWRGD blanking (TD5).

The PWM outputs are logic-level devices intended for driving

external gate drivers such as the ADP3120A. Because each

phase is monitored independently, operation approaching 100%

duty cycle is possible. In addition, more than one output can be

on at the same time to allow overlapping phases.

Rev. 0 | Page 10 of 32

ADP3192A

An additional resistor divider connected between CSREF and

CSCOMP (with the midpoint connected to LLSET) can be used

to set the load line required by the microprocessor. The current

information is then given as CSREF − LLSET. This difference

signal is used internally to offset the VID DAC for voltage

positioning. The difference between CSREF and CSCOMP is

then used as a differential input for the current-limit comparator.

This allows the load line to be set independently of the current-

limit threshold. In the event that the current-limit threshold

and load line are not independent, the resistor divider between

CSREF and CSCOMP can be removed, and the CSCOMP pin

can be directly connected to LLSET. To disable voltage position-

ing entirely (that is, no load line), connect LLSET to CSREF.

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3192A is set with an external

resistor connected from the RT pin to GND. The frequency

follows the graph in Figure 6. To determine the frequency per

phase, the clock is divided by the number of phases in use. If all

phases are in use, divide by 4. If PWM4 is tied to VCC, divide

the master clock by 3 for the frequency of the remaining phases.

If PWM3 and PWM4 are tied to VCC, divide by 2.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3192A combines differential sensing with a high

accuracy VID DAC and reference, and a low offset error ampli-

fier. This maintains a worst-case specification of 7.7 mV

differential sensing error over its full operating output voltage

and temperature range. The output voltage is sensed between

the FB pin and FBRTN pin. FB should be connected through

a resistor to the regulation point, usually the remote sense pin

of the microprocessor. FBRTN should be connected directly

to the remote sense ground point. The internal VID DAC

and precision reference are referenced to FBRTN, which has a

minimal current of 65 μA to allow accurate remote sensing. The

internal error amplifier compares the output of the DAC to the

FB pin to regulate the output voltage.

To provide the best accuracy for sensing current, the CSA is

designed to have a low offset input voltage. Also, the sensing gain

is determined by external resistors to make it extremely accurate.

ACTIVE IMPEDANCE CONTROL MODE

For controlling the dynamic output voltage droop as a function

of output current, a signal proportional to the total output current

at the LLSET pin can be scaled to equal the regulator droop

impedance multiplied by the output current. This droop voltage

is then used to set the input control voltage to the system. The

droop voltage is subtracted from the DAC reference input

voltage to tell the error amplifier where the output voltage

should be. This allows enhanced feed-forward response.

OUTPUT CURRENT SENSING

The ADP3192A provides a dedicated current-sense amplifier

(CSA) to monitor the total output current for proper voltage

positioning vs. load current and for current-limit detection.

Sensing the load current at the output gives the total average

current being delivered to the load. This is an inherently more

accurate method than peak current detection or sampling the

current across a sense element such as the low-side MOSFET.

This amplifier can be configured several ways, depending on

the objectives of the system, as follows:

CURRENT CONTROL MODE AND THERMAL

BALANCE

The ADP3192A has individual inputs (SW1 to SW4) for each

phase that are used for monitoring the current of each phase.

This information is combined with an internal ramp to create

a current balancing feedback system that has been optimized for

initial current balance accuracy and dynamic thermal balancing

during operation. This current balance information is independent

of the average output current information used for positioning

as described in the Output Current Sensing section.

•

Output inductor DCR sensing without a thermistor for

lowest cost

Output inductor DCR sensing with a thermistor for

improved accuracy with tracking of inductor temperature

Sense resistors for highest accuracy measurements

The magnitude of the internal ramp can be set to optimize the

transient response of the system. It also monitors the supply

voltage for feed-forward control for changes in the supply. A

resistor connected from the power input voltage to the RAMPADJ

pin determines the slope of the internal PWM ramp. External

resistors can be placed in series with individual phases to create

an intentional current imbalance if desired, such as when one

phase has better cooling and can support higher currents.

Resistor R_SW1through Resistor R_SW4(see Figure 10) can be used

for adjusting thermal balance in this 4-phase example. It is best

to have the ability to add these resistors during the initial design;

therefore, ensure that placeholders are provided in the layout.

The positive input of the CSA is connected to the CSREF pin,

which is connected to the output voltage. The inputs to the

amplifier are summed together through resistors from the sensing

element, such as the switch node side of the output inductors,

to the inverting input CSSUM. The feedback resistor between

CSCOMP and CSSUM sets the gain of the amplifier and a filter

capacitor is placed in parallel with this resistor. The gain of the

amplifier is programmable by adjusting the feedback resistor.

Rev. 0 | Page 11 of 32

ADP3192A

To increase the current in any given phase, enlarge R_SWfor that

phase (make R_SW= 0 for the hottest phase and do not change it

during balancing). Increasing R_SWto only 500 Ω makes a substan-

tial increase in phase current. Increase each R_SWvalue by small

amounts to achieve balance, starting with the coolest phase first.

FAST ENHANCED PWM MODE

Fast enhanced PWM mode (FEPWM) is intended to improve

the transient response of the ADP3192A to a load setup. In

previous generations of controllers, when a load step-up

occurred, the controller had to wait until the next turn-on of

the PWM signal to respond to the load change. Enhanced

PWM mode allows the controller to immediately respond when

a load step-up occurs. This allows the phases to respond more

quickly when a load increase takes place.

VOLTAGE CONTROL MODE

A high gain, high bandwidth, voltage mode error amplifier is

used for the voltage mode control loop. The control input voltage

to the positive input is set via the VID logic according to the

voltages listed in Table 4.

DELAY TIMER

This voltage is also offset by the droop voltage for active

positioning of the output voltage as a function of current,

commonly known as active voltage positioning. The output

of the amplifier is the COMP pin, which sets the termination

voltage for the internal PWM ramps.

The delay times for the start-up timing sequence are set with a

capacitor from the DELAY pin to GND. In UVLO, or when EN is

logic low, the DELAY pin is held at GND. After the UVLO and

EN signals are asserted, the first delay time (TD1 in Figure 7) is

initiated. A current flows out of the DELAY pin to charge C_DLY

.

This current is equal to IREF, which is typically 15 μA. A compara-

tor monitors the DELAY voltage with a threshold of 1.7 V. The

delay time is therefore set by the IREF current charging a capacitor

from 0 V to 1.7 V. This DELAY pin is used for multiple delay

timings (TD1, TD3, and TD5) during the start-up sequence. In

addition, DELAY is used for timing the current-limit latch off,

as explained in the Current-Limit, Short-Circuit, and Latch-Off

Protection section.

The negative input (FB) is tied to the output sense location with

Resistor R_Band is used for sensing and controlling the output

voltage at this point. A current source (equal to IREF) from the

FB pin flowing through R_Bis used for setting the no load offset

voltage from the VID voltage. The no load voltage is negative

with respect to the VID DAC. The main loop compensation is

incorporated into the feedback network between FB and COMP.

CURRENT REFERENCE

SOFT START

The IREF pin is used to set an internal current reference. This

reference current sets I_FB, I_DELAY, I_SS, I_LIMIT, and I_TTSENSE. A resistor

to ground programs the current based on the 1.5 V output.

The soft start times for the output voltage are set with a

capacitor from the SS pin to GND. After TD1 and the phase

detection cycle are complete, the SS time (TD2 in Figure 7)

starts. The SS pin is disconnected from GND, and the capacitor

is charged up to the 1.1 V boot voltage by the SS amplifier,

which has an output current equal to IREF (typically 15 μA).

The voltage at the FB pin follows the ramping voltage on the

SS pin, limiting the inrush current during startup. The soft start

time depends on the value of the boot voltage and C_SS.

1.5 V

IREF =

R_IREF

Typically, R_IREFis set to 100 kΩ to program IREF = 15 μA. The

following currents are then equal to

I_FB= IREF = 15 μA

I_DELAY= IREF = 15 μA

I_SS= IREF = 15 μA

Once the SS voltage is within 100 mV of the boot voltage, the

boot voltage delay time (TD3 in Figure 7) is started. The end of

the boot voltage delay time signals the beginning of the second

soft start time (TD4 in Figure 7). The SS voltage now changes

from the boot voltage to the programmed VID DAC voltage

(either higher or lower) using the SS amplifier with the output

current equal to IREF. The voltage of the FB pin follows the

ramping voltage of the SS pin, limiting the inrush current

during the transition from the boot voltage to the final DAC

voltage. The second soft start time depends on the boot voltage,

the programmed VID DAC voltage, and C_SS.

I_LIMIT= 2/3 (IREF) = 10 μA

Rev. 0 | Page 12 of 32

ADP3192A

If EN is taken low or if VCC drops below UVLO, DELAY and

SS are reset to ground to be ready for another soft start cycle.

Figure 8 shows typical start-up waveforms for the ADP3192A.

The latch-off function can be reset by either removing and

reapplying the supply voltage to the ADP3192A or by toggling

the EN pin low for a short time. To disable the short-circuit

latch-off function, an external resistor should be placed in

parallel with C_DLY. This prevents the DELAY capacitor from

charging up to the 1.7 V threshold. The addition of this resistor

causes a slight increase in the delay times.

1

2

During startup, when the output voltage is below 200 mV,

a secondary current limit is active. This is necessary because

the voltage swing of CSCOMP cannot go below GND. This

secondary current limit controls the internal COMP voltage

to the PWM comparators to 1.5 V. This limits the voltage drop

across the low-side MOSFETs through the current balance

circuitry. An inherent per-phase current limit protects

individual phases if one or more phases stop functioning

because of a faulty component. This limit is based on the

maximum normal mode COMP voltage. Typical overcurrent

latch-off waveforms are shown in Figure 9.

3

4

CH1 1V

CH3 1V

CH2 1V

CH4 10V

M

T

1ms

40.4%

A

CH1

700mV

Figure 8. Typical Start-Up Waveforms

(Channel 1: CSREF, Channel 2: DELAY,

Channel 3: SS, Channel 4: Phase 1 Switch Node)

CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-

OFF PROTECTION

1

2

The ADP3192A compares a programmable current-limit

setpoint to the voltage from the output of the current-sense

amplifier. The level of current limit is set with the resistor

from the ILIMIT pin to GND. During operation, the current

from ILIMIT is equal to 2/3 of IREF, giving 10 μA typically.

This current through the external resistor sets the ILIMIT

voltage, which is internally scaled to give a current-limit

threshold of 82.6 mV/V. If the difference in voltage between

CSREF and CSCOMP rises above the current-limit threshold,

the internal current-limit amplifier controls the internal COMP

voltage to maintain the average output current at the limit.

3

4

CH1 1V

CH3 2V

CH2 1V

CH4 10V

M 2ms

T 61.8%

A CH1

680mV

Figure 9. Overcurrent Latch-Off Waveforms

(Channel 1: CSREF, Channel 2: DELAY,

Channel 3: COMP, Channel 4: Phase 1 Switch Node)

If the limit is reached and TD5 in Figure 7 is complete, a latch-

off delay time starts, and the controller shuts down if the fault is

not removed. The current-limit delay time shares the

DELAY pin timing capacitor with the start-up sequence timing.

However, during current limit, the DELAY pin current is

reduced to IREF/4. A comparator monitors the DELAY voltage

and shuts off the controller when the voltage reaches 1.7 V.

Therefore, the current-limit latch-off delay time is set by the

current of IREF/4 charging the delay capacitor from 0 V to 1.7 V.

This delay is four times longer than the delay time during the

start-up sequence.

DYNAMIC VID

The ADP3192A has the ability to dynamically change the VID

inputs while the controller is running. This allows the output

voltage to change while the supply is running and supplying

current to the load, which is commonly referred to as VID on-

the-fly (OTF). A VID OTF can occur under light or heavy load

conditions. The processor signals the controller by changing the

VID inputs in multiple steps from the start code to the finish

code. This change can be positive or negative.

The current-limit delay time starts only after the TD5 is

complete. If there is a current limit during startup, the

ADP3192A goes through TD1 to TD5, and then starts the

latch-off time. Because the controller continues to cycle the

phases during the latch-off delay time, the controller returns to

normal operation and the DELAY capacitor is reset to GND if

the short is removed before the 1.7 V threshold is reached.

When a VID input changes state, the ADP3192A detects the

change and ignores the DAC inputs for a minimum of 400 ns.

This time prevents a false code due to logic skew while the eight

VID inputs are changing. Additionally, the first VID change

initiates the PWRGD and crowbar blanking functions for a

minimum of 100 μs to prevent a false PWRGD or crowbar

event. Each VID change resets the internal timer.

Rev. 0 | Page 13 of 32

ADP3192A

POWER-GOOD MONITORING

OUTPUT ENABLE AND UVLO

The power-good comparator monitors the output voltage via

the CSREF pin. The PWRGD pin is an open-drain output whose

high level, when connected to a pull-up resistor, indicates that

the output voltage is within the specified nominal limits based

on the VID voltage setting. PWRGD goes low if the output

voltage is outside of this specified range, if the VID DAC inputs

are in no CPU mode, or if the EN pin is pulled low. PWRGD is

blanked during a VID OTF event for a period of 200 μs to

prevent false signals during the time the output is changing.

For the ADP3192A to begin switching, the input supply (VCC)

to the controller must be higher than the UVLO threshold and

the EN pin must be higher than its 0.85 V threshold. This

initiates a system start-up sequence. If either UVLO or EN is

less than their respective thresholds, the ADP3192A is disabled.

This holds the PWM outputs at ground, shorts the DELAY

OD

capacitor to ground, and forces PWRGD and

signals low.

OD

In the application circuit (see Figure 10), the

pin should be

OD

connected to the

inputs of the ADP3120A drivers.

The PWRGD circuitry also incorporates an initial turn-on

delay time (TD5) based on the DELAY timer. Prior to the

SS voltage reaching the programmed VID DAC voltage and the

PWRGD masking-time finishing, the PWRGD pin is held low.

Once the SS pin is within 100 mV of the programmed DAC

voltage, the capacitor on the DELAY pin begins to charge.

A comparator monitors the DELAY voltage and enables

PWRGD when the voltage reaches 1.7 V. The PWRGD delay

time is set, therefore, by a current of IREF, charging a capacitor

from 0 V to 1.7 V.

OD

Grounding

disables the drivers such that both DRVH and

DRVL are grounded. This feature is important in preventing the

discharge of the output capacitors when the controller is shut

off. If the driver outputs are not disabled, a negative voltage can

be generated during output due to the high current discharge of

the output capacitors through the inductors.

THERMAL MONITORING

The ADP3192A includes a thermal monitoring circuit to detect

when a point on the VR has exceeded two different user-defined

temperatures. The thermal monitoring circuit requires an NTC

thermistor to be placed between TTSENSE and GND.

OUTPUT CROWBAR

To protect the load and output components of the supply, the

PWM outputs are driven low, which turns on the low-side

MOSFETs when the output voltage exceeds the upper crowbar

threshold. This crowbar action stops once the output voltage

falls below the release threshold of approximately 375 mV.

A fixed current of 8 × IREF (typically giving 123 μA) is sourced

out of the TTSENSE pin and into the thermistor. The current

source is internally limited to 5 V. An internal circuit compares

the TTSENSE voltage to a 1.105 V and a 0.81 V threshold, and

outputs an open-drain signal at the VRFAN and VRHOT

outputs, respectively. Once the voltage on the TTSENSE pin

drops below its respective threshold, the open-drain outputs

assert high to signal the system that an overtemperature event

has occurred. Because the TTSENSE voltage changes slowly

with respect to time, 50 mV of hysteresis is built into these com-

parators. The thermal monitoring circuitry does not depend on

EN and is active when UVLO is above its threshold. When UVLO

is below its threshold, VRFAN and VRHOT are forced low.

Turning on the low-side MOSFETs pulls down the output as

the reverse current builds up in the inductors. If the output

overvoltage is due to a short in the high-side MOSFET, this

action current limits the input supply or blows its fuse,

protecting the microprocessor from being destroyed.

Table 4.VR11 and VR10.x VID Codes for the ADP3192A

VR11 DAC CODES: VIDSEL = HIGH

VR10.x DAC CODES: VIDSEL = LOW

OUTPUT

OFF

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

N/A

1

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Rev. 0 | Page 14 of 32

ADP3192A

VR11 DAC CODES: VIDSEL = HIGH

VR10.x DAC CODES: VIDSEL = LOW

OUTPUT

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Rev. 0 | Page 15 of 32

ADP3192A

VR11 DAC CODES: VIDSEL = HIGH

VR10.x DAC CODES: VIDSEL = LOW

OUTPUT

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

OFF

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

N/A

OFF

N/A

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

0.81250

0.80625

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

N/A

Rev. 0 | Page 16 of 32

ADP3192A

VR11 DAC CODES: VIDSEL = HIGH

VR10.x DAC CODES: VIDSEL = LOW

OUTPUT

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

OFF

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

N/A

1

0

1

OFF

Rev. 0 | Page 17 of 32

ADP3192A

0 0 9 6 - 7 8 0 6

V C C

D 7 V I

F E I R

O D

D 6 V I

D 5 V I

D 4 V I

D 3 V I

D 2 V I

D 1 V I

D 0 V I

D

G N

P M

C S C O

C S S U M

C S R E F

E T L L S

A P D J R A M

R T

D S V E I L

I T M I I L

Figure 10. Typical 4-Phase Application Circuit

Rev. 0 | Page 18 of 32

ADP3192A

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 11-compliant

CPU application are as follows:

CURRENT-LIMIT LATCH-OFF DELAY TIMES

The start-up and current-limit delay times are determined by

the capacitor connected to the DELAY pin. The first step is to

set C_DLYfor the TD1, TD3, and TD5 delay times (see Figure 7).

The DELAY ramp (I_DELAY)is generated using a 15 μA internal

current source. The value for C_DLYcan be approximated using

•

Input voltage (V_IN) = 12 V

VID setting voltage (V_VID) = 1.300 V

Duty cycle (D) = 0.108

Nominal output voltage at no load (V_ONL) = 1.285 V

Nominal output voltage at 115 A load (V_OFL) = 1.170 V

Static output voltage drop based on a 1.0 mΩ load line (R_O)

TD(x)

V_DELAY(TH)

C_DLY= I_DELAY

×

(3)

from no load to full load (V_D) = V_ONL− V_OFL

1.285 V − 1.170 V = 115 mV

=

where:

TD(x) is the desired delay time for TD1, TD3, and TD5.

V_DELAY(TH), the DELAY threshold voltage, is given as 1.7 V.

•

Maximum output current (I_O) = 130 A

Maximum output current step (ΔI_O) = 100 A

Maximum output current slew rate (S_R) = 200 A/μs

Number of phases (n) = 4

In this example, 2 ms is chosen for all three delay times, which

meets Intel specifications. Solving for C_DLYgives a value of

17.6 nF. The closest standard value for C_DLYis 18 nF.

Switching frequency per phase (f_SW) = 330 kHz

When the ADP3192A enters current limit, the internal current

source changes from 15 μA to 3.75 μA. This makes the latch-off

delay time four times longer than the start-up delay time.

Longer latch-off delay times can be achieved by placing a

SETTING THE CLOCK FREQUENCY

The ADP3192A uses a fixed frequency control architecture. The

frequency is set by an external timing resistor (R_T). The clock

frequency and the number of phases determine the switching

frequency per phase, which relates directly to switching losses

as well as the sizes of the inductors, the input capacitors, and

output capacitors. With n = 4 for four phases, a clock frequency

of 1.32 MHz sets the switching frequency (f_SW) of each phase to

330 kHz, which represents a practical trade-off between the

switching losses and the sizes of the output filter components.

Figure 6 shows that to achieve a 1.32 MHz oscillator frequency,

the correct value for R_Tis 130 kΩ. Alternatively, the value for R_T

can be calculated using

resistor in parallel with C_DLY

.

INDUCTOR SELECTION

The choice of inductance for the inductor determines the ripple

current in the inductor. Less inductance leads to more ripple

current, which increases the output ripple voltage and conduction

losses in the MOSFETs. However, using smaller inductors

allows the converter to meet a specified peak-to-peak transient

deviation with less total output capacitance. Conversely, a higher

inductance means lower ripple current and reduced conduction

losses, but more output capacitance is required to meet the

same peak-to-peak transient deviation.

1

(1)

R_T

=

n × f_SW× 6 pF

In any multiphase converter, a practical value for the peak-to-

peak inductor ripple current is less than 50% of the maximum

dc current in the same inductor. Equation 4 shows the

relationship between the inductance, oscillator frequency, and

peak-to-peak ripple current in the inductor.

where 6 pF is the internal IC component values. For good initial

accuracy and frequency stability, a 1% resistor is recommended.

SOFT START DELAY TIME

The value of C_SSsets the soft start time. The ramp is generated

with a 15 μA internal current source. The value for C_SScan be

found using

V_VID

×

(

1− D

)

(4)

I_R

=

f_SW× L

TD2

V_BOOT

(2)

C_SS=15μA×

Equation 5 can be used to determine the minimum inductance

based on a given output ripple voltage.

where:

V_VID× R_O

×

(

1−

f_SW×V_RIPPLE

Solving Equation 5 for an 8 mV p-p output ripple voltage yields

1.3 V ×1.0 mꢀ × 1−0.432

(n×D)

)

(5)

L ≥

TD2 is the desired soft start time.

V_BOOTis internally set to 1.1 V.

Assuming a desired TD2 time of 3 ms, C_SSis 41 nF. The closest

standard value for C_SSis 39 nF. Although C_SSalso controls the

time delay for TD4 (determined by the final VID voltage), the

minimum specification for TD4 is 0 ns. This means that as long as

the TD2 time requirement is met, TD4 is within the specification.

(

)

L ≥

= 280 nH

330 kHz × 8 mV

Rev. 0 | Page 19 of 32

ADP3192A

If the resulting ripple voltage is less than what is designed for,

the inductor can be made smaller until the ripple value is met.

This allows optimal transient response and minimum output

decoupling.

Selecting a Standard Inductor

The following power inductor manufacturers can provide design

consultation and deliver power inductors optimized for high

power applications upon request:

The smallest possible inductor should be used to minimize

the number of output capacitors. For this example, choosing a

320 nH inductor is a good starting point and gives a calculated

ripple current of 11 A. The inductor should not saturate at the

peak current of 35.5 A and should be able to handle the sum of

the power dissipation caused by the average current of 30 A in

the winding and core loss.

•

Coilcraft®

Coiltronics®

Sumida Corporation®

CURRENT SENSE AMPLIFIER

Most designs require the regulator output voltage, measured at

the CPU pins, to drop when the output current increases. The

specified voltage drop corresponds to a dc output resistance (R_O),

also referred to as a load line. The ADP3192A has the flexibility

of adjusting R_O, independent of current-limit or compensation

components, and it can also support CPUs that do not require

a load line.

Another important factor in the inductor design is the dc

resistance (DCR), which is used for measuring the phase currents.

A large DCR can cause excessive power loss, though too small a

value can lead to increased measurement error. A good rule is

to have the DCR (R_L) be about 1 to 1½ times the droop resistance

(R_O). This example uses an inductor with a DCR of 1.4 mΩ.

For designs requiring a load line, the impedance gain of the

CS amplifier (R_CSA) must be to be greater than or equal to the load

line. All designs, whether they have a load line or not, should

keep R_CSA≥ 1 mΩ.

Designing an Inductor

Once the inductance and DCR are known, the next step is to

either design an inductor or find a standard inductor that comes

as close as possible to meeting the overall design goals. It is also

important to have the inductance and DCR tolerance specified

to control the accuracy of the system. Reasonable tolerances

most manufacturers can meet are 15% inductance and 7% DCR

at room temperature. The first decision in designing the inductor

is choosing the core material. Several possibilities for providing

low core loss at high frequencies include the powder cores (from

Micrometals, Inc., for example, or Kool Mu® from MAGNETICS®)

and the gapped soft ferrite cores (for example, 3F3 or 3F4 from

Philips®). Low frequency powdered iron cores should be avoided

due to their high core loss, especially when the inductor value is

relatively low, and the ripple current is high.

The output current is measured by summing the voltage across

each inductor and passing the signal through a low-pass filter.

This summer filter is the CS amplifier configured with resistors

R

_PH(X)(summers), and R_CSand C_CS(filter). The impedance gain

of the regulator is set by the following equations, where R_Lis the

DCR of the output inductors:

R_CS

R_PH

R_CSA

=

× R_L

(6)

(7)

(X )

L

C_CS

=

R_L× R_CS

The user has the flexibility to choose either R_CSor R_PH(X). However,

it is best to select R_CSequal to 100 kΩ, and then solve for R_PH(X)

by rearranging Equation 6. Here, R_CSA= R_O= 1 mΩ because this

is equal to the design load line.

The best choice for a core geometry is a closed-loop type, such

as a potentiometer core (PQ, U, or E core) or toroid. A good

compromise between price and performance is a core with

a toroidal shape.

R_L

R_CSA

R_PH

=

× R_CS

Many useful magnetics design references are available for

quickly designing a power inductor, such as

(

X

)

•

Intusoft Magnetics Designer Software

1.4 mꢀ

1.0 mꢀ

R_PH

=

×100 kꢀ =140 kꢀ

(

X

)

Designing Magnetic Components for High Frequency dc-dc

Converters, by Colonel Wm. T. McLyman,

Kg Magnetics, Inc., ISBN 1883107008

Next, use Equation 7 to solve for C_CS.

320 nH

C_CS

=

= 2.28 nF

1.4 mꢀ ×100 kꢀ

Rev. 0 | Page 20 of 32

ADP3192A

It is best to have a dual location for C_CSin the layout so that

standard values can be used in parallel to get as close to the

desired value. For best accuracy, C_CSshould be a 5% or 10%

NPO capacitor. This example uses a 5% combination for C_CS

of two 1 nF capacitors in parallel. Recalculating R_CSand R_PH(X)

using this capacitor combination yields 114 kΩ and 160 kΩ,

respectively. The closest standard 1% value for R_PH(X)is 158 kΩ.

4. Compute the relative values for R_CS1, R_CS2, and R_THusing

(

A − B

)

× r₁× r₂− A ×

A × 1− B × r₁− B ×

1− A

(

1− B

)

× r₂+ B ×

× r₂−

(

1− A

)

× r₁

)

r_CS2

=

(8)

(9)

(

)

(

1− A

)

(

A − B

(

)

r_CS1

1

A

−

1−r_CS2r₁−r_CS2

INDUCTOR DCR TEMPERATURE CORRECTION

1

r_TH

=

(10)

1

When the inductor DCR is used as the sense element and copper

wire is used as the source of the DCR, the user needs to compen-

sate for temperature changes of the inductor’s winding. Fortunately,

copper has a well-known temperature coefficient (TC) of 0.39%/°C.

−

1−r_CS2r_CS1

5. Calculate R_TH= r_TH× R_CS, then select the closest value of

thermistor available. Also, compute a scaling factor (k)

based on the ratio of the actual thermistor value used

relative to the computed one.

If R_CSis designed to have an opposite and equal percentage

change in resistance to that of the wire, it cancels the temperature

variation of the inductor DCR. Due to the nonlinear nature of

NTC thermistors, Resistor R_CS1and Resistor R_CS2are needed.

Refer to Figure 11 to linearize the NTC and produce the desired

temperature tracking.

R_TH

(

ACTUAL)

k =

(11)

R_TH

(

CALCULATED

)

6. Calculate values for R_CS1and R_CS2using Equation 12 and

Equation 13.

PLACE AS CLOSE AS POSSIBLE

TO NEAREST INDUCTOR

TO

SWITCH

NODES

TO

OR LOW-SIDE MOSFET

VOUT

SENSE

R_CS1= R_CS× k × r_CS1

R_CS2= R_CS1−k

(12)

(13)

R

TH

×

(

)

+

(

k × r_CS2

))

R

PH3

PH1

PH2

ADP3192A

In this example, R_CSis calculated to be 114 kΩ. Look for an

available 100 kΩ thermistor, 0603 size. One such thermistor

is the Vishay NTHS0603N01N1003JR NTC thermistor with

A = 0.3602 and B = 0.09174. From these values, r_CS1= 0.3795,

r_CS2= 0.7195, and r_TH= 1.075.

R

CS2

CS1

CSCOMP

17

C

CS2

KEEP THIS PATH

CS1

AS SHORT AS POSSIBLE

AND WELL AWAY FROM

SWITCH NODE LINES

CSSUM

CSREF

16

Solving for R_THyields 122.55 kΩ, so 100 kΩ is chosen, making

k = 0.816. Next, find R_CS1and R_CS2to be 35.3 kΩ and 87.9 kΩ.

Finally, choose the closest 1% resistor value, which yields a

choice of 35.7 kΩ and 88.7 kΩ.

15

Figure 11. Temperature Compensation Circuit Values

The following procedure and equations yield values to use for R_CS1,

R_CS2, and R_TH(the thermistor value at 25°C) for a given R_CSvalue:

Load Line Setting

For load line values greater than 1 mΩ, R_CSAcan be set equal

to R_O, and the LLSET pin can be directly connected to the

CSCOMP pin. When the load line value needs to be less than

1 mΩ, two additional resistors are required. Figure 12 shows

the placement of these resistors.

1. Select an NTC based on type and value. Because the value

is unknown, use a thermistor with a value close to R_CS. The

NTC should also have an initial tolerance of better than 5%.

2. Based on the type of NTC, find its relative resistance value at

two temperatures. Temperatures that work well are 50°C and

90°C. These resistance values are called A (R_TH(50°C))/R_TH(25°C)

and B (R_TH(90°C))/R_TH(25°C)). The relative value of the NTC is

always 1 at 25°C.

)

ADP3192A

CSCOMP

17

3. Find the relative value of R_CSrequired for each of these

temperatures. This is based on the percentage change

needed, which in this example is initially 0.39%/°C. These

temperatures are called r₁(1/(1 + TC × (T₁− 25°C))) and

r₂(1/(1 + TC × (T₂− 25°C))), where TC = 0.0039 for copper,

T₁= 50°C, and T₂= 90°C. From this, r₁= 0.9112 and

r₂= 0.7978.

CSSUM

16

CSREF

15

R

LL2

LL1

OPTIONAL LOAD LINE

SELECT SWITCH

LLSET

14

Q

LL

Figure 12. Load Line Setting Resistors

Rev. 0 | Page 21 of 32

ADP3192A

The two resistors R_LL1and R_LL2set up a divider between the

CSCOMP pin and CSREF pin. This resistor divider is input into

the LLSET pin to set the load line slope R_Oof the VR according

to the following equation:

OUTPUT OFFSET

The Intel specification requires that at no load, the nominal output

voltage of the regulator be offset to a value lower than the nominal

voltage corresponding to the VID code. The offset is set by a

constant current source flowing out of the FB pin (I_FB) and flowing

through R_B. The value of R_Bcan be found using Equation 19.

R_LL2

R_O

=

×R_CSA

(14)

R

_LL1+ R_LL2

The resistor values for R_LL1and R_LL2are limited by two factors.

V_VID−V_ONL

R_B

=

I_FB

•

The minimum value is based upon the loading of the

CSCOMP pin. This pin’s drive capability is 500 ꢁA, and the

majority of this should be allocated to the CSA feedback. If

the current through R_LL1and R_LL2is limited to 10% of this

drive capability (50 ꢁA), the following limit can be placed

1.3 V−1.285 V

=1.00 kꢀ

(19)

15 ꢁA

The closest standard 1% resistor value is 1.00 kΩ.

on the minimum value for R_LL1and R_LL2

:

C_OUTSELECTION

I

_LIM×R_CSA

50×10⁻⁶

The required output decoupling for the regulator is typically

recommended by Intel for various processors and platforms.

R

_LL1+ R_LL2

≥

(15)

Use some simple design guidelines to determine the require-

ments. These guidelines are based on having both bulk

capacitors and ceramic capacitors in the system.

Here, I_LIMis the current-limit current, which is the

maximum signal level that the CSA responds to.

•

The maximum value is based upon minimizing induced

dc offset errors based on the bias current of the LLSET pin.

To keep the induced dc error less than 1 mV, which makes

this error statistically negligible, place the following limit

First, select the total amount of ceramic capacitance. This is

based on the number and type of capacitor to be used. The best

location for ceramic capacitors is inside the socket with 12 to 18,

1206 size being the physical limit. Other capacitors can be

placed along the outer edge of the socket as well.

on the parallel combination of R_LL1and R_LL2

:

R

_LL1× R_LL2

1×10⁻³

To determine the minimum amount of ceramic capacitance

required, start with a worst-case load step occurring right after

a switching cycle stops. The ceramic capacitance then delivers

the charge to the load while the load is ramping up and until the

VR has responded with the next switching cycle.

= 8.33 kΩ

(16)

≤

_LL1+ R_LL2120 ×10⁻⁹

Select minimum value resistors to reduce the noise and parasitic

susceptibility of the feedback path.

By combining Equation 16 with Equation 14 and selecting

minimum values for the resistors, the following equations result:

Equation 20 gives the designer a rough approximation for

determining the minimum ceramic capacitance. Due to the

complexity of the PCB parasitics and bulk capacitors, the actual

amount of ceramic capacitance required can vary.

I_LIM× R_O

50μA

(17)

R_LL2

=

⎡

⎤

Δ I_O

2 S_R

⎛

⎜

⎝

⎞

R_CSA

R_O

1

⎛

⎜

⎞

⎠

(20)

⎟

C_Z

≥

×

− D −

R_LL1

=

−1 ×R_LL2

(18)

⎟

(

MIN

)

⎢

⎣

⎥

⎦

⎟

R_O

f_SW

n

⎝

⎠

The typical ceramic capacitors consist of multiple 10 μF or 22 μF

capacitors. For this example, Equation 20 yields 180.8 μF, therefore,

18, 10 ꢁF ceramic capacitors suffice.

Therefore, both R_LL1and R_LL2need to be in parallel and less than

8.33 kꢀ.

Another useful feature for some VR applications is the ability to

select different load lines. Figure 12 shows an optional MOSFET

switch that allows this feature. Here, design for R_CSA= R_O(MAX)

(selected with Q_LLon), and then use Equation 14 to set R_O= R_O(MIN)

(selected with Q_LLoff).

Next, an upper limit is imposed on the total amount of bulk

capacitance (C_X) when the user considers the VID on-the-fly

voltage stepping of the output (voltage step V_Vin time t_Vwith

error of V_ERR).

A lower limit is based on meeting the capacitance for load

release for a given maximum load step (ꢂI_O) and a maximum

allowable overshoot. The total amount of load release voltage

is given as ΔV_O= ΔI_O× R_O+ ΔV_rl, where ΔV_rlis the maximum

allowable overshoot voltage.

For this design, R_CSA= R_O= 1 mΩ. As a result, connect LLSET

directly to CSCOMP; the R_LL1and R_LL2resistors are not needed.

Rev. 0 | Page 22 of 32

ADP3192A

This is tested using

L_X≤ C_Z× R_O²× Q²

⎛

⎜

⎞

⎟

⎜

⎟

L × ꢂI_O

ΔV_rl

C_X

≥

−C_Z

(21)

(

MIN )

(23)

4

3

⎛

⎞

⎟

⎠

2

L_X≤ 180 ꢁF ×

(

1 mꢀ

)

×

= 240 pH

⎜

n × R_O+

×V_VID

⎜

⎝

⎟

⎠

ΔI_O

⎝

where Q²is limited to 4/3 to ensure a critically damped system.

≤

×

MAX

)

In this example, L_Xis approximately 240 pH for the 10, Al-Poly

capacitors, which satisfies this limitation. If the L_Xof the chosen

bulk capacitor bank is too large, the number of ceramic capacitors

needs to be increased, or lower ESL bulks need to be used if

there is excessive undershoot during a load transient.

2

⎛

⎞

⎛

⎞

⎟

⎠

V_V

V_VIDnKR_O

L

⎜

⎟

⎜

×

1+ t_V

×

− 1 −C_Z(22)

nK ²R_O²V_VID

V_V

L

⎜

⎝

⎟

⎜

⎝

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

V_ERR

V_V

where K = −1n

.

For this multimode control technique, all ceramic designs can

be used providing the conditions of Equation 20 through

Equation 23 are satisfied.

To meet the conditions of these equations and transient response,

the ESR of the bulk capacitor bank (R_X) should be less than two

times the droop resistance (R_O). If the C_X(MIN)is larger than

POWER MOSFETS

For this example, the N-channel power MOSFETs have been

selected for one high-side switch and two low-side switches per

phase. The main selection parameters for the power MOSFETs

are V_GS(TH), Q_G, C_ISS, C_RSS, and R_DS(ON). The minimum gate drive

voltage (the supply voltage to the ADP3120A) dictates whether

standard threshold or logic-level threshold MOSFETs must be

used. With V_GATE~10 V, logic-level threshold MOSFETs

(V_GS(TH)< 2.5 V) are recommended.

C

_X(MAX), the system cannot meet the VID on-the-fly specification

and may require the use of a smaller inductor or more phases

(and may have to increase the switching frequency to keep the

output ripple the same).

This example uses 18, 10 μF 1206 MLC capacitors (C_Z= 180 μF).

The VID on-the-fly step change is 450 mV in 230 μs with a

settling error of 2.5 mV. The maximum allowable load release

overshoot for this example is 50 mV. Therefore, solving for the

bulk capacitance yields the following:

The maximum output current (I_O) determines the R_DS(ON)

requirement for the low-side (synchronous) MOSFETs. With

the ADP3192A, currents are balanced between phases, thus, the

current in each low-side MOSFET is the output current divided

by the total number of MOSFETs (n_SF). With conduction losses

being dominant, Equation 24 shows the total power that is

dissipated in each synchronous MOSFET in terms of the ripple

current per phase (I_R) and average total output current (I_O).

C_X

≤

MIN )

(

⎛

⎜

⎞

⎟

⎜

⎟

320 nH ×100 A

⎟

−180 ꢁF = 3.92 mF

⎛

⎜

⎝

⎞

⎟

50 mV

100 A

⎜

⎟

⎠

4 × 1.0 mꢀ +

×1.3 V

⎜

⎝

⎟

⎠

2

⎡

⎢

⎤

⎥

n I

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

I_O

n_SF

1

12

R

P_SF

=

(

1− D

)

×

+

×

×R_DS

(24)

(

SF

)

320 nH × 450 mV

n_SF

⎢

⎣

⎥

⎦

C_X

≤

MAX

)

×

(

4 × 5.2²×

(

1.0 mꢀ

)

×1.3 V

2

Knowing the maximum output current being designed for and

the maximum allowed power dissipation, the user can find the

required R_DS(ON)for the MOSFET. For D-PAK MOSFETs up to

an ambient temperature of 50°C, a safe limit for P_SFis 1 W to 1.5 W

at a 120°C junction temperature. Therefore, for this example

(119 A maximum), R_DS(SF)(per MOSFET) < 7.5 mΩ. This R_DS(SF)

is also at a junction temperature of about 120°C. As a result,

users need to account for this when making this selection. This

example uses two lower-side MOSFETs at 4.8 mΩ, each at 120°C.

2

⎛

⎜

⎞

⎟

⎛

⎞

⎟

⎠

230 ꢁs ×1.3 V × 4 × 5.2 ×1.0 mꢀ

450 mV × 320 nH

⎜

⎝

1+

−1 −180 ꢁF

⎜

⎟

⎜

⎟

⎠

⎝

= 43.0 mF

where K = 5.2.

Using 10, 560 μF Al-Poly capacitors with a typical ESR of 6 mΩ

each yields C_X= 5.6 mF with an R_X= 0.6 mΩ.

One last check should be made to ensure that the ESL of the

bulk capacitors (L_X) is low enough to limit the high frequency

ringing during a load change.

Another important factor for the synchronous MOSFET is the

input capacitance and feedback capacitance. The ratio of the

feedback to input needs to be small (less than 10% is recom-

mended) to prevent accidental turn-on of the synchronous

MOSFETs when the switch node goes high.

Rev. 0 | Page 23 of 32

ADP3192A

Also, the time to switch the synchronous MOSFETs off should

not exceed the nonoverlap dead time of the MOSFET driver

(40 ns typical for the ADP3120A). The output impedance of

the driver is approximately 2 Ω, and the typical MOSFET input

gate resistances are about 1 Ω to 2 Ω. Therefore, a total gate

capacitance of less than 6000 pF should be adhered to. Because

two MOSFETs are in parallel, the input capacitance for each

synchronous MOSFET should be limited to 3000 pF.

Finally, consider the power dissipation in the driver for each

phase. This is best expressed as Q_Gfor the MOSFETs and is

given by Equation 27.

⎡

⎢

⎤

f_SW

2 ×n

P_DRV

=

×

(

n_MF×Q_GMF+ n_SF×Q_GSF

)

+ I_CC×V (27)

⎥

CC

⎢

⎣

⎥

⎦

where:

Q_GMFis the total gate charge for each main MOSFET.

The high-side (main) MOSFET has to be able to handle two main

power dissipation components: conduction and switching losses.

The switching loss is related to the amount of time it takes for

the main MOSFET to turn on and off, and to the current and

voltage that are being switched. Basing the switching speed on

the rise and fall time of the gate driver impedance and MOSFET

input capacitance, Equation 25 provides an approximate value

for the switching loss per main MOSFET.

Q

_GSFis the total gate charge for each synchronous MOSFET.

Also shown is the standby dissipation factor (I_CC× V_CC) of the

driver. For the ADP3120A, the maximum dissipation should be

less than 400 mW. In this example, with I_CC= 7 mA, Q_GMF= 5.8 nC,

and Q_GSF= 48 nC, there is 297 mW in each driver, which is

below the 400 mW dissipation limit. See the ADP3120A data

sheet for more details.

RAMP RESISTOR SELECTION

V_CC× I_O

n_MF

n

P_S

= 2 × f_SW

MF )

×

× R_G×

×C_ISS

(25)

(

The ramp resistor (R_R) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the best

combination of thermal balance, stability, and transient response.

Equation 28 is used for determining the optimum value.

n_MF

where:

_MFis the total number of main MOSFETs.

R_Gis the total gate resistance (2 Ω for the ADP3120A and about

1 Ω for typical high speed switching MOSFETs, making R_G= 3 Ω).

n

A_R× L

R_R=

3 × A_D× R_DS×C_R

C

_ISSis the input capacitance of the main MOSFET.

(28)

Adding more main MOSFETs (n_MF) does not help the switching

loss per MOSFET because the additional gate capacitance slows

switching. Use lower gate capacitance devices to reduce

switching loss.

0.2 × 320 nH

R_R=

= 356 kꢀ

3 × 5 × 2.4 mꢀ × 5 pF

where:

The conduction loss of the main MOSFET is given by

A_Ris the internal ramp amplifier gain.

A_Dis the current balancing amplifier gain.

R_DSis the total low-side MOSFET on resistance.

C_Ris the internal ramp capacitor value.

2

⎛ n × I_R⎞²

⎡

⎢

⎤

I

⎛

⎜

⎝

⎞

⎟

⎠

O

1

12

⎜

⎝

⎟ ⎥

× R_DS

P_C

= D ×

+

×

(26)

(

MF

)

(

MF

)

⎟

n_MF

⎠

⎢

⎣

⎥

⎦

where R_DS(MF)is the on resistance of the MOSFET.

The internal ramp voltage magnitude can be calculated by using

Typically, for main MOSFETs, the highest speed (low C_ISS)

A_R×

(

1− D

)×V_VID

V_R=

device is preferred, but these usually have higher on resistance.

Select a device that meets the total power dissipation (about

1.5 W for a single D-PAK) when combining the switching and

conduction losses.

R_R× C_R× f_SW

(29)

0.2 ×

1−0.108 ×1.3 V

( )

= 394 mV

357 kꢀ × 5 pF × 330 kHz

For this example, an NTD40N03 is selected as the main

MOSFET (eight total; n_MF= 8), with C_ISS= 584 pF (maximum)

and R_DS(MF)= 19 mΩ (maximum at T_J= 120°C). An NTD110N02is

selected as the synchronous MOSFET (eight total; n_SF= 8), with

The size of the internal ramp can be made larger or smaller.

If it is made larger, stability and noise rejection improves, but

transient degrades. Likewise, if the ramp is made smaller,

transient response improves at the sacrifice of noise rejection

and stability.

C

_ISS= 2710 pF (maximum) and R_DS(SF)= 4.8 mΩ (maximum at

T_J= 120°C). The synchronous MOSFET C_ISSis less than 3000 pF,

satisfying this requirement.

The factor of 3 in the denominator of Equation 28 sets a ramp

size that gives an optimal balance for good stability, transient

response, and thermal balance.

Solving for the power dissipation per MOSFET at I_O= 119 A and

I_R= 11 A yields 958 mW for each synchronous MOSFET and

872 mW for each main MOSFET. A guideline to follow is to limit

the MOSFET power dissipation to 1 W. The values calculated in

Equation 25 and Equation 26 comply with this guideline.

Rev. 0 | Page 24 of 32

ADP3192A

For the ADP3192A, the maximum COMP voltage (V_COMP(MAX)

is 4.0 V, and the COMP pin bias voltage (V_BIAS) is 1.1 V. In

this example, the maximum duty cycle is 0.61 and the peak

current is 62 A.

)

COMP PIN RAMP

A ramp signal on the COMP pin is due to the droop voltage

and output voltage ramps. This ramp amplitude adds to the

internal ramp to produce the following overall ramp signal

at the PWM input:

The limit of the peak per-phase current described earlier during

the secondary current limit is determined by

V_R

V_RT

=

(30)

V_COMP

−V_BIAS

CLAMPED

)

(

⎛

⎜

⎝

⎞

⎟

⎠

2×

(

1−n × D

)

(34)

I_PHLIM

≅

1−

A_D× R_DS

(

MAX )

n × f_SW×C_X× R_O

For the ADP3192A, the current balancing amplifier gain (A_D) is

5 and the clamped COMP pin voltage is 2 V. Using an R_DS(MAX)

of 2.8 mΩ (low-side on resistance at 150°C) results in a per-phase

peak current limit of 64 A. This current level can be reached only

with an absolute short at the output and only if the current-limit

latch-off function shuts down the regulator before overheating

can occur.

In this example, the overall ramp signal is 0.46 V. However,

if the ramp size is smaller than 0.5 V, increase the ramp size

to be at least 0.5 V by decreasing the ramp resistor for noise

immunity. Because there is only 0.46 V initially, a ramp resistor

value of 332 kΩ is chosen for this example, yielding an overall

ramp of 0.51 V.

CURRENT-LIMIT SETPOINT

FEEDBACK LOOP COMPENSATION DESIGN

To select the current-limit setpoint, first find the resistor value

for R_LIM. The current-limit threshold for the ADP3192A is set

with a constant current source flowing out of the ILIMIT pin,

which sets up a voltage (V_LIM) across R_LIMwith a gain of

82.6 mV/V (A_LIM). Thus, increasing R_LIMnow increases the

current limit. R_LIMcan be found using

Optimized compensation of the ADP3192A allows the best

possible response of the regulator output to a load change.

The basis for determining the optimum compensation is to

make the regulator and output decoupling appear as an output

impedance that is entirely resistive over the widest possible

frequency range, including dc, and equal to the droop

resistance (R_O). With the resistive output impedance, the output

voltage droops in proportion to the load current at any load

current slew rate. This ensures optimal positioning and

minimizes the output decoupling.

V_CL

I

_LIM×R_CSA

82.6 mV

R_LIM

=

×R_REF

(31)

A_LIM× I_ILIMIT

Here, I_LIMis the peak average current limit for the supply output.

The peak average current is the dc current limit plus the output

ripple current. In this example, choosing a dc current limit of

159 A and having a ripple current of 11 A gives an I_LIMof 170 A.

This results in an R_LIM= 205.8 kΩ, for which 205 kΩ is chosen

as the nearest 1% value.

Because of the multimode feedback structure of the ADP3192A,

the feedback compensation must be set to make the converter

output impedance work in parallel with the output decoupling

to make the load look entirely resistive. Compensation is

needed for several poles and zeros created by the output

inductor and the decoupling capacitors (output filter).

The per-phase initial duty cycle limit and peak current during a

load step are determined by

A type three compensator on the voltage feedback is adequate

for proper compensation of the output filter. Equation 35 to

Equation 39 are intended to yield an optimal starting point for

the design; some adjustments may be necessary to account for

PCB and component parasitic effects (see the Tuning the

ADP3192A section).

V_COMP

−V_BIAS

MAX )

(

(32)

(33)

D_MAX= D ×

V_RT

D_MAX

f_SW

(

V_IN−V_VID

×

)

I_PHMAX

≅

L

Rev. 0 | Page 25 of 32

ADP3192A

First, compute the time constants for all the poles and zeros in the system using Equation 35 to Equation 39.

R_L×V_RT2×L ×

(

1−n × D ×V_RT

)

R_E= n × R_O+ A_D× R_DS

+

V_VID

n × C_X× R_O×V_VID

1.4 mꢀ × 0.51V 2 × 320 nH ×

(

1−0.432

)

× 0.51 V

(35)

R_E= 4 ×1 mꢀ + 5 × 2.4 mꢀ +

+

= 22.9 mꢀ

1.3 V

4 × 5.6 mF ×1 mꢀ ×1.3 V

240 pH 1 mꢀ−0.5mꢀ

R_O− R'

R_X

L_X

R_O

T_A= C_X×

(

R_O−R'

)

+

×

=

= 5.6 mF ×

(

1 mꢀ−0.5 mꢀ

)

+

×

= 3.00 ꢁs

(36)

(37)

1 mꢀ

0.6mꢀ

T_B=

(

R_X+ R' − R_O

)

× C_X

(

0.6 mꢀ +0.5 mꢀ −1 mꢀ

)

× 5.6 mF = 560 ns

⎛

⎞

⎟

⎠

⎛

⎞

⎟

⎠

A_D× R_DS

2 × f_SW

5 × 2.4 mꢀ

2 × 330 kHz

⎜

V_RT× L −

0.51 V × 320 nH−

⎜

⎝

T_C=

T_D=

=

= 5.17 ꢁs

(38)

(39)

V_VID× R_E

1.3 V × 22.9 mꢀ

2

C_X×C × R²

5.6 mF×180ꢁF×

+ C_Z× R_O5.6 mF× 1mꢀ − 0.5mꢀ

(

1mꢀ

)

Z

O

=

= 338 ns

C_X×

(

R_O− R'

)

(

)

+180ꢁF×1mꢀ

where:

R' is the PCB resistance from the bulk capacitors to the ceramics.

_DSis the total low-side MOSFET on resistance per phase.

R

In this example, A_Dis 5, V_RTequals 0.51 V, R' is approximately 0.5 mΩ (assuming a 4-layer, 1 ounce motherboard), and L_Xis 240 pH for

the 10 Al-Poly capacitors.

Rev. 0 | Page 26 of 32

ADP3192A

The compensation values can then be solved using

C_INSELECTION AND INPUT CURRENT

di/dt REDUCTION

n × R_O×T_A4×1 mꢀ × 3.00 ꢁs

C_A

R_A

=

= 524 pF

(40)

(41)

(42)

(43)

In continuous inductor current mode, the source current of the

high-side MOSFET is approximately a square wave with a duty

ratio equal to n × V_OUT/V_INand an amplitude of one-nth the

maximum output current. To prevent large voltage transients,

a low ESR input capacitor, sized for the maximum rms current,

must be used. The maximum rms capacitor current is given by

R_E× R_B

5.17 ꢁs

C_A524 pF

22.9mꢀ ×1.00 kꢀ

T_C

=

= 9.87 kꢀ

T_B

560 ns

C_B

C_FB

=

= 560 pF

= 34.2 pF

R_B1.00 kꢀ

1

I_CRMS= D × I_O

×

−1

(44)

T_D

338 ns

=

N × D

R_A9.87 kꢀ

1

These are the starting values prior to tuning the design that

account for layout and other parasitic effects (see the Tuning the

I_CRMS= 0.108 ×119A ×

− 1 =14.7A

4 × 0.108

ADP3192A section). The final values selected after tuning are

The capacitor manufacturer’s ripple current ratings are often

based on only 2000 hours of life. As a result, it advisable to

further derate the capacitor or to choose a capacitor rated at a

higher temperature than required. Several capacitors can be

placed in parallel to meet size or height requirements in the

design. In this example, the input capacitor bank is formed by

two 2700 μF, 16 V aluminum electrolytic capacitors and eight

4.7 μF ceramic capacitors.

C_A= 560 pF

R_A= 10.0 kΩ

C_B= 560 pF

C_FB= 27 pF

Figure 13 and Figure 14 show the typical transient response

using these compensation values.

To reduce the input current di/dt to a level below the recom-

mended maximum of 0.1 A/μs, an additional small inductor

(L > 370 nH at 18 A) should be inserted between the converter

and the supply bus. This inductor also acts as a filter between

the converter and the primary power source.

1

THERMAL MONITOR DESIGN

A thermistor is used on the TTSENSE input of the ADP3192A

for monitoring the temperature of the VR. A constant current

of 123 μA is sourced out of this pin and runs through a

thermistor network such as the one shown in Figure 15.

ADP3192A

CH1 50mV

M 10µs

A CH1

–36mV

VRFAN

8

9

Figure 13. Typical Transient Response for Design Example Load Step

VRHOT

OPTIONAL

TEMPERATURE

ADJUST RESISTOR

10

TTSENSE

0.1µF

PLACE

THERMISTOR

NEAR CLOSEST

PHASE

1

R

TTSENSE

Figure 15. VR Thermal Monitor Circuit

A voltage is generated from this current through the thermistor

and sensed inside the IC. When the voltage reaches 1.105 V,

the VRFAN output gets set. When the voltage reaches 0.81 V,

the VRHOT gets set. This corresponds to R_TTSENSEvalues of

8.98 kΩ for VRFAN and 6.58 kΩ for VRHOT.

CH1 50mV

M 10µs

A CH1

–36mV

Figure 14. Typical Transient Response for Design Example Load Release

These values correspond to a thermistor temperature of ~100°C

and ~110°C when using the same type of 100 kΩ NTC thermistor

used in the current sense amplifier.

Rev. 0 | Page 27 of 32

ADP3192A

An additional fixed resistor in parallel with the thermistor allows

tuning of the trip point temperatures to match the hottest tem-

perature in the VR when the thermistor itself is directly sensing

a proportionately lower temperature. Setting this resistor value

is best accomplished with a variable resistor during thermal

validation and then fixing this value for the final design.

where:

V_IN(MAX)is the maximum voltage from the 12 V input supply (if

the 12 V input supply is 12 V 5%, V_IN(MAX)= 12.6 V; if the 12 V

input supply is 12 V 10%, V_IN(MAX)= 13.2 V).

V

_CC(MIN)is the minimum V_CCvoltage of the ADP3192A. This is

specified as 4.75 V.

R_SHUNTis the shunt resistor value.

Additionally, a 0.1 μF capacitor should be used for filtering noise.

The CECC standard specification for power rating in surface-

mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W.

SHUNT RESISTOR DESIGN

The ADP3192A uses a shunt to generate 5 V from the 12 V

supply range. A trade-off can be made between the power

dissipated in the shunt resistor and the UVLO threshold.

Figure 16 shows the typical resistor value needed to realize

certain UVLO voltages. It also gives the maximum power

dissipated in the shunt resistor for these UVLO voltages.

TUNING THE ADP3192A

1. Build a circuit based on the compensation values

computed from the design spreadsheet.

2. Hook up the dc load to the circuit, turn it on, and verify its

operation. Also, check for jitter at no load and full load.

550

500

450

400

350

300

250

200

150

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

DC Load Line Setting

3. Measure the output voltage at no load (V_NL). Verify that it

is within tolerance.

4. Measure the output voltage at full load cold (V_FLCOLD).

Let the board sit for ~10 minutes at full load, and then

measure the output (V_FLHOT). If there is a change of more

than a few millvolts, adjust R_CS1and R_CS2using Equation 46

and Equation 48.

P

R

SHUNT

V_NL−V_FLCOLD

V_NL−V_FLHOT

(46)

R_CS2

= R_CS2

×

OLD )

(

NEW

)

(

5. Repeat Step 4 until the cold and hot voltage measurements

remain the same.

7.0

7.5

8.0

8.5

9.0

(UVLO)

9.5

10.0

10.5

11.0

V

IN

6. Measure the output voltage from no load to full load using

5 A steps. Compute the load line slope for each change, and

then average to get the overall load line slope (R_OMEAS).

7. If R_OMEASis off from R_Oby more than 0.05 mΩ, use

Equation 47 to adjust the R_PHvalues.

Figure 16. Typical Shunt Resistor Value and Power Dissipation

for Different UVLO Voltage

The maximum power dissipated is calculated using Equation 45.

2

(

V

_IN(MAX)−V_CC(MIN)

)

P_MAX

=

(45)

R_SHUNT

R_OMEAS

(47)

R_PH

= R_PH

×

OLD )

(

NEW

)

(

R_O

8. Repeat Step 6 and Step 7 to check the load line. Repeat

adjustments if necessary.

9. When the dc load line adjustment is complete, do not

change R_PH, R_CS1, R_CS2, or R_THfor the remainder of the

procedure.

10. Measure the output ripple at no load and full load with

a scope and make sure it is within specifications.

1

R_CS1

=

NEW )

(48)

(

R_CS1

₎+ R_TH

1

(

OLD

(

25°C

)

−

R_CS1

₎× R_TH

+

(

R_CS1

₎− R_CS2

)

×

(

R_CS1

₎− R_TH

)

R_TH

(

OLD

(

25°C

)

(

OLD

(

NEW

)

(

OLD

(

25°C

)

(

25°C

)

Rev. 0 | Page 28 of 32

ADP3192A

AC Load Line Setting

11. Remove the dc load from the circuit and hook up the

dynamic load.

12. Hook up the scope to the output voltage and set it to dc

coupling with the time scale at 100 μs/div.

V

DROOP

13. Set the dynamic load for a transient step of about 40 A at

1 kHz with 50% duty cycle.

14. Measure the output waveform (use dc offset on scope to see

the waveform). Try to use a vertical scale of 100 mV/div or

finer. This waveform should look similar to Figure 17.

V

TRAN1

V

TRAN2

Figure 18. Transient Setting Waveform

19. If both overshoots are larger than desired, try making

adjustments using the following suggestions:

V

ACDRP

•

Make the ramp resistor larger by 25% (R_RAMP).

For V_TRAN1, increase C_Bor increase the switching

frequency.

V

DCDRP

•

For V_TRAN2, increase R_Aand decrease C_Aby 25%.

If these adjustments do not change the response, the design

is limited by the output decoupling. Check the output

response every time a change is made, and check the switch-

ing nodes to ensure that the response is still stable.

Figure 17. AC Load Line Waveform

15. Use the horizontal cursors to measure V_ACDRPand V_DCDRP

,

20. For load release (see Figure 19), if V_TRANRELis larger

than the allowed overshoot, there is not enough output

capacitance. Either more capacitance is needed, or the

inductor values need to be made smaller. When changing

inductors, start the design again using a spreadsheet and

this tuning procedure.

as shown in Figure 17. Do not measure the undershoot or

overshoot that happens immediately after this step.

16. If V_ACDRPand V_DCDRPare different by more than a few

millivolts, use Equation 49 to adjust C_CS.Users may need to

parallel different values to get the right one, because limited

standard capacitor values are available. It is recommended to

have locations for two capacitors in this layout.

V_ACDRP

V_DCDRP

(49)

C_CS

= C_CS

×

OLD )

(

NEW

)

(

V

TRANREL

V

DROOP

17. Repeat Step 11 to Step 13 and repeat the adjustments, if

necessary. Once complete, do not change C_CSfor the

remainder of the procedure. Set the dynamic load step to

maximum step size. Do not use a step size larger than

needed. Verify that the output waveform is square, which

means that V_ACDRPand V_DCDRPare equal.

Initial Transient Setting

18. With the dynamic load still set at the maximum step size,

expand the scope time scale to either 2 μs/div or 5 μs/div.

The waveform can have two overshoots and one minor

undershoot (see Figure 18). Here, V_DROOPis the final

desired value.

Figure 19. Transient Setting Waveform

Because the ADP3192A turns off all of the phases (switches

inductors to ground), no ripple voltage is present during load

release. Therefore, the user does not have to add headroom for

ripple. This allows load release V_TRANRELto be larger than V_TRAN1

by the amount of ripple and still meet specifications.

If V_TRAN1and V_TRANRELare less than the desired final droop, the

capacitors may be removed. When removing capacitors, check the

output ripple voltage to make sure it is still within specifications.

Rev. 0 | Page 29 of 32

ADP3192A

Power Circuitry Recommendations

LAYOUT AND COMPONENT PLACEMENT

The switching power path should be routed on the PCB to

encompass the shortest possible length to minimize radiated

switching noise energy (EMI) and conduction losses in the

board. Failure to take proper precautions often results in EMI

problems for the entire PC system and noise-related operational

problems in the power converter control circuitry. The

switching power path is the loop formed by the current path

through the input capacitors and the power MOSFETs, including

all interconnecting PCB traces and planes. Using short and wide

interconnection traces is especially critical in this path for two

reasons: it minimizes the inductance in the switching loop that

can cause high energy ringing, and it accommodates the high

current demand with minimal voltage loss.

The guidelines outlined in this section are recommended for

optimal performance of a switching regulator in a PC system.

General Recommendations

For effective results, a PCB with at least four layers is recom-

mended. This provides the needed versatility for control circuitry

interconnections with optimal placement, power planes for

ground, input and output power, and wide interconnection

traces in the remainder of the power delivery current paths.

Keep in mind that each square unit of 1 ounce copper trace

has a resistance of ~0.53 mΩ at room temperature.

Whenever high currents must be routed between PCB layers,

use vias liberally to create several parallel current paths, so the

resistance and inductance introduced by these current paths is

minimized, and the via current rating is not exceeded.

When a power dissipating component (for example, a power

MOSFET) is soldered to a PCB, it is recommended to liberally

use the vias, both directly on the mounting pad and immediately

surrounding it. Two important reasons for this are improved

current rating through the vias and improved thermal perform-

ance from vias extended to the opposite side of the PCB, where a

plane can more readily transfer the heat to the air. Make a

mirror image of any pad being used to heatsink the MOSFETs

on the opposite side of the PCB to achieve the best thermal

dissipation in the air around the board. To further improve

thermal performance, use the largest possible pad area.

If critical signal lines (including the output voltage sense lines of

the ADP3192A) must cross through power circuitry, it is best to

interpose a signal ground plane between those signal lines and

the traces of the power circuitry. This serves as a shield to

minimize noise injection into the signals at the expense of

making signal ground a bit noisier.

An analog ground plane should be used around and under the

ADP3192A as a reference for the components associated with

the controller. This plane should be tied to the nearest output

decoupling capacitor ground and should not be tied to any other

power circuitry to prevent power currents from flowing into it.

The output power path should also be routed to encompass a

short distance. The output power path is formed by the current

path through the inductor, the output capacitors, and the load.

The components around the ADP3192A should be located close

to the controller with short traces. The most important traces to

keep short and away from other traces are the FB pin and CSSUM

pin. The output capacitors should be connected as close as

possible to the load (or connector), for example, a microproc-

essor core, that receives the power. If the load is distributed, the

capacitors should also be distributed and generally be in

For best EMI containment, a solid power ground plane should

be used as one of the inner layers extending fully under all the

power components.

Signal Circuitry Recommendations

The output voltage is sensed and regulated between the FB pin

and the FBRTN pin, which connect to the signal ground at the

load. To avoid differential mode noise pickup in the sensed

signal, the loop area should be small. Thus, the FB trace and

FBRTN trace should be routed adjacent to each other on top

of the power ground plane back to the controller.

proportion to where the load tends to be more dynamic.

Avoid crossing any signal lines over the switching power path loop

(described in the Power Circuitry Recommendations section).

The feedback traces from the switch nodes should be connected

as close as possible to the inductor. The CSREF signal should be

connected to the output voltage at the nearest inductor to the

controller.

Rev. 0 | Page 30 of 32

ADP3192A

OUTLINE DIMENSIONS

6.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

31

40

1

30

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

4.25

4.10 SQ

3.95

5.75

BCS SQ

EXPOSED

PAD

(BOT TOM VIEW)

0.50

0.40

0.30

21

10

11

20

0.25 MIN

4.50

REF

12° MAX

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

Figure 20. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range Package Description

Package Option Ordering Quantity

CP-40-1 2,500

ADP3192AJCPZ-RL¹0°C to 85°C

40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

¹Z = RoHS Compliant Part.

Rev. 0 | Page 31 of 32

ADP3192A

NOTES

registered trademarks are the property of their respective owners.

D06786-0-5/07(0)

Rev. 0 | Page 32 of 32


型号：	ADP3192A
厂家：	ADI
描述：	8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller 8位可编程2至4相同步降压控制器控制器
文件：	总32页 (文件大小：1033K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP3192A [ADI]

相关型号：

ADP3192AJCPZ-RL

ADP3192JCPZ-RL

ADP3193

ADP3193A

ADP3193A

ADP3193AJCPZ-RL

ADP3193AJCPZ-RL

ADP3193JCPZ-RL

ADP3194

ADP3194JRUZ-RL

ADP3196

ADP3196