ADP3193A_技术文档

8-Bit, Programmable, 2- to 3-Phase,

Synchronous Buck Controller

ADP3193A

FUNCTIONAL BLOCK DIAGRAM

FEATURES

VCC

23

RT RAMPADJ

10

Selectable 2- or 3-phase operation at up to 1 MHz per phase

7.7 mV worst-case differential sensing error over

temperature

9

SHUNT

REGULATOR

OSCILLATOR

15

22

21

20

OD

UVLO

Logic-level PWM outputs for interface to external high

power drivers

Fast enhanced PWM (FEPWM) flex mode for excellent load

transient performance

Active current balancing between all output phases

Built-in power-good/crowbar blanking supports on-the-fly

VID code changes

Digitally programmable 0.5 V to 1.6 V output supports both

VR10.x and VR11 specifications

SHUTDOWN

SET EN

RESET

+

14

1

GND

EN

PWM1

PWM2

PWM3

CMP

–

+

850mV

+

CMP

RESET

DAC

+150mV

–

+

2-/3-PHASE

DRIVER LOGIC

CSREF

+

–

+

RESET

CMP

–

DAC

–350mV

CURRENT

LIMIT

DELAY

2

CROWBAR

PWRGD

Programmable short-circuit protection with programmable

latch-off delay

19

18

SW1

SW2

17 SW3

13

APPLICATIONS

CSCOMP

8

7

ILIMIT

CURRENT

11

12

+

–

CSREF

CSSUM

MEASUREMENT

AND LIMIT

Desktop PC power supplies for

Next generation Intel® processors

VRM modules

DELAY

16

5

IREF

–

+

4

6

FB

SS

COMP

GENERAL DESCRIPTION

–

PRECISION

REFERENCE

The ADP3193A¹is a highly efficient, multiphase, synchronous

buck switching regulator controller optimized for converting a

12 V main supply into the core supply voltage required by high

performance Intel processors. It uses an internal 8-bit DAC to read

a voltage identification (VID) code directly from the processor,

which is used to set the output voltage between 0.5 V and 1.6 V.

+

BOOT

VOLTAGE

AND

SOFT START

CONTROL

3

FBRTN

VIDSEL

VC DAC

32

ADP3193A

24

25

26

27

28

29

30

31

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Figure 1.

This device uses a multimode PWM architecture to drive the

logic-level outputs at a programmable switching frequency that

can be optimized for VR size and efficiency. The phase relation-

ship of the output signals can be programmed to provide 2- or

3-phase operation, allowing for the construction of up to three

complementary buck switching stages.

The ADP3193A has a built-in shunt regulator that allows the

part to be connected to the 12 V system supply through a series

resistor.

The ADP3193A is specified over the extended commercial

temperature range of 0°C to 85°C and is available in a

32-lead LFCSP.

The ADP3193A also includes programmable no load offset and

slope functions to adjust the output voltage as a function of the

load current, optimally positioning it for a system transient. The

ADP3193A also provides accurate and reliable short-circuit

protection, adjustable current limiting, and delayed power-good

output that accommodates on-the-fly output voltage changes

requested by the CPU.

¹Protected by U.S. Patent Number 6,683,441; other patents pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADP3193A

TABLE OF CONTENTS

Features .............................................................................................. 1

Dynamic VID ............................................................................. 12

Power-Good Monitoring........................................................... 12

Output Crowbar ......................................................................... 12

Output Enable and UVLO ........................................................ 13

Application Information................................................................ 19

Setting the Clock Frequency..................................................... 19

Soft Start Delay Time................................................................. 19

Current-Limit Latch-Off Delay Times .................................... 19

Inductor Selection...................................................................... 19

Current Sense Amplifier............................................................ 20

Inductor DCR Temperature Correction ................................. 21

Output Offset.............................................................................. 21

C_OUTSelection ............................................................................. 22

Power MOSFETs......................................................................... 23

Ramp Resistor Selection............................................................ 24

COMP Pin Ramp ....................................................................... 24

Current-Limit Setpoint.............................................................. 24

Feedback Loop Compensation Design.................................... 25

C_INSelection and Input Current di/dt Reduction.................. 26

Shunt Resistor Design................................................................ 26

Tuning Procedure for ADP3193A............................................ 27

Layout and Component Placement ......................................... 29

Outline Dimensions....................................................................... 30

Ordering Guide .......................................................................... 30

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Test Circuits ....................................................................................... 8

Theory of Operation ........................................................................ 9

Start-Up Sequence........................................................................ 9

Phase Detection Sequence........................................................... 9

Master Clock Frequency............................................................ 10

Output Voltage Differential Sensing........................................ 10

Output Current Sensing ............................................................ 10

Current Control Mode and Thermal Balance ........................ 10

Voltage Control Mode................................................................ 10

Current Reference ...................................................................... 11

Fast Enhanced PWM Mode ...................................................... 11

Delay Timer................................................................................. 11

Soft Start ...................................................................................... 11

Current-Limit, Short-Circuit, and Latch-Off Protection...... 11

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

ADP3193A

SPECIFICATIONS

VCC = 5 V, FBRTN = GND, T_A= 0°C to 85°C, unless otherwise noted.¹

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

REFERENCE CURRENT

Reference Bias Voltage

Reference Bias Current

ERROR AMPLIFIER

Output Voltage Range²

Accuracy

V_IREF

I_IREF

1.5

14.25 15

V

R_IREF= 100 kΩ

15.75 μA

V_COMP

V_FB

0

4.4

+7.7

V

mV

Relative to nominal DAC output, referenced −7.7

to FBRTN (see Figure 4)

V_FB(BOOT)

In startup

1.092 1.1

−1

1.108

+1

16.5

200

V

LSB

μA

MHz

V/μs

ms

Differential Nonlinearity

Input Bias Current

FBRTN Current

Output Current

Gain Bandwidth Product

Slew Rate

I_FB

I_FB= I_IREF

13.5

15

65

500

20

25

2

I_FBRTN

I_COMP

GBW_(ERR)

FB forced to V_OUT− 3%

COMP = FB

Boot Voltage Hold Time

VID INPUTS

t_BOOT

C_DELAY= 10 nF

Input Low Voltage

Input High Voltage

Input Current

VID Transition Delay Time²

No CPU Detection Turn-Off Delay Time²

OSCILLATOR

V_IL(VID)

V_IH(VID)

I_IN(VID)

VID(x), VIDSEL

0.4

V

μA

ns

μs

0.8

−1

VID code change to FB change

VID code change to PWM going low

400

5

Frequency Range²

Frequency Variation

f_OSC

f_PHASE

0.25

240

4

293

MHz

kHz

V

T_A= 25°C, R_T= 210 kΩ, 3-phase

T_A= 25°C, R_T= 100 kΩ, 3-phase

T_A= 25°C, R_T= 40 kΩ, 3-phase

R_T= 243 kΩ to GND

260

530

1000

2.0

Output Voltage

V_RT

V_RAMPADJ

I_RAMPADJ

1.9

−50

1

2.1

+50

50

RAMPADJ Output Voltage

RAMPADJ Input Current Range

CURRENT SENSE AMPLIFIER

Offset Voltage

Input Bias Current

Gain Bandwidth Product

Slew Rate

Input Common-Mode Range

Output Voltage Range

Output Current

Current Limit Latch-Off Delay Time

CURRENT BALANCE AMPLIFIER

Common-Mode Range

Input Resistance

RAMPADJ − FB

mV

μA

V_OS(CSA)

I_BIAS(CSSUM)

GBW_(CSA)

CSSUM − CSREF (see Figure 4)

−1.0

−10

+1.0

+10

mV

nA

MHz

V/μs

V

μA

ms

CSSUM = CSCOMP

C_CSCOMP= 10 pF

CSSUM and CSREF

10

0

0.05

3.5

I_CSCOMP

t_OC(DELAY)

500

8

C_DELAY= 10 nF

V_SW(x)CM

R_SW(x)

I_SW(x)

−600

10

8

+200

26

20

mV

kΩ

μA

%

SW(x) = 0 V

17

12

Input Current

Input Current Matching

−4

+4

ΔI_SW(x)

Rev. 0 | Page 3 of 32

ADP3193A

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

CURRENT LIMIT COMPARATOR

ILIMIT Bias Current

ILIMIT Voltage

Maximum Output Voltage

Current-Limit Threshold Voltage

Current-Limit Setting Ratio

DELAY TIMER

I_ILIMIT

V_ILIMIT

I_ILIMIT= 2/3 × I_IREF

R_ILIMIT= 121 kΩ (V_ILIMIT= (I_ILIMIT× R_ILIMIT))

9

1.09

3

10

1.21

11

1.33

μA

V

mV

mV/V

V_CL

V_CSREF− V_CSCOMP, R_ILIMIT= 121 kΩ

V_CL/V_ILIMIT

80

100

82.6

125

Normal Mode Output Current

Output Current in Current Limit

Threshold Voltage

SOFT START

I_DELAY

I_DELAY(CL)

V_DELAY(TH)

I_DELAY= I_IREF

I_DELAY(CL)= 0.25 × I_IREF

12

3.0

1.6

15

3.75

1.7

18

4.5

1.8

μA

V

Output Current

I_SS

During startup, I_SS= I_IREF

12

15

18

μA

ENABLE INPUT

Threshold Voltage

Hysteresis

Input Current

V_TH(EN)

V_HYS(EN)

I_IN(EN)

800

80

850

100

−1

2

900

125

mV

μA

Delay Time

t_DELAY(EN)

EN > 950 mV, C_DELAY= 10 nF

ms

OD OUTPUT

Output Low Voltage

V_OL(

160

5

500

mV

V

)

OD

Output High Voltage

V_OH(

4

)

OD

POWER-GOOD COMPARATOR

Undervoltage Threshold

Overvoltage Threshold

Output Low Voltage

Power-Good Delay Time

During Soft Start²

VID Code Changing

VID Code Static

Crowbar Trip Point

Crowbar Reset Point

Crowbar Delay Time

VID Code Changing

VID Code Static

V_PWRGD(UV)

V_PWRGD(OV)

V_OL(PWRGD)

Relative to nominal DAC output

I_PWRGD(SINK)= −4 mA

−400

100

−350 −300

mV

150

200

300

C_DELAY= 10 nF

2

ms

μs

ns

mV

100

250

200

150

375

V_CROWBAR

t_CROWBAR

Relative to nominal DAC output

Relative to FBRTN

Overvoltage to PWM going low

100

320

200

430

100

250

400

μs

ns

PWM OUTPUTS

Output Low Voltage

Output High Voltage

SUPPLY

V_OL(PWM)

V_OH(PWM)

I_PWM(SINK)= −400 μA

I_PWM(SOURCE)= 400 μA

160

5

500

mV

V

4.0

V_SYSTEM= 12 V, R_SHUNT= 340 Ω (see Figure 4)

VCC²

VCC

I_VCC

4.65

5

5.55

25

11

V

DC Supply Current

UVLO Turn-On Current

UVLO Threshold Voltage

UVLO Turn-Off Voltage

V_SYSTEM= 13.2 V, R_SHUNT= 340 Ω

mA

V

6.5

4.1

V_UVLO

VCC rising

VCC falling

9

V

¹All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

²Guaranteed by design or bench characterization, not tested in production.

Rev. 0 | Page 4 of 32

ADP3193A

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

VCC

FBRTN

−0.3 V to +6 V

−0.3 V to +0.3 V

−0.3 V to VCC + 0.3 V

−5 V to +25 V

−10 V to +25 V

−0.3 V to VCC + 0.3 V

−65°C to +150°C

0°C to 85°C

PWM1 to PWM3, RAMPADJ

SW1 to SW3

<200 ns

All Other Inputs and Outputs

Storage Temperature Range

Operating Ambient Temperature Range

Operating Junction Temperature

Thermal Impedance (θ_JA)

Lead Temperature

Soldering (10 sec)

Absolute maximum ratings apply individually only, not in

combination. Unless otherwise specified, all other voltages

are referenced to GND.

125°C

32.6°C/W

ESD CAUTION

300°C

260°C

Infrared (15 sec)

Rev. 0 | Page 5 of 32

ADP3193A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EN

PWRGD

FBRTN

FB

COMP

SS

1

2

3

4

5

6

7

8

24 VID7

23 VCC

22 PWM1

21 PWM2

20 PWM3

19 SW1

18 SW2

17 SW3

PIN 1

INDICATOR

ADP3193A

TOP VIEW

(Not to Scale)

DELAY

ILIMIT

NOTES

1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN

ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND.

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

4

EN

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.

Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range.

Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin

and the output voltage sets the no load offset point.

PWRGD

FBRTN

FB

5

6

7

COMP

SS

DELAY

Error Amplifier Output and Compensation Point.

Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start ramp-up time.

Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent latch-off

delay time, boot voltage hold time, EN delay time, and PWRGD delay time.

8

9

ILIMIT

RT

Current-Limit Set Point. An external resistor from this pin to GND sets the current-limit threshold of the converter.

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device.

10

11

RAMPADJ

CSREF

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp.

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier

and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors.

12

13

CSSUM

Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents

to measure the total output current.

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the

current sense amplifier and the positioning loop response time.

CSCOMP

14

15

GND

OD

Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO

threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.

16

IREF

Current Reference Input. An external resistor from this pin to ground sets the reference current for I_FB, I_DELAY, I_SS, and I_ILIMIT.

17 to 19 SW3 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be

left open.

20 to 22 PWM3 to PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3120A.

Connecting PWM3 output to VCC causes that phase to turn off, allowing the ADP3193A to operate as a 2- or 3-phase

controller.

23

24 to 31 VID7 to VID0

32 VIDSEL

VCC

Supply Voltage. A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal

shunt regulator maintains VCC = 5 V.

Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open. When

in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V (see Table 4).

VID DAC Selection Pin. The logic state of this pin determines whether the internal VID DAC decodes VID0 to VID7 as

extended VR10 or VR11 inputs.

Rev. 0 | Page 6 of 32

ADP3193A

TYPICAL PERFORMANCE CHARACTERISTICS

6000

5000

4000

MASTER CLOCK

3000

2000

1000

0

13 27 39 50 68 82 130 210 248 270 430 742 850

R

(kΩ)

T

Figure 3. Master Clock Frequency vs. R_T

Rev. 0 | Page 7 of 32

ADP3193A

TEST CIRCUITS

8-BIT CODE

12V

ADP3193A

32

12V

680ꢀ

VCC

680ꢀ

1

23

5

1.25V

EN

VID7

VCC

PWM1

PWM2

PWM3

SW1

PWRGD

FBRTN

FB

COMP

SS

COMP

FB

+

100nF

1µF

ADP3193A

1kꢀ

10kꢀ

DELAY

ILIMIT

SW2

SW3

4

10nF

250kꢀ

100kꢀ

CSREF

GND

VID

DAC

11

14

+

1V

20kꢀ

100nF

Figure 4. Closed-Loop Output Voltage Accuracy

Figure 6. Positioning Voltage

12V

ADP3193A

680ꢀ

VCC

23

CSCOMP

CSSUM

CSREF

GND

13

100nF

39kꢀ

12

11

14

1kꢀ

1V

CSCOMP – 1V

V

=

OS

40

Figure 5. Current Sense Amplifier Offset Voltage (V_OS

)

Rev. 0 | Page 8 of 32

ADP3193A

THEORY OF OPERATION

The ADP3193A combines a multimode, fixed-frequency PWM

control with multiphase logic outputs for use in 2- and 3-phase

synchronous buck CPU core supply power converters. The internal

VID DAC is designed to interface with the Intel 8-bit VRD/VRM 11

and 7-bit VRD/VRM 10.x CPUs. Multiphase operation is impor-

tant for producing the high currents and low voltages demanded by

today’s microprocessors. Handling the high currents in a single-

phase converter increases thermal demands on the components

in the system, such as the inductors and MOSFETs.

UVLO

5V

THRESHOLD

SUPPLY

0.85V

VTT I/O

(ADP3193A EN)

V

DELAY(TH)

(1.7V)

DELAY

V

BOOT

V

VID

(1.1V)

1V

SS

The multimode control of the ADP3193A ensures a stable,

high performance topology for the following:

TD3

V

BOOT

VID

(1.1V)

VCC_CORE

TD1

•

Balancing currents and thermals between phases

High speed response at the lowest possible switching

frequency and output decoupling

TD4

TD2

VR READY

(ADP3193A PWRGD)

•

Minimizing thermal switching losses by using lower

frequency operation

TD5

50µs

CPU

VID INPUTS

•

Tight load line regulation and accuracy

High current output due to 3-phase operation

Reduced output ripple due to multiphase cancellation

PC board layout noise immunity

Ease of use and design due to independent component

selection

VID INVALID

VID VALID

Figure 7. System Start-Up Sequence

PHASE DETECTION SEQUENCE

During startup, the number of operational phases and their

phase relationship is determined by the internal circuitry that

monitors the PWM outputs. Normally, the ADP3193A operates

as a 3-phase PWM controller. Connecting the PWM3 pin to

VCC programs 2-phase operation.

•

Flexibility in design by allowing optimization for either low

cost or high performance

START-UP SEQUENCE

Prior to soft start, while EN is low, the PWM3 pin sinks approxi-

mately 100 μA. An internal comparator checks the voltage on

PWM3 and compares it with a threshold of 3 V. If the pin is tied

to VCC, it is above the threshold. Otherwise, an internal current

sink pulls the pin to GND, which is below the threshold. PWM1

and PWM2 are low during the phase detection interval that occurs

during the first three clock cycles of TD2. After this time, if PWM3

is not pulled to VCC, the 100 μA current sink is removed, and it

functions as normal PWM output. If PWM3 is pulled to VCC,

the 100 μA current source is removed, and it is put into a high

impedance state.

The ADP3193A follows the VR11 start-up sequence shown in

Figure 7. After both the EN and UVLO conditions are met,

the DELAY pin goes through one cycle (TD1). The first three

clock cycles of TD2 are blanked from the PWM outputs and

used for phase detection, as explained in the Phase Detection

Sequence section. Then, the soft start ramp is enabled (TD2),

and the output increases to the boot voltage of 1.1 V. The boot

hold time is determined by the DELAY pin as it goes through a

second cycle (TD3). During TD3, the processor VID pins settle

to the required VID code. When TD3 is over, the ADP3193A

soft starts either up or down to the final VID voltage (TD4).

After TD4 has been completed and the PWRGD masking time

(equal to VID on-the-fly masking) is completed, a third ramp

on the DELAY pin sets the PWRGD blanking (TD5).

The PWM outputs are logic-level devices intended for driving

external gate drivers such as the ADP3120A. Because each phase

is monitored independently, operation approaching 100% duty

cycle is possible. In addition, more than one output can be on at

the same time to allow overlapping phases.

Rev. 0 | Page 9 of 32

ADP3193A

CURRENT CONTROL MODE AND

THERMAL BALANCE

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3193A is set with an external

resistor connected from the RT pin to ground. The frequency

follows the graph in Figure 3. To determine the frequency per

phase, the clock is divided by the number of phases in use. If all

phases are in use, divide by 3. If PWM3 is tied to VCC, divide

the master clock by 2 for the frequency of the remaining phases.

The ADP3193A has individual inputs (SW1 to SW3) for each

phase that are used to monitor the current. This information is

combined with an internal ramp to create a current-balancing

feedback system that has been optimized for initial current balance

accuracy and dynamic thermal balancing during operation. This

current balance information is independent of the average output

current information used for positioning, as described in the

Output Current Sensing section.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3193A includes differential sensing, high accuracy

VID DAC and reference, and a low offset error amplifier. This

maintains a worst-case specification of 7.7 mV differential

sensing error over its full operating output voltage and temperature

range. The output voltage is sensed between the FB pin and the

FBRTN pin. FB should be connected through a resistor to the

regulation point, usually the remote sensing pin of the micro-

processor. FBRTN should be connected directly to the remote

sensing ground point. The internal VID DAC and precision

reference are referenced to FBRTN, which has a minimal current

of 65 μA to allow accurate remote sensing. The internal error

amplifier compares the output of the DAC to the FB pin to

regulate the output voltage.

The magnitude of the internal ramp can be set to optimize the

transient response of the system. It also monitors the supply voltage

for feedforward control for changes in the supply. A resistor

connected from the power input voltage to the RAMPADJ pin

determines the slope of the internal PWM ramp. External resistors

can be placed in series with individual phases to create an inten-

tional current imbalance, such as when one phase has better

cooling and can support higher currents. Resistors R_SW1through

R_SW3(see Figure 10) can be used for adjusting thermal balance

in this 3-phase example. It is best to have the ability to add these

resistors during the initial design; therefore, ensure that place-

holders are provided in the layout.

OUTPUT CURRENT SENSING

To increase the current in any given phase, enlarge R_SWfor that

phase (make R_SW= 0 for the hottest phase, and do not change it

during balancing). Increasing R_SWto only 500 Ω results in a

substantial increase in phase current. Increase each R_SWvalue

by small amounts to achieve balance, starting with the coolest

phase first.

The ADP3193A provides a dedicated current sense amplifier

(CSA) to monitor the total output current for proper voltage

positioning vs. load current and for current-limit detection.

Sensing the load current at the output gives the total average

current being delivered to the load, which is an inherently more

accurate method than peak current detection or sampling the

current across a sensing element, such as the low-side MOSFET.

Depending on the objectives of the system, this amplifier can be

configured in several ways:

VOLTAGE CONTROL MODE

A high gain, high bandwidth voltage mode error amplifier is used

for the voltage mode control loop. The control input voltage to

the positive input is set via the VID logic according to the voltages

listed in Table 4.

•

Output inductor DCR sensing without a thermistor for

lowest cost.

Output inductor DCR sensing with a thermistor for

improved accuracy in tracking inductor temperature.

Sensing resistor for highest accuracy measurements.

This voltage is also offset by the droop voltage for active

positioning of the output voltage as a function of current,

commonly known as active voltage positioning. The output

of the amplifier is the COMP pin, which sets the termination

voltage for the internal PWM ramps.

The positive input of the CSA is connected to the CSREF pin,

which is connected to the output voltage. The inputs to the

amplifier are summed together through resistors from the sensing

element, such as the switch node side of the output inductors,

to the inverting input CSSUM. The feedback resistor between

CSCOMP and CSSUM sets the gain of the amplifier, and a filter

capacitor is placed in parallel with this resistor. The gain of the

amplifier is programmable by adjusting the feedback resistor.

The negative input (FB) is tied to the output sense location with

Resistor R_Band is used for sensing and controlling the output

voltage at this point. A current source (equal to IREF) from the

FB pin flowing through R_Bis used for setting the no load offset

voltage from the VID voltage. The no load voltage is negative with

respect to the VID DAC. The main loop compensation is incor-

porated into the feedback network between FB and COMP pins.

The difference between CSREF and CSCOMP is also used as a

differential input for the current-limit comparator.

To provide the best accuracy for sensing current, the CSA has a

low offset input voltage and the sensing gain is set by the external

resistor.

Rev. 0 | Page 10 of 32

ADP3193A

CURRENT REFERENCE

When the SS voltage is within 100 mV of the boot voltage, the

boot voltage delay time (TD3 in Figure 7) starts. The end of the

boot voltage delay time signals the beginning of the second soft

start time (TD4 in Figure 7). The SS voltage changes from the

boot voltage to the programmed VID DAC voltage (either higher

or lower) using the SS amplifier with the output current equal to

IREF. The voltage of the FB pin follows the ramping voltage of

the SS pin, limiting the inrush current during the transition from

the boot voltage to the final DAC voltage. The second soft start

time depends on the boot voltage, the programmed VID DAC

voltage, and the C_SS.

The IREF pin is used to set an internal current reference. This

reference current sets I_FB, I_DELAY, I_SS, and I_LIMIT. A resistor to

ground programs the current based on the 1.5 V output.

1.5 V

IREF =

R_IREF

Typically, R_IREFis set to 100 kΩ to program IREF = 15 μA.

Therefore,

I_FB= IREF = 15 μA

I_DELAY= IREF = 15 μA

I_SS= IREF = 15 μA

If EN is taken low or if VCC drops below UVLO, DELAY and

SS are reset to ground to be ready for another soft start cycle.

Figure 8 shows typical start-up waveforms for the ADP3193A.

I_LIMIT= 2/3 (IREF) = 10 μA

FAST ENHANCED PWM MODE

Fast enhanced PWM mode is intended to improve the transient

response of the ADP3193A to a load step-up. In previous genera-

tions of controllers, when a load step-up occurred, the controller

could only respond to the load change after the PWM signal

was turned on. Enhanced PWM mode allows the controller to

immediately respond when a load step-up occurs. This allows the

phases to respond more quickly when a load increase takes place.

1

2

3

4

DELAY TIMER

The delay times for the start-up timing sequence are set with

a capacitor from the DELAY pin to ground. In UVLO or when

EN is logic low, the DELAY pin is held at ground. After the

UVLO and EN signals are asserted, the first delay time (TD1 in

Figure 7) is initiated. A current flows out of the DELAY pin to

charge C_DLY. This current is equal to IREF, which is normally

15 μA. A comparator monitors the DELAY voltage with a

threshold of 1.7 V. The delay time is therefore set by the IREF

current charging a capacitor from 0 V to 1.7 V. This DELAY pin

is used for multiple delay timings (TD1, TD3, and TD5) during

the start-up sequence. In addition, DELAY is used for timing

the current-limit latch-off, as explained in the Current-Limit,

Short-Circuit, and Latch-Off Protection section.

CH1 1V

CH3 1V

CH2 1V

CH4 10V

M

1ms

A CH1

700mV

T 40.4%

Figure 8. Typical Start-Up Waveforms

(Channel 1: CSREF, Channel 2: DELAY,

Channel 3: SS, Channel 4: Phase 1 Switch Node)

CURRENT-LIMIT, SHORT-CIRCUIT, AND

LATCH-OFF PROTECTION

The ADP3193A compares a programmable current-limit

setpoint to the voltage from the output of the current sense

amplifier. The level of current limit is set with the resistor from

the ILIMIT pin to ground. During operation, the current from

ILIMIT is equal to 2/3 of IREF, resulting in 10 μA normally. This

current through the external resistor sets the ILIMIT voltage,

which is internally scaled to provide a current limit threshold of

82.6 mV/V. If the difference in voltage between CSREF and

CSCOMP rises above the current-limit threshold, the internal

current-limit amplifier controls the internal COMP voltage to

maintain the average output current at the limit.

SOFT START

The soft start times for the output voltage are set with a capacitor

from the SS pin to ground. After TD1 and the phase detection

cycle have been completed, the SS time (TD2 in Figure 7) starts.

The SS pin is disconnected from GND, and the capacitor is charged

up to the 1.1 V boot voltage by the SS amplifier, which has an

output current equal to IREF (normally 15 μA). The voltage at

the FB pin follows the ramping voltage on the SS pin, limiting

the inrush current during startup. The soft start time depends

on the value of the boot voltage and C_SS.

If the limit is reached and TD5 in Figure 7 has completed, a

latch-off delay time starts, and the controller shuts down if the

fault is not removed. The current-limit delay time shares the

DELAY pin timing capacitor with the start-up sequence timing.

However, during current limit, the DELAY pin current is reduced

to IREF/4. A comparator monitors the DELAY voltage and shuts

off the controller when the voltage reaches 1.7 V. Therefore,

Rev. 0 | Page 11 of 32

ADP3193A

the current-limit latch-off delay time is set by the current of

IREF/4 charging the delay capacitor from 0 V to 1.7 V. This delay

is four times longer than the delay time during the start-up

sequence.

DYNAMIC VID

The ADP3193A can dynamically change the VID inputs while

the controller is running. This allows the output voltage to

change while the supply is running and supplying current to the

load. This is commonly referred to as VID on-the-fly (OTF). A

VID OTF can occur under light or heavy load conditions. The

processor signals the controller by changing the VID inputs in

multiple steps from the start code to the finish code. This

change can be positive or negative.

The current-limit delay time starts only after the TD5 is

complete. If there is a current limit during startup, the

ADP3193A goes through TD1 to TD5, and then starts the

latch-off time. Because the controller continues to cycle the

phases during the latch-off delay time, the controller returns to

normal operation and the DELAY capacitor is reset to GND if

the short is removed before the 1.7 V threshold is reached.

When a VID input changes state, the ADP3193A detects the

change and ignores the DAC inputs for a minimum of 400 ns.

This time prevents a false code due to logic skew while the eight

VID inputs are changing. Additionally, the first VID change

initiates the PWRGD and crowbar blanking functions for a

minimum of 100 μs to prevent a false PWRGD or crowbar

event. Each VID change resets the internal timer.

The latch-off function can be reset by either removing and

reapplying the supply voltage to the ADP3193A or by briefly

toggling the EN pin low. To disable the short-circuit latch-off

function, an external resistor should be placed in parallel with

C_DLY. This prevents the DELAY capacitor from charging up to

the 1.7 V threshold. The addition of this resistor causes a slight

increase in the delay times.

POWER-GOOD MONITORING

The power-good comparator monitors the output voltage via

the CSREF pin. The PWRGD pin is an open-drain output whose

high level, when connected to a pull-up resistor, indicates that

the output voltage is within the specified nominal limits, which

are based on the VID voltage setting. PWRGD goes low if the

output voltage is outside of this specified range, if the VID DAC

inputs are in no CPU mode, or if the EN pin is pulled low. PWRGD

is blanked during a VID OTF event for a period of 200 μs to

prevent false signals during the time the output is changing.

During startup, when the output voltage is below 200 mV,

a secondary current limit is active. This is necessary because

the voltage swing of CSCOMP cannot go below ground. This

secondary current limit controls the internal COMP voltage

to the PWM comparators to 1.5 V. This limits the voltage drop

across the low-side MOSFETs through the current balance

circuitry. An inherent per-phase current limit protects individual

phases if one or more phases stop functioning because of a faulty

component. This limit is based on the maximum normal mode

COMP voltage. Typical overcurrent latch-off waveforms are

shown in Figure 9.

The PWRGD circuitry also incorporates an initial turn-on

delay time (TD5) based on the DELAY timer. Prior to the

SS voltage reaching the programmed VID DAC voltage and the

PWRGD masking time finishing, the PWRGD pin is held low.

When the SS pin is within 100 mV of the programmed DAC

voltage, the capacitor on the DELAY pin begins to charge.

A comparator monitors the DELAY voltage and enables

PWRGD when the voltage reaches 1.7 V. The PWRGD delay

time is, therefore, set by a current of IREF charging a capacitor

from 0 V to 1.7 V.

1

2

OUTPUT CROWBAR

3

4

To protect the load and output components of the supply, the

PWM outputs are driven low, which turns on the low-side

MOSFETs when the output voltage exceeds the upper crowbar

threshold. This crowbar action stops when the output voltage

falls below the release threshold of approximately 300 mV.

CH1 1V

CH3 2V

CH2 1V

CH4 10V

M 2ms

T 61.8%

A CH1

680mV

Figure 9. Overcurrent Latch-Off Waveforms

(Channel 1: CSREF, Channel 2: DELAY,

Channel 3: COMP, Channel 4: Phase 1 Switch Node)

Turning on the low-side MOSFETs pulls down the output as

the reverse current builds up in the inductors. If the output

overvoltage is due to a short in the high-side MOSFET, this

action current limits the input supply or blows its fuse,

protecting the microprocessor from being destroyed.

Rev. 0 | Page 12 of 32

ADP3193A

OUTPUT ENABLE AND UVLO

OD

In the application circuit (see Figure 10), the

pin should be

For the ADP3193A to begin switching, the input supply (VCC)

to the controller must be higher than the UVLO threshold and

the EN pin must be higher than its 0.85 V threshold. This

initiates a system start-up sequence. If either UVLO or EN is

less than its respective threshold, the ADP3193A is disabled.

This holds the PWM outputs at ground, shorts the DELAY

OD

connected to the

OD

inputs of the ADP3120A drivers. Grounding

disables the drivers such that both DRVH and DRVL are

grounded. This feature is important in preventing the discharge

of the output capacitors when the controller is shut off. If the

driver outputs are not disabled, a negative voltage can be generated

during output due to the high current discharge of the output

capacitors through the inductors.

OD

capacitor to ground, and forces PWRGD and

signals low.

Rev. 0 | Page 13 of 32

ADP3193A

Table 4. VR11 and VR10.x VID Codes for the ADP3193A

VR11 DAC Codes: VIDSEL = High

VR10.x DAC Codes: VIDSEL = Low

Output

Off

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

N/A

1

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Rev. 0 | Page 14 of 32

ADP3193A

VR11 DAC Codes: VIDSEL = High

VR10.x DAC Codes: VIDSEL = Low

Output

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

Off

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

N/A

Off

N/A

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Rev. 0 | Page 15 of 32

ADP3193A

VR11 DAC Codes: VIDSEL = High

VR10.x DAC Codes: VIDSEL = Low

Output

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

N/A

Rev. 0 | Page 16 of 32

ADP3193A

VR11 DAC Codes: VIDSEL = High

VR10.x DAC Codes: VIDSEL = Low

Output

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

Off

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

N/A

1

0

1

Off

Rev. 0 | Page 17 of 32

ADP3193A

9

0 0 2 - 6 5 0 6

0 2 1 1 D 0 T N N

Q 4

0 2 1 1 D 0 T N N

Q 3

4 1 4 8 1 4 N , D

4 1 4 8 1 2 N , D

4 1 4 8 1 3 N , D

O D

G N

P M O C S C

C S S U

F E C S R

D A J P M R A

5 D V I

4 D V I

3 D V I

2 D V I

1 D V I

D 0 V I

D

M

Figure 10. Typical 3-Phase Application Circuit

Rev. 0 | Page 18 of 32

ADP3193A

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 11 compliant

CPU application are as follows:

CURRENT-LIMIT LATCH-OFF DELAY TIMES

The start-up and current-limit delay times are determined by

the capacitor connected to the DELAY pin. The first step is to

set C_DLYfor the TD1, TD3, and TD5 delay times (see Figure 7).

The DELAY ramp (I_DELAY) is generated using a 15 μA internal

current source. The value for C_DLYcan be approximated using

•

Input voltage (V_IN) = 12 V

VID setting voltage (V_VID) = 1.400 V

Duty cycle (D) = 0.117

Nominal output voltage at no load (V_ONL) = 1.381 V

Nominal output voltage at 65 A load (V_OFL) = 1.316 V

Static output voltage drop based on a 1.0 mΩ load line (R_O)

TD(x)

V_DELAY(TH)

C_DLY= I_DELAY

×

(3)

from no load to full load (V_D) = V_ONL− V_OFL

1.381 V − 1.316 V = 65 mV

Maximum output current (I_O) = 65 A

Maximum output current step (ΔI_O) = 50 A

Maximum output current slew rate (S_R) = 200 A/μs

Number of phases (n) = 3

Switching frequency per phase (f_SW) = 330 kHz

=

where:

TD(x) is the desired delay time for TD1, TD3, and TD5.

V_DELAY(TH)is the DELAY threshold voltage and is given as 1.7 V.

•

In this example, 2 ms is chosen for all three delay times, which

meets Intel specifications. Solving for C_DLYresults in a value of

17.6 nF. The closest standard value for C_DLYis 18 nF.

SETTING THE CLOCK FREQUENCY

When the ADP3193A surpasses the current limit, the internal

current source changes from 15 μA to 3.75 μA. As a result, the

latch-off delay time becomes four times longer than the start-up

delay time. Note that longer latch-off delay times can be achieved

The ADP3193A uses a fixed-frequency control architecture.

The frequency is set by an external timing resistor (R_T). The

clock frequency and the number of phases determine the switching

frequency per phase, which relates directly to switching losses as

well as to the sizes of the inductors, the input capacitors, and the

output capacitors. With n = 3 for three phases, a clock frequency

of 990 kHz sets the switching frequency (f_SW) of each phase to

330 kHz, which represents a practical trade-off between the

switching losses and the sizes of the output filter components.

Figure 3 shows that to achieve a 990 kHz oscillator frequency,

the correct value for R_Tis 169 kΩ (closest 1% resistor is 169 kΩ).

Alternatively, the value for R_Tcan be calculated using

by placing a resistor in parallel with C_DLY

.

INDUCTOR SELECTION

The choice of inductance for the inductor determines the ripple

current in the inductor. Less inductance leads to more ripple

current, which increases the output ripple voltage and conduction

losses in the MOSFETs. However, using smaller inductors allows

the converter to meet a specified peak-to-peak transient deviation

with less total output capacitance. Conversely, a higher inductance

means lower ripple current and reduced conduction losses, but

more output capacitance is required to meet the same peak-to-

peak transient deviation.

1

(1)

R_T

=

n × f_SW× 6 pF

where 6 pF is the internal IC component values. For good initial

accuracy and frequency stability, a 1% resistor is recommended.

In any multiphase converter, a practical value for the peak-to-

peak inductor ripple current is less than 50% of the maximum

dc current in the same inductor. Equation 4 shows the relationship

between the inductance, oscillator frequency, and peak-to-peak

ripple current in the inductor.

SOFT START DELAY TIME

The value of C_SSsets the soft start time. The ramp is generated

with a 15 μA internal current source. The value for C_SScan be

found using

V_VID

×

(

1− D

)

(4)

I_R

=

f_SW× L

TD2

V_BOOT

(2)

C_SS=15μA×

Equation 5 can be used to determine the minimum inductance

based on a given output ripple voltage.

where TD2 is the desired soft start time, and V_BOOTis internally

set to 1.1 V.

V_VID× R_O

×

(

1−

(n×D)

)

(5)

L ≥

f_SW×V_RIPPLE

Assuming a desired TD2 time of 1.4 ms, C_SSis 19 nF. The closest

standard value for C_SSis 18 nF. Although C_SSalso controls the time

delay for TD4 (determined by the final VID voltage), the minimum

specification for TD4 is 0 ns. This means that as long as the TD2

time requirement is met, TD4 is within the specification.

Rev. 0 | Page 19 of 32

ADP3193A

Selecting a Standard Inductor

Solving Equation 5 for an output ripple voltage of 10 mV p-p yields

The following power inductor manufacturers can provide design

consultation and upon request deliver power inductors optimized

for high power applications.

1.4 V ×1.0 mꢀ × 1− 0.35

( )

L ≥

= 276 nH

330 kHz ×10 mV

If the resulting ripple voltage is less than what is designed for,

the inductor can be made smaller until the ripple value is met.

This allows optimal transient response and minimum output

decoupling.

•

Coilcraft, Inc.

Coiltronics

Sumida Corporation

CURRENT SENSE AMPLIFIER

The smallest possible inductor should be used to minimize the

number of output capacitors. Choosing a 320 nH inductor is a

good choice for a starting point, and it provides a calculated

ripple current of 11.7 A. The inductor should not saturate at the

peak current of 27.6 A, and it should be able to handle the sum

of the power dissipation caused by the average current of 21.7 A

in the winding and core loss.

Most designs require the regulator output voltage measured at

the CPU pins to droop when the output current increases. The

specified voltage drop corresponds to a dc output resistance (R_O),

also referred to as a load line.

The output current is measured by summing the voltage across

each inductor and passing the signal through a low-pass filter. This

summer filter is the CS amplifier configured with Resistor R_PH(x)

(summer) and Resistors R_CSand C_CS(filters). The impedance gain

of the regulator is set by the following equations, where R_Lis the

DCR of the output inductors:

Another important factor in the inductor design is the dc resistance

(DCR), which is used for measuring the phase currents. Too large

of a DCR causes excessive power losses, whereas too small of a

value leads to increased measurement error. A good rule is to

have the DCR (R_L) be about 1× to 1½× the droop resistance (R_O).

This example uses an inductor with a DCR of 1.4 mΩ.

R_CS

R_PH

( )

x

R_O=

× R_L

(6)

(7)

Designing an Inductor

L

C_CS

=

After the inductance and DCR are known, the next step is

either to design an inductor or to find a standard inductor that

best meets the overall design goals. It is also important to have

the inductance and DCR tolerance specified to control the accuracy

of the system. Reasonable tolerances that most manufacturers

can meet are 20% inductance and 7% DCR at room temperature.

R_L× R_CS

The user has the flexibility to choose either R_CSor R_PH(x). However,

it is best to select R_CSequal to 100 kΩ, and then solve for R_PH(x)

by rearranging Equation 6. In the following example, R_O= 1 mΩ

to equal the design load line.

R_L

R_O

The first decision in designing the inductor is choosing the core

material. Several possibilities for providing low core loss at high

frequencies include the powder cores (from Micrometals, Inc., for

example, or Kool-Mu® from Magnetics®) and the gapped soft ferrite

cores (for example, 3F3 or 3F4 from Philips). Low frequency

powdered iron cores should be avoided due to their high core

loss, especially when the inductor value is relatively low and the

ripple current is high.

R_PH

=

× R_CS

(

x

)

1.4 mꢀ

1.0 mꢀ

R_PH

=

×100 kꢀ = 140 kꢀ

(

x

)

Next, use Equation 7 to solve for C_CS.

320 nH

C_CS

=

= 2.28 nF

1.4 mꢀ ×100 kꢀ

The best choice for a core geometry is a closed-loop type of

inductor, such as a potentiometer core; a PQ, U, or E core; or a

toroid. A good compromise between price and performance is a

core with a toroidal shape.

It is best to include two locations for C_CSin the layout so that

standard values can be used in parallel to better achieve the

desired value. For best accuracy, C_CSshould be a 5% or 10%

NPO capacitor. This example uses a 5% combination for C_CS

of two 1 nF capacitors in parallel. Recalculating R_CSand R_PH(x)

using this capacitor combination yields 114 kΩ and 160 kΩ.

The closest standard 1% value for R_PH(x)is 158 kΩ.

Many useful magnetics design references are available for

quickly designing a power inductor, such as

•

Magnetic Designer Software from Intusoft

Designing Magnetic Components for High Frequency DC-

DC Converters, by William T. McLyman, K G Magnetics,

Inc., ISBN 1883107008

Rev. 0 | Page 20 of 32

ADP3193A

4. Compute the relative values for R_CS1, R_CS2, and R_THusing

INDUCTOR DCR TEMPERATURE CORRECTION

When the inductor DCR is used as the sense element and

copper wire is used as the source of the DCR, the user needs to

compensate for temperature changes of the inductor’s winding.

Fortunately, copper has a well-known temperature coefficient (TC)

of 0.39%/°C.

(

A − B

)

× r × r₂− A ×

(

1− B

(

)

× r₂+ B ×

× r₂−

(

1− A

)

× r

1

)

1

r_CS2

=

(8)

(9)

A ×

(1− B

)

× r − B × 1− A

)

(

A − B

1

(

1− A

)

r_CS1

1

A

−

1−r_CS2r₁−r_CS2

If R_CSis designed to have an opposite and equal percentage of

change in resistance to that of the wire, it cancels the tempera-

ture variation of the inductor DCR. Due to the nonlinear nature of

negative temperature coefficient (NTC) thermistors, Resistors R_CS1

and R_CS2are needed. See Figure 11 to linearize the NTC and

produce the desired temperature tracking.

1

r_TH

=

(10)

1

−

1−r_CS2r_CS1

Calculate R_TH= r_TH× R_CS, and then select the closest value

thermistor available. In addition, compute a scaling factor (k)

based on the ratio of the actual thermistor value used relative

to the computed one.

PLACE AS CLOSE AS POSSIBLE

TO NEAREST INDUCTOR

TO

SWITCH

NODES

TO

VOUT

SENSE

OR LOW-SIDE MOSFET

R

TH

R_TH

(

ACTUAL)

k =

(11)

R_TH

(

CALCULATED

)

R

PH3

PH1

PH2

ADP3193A

5. Calculate values for R_CS1and R_CS2using Equation 12 and

Equation 13.

R

CS2

CS1

CSCOMP

13

C

CS2

KEEP THIS PATH

CS1

R_CS1= R_CS× k × r_CS1

(12)

(13)

AS SHORT AS POSSIBLE

AND WELL AWAY FROM

SWITCH NODE LINES

CSSUM

CSREF

12

R_CS2= R_CS

×

(

1−k

)

+

(

k × r_CS2

))

11

In this example, R_CSis calculated to be 114 kΩ. Look for an

available 100 kΩ, 0603-size thermistor. One such thermistor

is the Vishay NTHS0603N01N1003JR NTC thermistor with

Figure 11. Temperature-Compensation Circuit Values

A = 0.3602 and B = 0.09174. From these values, r_CS1= 0.3795,

r_CS2= 0.7195, and r_TH= 1.075.

The following procedure and equations yield values to use for

R_CS1, R_CS2, and R_TH(the thermistor value at 25°C) for a given

R_CSvalue.

Solving for R_THyields 122.55 kΩ; therefore, 100 kΩ is chosen,

making k = 0.816. Next, find R_CS1and R_CS2to be 35.3 kΩ and

87.9 kΩ. Finally, choose the closest 1% resistor values, which

yields a choice of 35.7 kΩ and 88.7 kΩ.

1. Select an NTC based on type and value. Because the value

is unknown, use a thermistor with a value close to R_CS. The

NTC should also have an initial tolerance of better than 5%.

OUTPUT OFFSET

2. Based on the type of NTC, find its relative resistance

value at two temperatures. The temperatures that work

well are 50°C and 90°C. These resistance values are called

A (R_TH(50°C))/R_TH(25°C)) and B (R_TH(90°C))/R_TH(25°C)). The relative

value of the NTC is always 1 at 25°C.

The Intel specification requires that with no load the nominal

output voltage of the regulator be offset to a value lower than the

nominal voltage corresponding to the VID code. The offset is

set by a constant current source flowing out of the FB pin (I_FB)

and flowing through R_B. The value of R_Bcan be found using

Equation 14.

3. Find the relative value of R_CSrequired for each of these

temperatures. This is based on the percentage of change

needed, which in this example is initially 0.39%/°C. These

temperatures are called r₁(1/(1 + TC × (T₁− 25°C)))

and r₂(1/(1 + TC × (T₂− 25°C))), where TC = 0.0039 for

copper, T₁= 50°C, and T₂= 90°C. From this, r₁= 0.9112 and

r₂= 0.7978.

V_VID−V_ONL

R_B

=

(14)

I_FB

1.4 V−1.381 V

= 1.27 kꢀ

15 ꢁA

The closest standard 1% resistor value is 1.27 kΩ.

Rev. 0 | Page 21 of 32

ADP3193A

To meet the conditions of these equations and transient response,

the ESR of the bulk capacitor bank (R_X) should be less than two

times the droop resistance (R_O). If C_X(MIN)is larger than C_X(MAX)

the system cannot meet the VID on-the-fly specification and

to maintain the output ripple may require the use of a smaller

inductor or more phases (in addition to increasing the switching

frequency).

C_OUTSELECTION

The required output decoupling for the regulator is typically

recommended by Intel for various processors and platforms.

Use some simple design guidelines to determine the require-

ments. These guidelines are based on having both bulk

capacitors and ceramic capacitors in the system.

,

First, select the total amount of ceramic capacitance. This is

based on the number and type of capacitor to be used. The best

location for ceramic capacitors is inside the socket, with twelve

to eighteen 1206-size pieces being the physical limit. Other

capacitors can be placed along the outer edge of the socket as well.

This example uses twenty-six 10 μF 1206 MLC capacitors

(C_Z= 260 μF). The VID on-the-fly step change is 450 mV in

230 μs with a settling error of 2.5 mV. The maximum allowable

load release overshoot for this example is 50 mV; therefore,

solving for the bulk capacitance yields

To determine the minimum amount of ceramic capacitance

required, start with a worst-case load step that occurs immediately

after a switching cycle has stopped. The ceramic capacitance then

delivers the charge to the load while the load is ramping up until

the VR responds with the next switching cycle.

⎛

⎜

⎞

⎟

⎜

⎟

320 nH × 50 A

⎟

C_X

≤

MIN

)

−260 ꢁF =1.64 mF

(

⎛

⎜

⎝

⎞

50 mV

50 A

⎟

⎜

⎟

⎠

3× 1.0 mꢀ+

×1.4 V

⎜

⎟

⎝

⎠

Equation 15 provides the designer with a rough approximation

for determining the minimum ceramic capacitance. Due to the

complexity of the PCB parasitics and bulk capacitors, the actual

amount of ceramic capacitance required can vary.

320 nH × 450 mV

3× 5.2²× ²×1.4 V

1.0 mꢀ

≤

)

×

MAX

(

)

2

⎛

⎜

⎞

⎟

⎡

⎢

⎣

⎤

⎥

⎦

ΔI_O

2S_R

1

2R_O

1

f_SW

1

n

⎛

⎜

⎝

⎞

⎠

⎛

⎞

⎟

⎠

230 ꢁs ×1.4 V × 3× 5.2 ×1.0 mꢀ

450 mV × 320 nH

C_{Z(MIN )}

≥

×

− D −

(15)

⎟

⎜

⎝

1+

−1 −260 ꢁF = 42.7 mF

⎜

⎟

⎜

⎝

⎟

⎠

The typical ceramic capacitors consist of multiple 10 μF or

22 μF capacitors. For this example, Equation 15 yields 265 μF,

so twenty-six 10 ꢁF ceramic capacitors suffice.

where k = 5.2.

Using eight 560 μF aluminum-poly capacitors with a typical

ESR of 6 mΩ each yields C_X= 4.48 mF with an R_X= 0.75 mΩ.

Next, there is an upper limit imposed on the total amount of bulk

capacitance (C_X), considering the VID on-the-fly voltage stepping

of the output (voltage step, V_V, in time, t_V, with error of V_ERR).

One last check should be made to ensure that the ESL of the

bulk capacitors (L_X) is low enough to limit the high frequency

ringing during a load change.

A lower limit is based on meeting the capacitance for load

release at a given maximum load step (ꢂI_O) and a maximum

allowable overshoot. The total amount of load release voltage

is ΔV_O= ΔI_O× R_O+ ΔV_rl, where ΔV_rlis the maximum allowable

overshoot voltage.

This is tested using

L_X≤ C_Z× R_O²× Q²

(18)

4

3

2

⎛

⎜

⎞

⎟

L_X≤ 260 ꢁF ×

(

1 mꢀ

)

×

= 347 pH

⎜

⎟

L × ꢂ I_O

ΔV_rl

where Q²is limited to ⁴/₃to ensure a critically damped system.

C_X

≥

MIN

)

−C_Z

(16)

(

⎛

⎞

⎟

⎠

⎜

n × R_O+

×V_VID

⎜

⎝

⎟

⎠

In this example, L_Xis approximately 240 pH for the eight

aluminum-poly capacitors, which satisfies this limitation. If the

L_Xof the chosen bulk capacitor bank is too large, the number of

ceramic capacitors needs to be increased, or lower ESL bulks

need to be used if there is excessive undershoot during a load

transient.

ΔI_O

⎝

2

⎛

⎞

⎛

⎞

⎟

⎠

V_V

V_VIDnKR_O

V_V

L

⎜

⎟

⎜

C_X

≤

)

×

1+ t_V

×

− 1 −C_Z

MAX

⎜

⎝

⎟

nk²R_O²V_VID

L

⎜

⎝

⎟

⎠

(17)

⎛

⎜

⎝

⎞

⎟

⎠

V_ERR

V_V

For this multimode control technique, all ceramic designs can

be used if the conditions of Equation 15 through Equation 18

are satisfied.

where k = −ln

.

Rev. 0 | Page 22 of 32

ADP3193A

POWER MOSFETS

MOSFET input capacitance, the following expression provides

an approximate value for the switching loss per main MOSFET:

For our example, the N-channel power MOSFETs have been

selected for one high-side switch and two low-side switches per

phase. The main selection parameters for the power MOSFETs

are V_GS(TH), Q_G, C_ISS, C_RSS, and R_DS(ON). The minimum gate drive

voltage (the supply voltage to the ADP3120A) dictates whether

standard threshold or logic-level threshold MOSFETs must be

used. With V_GATE~10 V, logic-level threshold MOSFETs

(V_GS(TH)< 2.5 V) are recommended.

V_CC× I_O

n_MF

n

P_S

= 2 × f_SW

MF )

×

× R_G×

×C_ISS

(20)

(

n_MF

where:

_MFis the total number of main MOSFETs.

n

R_Gis the total gate resistance (2 Ω for the ADP3120A and about

1 Ω for typical high speed switching MOSFETs, making R_G= 3 Ω).

C

_ISSis the input capacitance of the main MOSFET.

The maximum output current (I_O) determines the R_DS(ON)

requirement for the low-side (synchronous) MOSFETs. With

the ADP3193A, currents are balanced between phases; therefore,

the current in each low-side MOSFET is the output current divided

by the total number of MOSFETs (n_SF). With conduction losses

being dominant, Equation 19 shows the total power that is

dissipated in each synchronous MOSFET in terms of the ripple

current per phase (I_R) and the average total output current (I_O):

Adding more main MOSFETs (n_MF) does not help the switching

loss per MOSFET because the additional gate capacitance slows

switching. Use lower gate capacitance devices to reduce

switching loss.

The conduction loss of the main MOSFET is given by the

following:

2

⎛ n× I_R⎞²

n_MF

2

⎡

⎢

⎤

⎥

⎡

⎢

⎤

⎥

⎛

⎜

⎝

⎞

⎟

⎠

I_O

n_MF

1

12

n I

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

I_O

n_SF

1

12

R

⎜

⎝

⎟

⎠

P_C₎= D ×

+

×

×R_DS

(MF )

(21)

P_SF

=

(1− D

)

×

+

×

×R_DS

(19)

(

MF

(

SF )

⎢

⎣

⎥

⎦

n_SF

⎢

⎣

⎥

⎦

where R_DS(MF)is the on resistance of the MOSFET.

Knowing the maximum output current being designed for and

the maximum allowed power dissipation, the user can find the

required R_DS(ON)for the MOSFET. For D-PAK MOSFETs up to

an ambient temperature of 50°C, a safe limit for P_SFis 1 W to

1.5 W at 120°C junction temperature. Therefore, for this example

(56 A maximum), R_DS(SF)(per MOSFET) is less than 4.7 mΩ. This

R_DS(SF)is also at a junction temperature of about 120°C. As a result,

users need to account for this when making this selection. This

example uses two low-side MOSFETs at 4.8 mΩ, each at 120°C.

Typically, for main MOSFETs, the highest speed (low C_ISS)

device is preferred, but such devices usually have higher on

resistance. Select a device that meets the total power dissipation

(about 1.5 W for a single D-PAK) when combining the switching

and conduction losses.

For this example, an NTD40N03L is selected as the main MOSFET

(three total, n_MF= 3), with C_ISS= 584 pF (maximum) and R_DS(MF)

=

19 mΩ (maximum at T_J= 120°C). An NTD110N02L is selected as

the synchronous MOSFET (three total, n_SF= 3), with C_ISS= 2710 pF

(maximum) and R_DS(SF)= 4.8 mΩ (maximum at T_J= 120°C). The

synchronous MOSFET C_ISSis less than 6000 pF, satisfying this

requirement.

Another important factor for the synchronous MOSFET is the

input capacitance and feedback capacitance. The ratio of the

feedback to the input must be small (less than 10% is recom-

mended) to prevent accidentally turning on the synchronous

MOSFETs when the switch node goes high.

Solving for the power dissipation per MOSFET at I_O= 56 A and

I_R= 11.7 A yields 1.53 W for each synchronous MOSFET and

1.06 W for each main MOSFET. As a guide, limit the MOSFET

power dissipation to 1.5 W. The values calculated in Equation 20

and Equation 21 will comply with this guideline.

In addition, the time to switch the synchronous MOSFETs off

should not exceed the nonoverlap dead time of the MOSFET

driver (45 ns typical for the ADP3120A). The output impedance

of the driver is approximately 2 Ω, and the typical MOSFET

input gate resistances are about 1 Ω to 2 Ω. Therefore, a total

gate capacitance of less than 6000 pF should be adhered to.

Because two MOSFETs are in parallel, the input capacitance for

each synchronous MOSFET should be limited to 6000 pF.

Finally, consider the power dissipation in the driver for each

phase. This is best expressed as Q_Gfor the MOSFETs and is

given by Equation 22.

The high-side (main) MOSFET must be able to handle two

main power dissipation components: conduction and switching

losses. The switching loss is related to the amount of time for

the main MOSFET to turn on and off and to the current and

voltage that are being switched. Basing the switching speed on

the rise and fall times of the gate driver impedance and

⎡

⎢

⎤

f_SW

2 ×n

P_DRV

=

×

(

n_MF×Q_GMF+ n_SF×Q_GSF

)

+ I_CC×V (22)

⎥

CC

⎢

⎣

⎥

⎦

where Q_GMFis the total gate charge for each main MOSFET, and

_GSFis the total gate charge for each synchronous MOSFET

Q

Also shown is the standby dissipation factor (I_CC× V_CC) of the

driver. For the ADP3120A, the maximum dissipation should be

Rev. 0 | Page 23 of 32

ADP3193A

less than 400 mW. In this example, with I_CC= 7 mA, Q_GMF= 5.8 nC,

and Q_GSF= 48 nC, there is 191 mW in each driver, which is below

the 400 mW dissipation limit. See the ADP3120A data sheet for

more details.

CURRENT-LIMIT SETPOINT

To select the current-limit setpoint, first find the resistor value

for R_LIM. The current-limit threshold for the ADP3193A is set with

a constant current source flowing out of the ILIMIT pin, which

sets up a voltage (V_LIM) across R_LIMwith a gain of 82.6 mV/V (A_LIM).

Therefore, increasing R_LIMnow increases the current limit. R_LIM

can be found using the following equation:

RAMP RESISTOR SELECTION

The ramp resistor (R_R) is used for setting the size of the internal

PWM ramp. The value of this resistor should be chosen to provide

the best combination of thermal balance, stability, and transient

response. Equation 23 is used for determining the optimum value.

V_CL

I

_LIM×R_CSA

82.6 mV

R_LIM

=

×R_REF

(26)

A_LIM× I_ILIMIT

A_R× L

In this equation, I_LIMis the peak average current limit for the

supply output and is equal to the dc current limit plus the

output ripple current. In this example, choosing a dc current

limit of 88.3 A and having a ripple current of 11.7 A yields an

I_LIMof 100 A, resulting in an R_LIMof 121 kΩ, for which 121 kΩ

is chosen as the nearest 1% value.

R_R

=

(23)

3 × A_D× R_DS× C_R

0.2 × 320 nH

=

=178 kꢀ

3 × 5 × 4.8 mꢀ × 5 pF

where:

A_Ris the internal ramp amplifier gain.

A_Dis the current-balancing amplifier gain.

The per-phase initial duty cycle limit and peak current during a

load step are determined by

R_DSis the total low-side MOSFET on resistance.

V_COMP

−V_BIAS

MAX )

(

C_Ris the internal ramp capacitor value.

(27)

(28)

D_MAX= D ×

V_RT

The internal ramp voltage magnitude can be calculated as follows:

D_MAX

f_SW

(

V_IN−V_VID

×

)

I_PHMAX

≅

A_R×

(

1− D

R_R× C_R× f_SW

0.2 × 1−0.117

178 kꢀ × 5 pF × 330 kHz

)×V_VID

L

(24)

V_R

=

For the ADP3193A, the maximum COMP voltage (V_COMP(MAX)

)

(

)

×1.4 V

is 3.4 V, and the COMP pin bias voltage (V_BIAS) is 1.1 V. In this

example, the maximum duty cycle is 0.23. Because this is small

due to the V_RTbeing much larger than 0.5 V, reduce the ramp

resistor to get closer to 0.5 V V_RTand to obtain a larger duty

cycle. Choosing a ramp resistor of 267 kΩ results in a V_RTof

0.79 V, a D_MAXof 0.34, and a peak current of 34 A.

= 842 mV

The size of the internal ramp can be increased or decreased. If it is

increased, stability and noise rejection improve, but the transient

response degrades. Conversely, if the ramp size is decreased, the

transient response improves, but noise rejection and stability

degrade.

The limit of the peak per-phase current during the secondary

current limit is determined by

In the denominator of Equation 23, the factor of 3 sets a ramp

size that produces an optimal balance for good stability, transient

response, and thermal balance.

V_COMP

−V_BIAS

CLAMPED

)

(

(29)

I_PHLIM

≅

A_D× R_DS

(

MAX )

COMP PIN RAMP

For the ADP3193A, the current balancing amplifier gain (A_D) is 5

and the clamped COMP pin voltage is 2 V. Using an R_DS(MAX)of

5.6 mΩ (low-side on resistance at 150°C) results in a per-phase

peak current limit of 36 A. This current level can be reached only

with an absolute short at the output, and the current-limit latch-off

function shuts down the regulator before overheating can occur.

In addition to the internal ramp, there is a ramp signal on the

COMP pin due to the droop voltage and output voltage ramps.

This ramp amplitude adds to the internal ramp to produce the

following overall ramp signal at the PWM input:

V_R

V_RT

=

(25)

⎛

⎜

⎝

⎞

⎟

⎠

2×

(

1−n × D

)

1−

n × f_SW×C_X× R_O

In this example, the overall ramp signal is 1.19 V. However,

if the ramp size is smaller than 0.5 V, increase the ramp size

to be at least 0.5 V by decreasing the ramp resistor for noise

immunity.

Rev. 0 | Page 24 of 32

ADP3193A

output impedance works in parallel with the output decoupling

to make the load look entirely resistive. In addition, it is necessary

to compensate for several poles and zeros created by the output

inductor and the decoupling capacitors (output filter).

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3193A allows the best

possible response of the regulator’s output to a load change. The

basis for determining the optimum compensation is to make the

regulator and output decoupling appear as an output impedance

that is entirely resistive over the widest possible frequency range,

including dc, and that is equal to the droop resistance (R_O). With

the resistive output impedance, the output voltage droops in

proportion to the load current at any load current slew rate.

This ensures optimal positioning and minimizes the output

decoupling.

A Type III compensator on the voltage feedback is adequate for

proper compensation of the output filter.

Equation 30 to Equation 34 are intended to yield an optimal

starting point for the design; some adjustments may be necessary

to account for PCB and component parasitic effects (see the

Tuning Procedure for ADP3193A section).

First, compute the time constants for all the poles and zeros in

the system using Equation 30 to Equation 34.

Because of the multimode feedback structure of the ADP3193A, it

is necessary to set the feedback compensation so that the converter

R_L×V_RT2×L ×

(

1−n × D ×V_RT

)

(30)

R_E= n × R_O+ A_D× R_DS

+

V_VID

n × C_X× R_O×V_VID

1.4 mꢀ × 0.79 V 2 × 320 nH ×

(

1−0.35

)

× 0.79 V

R_E= 3 ×1 mꢀ + 5 × 4.8 mꢀ +

+

= 45.3 mꢀ

1.4 V

R_O− R'

R_X

0.75 mꢀ + 0.5 mꢀ −1 mꢀ

3 × 4.48 mF ×1 mꢀ ×1.4 V

347 pH 1 mꢀ −0.5mꢀ

L_X

R_O

T_A= C_X

×

(

R_O− R'

)

+

×

=

= 4.48 mF ×

(

1 mꢀ −0.5 mꢀ

)

+

×

= 2.47 ꢁs

(31)

(32)

1 mꢀ

× 4.48 mF =1120 ns

0.75mꢀ

T_B=

(

R_X+ R' − R_O

)

× C_X

(

)

⎛

⎞

⎛

⎞

⎟

⎠

A_D× R_DS

2 × f_SW

5 × 4.8 mꢀ

2 × 330 kHz

⎜

⎟

⎠

⎜

V_RT× L −

0.79 V × 320 nH−

⎜

⎝

T_C=

=

= 3.53 ꢁs

(33)

(34)

V_VID× R_E

C_X× C_Z× R_O²

R_O− R' +C_Z× R_O4.48 mF ×

1.4 V × 45.3 mꢀ

4.48 mF × 260 ꢁF ×

1 mꢀ − 0.5mꢀ

2

(

1 mꢀ

)

T_D

=

= 466 ns

C_X

×

(

)

(

)

+ 260 ꢁF ×1 mꢀ

where:

R' is the PCB resistance from the bulk capacitors to the ceramics and is approximately 0.5 mΩ (assuming a 4-layer, 1 oz motherboard).

_DSis the total low-side MOSFET on resistance per phase.

A_D= 5.

_RT= 0.79 V.

L_X= 347 pH for the eight aluminum-poly capacitors.

R

V

Rev. 0 | Page 25 of 32

ADP3193A

C_INSELECTION AND INPUT CURRENT

di/dt REDUCTION

The compensation values can then be solved using

n× R_O×T_A3×1mꢀ × 2.47 ꢁs

C_A=

R_A=

C_B=

=

=128 pF

(35)

(36)

(37)

(38)

In continuous inductor current mode, the source current of the

high-side MOSFET is approximately a square wave with a duty

ratio equal to n × V_OUT/V_INand an amplitude of one-n^ththe

maximum output current. To prevent large voltage transients,

use a low ESR input capacitor sized for the maximum rms

current. The maximum rms capacitor current is given by

R_E× R_B

3.53ꢁs

45.3mꢀ ×1.27 kꢀ

T_C

=

= 27.5 kꢀ

C_A128 pF

T_B

1120ns

=

= 882 pF

=16.9 pF

R_B1.27 kꢀ

1

I_CRMS= D × I_O

×

−1

(39)

T_D

466ns

N × D

C_FB

=

R_A27.5 kꢀ

1

I_CRMS= 0.117 × 65A ×

− 1 =10.3A

These equations result in the starting values prior to tuning the

design that account for layout and other parasitic effects (see

the Tuning Procedure for ADP3193A section). The final values

selected after tuning are

3 × 0.117

The capacitor manufacturer’s ripple-current ratings are often

based on only 2000 hours of life. As a result, it is advisable to

further derate the capacitor or to choose a capacitor rated at a

higher temperature than is required. Several capacitors can be

placed in parallel to meet size or height requirements in the

design. In this example, the input capacitor bank is formed by

two 2700 μF, 16 V aluminum electrolytic capacitors and eight

4.7 μF ceramic capacitors.

C_A= 220 pF

R_A= 22.1 kΩ

C_B= 560 pF

C_FB= 15 pF

Figure 12 and Figure 13 show the typical transient response

using these compensation values.

To reduce the input current, di/dt, to a level below the recom-

mended maximum of 0.1 A/μs, an additional small inductor

(L > 370 nH at 18 A) should be inserted between the converter

and the supply bus. This inductor also acts as a filter between

the converter and the primary power source.

SHUNT RESISTOR DESIGN

The ADP3193A uses a shunt to generate 5 V from the 12 V

supply range. A trade-off can be made between the power

dissipated in the shunt resistor and the UVLO threshold.

Figure 14 shows the typical resistor value needed to realize

certain UVLO voltages and the maximum power dissipated in

the shunt resistor for these UVLO voltages.

20mV/DIV

550

500

450

400

350

300

250

200

150

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

2µs/DIV

Figure 12. Typical Transient Response for Design Example Load Step

P

R

SHUNT

7.0

7.5

8.0

8.5

9.0

(UVLO)

9.5

10.0

10.5

11.0

20mV/DIV

V

IN

Figure 14. Typical Shunt Resistor Value and Power Dissipation

for Different UVLO Voltages

2µs/DIV

Figure 13. Typical Transient Response for Design Example Load Release

Rev. 0 | Page 26 of 32

ADP3193A

The maximum power dissipated is calculated using Equation 40.

2. Measure the output voltage with a full load when the

device is cold (V_FLCOLD). Allow the board to run for ~10

minutes at full load, and then measure the output when the

device is hot (V_FLHOT). If the difference between the two

measured voltages is more than a few millivolts, adjust R_CS1

and R_CS2using Equation 41 and Equation 43.

2

(

V

_IN(MAX)−V_CC(MIN)

)

P_MAX

=

(40)

R_SHUNT

where:

_IN(MAX)is the maximum voltage from the 12 V input supply

(if the 12 V input supply is 12 V 5%, V_IN(MAX)= 12.6 V;

if the 12 V input supply is 12 V 10%, V_IN(MAX)= 13.2 V).

V

V_NL−V_FLCOLD

(41)

R_CS2

= R_CS2

×

OLD )

(

NEW

)

(

V_NL−V_FLHOT

V

_CC(MIN)is the minimum V_CCvoltage of the ADP3193A. This is

specified as 4.75 V.

_SHUNTis the shunt resistor value.

3. Repeat Step 2 until no adjustment of R_CS1and R_CS2is needed.

R

4. Compare the output voltage with no load to that with a full

load using 5 A steps. Compute the load line slope for each

change, and then calculate the average to determine the

overall load line slope (R_OMEAS).

The CECC standard specification for power rating in surface-

mount resistors is 0.1 W for 0603-size resistors, 0.125 W for 0805-

size resistors, and 0.25 W for 1206-size resistors.

5. If the difference between R_OMEASand R_Ois more than 0.05 mΩ,

use Equation 42 to adjust the R_PHvalues.

TUNING PROCEDURE FOR ADP3193A

Set Up and Test the Circuit

R_OMEAS

1. Build a circuit based on the compensation values

computed from the design spreadsheet.

(42)

R_PH

= R_PH

×

OLD )

(

NEW

)

(

R_O

2. Connect a dc load to the circuit.

3. Turn on the ADP3193A and verify that it operates properly.

4. Check for jitter with no load and full load conditions.

6. Repeat Step 6 and Step 7 until no adjustment of R_PHis needed.

Once this is achieved, do not change R_PH, R_CS1, R_CS2, or R_TH

for the remainder of the procedure.

Set the DC Load Line

7. Measure the output ripple with no load and with a full load

with scope, making sure both are within specifications.

1. Measure the output voltage with no load (V_NL) and verify

that it is within the specified tolerance range.

1

R_CS1(NEW)

=

(43)

R

_CS1(OLD)+ R_TH(25°C)

1

−

R

_CS1(OLD)×R_TH(25°C)+(R_CS1(OLD)−R_CS2(NEW))×(R_CS1(OLD)− R_TH(25°C)

)

R_TH(25°C)

Rev. 0 | Page 27 of 32

ADP3193A

one minor undershoot before achieving the final desired

value after V_DROOP(see Figure 16).

Set the AC Load Line

1. Remove the dc load from the circuit and connect the

dynamic load.

2. Connect the scope to the output voltage and set it to dc-

coupling mode with the time scale of 100 μs/div.

V

DROOP

3. Set the dynamic load for a transient step of about 40 A at

1 kHz with 50% duty cycle.

4. Measure the output waveform. (Note that use of a dc offset

on the scope may be necessary to see the waveform.) Try to

use a vertical scale of 100 mV/div or finer. This waveform

should look similar to Figure 15.

V

TRAN1

V

TRAN2

Figure 16. Transient Setting Waveform

2. If both overshoots are larger than desired, try the following

adjustments in the order shown:

V

ACDRP

•

Increase the ramp resistor by 25% (R_RAMP).

For V_TRAN1, increase C_Bor increase the switching

frequency.

V

DCDRP

•

For V_TRAN2, increase R_Aby 25% and decrease C_Aby 25%.

If these adjustments do not change the response, it is

because the system is limited by the output decoupling.

Check the output response and the switching nodes each

time a change is made to ensure that the response is stable.

Figure 15. AC Load Line Waveform

5. Use the horizontal cursors to measure V_ACDRPand V_DCDRP

,

3. For load release (see Figure 17), if V_TRANRELis larger than

the allowed overshoot, there is not enough output

capacitance. Either increase the capacitance directly or

decrease the inductor values. If the inductors are changed,

however, it will be necessary to redesign the circuit using

the information from the spreadsheet and to repeat all

tuning guide procedures.

as shown in Figure 15. Do not measure the undershoot or

overshoot that occurs immediately after this step.

6. If the difference between V_ACDRPand V_DCDRPis more than

a few millivolts, use Equation 44 to adjust C_CS. It may be

necessary to try several parallel values to obtain an adequate

one, because there are limited standard capacitor values

available. It is a good idea to have locations for two capacitors

in the layout for this reason.

V_ACDRP

V_DCDRP

(44)

C_CS

= C_CS

×

OLD )

V

(

NEW

)

(

TRANREL

V

DROOP

7. Repeat Step 5 and Step 6 until no further adjustment of C_CS

is needed. Once this is achieved, do not change C_CSfor the

remainder of the procedure.

8. Set the dynamic load step to its maximum step size (but do

not use a step size that is larger than needed) and verify

that the output waveform is square, meaning V_ACDRPand

V_DCDRPare equal.

Figure 17. Transient Setting Waveform

Set the Initial Transient

Because the ADP3193A turns off all of the phases (switches

inductors to ground), no ripple voltage is present during load

release. Therefore, the user does not have to add headroom for

ripple, which allows load release V_TRANRELto be larger than

1. With the dynamic load set at the maximum step size,

expand the scope time scale to either 2 μs/div or 5 μs/div.

This may result in a waveform that has two overshoots and

Rev. 0 | Page 28 of 32

ADP3193A

V_TRAN1by the amount of ripple while still meeting the

specifications.

Power Circuitry Recommendations

The switching power path on the PCB should be routed to

encompass the shortest possible length to minimize radiated

switching noise energy (that is, EMI) and conduction losses in

the board. Failure to take proper precautions often results in

EMI problems for the entire PC system and noise-related

operational problems in the power-converter control circuitry.

The switching power path is the loop formed by the current

path through the input capacitors and the power MOSFETs,

including all interconnecting PCB traces and planes. Using

short, wide interconnection traces is especially critical in this

path for two reasons: it minimizes the inductance in the switching

loop, which can cause high energy ringing, and it accommodates

the high current demand with minimal voltage loss.

If V_TRAN1and V_TRANRELare less than the desired final droop, this

implies that capacitors can be removed. When removing capaci-

tors, also check the output ripple voltage to ensure that it is still

within specifications.

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal

performance of a switching regulator in a PC system.

General Recommendations

For good results, a PCB with at least four layers is recommended.

This provides the needed versatility for control circuitry

interconnections with optimal placement, power planes for

ground, input and output power, and wide interconnection

traces in the remainder of the power-delivery current paths.

Keep in mind that each square unit of 1 oz copper trace has a

resistance of ~0.53 mΩ at room temperature.

When a power-dissipating component, such as a power MOSFET,

is soldered to a PCB, it is recommended to use vias liberally both

directly on the mounting pad and immediately surrounding it. Two

important reasons for this are improved current rating through

the vias and improved thermal performance from vias extended

to the opposite side of the PCB, where a plane can more readily

transfer the heat to the air. Make a mirror image on the opposite

side of the PCB of any pad being used to heat-sink the MOSFETs.

This helps achieve the best thermal dissipation in the air around

the board. To further improve thermal performance, use the largest

pad area possible.

When high currents must be routed between PCB layers, use

vias liberally to create several parallel current paths so that the

resistance and inductance introduced by these current paths are

minimized and the via current rating is not exceeded.

If critical signal lines (including the output voltage sense lines of

the ADP3193A) must cross through power circuitry, it is best to

interpose a signal ground plane between those signal lines and

the traces of the power circuitry. This serves as a shield to

minimize noise injection into the signals at the expense of

increasing signal ground noise.

The output power path should also be routed to encompass a

short distance. The output power path is formed by the current

path through the inductor, the output capacitors, and the load.

For best EMI containment, a solid power ground plane should

be used as one of the inner layers, extending fully under all the

power components.

An analog ground plane should be used around and under the

ADP3193A as a reference for the components associated with

the controller. This plane should be tied to the nearest output-

decoupling capacitor ground and should not be tied to any other

power circuitry to prevent power currents from flowing into it.

Signal Circuitry Recommendations

The output voltage is sensed and regulated between the FB and

FBRTN pins, which connect to the signal ground at the load. To

avoid differential mode noise pickup in the sensed signal, the

loop area should be small. Therefore, the FB and FBRTN traces

should be routed adjacent to each other on top of the power

ground plane back to the controller.

The components around the ADP3193A should be located close

to the controller with short traces. The most important traces to

keep short and away from other traces are those to the FB and

CSSUM pins. The output capacitors should be connected as

close as possible to the load (or connector) that receives the

power, for example, as close as possible to a microprocessor

core. If the load is distributed, the capacitors should also be

distributed and placed in greater proportion where the load

tends to be more dynamic.

The feedback traces from the switch nodes should be connected

as close as possible to the inductor, and the CSREF signal

should be connected to the output voltage at the nearest

inductor to the controller.

Avoid crossing any signal lines over the switching power path loop

(described in the Power Circuitry Recommendations section).

Rev. 0 | Page 29 of 32

ADP3193A

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

3.25

3.10 SQ

2.95

EXPOSED

PAD

(BOTTOM VIEW)

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

3.50 REF

0.80 MAX

0.65 TYP

12° MAX

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range Package Description

Package Option Ordering Quantity

ADP3193AJCPZ-RL¹0°C to 85°C

32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2

2,500

¹Z = RoHS Compliant Part.

Rev. 0 | Page 30 of 32

ADP3193A

NOTES

Rev. 0 | Page 31 of 32

ADP3193A

NOTES

registered trademarks are the property of their respective owners.

D06652-0-5/07(0)

Rev. 0 | Page 32 of 32


型号：	ADP3193A
厂家：	ADI
描述：	8-Bit, Programmable, 2- to 3-Phase, Synchronous Buck Controller 2-8位，可编程，到3相，同步降压控制器控制器
文件：	总32页 (文件大小：1025K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP3193A [ADI]

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