ADP3180 [ADI]
6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller; 6位可编程2-， 3-， 4相同步降压控制器
| 型号： | ADP3180 |
| 厂家： | 
ADI |
| 描述： | 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 文件： | 总20页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6-Bit Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller
ADP3180*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Selectable 2-, 3-, or 4-Phase Operation at up to
1 MHz per Phase
VCC
28
RAMPADJ RT
14 13
؎14.5 mVWorst-Case Differential Sensing Error over
Temperature
Logic-Level PWM Outputs for Interface to
External High Power Drivers
ADP3180
UVLO
SHUTDOWN
AND BIAS
11
EN
OSCILLATOR
Active Current Balancing between All Output Phases
Built-In Power Good/Crowbar Blanking Supports
On-the-FlyVID Code Changes
6-Bit Digitally Programmable 0.8375V to 1.6V Output
Programmable Short Circuit Protection with
Programmable Latch-Off Delay
SET EN
RESET
P
27
PWM1
19
GND
DAC
+150mV
RESET
P
26
PWM2
CSREF
CURRENT
BALANCING
CIRCUIT
2-, 3-, 4-PHASE
DRIVER LOGIC
RESET
P
25
PWM3
APPLICATIONS
DAC
Desktop PC Power Supplies for:
Next Generation Intel® Processors
VRM Modules
–250mV
P RESET
24
PWM4
10
PWRGD
DELAY
CROWBAR
CURRENT
LIMIT
GENERAL DESCRIPTION
23
SW1
The ADP3180 is a highly efficient multiphase synchronous buck
switching regulator controller optimized for converting a 12V
main supply into the core supply voltage required by high per-
formance Intel processors. It uses an internal 6-bit DAC to read
a voltage identification (VID) code directly from the processor,
which is used to set the output voltage between 0.8375V and
1.6V, and uses a multimode PWM architecture to drive the logic
level outputs at a programmable switching frequency that can be
optimized forVR size and efficiency.The phase relationship of the
output signals can be programmed to provide 2-, 3-, or 4-phase
operation, allowing for the construction of up to four comple-
mentary buck switching stages.
22
SW2
21
SW3
15
ILIMIT
20
SW4
EN
17
CSSUM
CURRENT
LIMIT
CIRCUIT
16
CSREF
12
DELAY
18
CSCOMP
SOFT-
START
The ADP3180 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a system
transient.The ADP3180 also provides accurate and reliable short
circuit protection, adjustable current limiting, and a delayed
Power Good output that accommodates on-the-fly output voltage
changes requested by the CPU.
8
9
FB
COMP
PRECISION
REFERENCE
VID
DAC
ADP3180 is specified over the commercial temperature range of
0°C to 85°C and is available in a 28-leadTSSOP package.
7
1
2
3
4
5
6
FBRTN
VID4 VID3 VID2 VID1 VID0 VID5
*Patent Pending
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed byAnalog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
andregisteredtrademarksarethepropertyoftheirrespectivecompanies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
ADP3180–SPECIFICATIONS1
(VCC = 12 V, FBRTN = GND, TA = 0؇C to 85؇C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIER
OutputVoltage Range
Accuracy
VCOMP
VFB
0.5
–14.5
3.5
+14.5 mV
V
Relative to Nominal DAC Output,
Referenced to FBRTN,
CSSUM = CSCOMP (Figure 3)
VCC = 10V to 14V
Line Regulation
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
DVFB
0.05
15.5
90
500
20
%
µA
µA
µA
MHz
V/µs
IFB
14
17
120
IFBRTN
IO(ERR)
GBW(ERR)
FB Forced toVOUT – 3%
COMP = FB
CCOMP = 10 pF
50
VID INPUTS
Input LowVoltage
Input HighVoltage
Input Current, InputVoltage Low
Input Current, InputVoltage High
Pull-Up Resistance
Internal Pull-UpVoltage
VIDTransition DelayTime2
No CPU DetectionTurn-Off
DelayTime2
VIL(VID)
VIH(VID)
IIL(VID)
IIH(VID)
RVID
0.4
V
V
0.8
35
VID(X) = 0V
VID(X) = 1.25V
–20
15
60
–30
25
115
µA
µA
kW
V
ns
ns
0.825 1.00
400
400
VID Code Change to FB Change
VID Code Change to 11111 to
PWM Going Low
OSCILLATOR
Frequency Range2
FrequencyVariation
fOSC
fPHASE
0.25
155
4
245
MHz
kHz
kHz
kHz
V
mV
µA
TA = 25°C, RT = 250 kW, 4-Phase
TA = 25°C, RT = 115 kW, 4-Phase
TA = 25°C, RT = 75 kW, 4-Phase
RT = 100 kW to GND
200
400
600
2.0
OutputVoltage
RAMPADJ OutputVoltage
RAMPADJ Input Current Range
VRT
VRAMPADJ
IRAMPADJ
1.9
–50
0
2.1
+50
100
RAMPADJ – FB
CURRENT SENSE AMPLIFIER
OffsetVoltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
Input Common-Mode Range
Positioning Accuracy
OutputVoltage Range
Output Current
VOS(CSA)
IBIAS(CSA)
GBW(CSA)
CSSUM – CSREF, SeeTest Circuit 1
–3
–50
+3
+50
mV
nA
MHz
V/µs
V
mV
V
20
50
CCSCOMP = 10 pF
CSSUM and CSREF
SeeTest Circuit 2
0
–77
0.05
3
–83
3.3
DVFB
–80
500
ICSCOMP
= 100µA
ICSCOMP
µA
CURRENT BALANCE CIRCUIT
Common-Mode Range
Input Resistance
Input Current
Input Current Matching
VSW(X)CM
RSW(X)
ISW(X)
–600
20
4
+200
40
10
mV
kW
µA
%
SW(X) = 0V
SW(X) = 0V
SW(X) = 0V
30
7
DISW(X)
–5
+5
CURRENT LIMIT COMPARATOR
ILIMIT OutputVoltage
Normal Mode
In Shutdown
VILIMIT(NM) EN > 1.7V, RILIMIT = 250 kW
2.9
3
3.1
400
V
VILIMIT(SD)
IILIMIT(NM)
EN < 0.8V, IILIMIT = –100 µA
EN > 1.7V, RILIMIT = 250 kW
EN > 1.7V
mV
µA
µA
mV
mV/µA
V
Output Current, Normal Mode
Maximum Output Current
Current LimitThresholdVoltage
Current Limit Setting Ratio
DELAY Normal ModeVoltage
DELAY OvercurrentThreshold
Latch-Off DelayTime
12
60
105
VCL
VCSREF –VCSCOMP, RILIMIT = 250 kW
VCL/IILIMIT
125
10.4
3
1.8
600
145
VDELAY(NM)
VDELAY(OC)
tDELAY
2.9
1.7
3.1
1.9
V
µs
RDELAY = 250 kW, CDELAY = 4.7 nF
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2Guaranteed by design, not tested in production.
Specifications subject to change without notice.
–2–
REV. 0
ADP3180
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SOFT START
Output Current, Soft-Start Mode
Soft-Start DelayTime
IDELAY(SS)
tDELAY(SS)
During Startup, DELAY < 2.8V
RDELAY = 250 kW, CDELAY = 4.7 nF
VID Code = 011111
15
20
350
25
µA
µs
ENABLE INPUT
Input LowVoltage
Input HighVoltage
Input Current, InputVoltage Low
Input Current, InputVoltage High
VIL(EN)
VIH(EN)
IIL(EN)
IIH(EN)
0.4
V
V
µA
µA
0.8
–1
EN = 0V
EN = 1.25V
+1
25
10
POWER GOOD COMPARATOR
UndervoltageThreshold
OvervoltageThreshold
Output LowVoltage
Power Good DelayTime
VID Code Changing
VID Code Static
VPWRGD(UV) Relative to Nominal DAC Output
VPWRGD(OV) Relative to Nominal DAC Output
VOL(PWRGD) IPWRGD(SINK) = 4 mA
–200
+90
–250
+150
+225
–325
+200
+400
mV
mV
mV
100
250
200
150
550
µs
ns
mV
mV
CrowbarTrip Point
VCROWBAR
tCROWBAR
Relative to Nominal DAC Output
Relative to FBRTN
Overvoltage to PWM Going Low
90
450
200
650
Crowbar Reset Point
Crowbar DelayTime
VID Code Changing
VID Code Static
100
250
400
µs
ns
PWM OUTPUTS
OutputVoltage Low
OutputVoltage High
VOL(PWM)
VOH(PWM)
IPWM(SINK) = 400 µA
IPWM(SOURCE) = 400 µA
160
5.0
500
mV
V
4.0
SUPPLY
DC Supply Current
UVLOThresholdVoltage
UVLO Hysteresis
6
6.9
0.9
10
7.3
1.1
mA
V
V
VUVLO
VCC Rising
6.5
0.7
Specifications subject to change without notice.
REV. 0
–3–
ADP3180
ABSOLUTE MAXIMUM RATINGS*
Junction to AirThermal Resistance (JA) . . . . . . . . . . . 100°C/W
LeadTemperature (Soldering, 10 sec) . . . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +15V
FBRTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +0.3V
VID0–VID5, EN, DELAY, ILIMIT, CSCOMP, RT,
PWM1–PWM4, COMP . . . . . . . . . . . . . . . . –0.3V to +5.5V
SW1–SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5V to +25V
All Other Inputs and Outputs . . . . . . . . . –0.3V toVCC + 0.3V
Operating AmbientTemperature Range . . . . . . . . 0°C to 85°C
Operating JunctionTemperature . . . . . . . . . . . . . . . . . . . 125°C
StorageTemperature Range . . . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed underAbsolute Maximum Ratings may cause permanent
damage to the device.This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. Absolute maximum ratings apply
individually only, not in combination. Unless otherwise specified, all other voltages
are referenced to GND.
ORDERING GUIDE
Temperature
Range
Package
Options
Quantity
per Reel
Model
ADP3180JRU-REEL7
ADP3180JRU-REEL
0°C to 85°C
0°C to 85°C
RU-28 (TSSOP-28)
RU-28 (TSSOP-28)
1000
2500
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the ADP3180
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high
energy electrostatic discharges.Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VID3
VCC
PWM1
PWM2
PWM3
PWM4
SW1
3
VID2
4
VID1
5
VID0
ADP3180
6
VID5
7
FBRTN
FB
SW2
TOP VIEW
(Not to Scale)
8
SW3
9
COMP
PWRGD
EN
SW4
10
11
12
13
14
GND
CSCOMP
CSSUM
CSREF
ILIMIT
DELAY
RT
RAMPADJ
–4–
REV. 0
ADP3180
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
Function
1–6
VID4–VID0, Voltage Identification DAC Inputs.These six pins are pulled up to an internal reference, providing a logic
VID5
one if left open.When in normal operation mode, the DAC output programs the FB regulation voltage from
0.8375V to 1.6V. LeavingVID4 throughVID0 open results in the ADP3180 going into a “No CPU” mode,
shutting off its PWM outputs.
7
8
FBRTN
FB
Feedback Return.VID DAC and error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no-load offset point.
9
COMP
Error Amplifier Output and Compensation Point
10
PWRGD
Power Good Output. Open-drain output that pulls to GND when the output voltage is outside of the proper
operating range.
11
12
EN
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.
DELAY
Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND set the soft-start ramp-up time and the overcurrent latch-off delay time.
13
14
15
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the
oscillator frequency of the device.
RAMPADJ
ILIMIT
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the
internal PWM ramp.
Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit
threshold of the converter.This pin is actively pulled low when the ADP3180 EN input is low or whenVCC is
below its UVLO threshold to signal to the driver IC that the driver high side and low side outputs should go low.
16
CSREF
Current Sense ReferenceVoltage Input.The voltage on this pin is used as the reference for the current sense
amplifier and the Power Good and Crowbar functions.This pin should be connected to the common point
of the output inductors.
17
18
CSSUM
Current Sense Summing Node. External resistors from each switch node to this pin sum the average
inductor currents together to measure the total output current.
CSCOMP
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope
of the load line and the positioning loop response time.
19
GND
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20–23
SW4–SW1
Current Balance Inputs. Inputs for measuring the current level in each phase.The SW pins of unused
phases should be left open.
24–27
28
PWM4–
PWM1
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as
the ADP3413 or ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND will cause that phase
to turn off, allowing the ADP3180 to operate as a 2-, 3-, or 4-phase controller.
VCC
SupplyVoltage for the Device.
REV. 0
–5–
ADP3180–Typical Performance Characteristics
4
3
2
1
0
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
T
= 25؇C
A
4-PHASE OPERATION
0
50
100
150
200
250
300
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
R
VALUE – k⍀
T
MASTER CLOCK FREQUENCY – MHz
SEE EQUATION 1 FOR FREQUENCIES NOT ON THIS GRAPH
TPC 2. Supply Current vs. Master Clock Frequency
TPC 1. Master Clock Frequency vs. RT
TEST CIRCUITS
ADP3180
28
18
12V
VCC
ADP3180
CSCOMP
CSSUM
CSREF
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VCC
PWM1
PWM2
PWM3
PWM4
SW1
12V
+
1F
100nF
39k⍀
100nF
VID3
17
16
19
3
VID2
6-BIT CODE
1k⍀
4
VID1
5
VID0
1.0V
CSCOMP – 1V
40
V
=
OS
6
VID5
GND
7
FBRTN
FB
SW2
8
SW3
Test Circuit 1. Current Sense Amplifier VOS
9
COMP
PWRGD
EN
SW4
1k⍀
ADP3180
10
11
12
13
14
GND
28
8
12V
VCC
1.25V
CSCOMP
CSSUM
CSREF
ILIMIT
20k⍀
100nF
DELAY
RT
FB
4.7nF
250k⍀
10k⍀
RAMPADJ
9
COMP
250k⍀
200k⍀
CSCOMP
18
17
16
19
100nF
200k⍀
⌬V
Test Circuit 3. Closed-Loop Output Voltage Accuracy
CSSUM
CSREF
1.0V
GND
– FB
⌬V
= FB
FB
⌬V = 80mV
⌬V = 0mV
Test Circuit 2. Positioning Voltage
–6–
REV. 0
ADP3180
Table I. OutputVoltage vs.VID Code
VID4 VID3 VID2 VID1 VID0 VID5 VOUT(NOM) VID4 VID3 VID2 VID1 VID0 VID5 VOUT(NOM)
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
No CPU
0.8375V
0.850V
0.8625V
0.875V
0.8875V
0.900V
0.9125V
0.925V
0.9375V
0.950V
0.9625V
0.975V
0.9875V
1.000V
1.0125V
1.025V
1.0375V
1.050V
1.0625V
1.075V
1.0875V
1.100V
1.1125V
1.125V
1.1375V
1.150V
1.1625V
1.175V
1.1875V
1.200V
1.2125V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.225V
1.2375V
1.250V
1.2625V
1.275V
1.2875V
1.300V
1.3125V
1.325V
1.3375V
1.350V
1.3625V
1.375V
1.3875V
1.400V
1.4125V
1.425V
1.4375V
1.450V
1.4625V
1.475V
1.4875V
1.500V
1.5125V
1.525V
1.5375V
1.550V
1.5625V
1.575V
1.5875V
1.600V
X = Don't Care
∑
∑
Ease of use and design due to independent component selection
THEORY OF OPERATION
The ADP3180 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal 6-bitVID DAC conforms to Intel’sVRD/VRM 10
specifications. Multiphase operation is important for produc-
ing the high currents and low voltages demanded by today’s
microprocessors. Handling the high currents in a single-phase
converter would place high thermal demands on the components
in the system such as the inductors and MOSFETs.
Flexibility in operation for tailoring design to low cost or high
performance
Number of Phases
The number of operational phases and their phase relationship
is determined by the internal circuitry that monitors the PWM
outputs. Normally, the ADP3180 operates as a 4-phase PWM
controller. Grounding the PWM4 pin programs 3-phase opera-
tion, and grounding the PWM3 and PWM4 pins programs
2-phase operation.
The multimode control of the ADP3180 ensures a stable, high
performance topology for:
When the ADP3180 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 550 mV. An inter-
nal comparator checks each pin’s voltage versus a threshold of
400 mV. If the pin is grounded, then it will be below the thresh-
old and the phase will be disabled.The output resitance of the
PWM pin is approximately 5 kW during this detection time. Any
external pull-down resistance connected to the PWM pin should
not be less than 25 kW to ensure proper operation.The phase
detection is made during the first two clock cycles of the internal
oscillator. After this time, if the PWM output was not grounded,
the 5 kW resistance is removed and will switch between 0V and
5V. If the PWM output was grounded, it will remain off.
∑
∑
Balancing currents and thermals between phases
High speed response at the lowest possible switching frequency
and output decoupling
∑
Minimizing thermal switching losses due to lower frequency
operation
∑
∑
∑
∑
Tight load line regulation and accuracy
High current output from having up to 4-phase operation
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
REV. 0
–7–
ADP3180
Active Impedance Control Mode
The PWM outputs become logic-level devices once normal
operation starts.The detection is normal and is intended for driv-
ing external gate drivers, such as the ADP3418. Since each phase
is monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output cur-
rent at the CSCOMP pin can be scaled to be equal to the droop
impedance of the regulator times the output current.This droop
voltage is then used to set the input control voltage to the system.
The droop voltage is subtracted from the DAC reference input
voltage directly to tell the error amplifier where the output volt-
age should be.This differs from previous implementations and
allows enhanced feed-forward response.
Master Clock Frequency
The clock frequency of the ADP3180 is set with an external
resistor connected from the RT pin to ground.The frequency fol-
lows the graph inTPC 1.To determine the frequency per phase,
the clock is divided by the number of phases in use. If PWM4 is
grounded, divide the master clock by 3 for the frequency of the
remaining phases. If PWM3 and PWM4 are grounded, divide by 2.
If all phases are in use, divide by 4.
Current Control Mode andThermal Balance
The ADP3180 has individual inputs that are used for monitoring
the current in each phase.This information is combined with an
internal ramp to create a current balancing feedback system that
has been optimized for initial current balance accuracy and
dynamic thermal balancing during operation.This current bal-
ance information is independent of the average output current
information used for positioning described previously.
OutputVoltage Differential Sensing
The ADP3180 combines differential sensing with a high accuracy
VID DAC and reference and a low offset error amplifier to main-
tain a worst-case specification of 10 mV differential sensing
error with aVID input of 1.6000V over its full operating output
voltage and temperature range.The output voltage is sensed between
the FB and FBRTN pins. FB should be connected through a
resistor to the regulation point, usually the remote sense pin of
the microprocessor. FBRTN should be connected directly to the
remote sense ground point.The internalVID DAC and precision
reference are referenced to FBRTN, which has a minimal current
of 90 µA to allow accurate remote sensing.The internal error
amplifier compares the output of the DAC to the FB pin to regu-
late the output voltage.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply volt-
age for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the
RAMPADJ pin determines the slope of the internal PWM ramp.
Detailed information about programming the ramp is given in
the Application Information section.
External resistors can be placed in series with individual phases
to create an intentional current imbalance if desired, such as
when one phase may have better cooling and can support higher
currents. Resistors RSW1 through RSW4 (see the typical application
circuit in Figure 4) can be used for adjusting thermal balance. It
is best to have the ability to add these resistors during the initial
design, so make sure placeholders are provided in the layout.
Output Current Sensing
The ADP3180 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low side MOSFET.
This amplifier can be configured several ways, depending on the
objectives of the system:
To increase the current in any given phase, make RSW for that
phase larger (make RSW = 0 for the hottest phase and do not
change during balancing). Increasing RSW to only 500 W will
make a substantial increase in phase current. Increase each RSW
value by small amounts to achieve balance, starting with the cool-
est phase first.
∑
∑
Output inductor ESR sensing without thermistor for lowest cost
Voltage Control Mode
A high gain-bandwidth voltage mode error amplifier is used for
the voltage-mode control loop.The control input voltage to the
positive input is set via theVID 6-bit logic code according to the
voltages listed inTable I.This voltage is also offset by the droop
voltage for active positioning of the output voltage as a function
of current, commonly known as active voltage positioning.The
output of the amplifier is the COMP pin, which sets the termina-
tion voltage for the internal PWM ramps.
Output inductor ESR sensing with thermistor for improved
accuracy with tracking of inductor temperature
∑
Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage.The inputs to the
amplifier are summed together through resistors from the sensing
element (such as the switch node side of the output inductors)
to the inverting input, CSSUM.The feedback resistor between
CSCOMP and CSSUM sets the gain of the amplifier, and a filter
capacitor is placed in parallel with this resistor.The gain of the
amplifier is programmable by adjusting the feedback resistor to
set the load line required by the microprocessor.The current
information is then given as the difference of CSREF – CSCOMP.
This difference signal is used internally to offset theVID DAC
for voltage positioning and as a differential input for the current
limit comparator.
The negative input (FB) is tied to the output sense location with
a resistor RB and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from the
VID voltage.The no-load voltage will be negative with respect to
theVID DAC.The main loop compensation is incorporated into
the feedback network between FB and COMP.
Soft-Start
The power-on ramp up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch-off
time as explained in the following section. In UVLO or when
To provide the best accuracy for the sensing of current, the CSA
has been designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors so that it can be
made extremely accurate.
–8–
REV. 0
ADP3180
EN is a logic low, the DELAY pin is held at ground. After the
UVLO threshold is reached and EN is a logic high, the DELAY
capacitor is charged up with an internal 20 µA current source.
The output voltage follows the ramping voltage on the DELAY
pin, limiting the inrush current.The soft-start time depends on
the values ofVID DAC and CDLY, with a secondary effect from
RDLY. Refer to the Application Information section for detailed
PWRGD. If the output voltage is within the PWRGD window,
the controller resumes normal operation. However, if a short
circuit has caused the output voltage to drop below the PWRGD
threshold, a soft-start cycle is initiated.
The latch-off function can be reset either by removing and reap-
plyingVCC to the ADP3180 or by pulling the EN pin low for
a short time.To disable the short circuit latch-off function, the
external resistor to ground should be left open, and a high value
(>1 MW) resistor should be connected from DELAY toVCC.
This prevents the DELAY capacitor from discharging, so the
1.8V threshold is never reached.The resistor will have an impact
on the soft-start time because the current through it will add to
the internal 20 µA current source.
information on setting CDLY
.
When the PWRGD threshold is reached, the soft-start cycle is
stopped and the DELAY pin is pulled up to 3V. This ensures
that the output voltage is at theVID voltage when the PWRGD
signals to the system that the output voltage is good. If EN is
taken low orVCC drops below UVLO, the DELAY capacitor is
reset to ground to be ready for another soft-start cycle. Figure 1
shows a typical start-up sequence for the ADP3180.
Figure 2. Overcurrent Latch-Off Waveforms,
Circuit of Figure 4.
Channel 1–PWRGD, Channel 2–VOUT
Channel 3–CSCOMP Pin of ADP3180,
Channel 4–High Side MOSFET VGS
,
Figure 1. Start-Up Waveforms, Circuit of Figure 5.
Channel 1–PWRGD, Channel 2–VOUT
,
Channel 3–High Side MOSFET VGS
,
Channel 4–Low Side MOSFET VGS
During startup when the output voltage is below 200 mV, a
secondary current limit is active.This is necessary because the
voltage swing of CSCOMP cannot go below ground.This sec-
ondary current limit controls the internal COMP voltage to the
PWM comparators to 2V. This will limit the voltage drop across
the low side MOSFETs through the current balance circuitry.
Current Limit, Short Circuit, and Latch-Off Protection
The ADP3180 compares a programmable current limit set point
to the voltage from the output of the current sense amplifier.The
level of current limit is set with the resistor from the ILIMIT pin
to ground. During normal operation, the voltage on ILIMIT is
3V. The current through the external resistor is internally scaled
to give a current limit threshold of 10.4 mV/µA. If the differ-
ence in voltage between CSREF and CSCOMP rises above the
current limit threshold, the internal current limit amplifier will
control the internal COMP voltage to maintain the average out-
put current at the limit.
There is also an inherent per phase current limit that will protect
individual phases in the case where one or more phases may stop
functioning because of a faulty component.This limit is based on
the maximum normal mode COMP voltage.
DynamicVID
The ADP3180 incorporates the ability to dynamically change the
VID input while the controller is running.This allows the output
voltage to change while the supply is running and supplying cur-
rent to the load.This is commonly referred to asVID on-the-fly
(OTF). AVID OTF can occur under either light load or heavy
load conditions.The processor signals the controller by changing
theVID inputs in multiple steps from the start code to the finish
code.This change can be either positive or negative.
After the limit is reached, the 3V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops below
1.8V. The current limit latch-off delay time is therefore set by the
RC time constant discharging from 3V to 1.8V. The Application
Information section discusses the selection of CDLY and RDLY
.
Because the controller continues to cycle the phases dur-
When aVID input changes state, the ADP3180 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time is to prevent a false code due to logic skew while the
ing the latch-off delay time, if the short is removed before the
1.8V threshold is reached, the controller will return to normal
operation.The recovery characteristic depends on the state of
REV. 0
–9–
ADP3180
Output Enable and UVLO
sixVID inputs are changing. Additionally, the firstVID change
initiates the PWRGD and CROWBAR blanking functions for a
minimum of 250 µs to prevent a false PWRGD or CROWBAR
event. EachVID change will reset the internal timer. Figure 3
showsVID on-the-fly performance when the output voltage is
stepping up and the output current is switching between mini-
mum and maximum values, which is the worst-case situation.
The input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher than its
logic threshold for the ADP3180 to begin switching. If UVLO is
less than the threshold or the EN pin is a logic low, the ADP3180
is disabled.This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at
ground.
In the application circuit, the ILIMIT pin should be connected
to the OD pins of the ADP3418 drivers. Because ILIMIT is
grounded, this disables the drivers such that both DRVH and
DRVL are grounded.This feature is important to prevent dis-
charging of the output capacitors when the controller is shut off.
If the driver outputs were not disabled, a negative voltage could
be generated on the output due to the high current discharge of
the output capacitors through the inductors.
APPLICATION INFORMATION
The design parameters for a typical IntelVRD 10 compliant
CPU application are as follows:
∑
∑
∑
∑
∑
∑
Input voltage (VIN) = 12V
VID setting voltage (VVID) = 1.500V
Duty cycle (D) = 0.125
Nominal output voltage at no load (VONL) = 1.480V
Nominal output voltage at 65 A load (VOFL) = 1.3955V
Figure 3. VID On-the-FlyWaveforms, Circuit of Figure 5.
VID Change = 5 mV, 5 µs per Step, 50 Steps,
I
OUT Change = 5 A to 65 A
Static output voltage drop based on a 1.3 mW load line (RO)
from no load to full load
Power Good Monitoring
The Power Good comparator monitors the output voltage via the
CSREF pin.The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified in the
Specifications table based on theVID voltage setting. PWRGD
will go low if the output voltage is outside of this specified range.
PWRGD is blanked during aVID OTF event for a period of
250 µs to prevent false signals during the time the output is
changing.
∑
∑
∑
∑
∑
(VD) =VONL –VOFL = 1.480V – 1.3955V = 84.5 mV
Maximum Output Current (IO) = 65 A
Maximum Output Current Step (DIO) = 60 A
Number of Phases (n) = 3
Switching frequency per phase (fSW) = 267 kHz
Output Crowbar
As part of the protection for the load and output components of
the supply, the PWM outputs will be driven low (turning on the
low side MOSFETs) when the output voltage exceeds the upper
Power Good threshold.This crowbar action will stop once the
output voltage has fallen below the release threshold of approxi-
mately 450 mV.
Turning on the low side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output overvolt-
age is due to a short of the high side MOSFET, this action will
current limit the input supply or blow its fuse, protecting the
microprocessor from destruction.
–10–
REV. 0
ADP3180
L1
1.6H
470F/16V
؋
6 Nichicon PW Series
V
12V
IN
+
+
C9
4.7F
C1
C6
V
RTN
IN
U2
C8
ADP3418 100nF
D1
1N4148WS
D2
Q1
IPD12N03L
1
2
3
4
BST
IN
DRVH
SW
8
7
6
5
820F/2.5V
؋
8 Fujitsu RE Series
8m⍀ ESR (each)
1N4148WS
L2
600nH/1.6m⍀
V
CC(CORE)
0.8375V–1.6V
OD
PGND
DRVL
+
+
C10
4.7nF
R1
65A AVG, 74A PK
VCC
C28
C21
C7
4.7F
V
CC(CORE) RTN
2.2⍀
Q3
IPD06N03L
Q2
IPD06N03L
10F
؋
23MLCC AROUND
SOCKET
C13
C12
U3
4.7F
ADP3418100nF
D3
1N4148WS
Q4
IPD12N03L
1
2
3
4
BST
DRVH
8
7
6
5
L3
IN
SW
600nH/1.6m⍀
OD
PGND
DRVL
C14
4.7nF
VCC
C11
R2
2.2⍀
4.7F
Q6
IPD06N03L
Q5
IPD06N03L
C17
4.7F
U4
ADP3418
C16
100nF
D4
1N4148WS
Q7
IPD12N03L
BST
DRVH
1
2
3
4
8
7
6
5
L4
IN
SW
PGND
DRVL
600nH/1.6m⍀
OD
C18
4.7nF
VCC
R3
2.2⍀
C15
R
TH
4.7F
100k⍀, 5%
Q9
IPD06N03L
Q8
IPD06N03L
+
R4
10⍀
C19
1F
C20
33F
U1
ADP3180
R
R
383k⍀
VID4
VID3
VID2
VID1
VID0
VID5
FBRTN
FB
VCC
PWM1
PWM2
1
2
3
4
5
6
7
8
9
28
27
26
FROM CPU
PWM3 25
PWM4 24
R
*
SW1
SW1
23
R
*
SW2
SW2 22
SW3 21
C
1.5nF
B
R
*
SW3
C
33pF
FB
R
PH1
124k⍀
R
PH3
COMP
SW4 20
C
R
R
A
16.9k⍀
124k⍀
A
B
POWER
GOOD
390pF
1.33k⍀
R
PH2
124k⍀
10 PWRGD
11 EN
GND 19
R
R
CS2
C
CS1
CS2
1.5nF
35.7k⍀ 73.2k⍀
ENABLE
CSCOMP 18
CSSUM 17
CSREF 16
ILIMIT 15
12 DELAY
13 RT
C
CS1
C
2.2nF
DLY
39nF
R
DLY
*SEE THEORY OF
OPERATION
390k⍀
R
T
249k⍀
14 RAMPADJ
R
SECTION FOR
DESCRIPTION
OF OPTIONAL
LIM
200k⍀
R
RESISTORS
SW
Figure 4. 65 A Intel Pentium® 4 CPU Supply Circuit, VRD 10 Design
REV. 0
–11–
ADP3180
Setting the Clock Frequency
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage:
The ADP3180 uses a fixed-frequency control architecture.The
frequency is set by an external timing resistor (RT).The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 800 kHz sets
the switching frequency of each phase, fSW, to 267 kHz, which
represents a practical trade-off between the switching losses and
the sizes of the output filter components.TPC 1 shows that to
achieve an 800 kHz oscillator frequency, the correct value for RT
is 249 kW. Alternatively, the value for RT can be calculated using:
VVID × 1− D
(
)
(4)
IR
=
fSW × L
VVID × R × 1− n × D
(
)
)
(
O
(5)
L ≥
fSW × VRIPPLE
Solving Equation 5 for a 10 mV p-p output ripple voltage yields:
1.5 V × 1.3 mΩ × 1− 0.375
(
)
L ≥
= 456 nH
1
267 kHz × 10 mV
RT =
1
(1)
If the ripple voltage ends up less than that designed for, the
inductor can be made smaller until the ripple value is met.This
will allow optimal transient response and minimum output
decoupling.
n × f × 5.83 pF −
(
)
SW
1.5 MΩ
where 5.83 pF and 1.5 MW are internal IC component values.
For good initial accuracy and frequency stability, it is recom-
mended to use a 1% resistor.
The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 600 nH inductor is
a good choice for a starting point and gives a calculated ripple
current of 8.2 A.The inductor should not saturate at the peak
current of 25.8 A and should be able to handle the sum of the
power dissipation caused by the average current of 22.7 A in the
winding and core loss.
Soft-Start and Current Limit Latch-Off DelayTimes
Because the soft-start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together.The first step is to set CDLY for the soft-start ramp.This
ramp is generated with a 20 µA internal current source.The value
of RDLY will have a second order impact on the soft-start time
because it sinks part of the current source to ground. However, as
long as RDLY is kept greater than 200 kW, this effect is minor.The
value for CDLY can be approximated using:
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR will
cause excessive power losses, while too small a value will lead to
increased measurement error. A good rule of thumb is to have the
DCR be about 1 to 1½ times the droop resistance (RO). For our
example, we are using an inductor with a DCR of 1.6 mW.
VVID
2 × RDLY
tSS
VVID
CDLY = 20 µA −
×
(2)
where tSS is the desired soft-start time. Assuming an RDLY of
390 kW and a desired a soft-start time of 3 ms, CDLY is 36 nF.
The closest standard value for CDLY is 39 nF. Once CDLY has been
chosen, RDLY can be calculated for the current limit latch-off
time using:
Designing an Inductor
Once the inductance and DCR are known, the next step is to
either design an inductor or find a standard inductor that comes
as close as possible to meeting the overall design goals. It is also
important to have the inductance and DCR tolerance specified
to control the accuracy of the system. 15% inductance and 8%
DCR (at room temperature) are reasonable tolerances that most
manufacturers can meet.
1.96 × tDELAY
RDLY
=
(3)
CDLY
The first decision in designing the inductor is to choose the core
material.There are several possibilities for providing low core
loss at high frequencies.Two examples are the powder cores (e.g.,
Kool-Mµ® from Magnetics, Inc. or Micrometals) and the gapped
soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency
powdered iron cores should be avoided due to their high core
loss, especially when the inductor value is relatively low and the
ripple current is high.
If the result for RDLY is less than 200 kW, a smaller soft-start time
should be considered by recalculating the equation for CDLY, or a
longer latch-off time should be used. In no case should RDLY be
less than 200 kW. In this example, a delay time of 8 ms gives
RDLY = 402 kW. The closest standard 5% value is 390 kW.
Inductor Selection
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple cur-
rent, which increases the output ripple voltage and conduction
losses in the MOSFETs, but allows using smaller inductors and,
for a specified peak-to-peak transient deviation, less total output
capacitance. Conversely, a higher inductance means lower ripple
current and reduced conduction losses but requires larger
inductors and more output capacitance for the same peak-to-
peak transient deviation. In any multiphase converter, a practical
value for the peak-to-peak inductor ripple current is less than
50% of the maximum dc current in the same inductor. Equation 4
shows the relationship between the inductance, oscillator fre-
quency, and peak-to-peak ripple current in the inductor.
The best choice for a core geometry is a closed-loop type, such
as a pot core, PQ, U, and E core, or toroid. A good compromise
between price and performance is a core with a toroidal shape.
There are many useful references for quickly designing a power
inductor, such as:
Magnetics Design References
∑
Magnetic Designer Software
Intusoft (www.intusoft.com)
∑
Designing Magnetic Components for High-Frequency DC-DC
Converters, byWilliamT. McLyman, Kg Magnetics, Inc.
ISBN 1883107008
–12–
REV. 0
ADP3180
Selecting a Standard Inductor
Inductor DCRTemperature Correction
The companies listed below can provide design consultation and
deliver power inductors optimized for high power applications
upon request.
With the inductor’s DCR being used as the sense element and
copper wire being the source of the DCR, one needs to com-
pensate for temperature changes of the inductor’s winding.
Fortunately, copper has a well known temperature coefficient
(TC) of 0.39%/°C.
Power Inductor Manufacturers
∑
∑
∑
∑
Coilcraft
(847)639-6400
www.coilcraft.com
If RCS is designed to have an opposite and equal percentage
change in resistance to that of the wire, it will cancel the tempera-
ture variation of the inductor’s DCR. Due to the nonlinear nature
of NTC thermistors, resistors RCS1 and RCS2 are needed (see
Figure 5) to linearize the NTC and produce the desired tempera-
ture tracking.
Coiltronics
(561)752-5000
www.coiltronics.com
Sumida Electric Company
(510) 668-0660
www.sumida.com
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
TO
TO
OUT
OR LOW SIDE MOSFET
SWITCH
NODES
V
R
SENSE
TH
Vishay Intertechnology
(402) 563-6866
www.vishay.com
R
R
R
PH3
PH1
PH2
ADP3180
R
R
CS2
Output Droop Resistance
CS1
CSCOMP
CSSUM
CSREF
18
17
16
The design requires that the regulator output voltage measured
at the CPU pins drops when the output current increases. The
specified voltage drop corresponds to a dc output resistance (RO).
C
1.8nF
CS
KEEP THIS PATH
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES
The output current is measured by summing together the voltage
across each inductor and passing the signal through a low-pass
filter.This summer filter is the CS amplifier configured with
resistors RPH(X) (summers), and RCS and CCS (filter).The output
resistance of the regulator is set by the following equations, where
RL is the DCR of the output inductors:
Figure 5.Temperature Compensation Circuit Values
The following procedure and expressions will yield values to use
for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given
RCS value.
RCS
RO =
× RL
(6)
RPH
X
(
)
1. Select an NTC to be used based on type and value. Since
we do not have a value yet, start with a thermistor with a
value close to RCS. The NTC should also have an initial
tolerance of better than 5%.
L
CCS
=
(7)
RL × RCS
One has the flexibility of choosing either RCS or RPH(X). It is best
to select RCS equal to 100 kW, and then solve for RPH(X) by rear-
ranging Equation 6.
2. Based on the type of NTC, find its relative resistance value
at two temperatures. The temperatures that work well
are 50°C and 90°C. We will call these resistance values
A (RTH(50°C)/RTH(25°C)) and B (RTH(90°C)/RTH(25°C)). Note that
the NTC’s relative value is always 1 at 25°C.
RL
RO
RPH
RPH
=
=
× RCS
X
X
(
)
3. Find the relative value of RCS required for each of these
temperatures.This is based on the percentage change need-
ed, which we will initially make 0.39%/°C.We will call these
r1 (1/(1+TC ϫ (T1 – 25))) and r2 (1/(1 +TC ϫ (T2 – 25))),
where TC = 0.0039, T1 = 50°C and T2 = 90°C.
1.6 mΩ
1.3 mΩ
× 100 kΩ = 123 kΩ
(
)
Next, use Equation 6 to solve for CCS:
600 nH
CCS
=
= 3.75 nF
4. Compute the relative values for RCS1, RCS2, and RTH using:
A − B × r × r − A × 1− B × r + B × 1− A × r
1.6 mΩ × 100 kΩ
(
)
(
)
(
)
)
1
2
2
1
RCS2
=
It is best to have a dual location for CCS in the layout so standard
values can be used in parallel to get as close to the value desired.
For this example, choosing CCS to be a 1.5 nF and 2.2 nF in
parallel is a good choice. For best accuracy, CCS should be a 5%
or 10% NPO capacitor. The closest standard 1% value for RPH(X)
is 124 kW.
A × 1− B × r − B × 1− A × r − A − B
(
)
(
)
(
1
2
1− A
(
)
RCS1
=
1
A
(8)
−
1− RCS2 r − RCS2
1
1
RTH
=
1
1
−
1− RCS2 RCS1
REV. 0
–13–
ADP3180
5. Calculate RTH = RTH ϫ RCS, then select the closest value of
thermistor available. Also compute a scaling factor k based
on the ratio of the actual thermistor value used relative to the
computed one:
CX (
≤
MAX
)
VVID nKRO 2
L
VV
×
×
1+ tV
×
− 1 − C
Z (13)
nK2RO2
VVID
VV
L
RTH
ACTUAL
(
)
k =
(9)
VVERR
RTH CALCULATED
(
)
where K = − ln
VV
6. Finally, calculate values for RCS1 and RCS2 using
To meet the conditions of these expressions and transient
Equation 10:
response, the ESR of the bulk capacitor bank (RX) should be less
than two times the droop resistance, RO. If the CX(MIN) is larger
than CX(MAX), the system will not meet theVID on-the-fly speci-
fication and may require the use of a smaller inductor or more
phases (and may have to increase the switching frequency to keep
the output ripple the same).
RCS1 = RCS × k × rCS1
(10)
RCS2 = RCS × 1− k + k × r
(
)
(
)
)
(
CS2
For this example, RCS has been chosen to be 100 kW, so we start
with a thermistor value of 100 kW. Looking through available
0603 size thermistors, we find aVishay NTHS0603N01N1003JR
NTC thermistor with A = 0.3602 and B = 0.09174. From these
we compute RCS1 = 0.3796, RCS2 = 0.7195 and RTH = 1.0751.
Solving for RTH yields 107.51 kW, so we choose 100 kW, making
k = 0.9302. Finally, we find RCS1 and RCS2 to be 35.3 kW and
73.9 kW. Choosing the closest 1% resistor values yields a choice
of 35.7 kW and 73.2 kW.
For our example, 23 10 µF 1206 MLC capacitors (CZ = 230 µF)
were used.TheVID on-the-fly step change is 250 mV in 150 µs
with a setting error of 2.5 mV. Solving for the bulk capacitance
yields:
600 nH × 60 A
3 × 1.3 mΩ × 1.5 V
CX ( MIN
≥
− 230 µF = 5.92 mF
)
600 nH × 250 mV
Output Offset
CX ( MAX
≤
×
)
3 × 4.62 × (1.3 mΩ)2 × 1.5 V
Intel’s specification requires that at no load the nominal output
voltage of the regulator be offset to a lower value than the nomi-
nal voltage corresponding to theVID code.The offset is set by a
constant current source flowing out of the FB pin (IFB) and flow-
ing through RB. The value of RB can be found using Equation 11:
150 µs × 1.5 V × 3 × 4.6 × 1.3 mΩ 2
1+
− 1 − 230 µF
250 mV × 600 nH
= 23.9 mF
VVID − VONL
RB =
=
Using eight 820 µF A1-Polys with a typical ESR of 8 mW, each
yields CX = 6.56 mF with an RX = 1.0 mW.
IFB
(11)
1.5 V − 1.480 V
RB =
= 1.33 kΩ
15 µA
One last check should be made to ensure that the ESL of the
bulk capacitors (LX) is low enough to limit the initial high fre-
quency transient spike.This is tested using:
The closest standard 1% resistor value is 1.33 kW.
COUT Selection
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms. One
can also use some simple design guidelines to determine what
is required.These guidelines are based on having both bulk and
ceramic capacitors in the system.
LX ≤ CZ × RO2
LX ≤ 230 µF × (1.3 mΩ)2 = 389 pH
(14)
In this example, LX is 375 pH for the eight A1-Polys capacitors,
which satisfies this limitation. If the LX of the chosen bulk capaci-
tor bank is too large, the number of capacitors must be increased.
The first thing is to select the total amount of ceramic capaci-
tance.This is based on the number and type of capacitor to be
used.The best location for ceramics is inside the socket, with 12
to 18 of size 1206 being the physical limit. Others can be placed
along the outer edge of the socket as well.
One should note for this multimode control technique, all
ceramic designs can be used as long as the conditions of
Equations 11, 12, and 13 are satisfied.
Power MOSFETs
Combined ceramic values of 200 µF–300 µF are recommended,
usually made up of multiple 10 µF or 22 µF capacitors. Select the
number of ceramics and find the total ceramic capacitance (CZ).
For this example, the N-channel power MOSFETs have been
selected for one high side switch and two low side switches per
phase.The main selection parameters for the power MOSFETs
areVGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive
voltage (the supply voltage to the ADP3418) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used.WithVGATE ~10V, logic-level threshold MOSFETs (VGS(TH)
< 2.5V) are recommended.
Next, there is an upper limit imposed on the total amount of bulk
capacitance (CX) when one considers theVID on-the-fly voltage
stepping of the output (voltage step VV in time tV with error of
V
ERR) and a lower limit based on meeting the critical capacitance
for load release for a given maximum load step DIO:
L × ∆IO
The maximum output current IO determines the RDS(ON)
requirement for the low side (synchronous) MOSFETs.With
the ADP3180, currents are balanced between phases, thus the
current in each low side MOSFET is the output current divided
by the total number of MOSFETs (nSF).With conduction losses
CX (
≥
− CZ
(12)
MIN
)
n × R × V
O
VID
–14–
REV. 0
ADP3180
being dominant, the following expression shows the total power
being dissipated in each synchronous MOSFET in terms of
the ripple current per phase (IR) and average total output cur-
rent (IO);
1.5W for a single D-PAK) when combining the switching and
conduction losses.
For our example, we have selected an Infineon IPD12N03L as
the main MOSFET (three total; nMF = 3), with a CISS = 1460 pF
(max) and RDS(MF) = 14 mW (max atTJ = 120ºC) and an Infineon
IPD06N03L as the synchronous MOSFET (six total; nSF = 6),
with CISS = 2370 pF (max) and RDS(SF) = 8.4 mW (max atTJ =
120ºC).The synchronous MOSFET CISS is less than 3000 pF,
satisfying that requirement. Solving for the power dissipation per
MOSFET at IO = 65 A and IR = 8.2 A yields 863 mW for each
synchronous MOSFET and 1.44W for each main MOSFET.
These numbers work well considering there is usually more PCB
area available for each main MOSFET versus each synchronous
MOSFET.
IO 2
1
12
n × IR
nSF
2
PSF = 1− D ×
+
×
× RDS SF
(15)
(
)
(
)
n
SF
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, one can find the
required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to
an ambient temperature of 50ºC, a safe limit for PSF is 1W–1.5W
at 120ºC junction temperature.Thus, for our example (65 A
maximum), we find RDS(SF) (per MOSFET) < 8.7 mW. This
RDS(SF) is also at a junction temperature of about 120ºC, so we
need to make sure we account for this when making this selec-
tion. For our example, we selected two lower side MOSFETs
at 7 mW each at room temperature, which gives 8.4 mW at high
temperature.
One last thing to look at is the power dissipation in the driver
for each phase.This is best described in terms of the QG for the
MOSFETs and is given by the following, where QGMF is the total
gate charge for each main MOSFET and QGSF is the total gate
charge for each synchronous MOSFET:
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance.The ratio of the
feedback to input needs to be small (less than 10% is recom-
mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.
fSW
(18)
PDRV
=
× n × QGMF + nSF × QGSF + I
× VCC
(
)
MF
CC
2 × n
Also shown is the standby dissipation factor (ICC times the VCC
for the driver. For the ADP3418, the maximum dissipation
)
Also, the time to switch the synchronous MOSFETs off should
not exceed the non overlap dead time of the MOSFET driver
(40 ns typical for the ADP3418).The output impedance of the
driver is about 2 W and the typical MOSFET input gate resis-
tances are about 1 W–2 W, so a total gate capacitance of less than
6000 pF should be adhered to. Since there are two MOSFETs in
parallel, we should limit the input capacitance for each synchro-
nous MOSFET to 3000 pF.
should be less than 400 mW. For our example, with ICC = 7 mA,
GMF = 22.8 nC, and QGSF = 34.3 nC, we find 260 mW in each
Q
driver, which is below the 400 mW dissipation limit. See the
ADP3418 data sheet for more details.
Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the internal
PWM ramp.The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response.The following expression is used for determining the
optimum value:
The high side (main) MOSFET has to be able to handle two
main power dissipation components: conduction and switching
losses.The switching loss is related to the amount of time it takes
for the main MOSFET to turn on and off and to the current and
voltage that are being switched. Basing the switching speed on
the rise and fall time of the gate driver impedance and MOSFET
input capacitance, the following expression provides an approxi-
mate value for the switching loss per main MOSFET, where nMF
is the total number of main MOSFETs:
AR × L
RR =
3 × AD × RDS × CR
(19)
0.2 × 600 nH
3 × 5 × 4.2 mΩ × 5 pF
RR =
= 381 kΩ
where AR is the internal ramp amplifier gain, AD is the current
balancing amplifier gain, RDS is the total low side MOSFET ON
resistance, and CR is the internal ramp capacitor value.The clos-
est standard 1% resistor value is 383 kW.
VCC × IO
nMF
n
PS( MF = 2 × fSW
×
× RG ×
× CISS
(16)
)
nMF
Here, RG is the total gate resistance (2 W for the ADP3418 and
about 1 W for typical high speed switching MOSFETs, making
RG = 3 W) and CISS is the input capacitance of the main MOS-
FET. It is interesting to note that adding more main MOSFETs
(nMF) does not really help the switching loss per MOSFET since
the additional gate capacitance slows down switching.The best
thing to reduce switching loss is to use lower gate capacitance
devices.
The internal ramp voltage magnitude can be calculated using:
A × 1− D × V
RR × CR × fSW
(
)
R
VID
VR =
VR =
(20)
0.2 × 1− 0.125 × 1.5 V
(
)
= 0.51 V
383 kΩ × 5 pF × 267 kHz
The size of the internal ramp can be made larger or smaller. If
it is made larger, stability and transient response will improve,
but thermal balance will degrade. Likewise, if the ramp is made
smaller, thermal balance will improve at the sacrifice of transient
response and stability.The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.
The conduction loss of the main MOSFET is given by the fol-
lowing, where RDS(MF) is the ON resistance of the MOSFET:
IO 2
1
12
n × IR
nMF
2
PC(
= D ×
+
×
× RDS MF
(17)
MF
)
(
)
n
MF
Typically, for main MOSFETs, one wants the highest speed (low
CISS) device, but these usually have higher ON resistance. One
must select a device that meets the total power dissipation (about
REV. 0
–15–
ADP3180
COMP Pin Ramp
This limit can be adjusted by changing the ramp voltage VR. But
make sure not to set the per phase limit lower than the average
per phase current (ILIM/n).
There is a ramp signal on the COMP pin due to the droop volt-
age and output voltage ramps.This ramp amplitude adds to the
internal ramp to produce the following overall ramp signal at the
PWM input.
There is also a per phase initial duty cycle limit determined by:
VCOMP
− VBIAS
MAX
(
)
VR
(24)
DMAX = D ×
VRT
=
VRT
2 × 1− n × D
(
)
(21)
1−
For this example, the maximum duty cycle is found to be 0.42.
n × fSW × CX × RO
Feedback Loop Compensation Design
For this example, the overall ramp signal is found to be 0.63V.
Optimized compensation of the ADP3180 allows the best pos-
sible response of the regulator’s output to a load change.The
basis for determining the optimum compensation is to make the
regulator and output decoupling appear as an output imped-
ance that is entirely resistive over the widest possible frequency
range, including dc, and equal to the droop resistance (RO).With
the resistive output impedance, the output voltage will droop in
proportion with the load current at any load current slew rate;
this ensures the optimal positioning and allows the minimization
of the output decoupling.
Current Limit Set Point
To select the current limit set point, we need to find the resistor
value for RLIM. The current limit threshold for the ADP3180 is set
with a 3V source (VLIM) across RLIM with a gain of 10.4 mV/µA
(ALIM). RLIM can be found using the following:
ALIM × VLIM
ILIM × RO
RLIM
=
(22)
For values of RLIM greater than 500 kW, the current limit may be
lower than expected, so some adjustment of RLIM may be needed.
Here, ILIM is the average current limit for the output of the sup-
ply. For our example, choosing 120 A for ILIM, we find RLIM to be
200 kW, for which we chose 200 kW as the nearest 1% value.
With the multimode feedback structure of the ADP3180, one
needs to set the feedback compensation to make the converter’s
output impedance working in parallel with the output decoupling
meet this goal.There are several poles and zeros created by the
output inductor and decoupling capacitors (output filter) that
need to be compensated for.
The per phase current limit described earlier has its limit deter-
mined by the following:
A type-three compensator on the voltage feedback is adequate for
proper compensation of the output filter.The expressions given
in Equations 25–29 are intended to yield an optimal starting
point for the design; some adjustments may be necessary to
account for PCB and component parasitic effects (See theTuning
Procedure for the ADP3180 section).
VCOMP
− VR − VBIAS
IR
2
MAX
(
)
IPHLIM
≅
−
(23)
AD × RDS MAX
(
)
For the ADP3180, the maximum COMP voltage (VCOMP(MAX)) is
3.3V, the COMP pin bias voltage (VBIAS) is 1.2V, and the cur-
rent balancing amplifier gain (AD) is 5. Using VR of 0.63V and
The first step is to compute the time constants for all of the poles
and zeros in the system:
R
DS(MAX) of 4.2 mW (low side ON resistance at 150°C), we find a
per phase limit of 66 A.
2 × L × 1− n × D × V
RL × VRT
VVID
(
)
RT
RE = n × RO + AD × RDS
+
+
n × CX × RO × VVID
(25)
2 × 600 nH × 1− 0.375 × 0.63 V
3 × 6.56 mF × 1.3 mΩ × 1.5 V
1.6 mΩ × 0.63 V
1.5 V
(
)
RE = 3 × 1.3 mΩ + 5 × 4.2 mΩ +
+
= 37.9 mΩ
LX RO − R'
375 pH 1.3 mΩ − 0.6 mΩ
TA = CX × R − R' +
×
= 6.56 mF × 1.3 mΩ − 0.6 mΩ +
×
= 4.79 µs
(26)
(27)
(28)
(
)
(
)
O
RO
RX
1.3 mΩ
1.0 mΩ
T = R + R'−RO × C = 1.0 mΩ + 0.6 mΩ − 1.3 mΩ × 6.56 mF = 1.97 µs
(
)
(
)
B
X
X
AD × RDS
2 × fSW
5 × 4.2 mΩ
VRT × L −
0.63 V × 600 nH −
2 × 267 kHz
TC =
=
= 6.2 µs
VVID × RE
CX × CZ × RO2
CX × R − R' + C × RO 6.56 mF × 1.3 mΩ − 0.6 mΩ + 230 µF × 1.3 mΩ
1.5 V × 37.9 mΩ
6.56 mF × 230 µF × (1.3 mΩ)2
TD
=
=
= 521 ns
(29)
(
)
(
)
O
Z
The compensation values can then be solved using the following:
where, for the ADP3180, R' is the PCB resistance from the
bulk capacitors to the ceramics and where RDS is the total low
side MOSFET ON resistance per phase. For this example, AD
is 5, VRT equals 0.63V, R' is approximately 0.6 mW (assuming
a 4-layer motherboard), and LX is 375 pH for the eight Al-Poly
capacitors.
n × RO × TA
RE × RB
CA
CA
=
=
(30)
3 × 1.3 mΩ × 4.79 µs
37.9 mΩ × 1.33 kΩ
= 371 pF
–16–
REV. 0
ADP3180
maximum of 0.1 A/µs, an additional small inductor (L > 1 µH @
15 A) should be inserted between the converter and the supply
bus.That inductor also acts as a filter between the converter and
the primary power source.
TC
6.2 µs
RA =
=
= 16.7 kΩ
= 1.48 nF
= 31.2 pF
(31)
(32)
(33)
CA 371 pF
TB 1.97 µs
RB 1.33 kΩ
CB
=
=
V
− VFLCOLD
− VFLHOT
(
)
NL
RCS2 NEW = RCS2 OLD
×
(35)
(
)
(
)
V
(
)
NL
TD 521 ns
RA 16.7 kΩ
CFB
=
=
100
80
60
40
20
0
Choosing the closest standard values for these components yields:
CA = 390 pF, RA = 16.9 kW, CB = 1.5 nF, and CFB = 33 pF.
Figure 6 shows the typical transient response using the compen-
sation values.
0
10
20
30
40
50
60
OUTPUT CURRENT – A
Figure 7. Efficiency of the Circuit of Figure 4
vs. Output Current
TUNING PROCEDURE FORTHE ADP3180
1. Build circuit based on compensation values computed from
design spreadsheet.
2. Hook up dc load to circuit, turn on and verify operation.
Also check for jitter at no-load and full-load.
Figure 6.TypicalTransient Response for Design Example
DC Loadline Setting
CIN Selection and Input Current di/dt Reduction
3. Measure output voltage at no-load (VNL).Verify it is within
tolerance.
In continuous inductor-current mode, the source current of the
high side MOSFET is approximately a square wave with a duty
ratio equal to n ϫ VOUT/VIN and an amplitude of one-nth of the
maximum output current.To prevent large voltage transients,
a low ESR input capacitor sized for the maximum rms current
must be used.The maximum rms capacitor current is given by:
4. Measure output voltage at full-load cold (VFLCOLD). Let
board set for ~10 minutes at full-load and measure output
(VFLHOT). If there is a change of more than a couple of mil-
livolts, adjust RCS1 and RCS2 using Equations 35 and 37.
5. Repeat Step 4 until cold and hot voltage measurements
remain the same.
1
ICRMS = D × IO ×
− 1
N × D
(34)
6. Measure output voltage from no-load to full-load using 5 A
steps. Compute the loadline slope for each change and then
average to get overall loadline slope (ROMEAS).
1
ICRMS = 0.125× 65 A ×
− 1 = 10.5 A
3 × 0.125
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2,000 hours of life.This makes it advisable
to further derate the capacitor or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 2200 µF, 16V Nichicon capacitors with a ripple current
rating of 3.5 A each.
7. If ROMEAS is off from RO by more than 0.05 mW, use the fol-
lowing to adjust the RPH values:
ROMEAS
RO
RPH
= RPH OLD ×
(36)
NEW
(
)
(
)
8. Repeat Steps 6 and 7 to check loadline and repeat adjust-
ments if necessary.
To reduce the input-current di/dt to below the recommended
9. Once complete with dc loadline adjustment, do not change
RPH, RCS1, RCS2, or RTH for rest of procedure.
1
RCS2 NEW
=
(
)
RCS1 OLD + RTH 25°C
1
−
(
)
(
)
(37)
RTH 25°C
RCS1 OLD × RTH 25°C + R
− RCS2 NEW × R
− RTH 25°C
(
)
(
)
(
)
CS2 OLD
CS1 OLD
(
)
(
)
(
)
(
)
(
)
(
)
REV. 0
–17–
ADP3180
10. Measure output ripple at no-load and full-load with scope
and make sure it is within spec.
form that may have two overshoots and one minor undershoot
(see Figure 9). Here,VDROOP is the final desired value.
AC Loadline Setting
11. Remove dc load from circuit and hook up dynamic load.
12. Hook up scope to output voltage and set to dc coupling
with time scale at 100 µs/div.
V
DROOP
13. Set dynamic load for a transient step of about 40 A at 1 kHz
with 50% duty cycle.
14. Measure output waveform (may have to use dc offset on
scope to see waveform).Try to use vertical scale of
100 mV/div or finer.
V
TRAN1
V
TRAN2
15. You will see a waveform that looks something like Figure 8.
Use the horizontal cursors to measureVACDRP andVDCDRP
as shown. DO NOT MEASURETHE UNDERSHOOT
OR OVERSHOOTTHAT HAPPENS IMMEDIATELY
AFTERTHE STEP.
Figure 9. Transient Setting Waveform
20. If both overshoots are larger than desired, try making the
following adjustments in this order. (NOTE: If these adjust-
ments do not change the response, you are limited by the
output decoupling.) Check the output response each time
you make a change as well as the switching nodes (to make
sure it is still stable).
V
ACDRP
a. Make ramp resistor larger by 25% (RRAMP).
V
b. ForVTRAN1, increase CB or increase switching frequency.
c. ForVTRAN2, increase RA and decrease CA by 25%.
DCDRP
21. For load release (see Figure 10), if VTRANREL is larger than
VTRAN1 (see Figure 9), you do not have enough output
capacitance.You will either need more capacitance or to
make the inductor values smaller (if you change inductors,
you need to start the design over using the spreadsheet and
this tuning procedure).
Figure 8. AC Loadline Waveform
16. If theVACDRP andVDCDRP are different by more than a
couple of millivolts, use Equation 38 to adjust CCS.You may
need to parallel different values to get the right one since
there are limited standard capacitor values available (it is a
good idea to have locations for two capacitors in the layout
for this).
V
TRANREL
V
DROOP
VACDRP
VDCDRP
CCS NEW = CCS OLD
×
(38)
(
)
(
)
17. Repeat Steps 11 to 13 and repeat adjustments if necessary.
Once complete, do not change CCS for the rest of the
procedure.
18. Set dynamic load step to maximum step size (do not use a
step size larger than needed) and verify that the output wave-
form is square (which meansVACDRP andVDCDRP are equal).
Figure 10. Transient Setting Waveform
NOTE: MAKE SURE LOAD STEP SLEW RATE AND
TURN-ON ARE SET FOR A SLEW RATE OF
~150–250 A/µs (for example, a load step of 50 A should take
200 ns–300 ns)WITH NO OVERSHOOT. Some dynamic
loads will have an excessive turn-on overshoot if a minimum
current is not set properly (this is an issue if using aVTT tool).
Since the ADP3180 turns off all of the phases (switches inductors
to ground), there is no ripple voltage present during load release.
Thus, you do not have to add headroom for ripple, allowing your
load releaseVTRANREL to be larger thanVTRAN1 by that amount
and still be meeting spec.
If VTRAN1 andVTRANREL are less than the desired final droop, this
implies that capacitors can be removed.When removing capaci-
tors, make sure to check the output ripple voltage as well to make
sure it is still within spec.
InitialTransient Setting
19. With dynamic load still set at maximum step size, expand
scope time scale to see 2 µs/div to 5 µs/div. You will see a wave-
–18–
REV. 0
ADP3180
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system. Key layout issues
are illustrated in Figure 11.
∑
∑
The output capacitors should be connected as closely as pos-
sible to the load (or connector) that receives the power (e.g.,
a microprocessor core). If the load is distributed, the capaci-
tors should also be distributed and generally in proportion to
where the load tends to be more dynamic.
SWITCH NODE
12V CONNECTOR
INPUT POWER PLANE
PLANES
Avoid crossing any signal lines over the switching power path
loop, described in the Power Circuitry section.
Power Circuitry
∑
The switching power path should be routed on the PCB to
encompass the shortest possible length in order to minimize
radiated switching noise energy (i.e., EMI) and conduc-
tion losses in the board. Failure to take proper precautions
often results in EMI problems for the entire PC system as
well as noise-related operational problems in the power con-
verter control circuitry.The switching power path is the loop
formed by the current path through the input capacitors and
the power MOSFETs including all interconnecting PCB
traces and planes.The use of short and wide interconnec-
tion traces is especially critical in this path for two reasons:
it minimizes the inductance in the switching loop, which can
cause high energy ringing, and it accommodates the high cur-
rent demand with minimal voltage loss.
THERMISTOR
KEEP-OUT
AREA
OUTPUT
POWER
PLANE
KEEP-OUT
AREA
KEEP-OUT
AREA
CPU
SOCKET
∑
Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding
it, is recommended.Two important reasons for this are improved
current rating through the vias and improved thermal perfor-
mance from vias extended to the opposite side of the PCB
where a plane can more readily transfer the heat to the air.
Make a mirror image of any pad being used to heatsink the
MOSFETs on the opposite side of the PCB to achieve the
best thermal dissipation to the air around the board. To fur-
ther improve thermal performance, the largest possible pad
area should be used.
KEEP-OUT
AREA
Figure 11. Layout Recommendations
General Recommendations
∑
For good results, at least a 4-layer PCB is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input, and output power, and wide interconnection
traces in the rest of the power delivery current paths. Keep
in mind that each square unit of 1 ounce copper trace has a
resistance of ~0.53 mW at room temperature.
∑
∑
The output power path should also be routed to encompass a
short distance.The output power path is formed by the cur-
rent path through the inductor, the output capacitors, and
the load.
∑
∑
Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating is
not exceeded.
For best EMI containment, a solid power ground plane
should be used as one of the inner layers extending fully
under all the power components.
If critical signal lines (including the output voltage sense lines
of the ADP3180) must cross through power circuitry, it is
best if a signal ground plane can be interposed between those
signal lines and the traces of the power circuitry.This serves
as a shield to minimize noise injection into the signals at the
expense of making signal ground a bit noisier.
Signal Circuitry
∑
The output voltage is sensed and regulated between the FB
pin and the FBRTN pin, which connects to the signal ground
at the load.To avoid differential mode noise pickup in the
sensed signal, the loop area should be small.Thus the FB and
FBRTN traces should be routed adjacent to each other atop
the power ground plane back to the controller.
∑
∑
An analog ground plane should be used around and under
the ADP3180 as a reference for the components associated
with the controller.This plane should be tied to the nearest
output decoupling capacitor ground and should not be tied
to any other power circuitry to prevent power currents from
flowing in it.
∑
The feedback traces from the switch nodes should be con-
nected as close as possible to the inductor.The CSREF signal
should be connected to the output voltage at the nearest
inductor to the controller.
The components around the ADP3180 should be located
close to the controller with short traces.The most important
traces to keep short and away from other traces are the FB
and CSSUM pins. Refer to Figure 11 for more details on
layout for the CSSUM node.
REV. 0
–19–
ADP3180
OUTLINE DIMENSIONS
28-LeadThin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
9.80
9.70
9.60
28
15
14
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8؇
0؇
0.30
0.19
0.20
0.09
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AE
–20–
REV. 0
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