ADP2380AREZ-R7 [ADI]
20 V, 4 A Synchronous Step-Down Regulator with Low-Side Driver; 20 V ，4A同步降压型稳压器，低侧驱动器
| 型号： | ADP2380AREZ-R7 |
| 厂家： | 
ADI |
| 描述： | 20 V, 4 A Synchronous Step-Down Regulator with Low-Side Driver |
| 文件： | 总28页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
20 V, 4 A Synchronous Step-Down
Regulator with Low-Side Driver
Data Sheet
ADP2380
FEATURES
TYPICAL APPLICATIONS CIRCUIT
V
Input voltage: 4.5 V to 20 V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
PVIN
PVIN
BST
Integrated 44 mΩ high-side MOSFET
0.6 V 1% reference voltage over temperature
Continuous output current: 4 A
Programmable switching frequency: 250 kHz to 1.4 MHz
Synchronizes to external clock: 250 kHz to 1.4 MHz
180° out-of-phase synchronization
Programmable UVLO
L
C
V
BST
OUT
C
IN
SW
SW
C
OUT
UVLO ADP2380
PGOOD
FET
LD
C
RT
VREG
PGND
GND
VREG
R
OSC
11
10
9
SYNC
EN/SS
COMP
R
R
TOP
C
SS
Power-good output
FB
External compensation
BOT
C
C_EA
R
Internal soft start with external adjustable option
Startup into a precharged output
Supported by ADIsimPower design tool
C_EA
C
CP_EA
Figure 1.
APPLICATIONS
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point of load application
100
95
90
85
80
75
70
65
60
55
50
V
V
V
= 1.2V
= 3.3V
= 5V
OUT
OUT
OUT
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current, VIN = 12 V, fSW = 250 kHz
GENERAL DESCRIPTION
The ADP2380 is a current mode control, synchronous, step-down,
dc-to-dc regulator. It integrates a 44 mΩ high-side power MOSFET
and a low-side driver to provide a high efficiency solution. The
ADP2380 runs from an input voltage of 4.5 V to 20 V and can
deliver 4 A of output current. The output voltage can be adjusted
to 0.6 V to 90% of the input voltage. The switching frequency of
the ADP2380 can be programmed from 250 kHz to 1.4 MHz or
fixed at 290 kHz or 540 kHz. The synchronization function allows
the switching frequency to be synchronized to an external clock
to minimize system noise.
External compensation and an adjustable soft start provide
design flexibility. The power-good output provides simple and
reliable power sequencing. Additional features include
programmable undervoltage lockout (UVLO), overvoltage
protection (OVP), overcurrent protection (OCP), and thermal
shutdown (TSD).
The ADP2380 operates over the −40°C to +125°C junction
temperature range and is available in a 16-lead TSSOP_EP
package.
Rev. 0
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Technical Support
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www.analog.com
ADP2380
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 15
Input Capacitor Selection.......................................................... 15
Output Voltage Setting .............................................................. 15
Voltage Conversion Limitations............................................... 15
Inductor Selection ...................................................................... 15
Output Capacitor Selection....................................................... 17
Low-Side Power Device Selection............................................ 17
Programming Input Voltage UVLO ........................................ 18
Compensation Design ............................................................... 18
ADIsimPower Design Tool ....................................................... 19
Design Example.............................................................................. 20
Output Voltage Setting .............................................................. 20
Frequency Setting....................................................................... 20
Inductor Selection ...................................................................... 20
Output Capacitor Selection....................................................... 20
Low-Side MOSFET Selection ................................................... 21
Compensation Components..................................................... 21
Soft Start Time Program ........................................................... 21
Input Capacitor Selection.......................................................... 21
Recommended External Components ........................................ 22
Circuit Board Layout Recommendations ................................... 24
Typical Applications Circuits........................................................ 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Information................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Functional Block Diagram ............................................................ 12
Theory of Operation ...................................................................... 13
Control Scheme .......................................................................... 13
Internal Regulator (VREG)....................................................... 13
Bootstrap Circuitry .................................................................... 13
Low-Side Driver.......................................................................... 13
Oscillator ..................................................................................... 13
Synchronization.......................................................................... 13
Enable and Soft Start.................................................................. 13
Power Good................................................................................. 14
Peak Current-Limit and Short-Circuit Protection................. 14
Overvoltage Protection (OVP)................................................. 14
Undervoltage Lockout (UVLO) ............................................... 14
Thermal Shutdown..................................................................... 14
REVISION HISTORY
12/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
ADP2380
SPECIFICATIONS
VIN = 12 V, T J = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
PVIN
PVIN Voltage Range
Quiescent Current
Shutdown Current
PVIN Undervoltage Lockout Threshold
VPVIN
IQ
ISHDN
4.5
2.2
85
20
V
No switching
EN/SS = GND
PVIN rising
2.8
125
4.3
3.9
3.4
170
4.5
mA
µA
V
PVIN falling
3.7
V
FB
FB Regulation Voltage
VFB
IFB
0°C < TJ < 85°C
−40°C < TJ < +125°C
0.594
0.591
0.6
0.6
0.01
0.606
0.609
0.1
V
V
µA
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
EA Sink Current
gm
ISOURCE
ISINK
340
45
45
470
60
60
590
75
75
µS
µA
µA
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
VVREG
VPVIN = 12 V, IVREG = 50 mA
VPVIN = 12 V, IVREG = 50 mA
7.7
65
8
350
100
8.4
V
mV
mA
Regulator Current Limit
130
SW
High-Side On Resistance1
High-Side Peak Current Limit
Negative Current-Limit Threshold Voltage2
SW Minimum On Time
SW Minimum Off Time
LOW-SIDE DRIVER (LD)
Rising Time2
VBST − VSW = 5 V
44
7
20
120
195
70
9
mΩ
A
mV
ns
4.8
tMIN_ON
tMIN_OFF
155
280
ns
tR
tF
CDL = 2.2 nF; see Figure 17
CDL = 2.2 nF; see Figure 20
20
10
4
ns
ns
Ω
Falling Time2
Sourcing Resistor
Sinking Resistor
6.5
4.5
2
Ω
BST
Bootstrap Voltage
OSCILLATOR (RT PIN)
Switching Frequency
VBOOT
fSW
4.7
5
5.6
V
RT pin connected to GND
RT pin open
ROSC = 100 kΩ
210
410
440
250
290
540
500
350
650
560
1400
kHz
kHz
kHz
kHz
Switching Frequency Range
SYNC
fSW
Synchronization Range
SYNC Minimum Pulse Width
SYNC Minimum Off Time
SYNC Input High Voltage
SYNC Input Low Voltage
EN/SS
Enable Threshold
Internal Soft Start
SS Pin Pull-Up Current
250
100
100
1.3
1400
kHz
ns
ns
V
0.4
0.5
3.6
V
V
1600
3.2
Clock cycles
µA
ISS_UP
2.4
Rev. 0 | Page 3 of 28
ADP2380
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER GOOD (PGOOD)
PGOOD Range
FB rising threshold
FB falling threshold
PGOOD from low to high
PGOOD from high to low
VPGOOD = 5 V
95
90
1024
16
0.01
125
%
%
PGOOD Deglitch Time
Clock cycles
Clock cycles
µA
PGOOD Leakage Current
PGOOD Output Low Voltage
UVLO
0.1
185
IPGOOD = 1 mA
mV
Rising Threshold
Falling Threshold
1.2
1.1
1.24
V
V
1.06
THERMAL
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
150
25
°C
°C
1 Pin-to-pin measurement.
2 Guaranteed by design.
Rev. 0 | Page 4 of 28
Data Sheet
ADP2380
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
Table 2.
Parameter
Rating
PVIN, PGOOD
SW
−0.3 V to +22 V
−1 V to +22 V
THERMAL INFORMATION
BST
VSW + 6 V
Table 3. Thermal Resistance
Package Type
UVLO, FB, EN/SS, COMP, SYNC, RT
VREG, LD
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
−0.3 V to +6 V
−0.3 V to +12 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
θJA
39.48
Unit
16-lead TSSOP_EP
°C/W
θJA is specified for the worst-case conditions, that is, a device
soldered in circuit board (4-layer, JEDEC standard board) for
surface-mount packages.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 28
ADP2380
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PVIN
PVIN
BST
SW
UVLO
PGOOD
RT
SW
ADP2380
TOP VIEW
(Not to Scale)
LD
VREG
PGND
GND
FB
SYNC
EN/SS
COMP
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED
TO A LARGE EXTERNAL COPPER GROUND PLANE
UNDERNEATH THE IC FOR THERMAL DISSIPATION.
Figure 3. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2
PVIN
Power Input. Connect PVIN to the input power source and connect a bypass capacitor between this pin
and PGND.
3
4
UVLO
PGOOD
Undervoltage Lockout Pin. An external resistor divider can be used to set the turn-on threshold.
Power-Good Output (Open Drain). It is recommended that a pull-up resistor of 10 kΩ to 100 kΩ be
connected to PGOOD.
5
RT
Frequency Setting. Connect a resistor between RT and GND to program the switching frequency
between 250 kHz and 1.4 MHz. If the RT pin is connected to GND, the switching frequency is set to 290 kHz.
If the RT pin is open, the switching frequency is set to 540 kHz.
6
7
SYNC
EN/SS
Synchronization Input. Connect this pin to an external clock to synchronize the switching frequency
between 250 kHz and 1.4 MHz (see the Oscillator section and the Synchronization section for details).
Enable (EN). When this pin voltage falls below 0.5 V, the regulator is disabled.
Soft Start (SS). This pin can also be used to set the soft start time. Connect a capacitor from SS to GND to
program the slow soft start time. If this pin is open, the regulator is enabled and uses the internal soft start.
8
9
COMP
FB
GND
PGND
VREG
LD
SW
BST
EPAD
Error Amplifier Output. Connect an RC network from COMP to FB.
Feedback Voltage Sense Input. Connect this pin to a resistor divider from VOUT
Analog Ground. Connect this pin to the ground plane.
Power Ground. Connect this pin to the source of the synchronous N-channel MOSFET.
Internal 8 V Regulator Output. Place a 1 µF ceramic capacitor between this pin and GND.
Low-Side Gate Driver Output. Connect this pin to the gate of the synchronous N-MOSFET.
Switch Node Output. Connect this pin to the output inductor.
.
10
11
12
13
14, 15
16
17
Supply Rail for the High-Side Gate Drive. Place a 0.1 µF ceramic capacitor between SW and BST.
Exposed Pad. The exposed pad should be soldered to a large external copper ground plane underneath
the IC for thermal dissipation.
Rev. 0 | Page 6 of 28
Data Sheet
ADP2380
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25oC, VIN = 12 V, VOUT = 3.3 V, L = 4.7 µH, COUT = 2 × 100 µF, fSW = 500 kHz, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
OUT
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
OUT
INDUCTOR: FDVE1040-3R3M
MOSFET: FDS6298
INDUCTOR: FDVE1040-6R8M
MOSFET: FDS6298
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 4. Efficiency at VIN = 12 V, fSW = 500 kHz
Figure 7. Efficiency at VIN = 12 V, fSW = 250 kHz
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V
V
V
V
V
V
= 1.0V
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
INDUCTOR: FDVE1040-4R7M
MOSFET: FDS6298
INDUCTOR: FDVE1040-1R5M
MOSFET: FDS6298
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 5. Efficiency at VIN = 18 V, fSW = 500 kHz
Figure 8. Efficiency at VIN = 5 V, fSW = 500 kHz
160
150
140
130
120
110
100
90
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
T
T
T
= –40°C
= +25°C
= +125°C
T
T
T
= –40°C
= +25°C
= +125°C
J
J
J
J
J
J
4
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
20
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 6. Shutdown Current vs. VIN
Figure 9. Quiescent Current vs. VIN
Rev. 0 | Page 7 of 28
ADP2380
Data Sheet
4.5
1.30
1.25
1.20
1.15
1.10
1.05
1.00
RISING
FALLING
RISING
FALLING
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
–40
–20
0
20
40
60
80
100 120
–40
–20
0
20
40
60
80
100
120
120
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. PVIN UVLO Threshold vs. Temperature
Figure 13. UVLO Pin Threshold vs. Temperature
3.3
3.2
3.1
3.0
2.9
2.8
606
604
602
600
598
596
594
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. SS Pin Pull-Up Current vs. Temperature
Figure 14. FB Voltage vs. Temperature
530
520
510
500
490
480
470
8.4
8.3
8.2
8.1
8.0
7.9
7.8
7.7
7.6
R
= 100kΩ
OSC
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. VREG Voltage vs. Temperature
Figure 12. Frequency vs. Temperature
Rev. 0 | Page 8 of 28
Data Sheet
ADP2380
8.0
7.5
7.0
6.5
6.0
5.5
5.0
70
60
50
40
30
20
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. MOSFET RDSON vs. Temperature
Figure 19. Current-Limit Threshold vs. Temperature
SW
SW
1
1
2
LD
LD
2
CH1 5.00V CH2 5.00V
M20.0ns
50.00%
A
CH2
5.50V
CH1 5.00V CH2 5.00V
M20.0ns
40.00%
A
CH2
3.70V
T
T
Figure 17. Low-Side Driver Rising Edge Waveform, CDL = 2.2 nF
Figure 20. Low-Side Driver Falling Edge Waveform, CDL = 2.2 nF
V
(AC)
OUT
EN/SS
3
1
I
L
V
OUT
1
SW
I
OUT
4
2
4
2
PGOOD
B
B
B
CH1 10mV
CH2 10V
CH4 2A Ω
M2.00µs
50.20%
A
CH2
8.00V
CH1 2.00V
CH3 5.00V
CH2 5.00V
B
CH4 2.00A Ω
M2.00ms
60.40%
A
CH2
4.40V
W
W
W
B
T
T
W
W
Figure 18. Working Mode Waveform
Figure 21. Soft Start with Full Load
Rev. 0 | Page 9 of 28
ADP2380
Data Sheet
SYNC
EN/SS
3
3
V
OUT
1
2
SW
PGOOD
2
I
L
4
B
B
B
CH1 2.00V
CH3 5.00V
CH2 5.00V
M2.00ms
60.40%
A
CH2
4.40V
2.96A
1.32V
CH3 5.00V
CH2 10.0V M1.00µs
50.40%
A
CH2
7.40V
W
W
W
B
CH4 2.00A Ω
T
T
W
Figure 22. Precharged Output
Figure 25. External Synchronization
V
(AC)
OUT
V
(AC)
OUT
1
1
V
IN
SW
I
3
2
OUT
4
B
W
B
B
CH1 20mV
CH3 5V Ω
CH2 10V
M1ms
30%
A
CH3
13.8V
CH1 100mV
M200µs
70.40%
A
CH4
W
W
B
T
B
CH4 2.00A Ω
T
W
W
Figure 23. Load Transient Response, 1 A to 4 A
Figure 26. Line Transient Response, VIN from 10 V to 16 V, IOUT = 4 A
V
V
OUT
OUT
1
2
4
1
SW
SW
2
I
I
L
L
4
B
B
CH1 2.00V
CH2 10.0V
CH4 5.00A Ω
M4.00ms
20.40%
A CH1
CH1 2.00V
CH2 10.0V
CH4 5.00A Ω
M4.00ms
70.20%
A
CH1
1.96V
W
W
B
B
W
T
W
T
Figure 24. Output Short Entry
Figure 27. Output Short Recovery
Rev. 0 | Page 10 of 28
Data Sheet
ADP2380
5
4
3
2
5
4
3
2
1
V
V
V
V
V
V
= 1V
OUT
OUT
OUT
OUT
OUT
OUT
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
1
V
OUT
V
OUT
V
OUT
0
45
0
45
55
65
75
85
95
105
55
65
75
85
95
105
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 28. Load Current vs. Ambient Temperature, VIN = 12 V,
SW = 500 kHz
Figure 29. Load Current vs. Ambient Temperature, VIN = 12 V,
SW = 250 kHz
f
f
Rev. 0 | Page 11 of 28
ADP2380
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
VREG
ADP2380
CLK
RT
BIAS AND DRIVER
REGULATOR
PVIN
OSCILLATOR
SYNC
SLOPE RAMP
UVLO
PVIN
320kΩ
BOOST
REGULATOR
UVLO
+
125kΩ
1.2V
–
+
A
CS
–
+
OCP
–
HICCUP
MODE
I
MAX
SLOPE RAMP
Σ
COMP
BST
SW
0.6V
+
I
SS
+
CMP
–
NFET
EN/SS
FB
+
DRIVER
AMP
–
CONTROL
LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
OVP
0.7V
–
VREG
PROTECTION
+
–
CLK
DRIVER
LD
0.54V
PGND
+
PGOOD
GND
NEGATIVE
CURRENT-LIMIT
CMP
DEGLITCH
–
+
Figure 30. Functional Block Diagram
Rev. 0 | Page 12 of 28
Data Sheet
ADP2380
THEORY OF OPERATION
The ADP2380 is a synchronous, step-down, dc-to-dc regulator.
It uses current mode architecture with an integrated high-side
power switch and a low-side driver. It targets high performance
applications that require high efficiency and design flexibility.
A 100 kΩ resistor sets the frequency to 500 kHz, and a 215 kΩ
resistor sets the frequency to 250 kHz. Figure 31 shows the typical
relationship between fSW and ROSC
.
1400
The ADP2380 can operate with an input voltage from 4.5 V to
20 V and regulate the output voltage down to 0.6 V. Additional
features for design flexibility include programmable switching
frequency, soft start, external compensation, and power-good pin.
1200
1000
800
600
400
200
0
CONTROL SCHEME
The ADP2380 uses fixed frequency, peak current mode PWM
control architecture. At the start of each oscillator cycle, the
high-side N-MOSFET is turned on, putting a positive voltage
across the inductor. Current in the inductor increases until
the current sense signal crosses the peak inductor current thresh-
old that turns off the high-side N-MOSFET and turns on the
low-side N-MOSFET. This puts a negative voltage across the
inductor, causing the inductor current to decrease. The low-
side N-MOSFET stays on for the rest of the cycle.
20
60
100
140
180
(kΩ)
220
260
300
R
OSC
Figure 31. Switching Frequency vs. ROSC
SYNCHRONIZATION
INTERNAL REGULATOR (VREG)
To synchronize the ADP2380, connect an external clock to the
SYNC pin. The frequency of the external clock can be in the
range of 250 kHz to 1.4 MHz. During synchronization, the
switching rising edge runs 180° out of phase with the external
clock rising edge.
The internal regulator provides a stable supply for the internal
circuits and provides bias voltage for the low-side gate driver.
Placing a 1 µF ceramic capacitor between VREG and GND is
recommended. The internal regulator also includes a current-
limit circuit to protect the circuit if the maximum external
load is added.
When the ADP2380 is being synchronized, connect a resistor
from the RT pin to GND to program the internal oscillator to
run at 90% to 110% of the external synchronization clock.
BOOTSTRAP CIRCUITRY
The ADP2380 has integrated the boot regulator to provide the
gate drive voltage for the high-side N-MOSFET. It generates a
5 V bootstrap voltage between BST and SW by differential
sensing.
ENABLE AND SOFT START
When the voltage of the EN/SS pin exceeds 0.5 V, the ADP2380
starts operation.
The ADP2380 has an internal digital soft start. The internal soft
start time can be calculated by using the following equation:
It is recommended to place a 0.1 µF, X7R or X5R ceramic
capacitor between the BST pin and the SW pin.
1600
LOW-SIDE DRIVER
tSS _ INT
=
(ms)
f
SW [kHz]
The LD pin provides the gate driver for the low-side N-channel
MOSFET. Internal circuitry monitors the external MOSFET to
ensure break-before-make switching to prevent cross conduction.
A slow soft start time can be programmed by the EN/SS pin.
Place a capacitor between the EN/SS pin and GND. An internal
current charges this capacitor to establish the soft start ramp.
The soft start time can be calculated by using the following
equation:
OSCILLATOR
The ADP2380 switching frequency is controlled by the RT pin.
If the RT pin is connected to GND, the switching frequency is
set to 290 kHz. If the RT pin is open, the switching frequency is
set to 540 kHz. A resistor connected from RT to GND can
program the switching frequency according to the following
equation:
0.6V×CSS
ISS _UP
tSS _ EXT
=
where:
SS is the soft start capacitance.
SS_UP is the soft start pull-up current (3.2 µA).
C
I
57,600
OSC[kΩ]+15
f
SW[kHz]=
R
The internal error amplifier includes three positive inputs: the
internal reference voltage, the internal digital soft start voltage,
and the EN/SS voltage. The error amplifier regulates the FB
voltage to the lowest of the three voltages.
Rev. 0 | Page 13 of 28
ADP2380
Data Sheet
If the output voltage is charged prior to turn-on, the ADP2380
prevents the low-side MOSFET from turning on, which discharges
the output voltage until the soft start voltage exceeds the voltage
on the FB pin.
If the current-limit fault is cleared, the regulator resumes
normal operation. Otherwise, it reenters hiccup mode.
The ADP2380 also provides a sink current limit to prevent the
low-side MOSFET from sinking a large amount of current from
the load. When the voltage across the low-side MOSFET exceeds
the sink current-limit threshold, which is typically 20 m V, the
low-side MOSFET turns off immediately for the rest of this cycle.
Both high-side and low-side MOSFETs turn off until the next
clock cycle.
When the regulator is disabled or a current fault happens, the
soft start capacitor is discharged, and the internal digital soft
start is reset to 0 V.
POWER GOOD
The power-good (PGOOD) pin is an active high, open-drain
output that requires a pull-up resistor. A logic high indicates
that the voltage at the FB pin (and, therefore, the output
voltage) is above 95% of the reference voltage and there is a
1024 cycle waiting period before PGOOD is pulled high. A logic
low indicates that the voltage at the FB pin is below 90% of the
reference voltage and there is a 16-cycle waiting period before
PGOOD is pulled low.
In some cases, the input voltage (PVIN) ramp rate is too slow or
the output capacitor is too large to support the setting regulation
voltage during the soft start, causing the regulator to enter hiccup
mode. To avoid such cases, use a resistor divider at the UVLO
pin to program the UVLO input voltage, or use a longer soft
start time.
OVERVOLTAGE PROTECTION (OVP)
The ADP2380 provides an overvoltage protection feature to
protect the system against an output that shorts to a higher
voltage supply or the occurrence of a strong load transient.
If the feedback voltage increases to 0.7 V, the internal high-side
MOSFET and low-side driver are turned off until the voltage at FB
decreases to 0.63 V. At that time, the ADP2380 resumes normal
operation.
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2380 has a peak current-limit protection circuit to
prevent current runaway. During soft start, the ADP2380 uses
frequency foldback to prevent output current runaway. The
switching frequency is reduced according to the voltage on the
FB pin, which allows more time for the inductor to discharge.
The correlation between the switching frequency and FB pin
voltage is shown in Table 5.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO pin enable threshold is 1.2 V with 100 mV hysteresis.
The ADP2380 has an internal voltage divider that consists of
two resistors from PVIN to GND, with 320 kΩ for the high-side
resistor and 125 kΩ for the low-side resistor. An external resistor
divider from PVIN to GND can be used to override the internal
resistor divider.
Table 5. Switching Frequency and FB Pin Voltage
FB Pin Voltage
Switching Frequency
VFB ≥ 0.4 V
fSW
0.4 V > VFB ≥ 0.2 V
VFB < 0.2 V
fSW/2
fSW/4
THERMAL SHUTDOWN
For heavy load protection, the ADP2380 uses hiccup mode for
overcurrent protection. When the inductor peak current reaches
the current-limit value, the high-side MOSFET turns off and
the low-side driver turns on until the next cycle, while the
overcurrent counter increments. If the overcurrent counter
reaches 10, or the FB pin voltage falls to ≤0.4 V after the soft
start, the regulator enters hiccup mode. The high-side MOSFET
and low-side MOSFET are both turned off. The regulator remains
in this mode for 4096 clock cycles and then attempts to restart.
In the event that the ADP2380 junction temperatures rise above
150°C, the thermal shutdown circuit turns off the regulator.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, and/or high ambient
temperature. A 25°C hysteresis is included so that, when thermal
shutdown occurs, the ADP2380 does not return to operation until
the on-chip temperature drops below 125°C. Upon recovery, soft
start is initiated prior to normal operation.
Rev. 0 | Page 14 of 28
Data Sheet
ADP2380
APPLICATIONS INFORMATION
The maximum output voltage for a given input voltage and
INPUT CAPACITOR SELECTION
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is typically
200 ns, and the maximum duty cycle of the ADP2380 is
typically 90%.
The input decoupling capacitor is used to attenuate high
frequency noise on the input. This capacitor should be a
ceramic capacitor in the range of 10 µF to 47 µF. Place the
capacitor close to the PVIN pin. The loop composed of this
input capacitor, high-side NFET, and low-side NFET must be
kept as small as possible.
The maximum output voltage limited by the minimum off time
at a given input voltage and frequency can be calculated using
the following equation:
The voltage rating of the input capacitor must be greater than
the maximum input voltage. The rms current rating of the input
capacitor should be larger than the following equation:
V
OUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) ×
OUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT_MAX
where:
OUT_MAX is the maximum output voltage.
MIN_OFF is the minimum off time.
I
(2)
IC
= IOUT × D ×(1 − D)
_RMS
IN
V
t
I
OUTPUT VOLTAGE SETTING
OUT_MAX is the maximum output current.
The output voltage of ADP2380 can be set by an external
resistive divider using the following equation:
The maximum output voltage, limited by the maximum duty
cycle at a given input voltage, can be calculated by using the
following equation:
RTOP
RBOT
VOUT = 0.6 × 1 +
VOUT_MAX = DMAX × VIN
(3)
To limit output voltage accuracy degradation due to FB bias
current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT is less than 30 kΩ.
where DMAX is the maximum duty.
As Equation 1 to Equation 3 show, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.
Table 6 lists the recommended resistor divider values for
various output voltage options.
INDUCTOR SELECTION
Table 6. Resistor Divider for Different Output Voltages
The inductor value is determined by the operating frequency,
VOUT (V)
RTOP
,
1% (kΩ)
RBOT, 1% (kΩ)
input voltage, output voltage, and inductor ripple current. Using
a small inductor leads to a faster transient response but degrades
efficiency, due to larger inductor ripple current; whereas, using
a large inductor value leads to smaller ripple current and better
efficiency but results in a slower transient response.
1.0
10
15
1.2
10
10
1.5
15
10
1.8
20
10
2.5
3.3
5.0
47.5
10
22
15
2.21
3
As a guideline, the inductor ripple current, ΔIL, is typically set
to 1/3 of the maximum load current. The inductor can be
calculated using the following equation:
VOLTAGE CONVERSION LIMITATIONS
(
VIN − VOUT
)
× D
L =
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2380 is typically 120 ns. The
minimum output voltage at a given input voltage and frequency
can be calculated using the following equation:
∆IL × fSW
where:
V
V
IN is the input voltage.
OUT is the output voltage.
ΔIL is the inductor current ripple.
SW is the switching frequency.
D is the duty cycle.
V
OUT_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) ×
OUT_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT_MIN
where:
OUT_MIN is the minimum output voltage.
MIN_ON is the minimum on time.
SW is the switching frequency.
f
I
(1)
VOUT
D =
V
t
VIN
The ADP2380 uses adaptive slope compensation in the current
loop to prevent subharmonic oscillations when the duty cycle
is larger than 50%. The internal slope compensation limits the
minimum inductor value.
f
R
R
DSON_HS is the high-side MOSFET on resistance.
DSON_LS is the low-side MOSFET on resistance.
IOUT_MIN is the minimum output current.
RL is the series resistance of the output inductor.
Rev. 0 | Page 15 of 28
ADP2380
Data Sheet
For a duty cycle that is larger than 50%, the minimum inductor
value is determined by the following equation:
The saturation current of the inductor must be larger than
the peak inductor current. For the ferrite core inductors with
a quick saturation characteristic, the saturation current rating
of the inductor must be higher than the current-limit threshold of
the switch to prevent the inductor from becoming saturated.
VOUT × (1 − D)
L(Minimum) =
2 × fSW
The inductor peak current is calculated using the following
equation:
The rms current of the inductor can be calculated by
∆IL2
IRMS
= +
IO2UT
∆IL
IPEAK = IOUT +
12
2
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 7 lists some recommended inductors.
Table 7. Recommended Inductors
Vendor
Part No.
Value (µH)
1.5
2.2
3.3
4.7
ISAT (A)
13.7
11.4
9.8
8.2
7.1
IRMS (A)
14.6
11.6
9.0
8.0
7.1
5.2
17.5
15
12
10
9.5
8.0
6.8
20
DCR (mΩ)
4.6
6.8
10.1
13.8
20.2
34.1
4.1
Toko
FDVE1040-1R5M
FDVE1040-2R2M
FDVE1040-3R3M
FDVE1040-4R7M
FDVE1040-6R8M
FDVE1040-100M
IHLP4040DZ-1R0M-01
IHLP4040DZ-1R5M-01
IHLP4040DZ-2R2M-01
IHLP4040DZ-3R3M-01
IHLP4040DZ-4R7M-01
IHLP4040DZ-6R8M-01
IHLP4040DZ-100M-01
744 325 120
6.8
10
6.1
Vishay
1.0
1.5
2.2
3.3
4.7
6.8
10
36
27.5
25.6
18.6
17
13.5
12
5.8
9
14.4
16.5
23.3
36.5
1.8
Würth Elektronik
1.2
25
744 325 180
1.8
18
16
3.5
744 325 240
2.4
17
14
4.75
5.9
744 325 330
3.3
15
12
744 325 420
4.2
14
11
7.1
744 325 550
5.5
12
10
10.3
Rev. 0 | Page 16 of 28
Data Sheet
ADP2380
Select the largest output capacitance given by COUT_UV, COUT_OV
and COUT_RIPPLE to meet both load transient and output ripple
performance.
,
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output ripple
voltage and the loop dynamics of the regulator.
The selected output capacitor voltage rating should be greater
than the output voltage. The rms current rating of the output
capacitor should be larger than the result of the following equation:
During a load step transient on the output, for example, when
the load is suddenly increased, the output capacitor supplies the
load until the control loop has a chance to ramp up the inductor
current, which causes the output to undershoot. The output
capacitance required to satisfy the voltage droop requirement
can be calculated using the following equation:
∆IL
IC
=
_ RMS
OUT
12
LOW-SIDE POWER DEVICE SELECTION
KUV × ∆ISTEP2 × L
The ADP2380 has an integrated low-side MOSFET driver that
drives the low-side NFET. The selection of the low-side NFET
affects the dc-to-dc regulator performance.
COUT _UV
=
2 ×
(
VIN −VOUT × ∆VOUT _UV
)
where:
UV is a factor typically of 2.
ΔISTEP is the load step.
The selected MOSFET must meet the following requirements:
K
•
•
•
Drain-source voltage (VDS) must be greater than
1.2 × VIN.
Drain current (ID) must be greater than 1.2 × ILIMIT_MAX
which is the selected maximum current-limit threshold.
The ADP2380 low-side gate drive voltage is 8 V. Ensure
that the selected MOSFET can fully turn on at 8 V. Total
gate charge (Qg at 8 V) must be less than 50 nC. Lower Qg
characteristics constitute higher efficiency.
ΔVOUT_UV is the allowable undershoot on the output voltage.
Another case occurs when a load is suddenly removed from
the output. The energy stored in the inductor rushes into the
capacitor, which causes the output to overshoot. The output
capacitance required to meet the overshoot requirement can
be calculated using the following equation:
,
2
KOV × ∆ISTEP × L
COUT _ OV
=
•
The low-side MOSFET carries the inductor current when
the high-side MOSFET is turned off. For low duty cycle
applications, the low-side MOSFET carries the output
current during most of the period. To achieve higher
efficiency, it is important to select a low on-resistance
MOSFET. The power conduction loss of the low-side
MOSFET can be calculated by using the following
equation:
2
(
VOUT + ∆VOUT _ OV
)
2 −VOUT
where:
OV is a factor, typically, of 2.
K
ΔVOUT_OV is the allowable overshoot on the output voltage.
The output ripple is determined by the ESR and the capaci-
tance. Use the following equation to select a capacitor that can
meet the output ripple requirements:
P
FET_LOW = IOUT2 × RDSON × (1 – D)
∆IL
COUT _ RIPPLE
=
where RDSON is the on resistance of the low-side MOSFET.
Make sure that the MOSFET can handle the thermal
dissipation due to the power loss.
8 × fSW × ∆VOUT _ RIPPLE
•
∆VOUT _RIPPLE
RESR
=
∆IL
Some recommended MOSFETs are listed in Table 8.
where:
ΔVOUT_RIPPLE is the allowable output ripple voltage.
ESR is the equivalent series resistance of the output capacitor.
R
Table 8. Recommended MOSFETs
Vendor
Fairchild
Fairchild
Fairchild
Vishay
AOS
Part No.
FDS6298
FDS8880
FDMS7578
SiA430DJ
AON7402
AO4884L
VDS (V)
30
30
25
20
ID (A)
13
10.7
17
10.8
39
10
RDSON (mΩ)
Qg (nC)
10
12
8
5.3
12
12
8
18.5
15
16
30
40
7.1
13.6
AOS
Rev. 0 | Page 17 of 28
ADP2380
Data Sheet
The control to output transfer function is given by
PROGRAMMING INPUT VOLTAGE UVLO
The internal voltage divider from PVIN to GND sets the default
start/stop values of the input voltage to achieve undervoltage
lockout (UVLO) performance. The default rising/falling threshold
of PVIN and UVLO are listed in Table 9. For a more accurate,
externally adjustable UVLO, these default values can be replaced
by using an external voltage divider, as shown in Figure 32.
Lower values of the external resistors are recommended to obtain
a high accuracy UVLO threshold because the values of the internal
320 kΩ and 125 kΩ resistors may vary by as much as 20%.
s
1+
1+
2×π × fZ
s
VOUT (s)
GVD (s) =
= AVI ×R×
VCOMP (s)
2×π × fP
1
fZ
=
=
2×π × RESR ×COUT
1
fP
2×π × (R + RESR )×COUT
Table 9. Default Rising/Falling Voltage Threshold
where:
VI = 8.7 A/V.
R is the load resistance.
OUT is the output capacitance.
ESR is the equivalent series resistance of the output capacitor.
Pin
Rising Threshold (V)
Falling Threshold (V)
A
PVIN
UVLO
4.28
1.2
3.92
1.1
C
R
ADP2380
V
PVIN
The external voltage loop is compensated by a transconductance
amplifier with a simple external RC network placed either between
COMP and GND or between COMP and FB, as shown in
Figure 33 and Figure 34, respectively.
IN
320kΩ
R1
R2
UVLO
125kΩ
Compensation Network Between COMP and GND
Figure 33 shows the simplified peak current mode control,
small signal circuit with a compensation network placed
between COMP and GND.
Figure 32. External Programmable UVLO
A 1 kΩ resistor is an appropriate choice for R2. Use the following
equation to obtain the value of R1 for a chosen input voltage
rising threshold:
V
V
OUT
OUT
R
ADP2380
TOP
COMP
V
COMP
FB
+
–
A
VI
(
VIN _ RISING −1.2 V
)
× R2
C
OUT
ESR
–
gm
R1 =
1.2 V
+
R
R
BOT
R
C
C
CP
where VIN_RISING is the rising threshold of VIN.
The falling threshold of VIN can be determined by
1.1 V × R1
R
C
C
GND
VIN _ FALLING
=
+ 1.1 V
Figure 33. Small Signal Circuit with Compensation Network Between COMP
and GND
R2
where VIN_FALLING is the falling threshold of VIN.
The RC and CC compensation components contribute a zero,
and the optional CCP and RC contribute an optional pole.
COMPENSATION DESIGN
The ADP2380 uses a peak current mode control architecture
for excellent load and line transient response. For peak current
mode control, the power stage can be simplified as a voltage
controlled current source, supplying current to the output
capacitor and load resistor. It consists of one domain pole and
one zero contributed by the output capacitor ESR.
The closed-loop transfer function is as follows:
RBOT
−gm
1+ RC ×CC ×s
RC ×CC ×CCP
TV (s) =
×
×
×GVD (s)
RBOT + RTOP CC +CCP
s× 1+
×s
CC +CCP
Rev. 0 | Page 18 of 28
Data Sheet
ADP2380
Use the following design guidelines to select the RC, CC, and CCP
compensation components:
Assuming that the compensation networks of Figure 33 and
Figure 34 have the same pole and zero,
•
Determine the cross frequency, fC. Generally, fc is between
SW/12 and fSW/6.
RC can be calculated by
CCP _ EA +CC _ EA
RCCC = RC _ EACC _ EA
−
f
gm
•
r0 RCCCCCP = r0 RC _ EACC _ EACCP _ EA
+
2×π ×VOUT × COUT × fC
RC =
VREF ×gm × A
VI
RC _ EACC _ EACCP _ EA (RTOP // RBOT )(1 + gm ×r0 )
where:
V
REF = 0.6 V.
r0 (CCP +CC ) + RCCC =
r0 (CCP _ EA +CC _ EA ) + RC _ EACC _ EA
(CCP _ EA + CC _ EA )(RTOP // RBOT )(1 + gm × r0 )
where:
gm = 470 µS.
+
•
•
Place the compensation zero at the domain pole, fP. CC can
be determined by
(R+ RESR )×COUT
CC =
r0 is the equivalent output impedance of the transconductance
amplifier, 40 MΩ.
RC
C
CP is optional, and it can be used to cancel the zero caused
RTOPRBOT
by the ESR of the output capacitors.
RTOP // RBOT
=
RTOP + RBOT
RESR ×COUT
CCP
=
Solve the preceding equations to obtain
RC
r RCCCCCP
0
Compensation Network Between COMP and FB
CC _ EA = B × gm
−
(B + RCCC )(r + A)
0
The compensation RC network can also be placed between
COMP and FB, as shown in Figure 34.
B + RCCC
CC _ EA
RC _ EA
CCP _ EA
where:
=
C
CP_EA
r RCCCCCP
0
=
C
R
C_EA
C_EA
(B + RCCC )(r + A)
0
V
V
R
OUT
OUT
R
R
ADP2380
TOP
A = (RTOP // RBOT )(1 + gm × r )
COMP
FB
0
+
–
A
VI
C
–
gm
OUT
r (CCP + CC )
1 + gm (A + r )
V
COMP
0
B =
+
0
BOT
R
ESR
ADIsimPOWER DESIGN TOOL
GND
The ADP2380 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs that are optimized for a specific design goal. The
tools enable the user to generate a full schematic and bill of
materials and calculate performance in minutes. ADIsimPower
can optimize designs for cost, area, efficiency, and parts count,
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For
more information about the ADIsimPower design tools, visit
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can request an unpopulated board.
Figure 34. Small Signal Circuit with Compensation Network Between COMP
and FB
When connecting the compensation network as shown in
Figure 34, it requires the same pole and zero as in Figure 33
to maintain the same compensation performance.
Rev. 0 | Page 19 of 28
ADP2380
Data Sheet
DESIGN EXAMPLE
This section provides the procedures for selecting the external
components based on the example specifications listed in Table 10.
The schematic of this design example is shown in Figure 36.
Calculate the rms current flowing through the inductor using
the following equation:
2
∆IL
12
2
IRMS
=
IOUT
+
Table 10. Step-Down DC-to-DC Regulator Requirements
Parameter
Specification
VIN = 12.0 V 10%
VOUT = 3.3 V
This results in IRMS = 4.01 A.
Input Voltage
According to the calculated rms and peak inductor current
values, select an inductor with a minimum rms current rating of
4.01 A and a minimum saturation current rating of 4.51 A.
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
IOUT = 4 A
∆VOUT_RIPPLE = 33 mV
5%, 1 A to 4 A, 2 A/μs
fSW = 500 kHz
To protect the inductor from reaching its saturation limit, the
inductor should be rated for at least a 7 A saturation current for
reliable operation.
Switching Frequency
OUTPUT VOLTAGE SETTING
Based on these requirements, select a 4.7 μH inductor, such as
the FDVE1040-4R7M from Toko, which has a 13.8 mΩ DCR
and an 8.2 A saturation current.
Choose a 10 kΩ resistor as the top feedback resistor (RTOP) and
calculate the bottom feedback resistor (RBOT).
0.6
OUTPUT CAPACITOR SELECTION
RBOT = RTOP
×
VOUT − 0.6
The output capacitor is required to meet both the output voltage
ripple requirement and the load transient response.
To set the output voltage to 3.3 V, the resistors values are
TOP = 10 kΩ, RBOT = 2.21 kΩ.
R
To meet the output voltage ripple requirement, use the following
equation to calculate the ESR and capacitance of the output
capacitor:
FREQUENCY SETTING
Connect a 100 kΩ resistor from the RT pin to GND to set the
switching frequency at 500 kHz.
∆IL
COUT _ RIPPLE
=
8 × fSW × ∆VOUT _ RIPPLE
INDUCTOR SELECTION
∆VOUT _ RIPPLE
The peak-to-peak inductor ripple current, ∆IL, is set to 30% of
the maximum output current. Use the following equation to
estimate the inductor value:
RESR
=
∆IL
This results in COUT_RIPPLE = 7.7 μF and RESR = 32 mΩ.
(VIN −VOUT ) × D
L =
To meet the 5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
∆IL × fSW
where:
V
IN = 12 V.
2
KOV × ∆ISTEP × L
VOUT = 3.3 V.
COUT _ OV
=
=
2
(VOUT + ∆VOUT _ OV )2 − VOUT
D = VOUT/VIN = 0.275.
∆IL = 1.2A.
2
KUV × ∆ISTEP × L
COUT _UV
fSW = 500 kHz.
2 × (VIN −VOUT ) × ∆VOUT _UV
This results in L = 3.987 μH. Choose the standard inductor
value of 4.7 μH.
where:
OV = KUV = 2, the coefficients for estimation purposes.
∆ISTEP = 3 A, the load transient step.
∆VOUT_OV = 5%VOUT, the overshoot voltage.
∆VOUT_UV = 5%VOUT, the undershoot voltage.
K
Calculate the peak-to-peak inductor ripple current using the
following equation:
(
VIN − VOUT × D
)
∆IL
=
L × fSW
This results in COUT_OV = 76 μF and COUT_UV = 30 μF.
This results in ∆IL = 1.02 A.
According to the preceding calculation, the output capacitance
must be larger than 76 μF, and the ESR of the output capacitor
must be smaller than 32 mΩ. It is recommended that two pieces
of 47 μF/X5R/6.3 V ceramic capacitors be used, such as the
GRM32ER60J476ME20 from Murata, with an ESR of 2 mΩ.
Calculate the peak inductor current using the following equation:
∆IL
2
IPEAK = IOUT
+
This results in IPEAK = 4.51 A.
Rev. 0 | Page 20 of 28
Data Sheet
ADP2380
This results in the following:
C_EA = 52.3 kΩ.
LOW-SIDE MOSFET SELECTION
R
A low RDSON N-channel MOSFET is chosen as a high efficiency
solution. The breakdown voltage of the MOSFET must be
higher than 1.2 × VIN, and the drain current must be larger than
CC_EA = 1055 pF.
CCP_EA = 2.45 pF.
Choose the standard values for RC_EA = 49.9 kΩ, CC_EA = 1000 pF,
and CCP_EA = 2.2 pF.
1.2 × ILIMIT
.
It is recommended to use a 30 V, N -channel MOSFET, such as
the FDS6298 from Fairchild. The RDSON of the FDS6298 at a 4.5 V
driver voltage is 9.4 mΩ, and the total gate charge at 5 V is 10 nC.
Figure 35 shows the Bode plot at 4 A. The cross frequency is
43 kHz, and the phase margin is 59°.
60
180
144
108
72
COMPENSATION COMPONENTS
48
For better load transient and stability performance, set the cross
frequency, fC, at fSW/10. In this case, fC = 1/500 kHz = 50 kHz.
36
24
r0 RCCCCCP
CC _ EA = B × gm
−
12
36
(B + RCCC )(r + A)
0
0
0
B + RCCC
CC _ EA
RC _ EA
=
–12
–24
–36
–48
–36
–72
–108
–144
r RCCCCCP
0
CCP _ EA
=
(B + RCCC )(r + A)
0
where:
RC =
–60
1k
–180
10k
100k
1M
2 × π ×VOUT × COUT × fC
VREF × gm × AVI
FREQUENCY (Hz)
=
Figure 35. Bode Plot at 4 A
2 × π × 3.3 V × 2 × 32 μF × 50kHz
0.6 V × 470 μS × 8.7 A/V
SOFT START TIME PROGRAM
= 27.1 kΩ
= 1.96 nF
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
(
R + RESR × COUT
)
CC =
=
RC
(3.3 V/ 4 A + 0.002 Ω) × 2 × 32 μF
27.1 kΩ
tSS _ EXT × ISS _UP
4ms × 3.2μA
CSS
=
=
= 21.3 nF
0.6 V
0.6 V
RESR × COUT
0.002 Ω × 2 × 32 μF
CCP
=
=
= 4.73 pF
RC
27.1 kΩ
Choose a standard component value, CSS = 22 nF.
INPUT CAPACITOR SELECTION
RTOP RBOT
10 kΩ × 2.21 kΩ
10 kΩ + 2.21 kΩ
A =
(
1 + gm × r0
)
=
×
RTOP + RBOT
(1 + 470 µS × 40 MΩ) = 3.4 × 107
A minimum 10 μF ceramic capacitor must be placed near the
PVIN pin. In this application, one 10 μF, X5R, 25 V ceramic
capacitor is recommended.
r0 (CCP + CC )
1 + gm (A + r0 )
2.26 × 10−6
40 MΩ × (4.73 pF + 1.96 nF)
1 + 470 μS × (3.4 × 107 + 40 MΩ
B =
=
=
V
= 12V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L1
C
0.1µF
PVIN
PVIN
BST
BST
4.7µH
V
= 3.3V
OUT
C
IN
SW
SW
10µF
25V
C
C
OUT2
OUT1
47µF
6.3V
47µF
6.3V
UVLO ADP2380
PGOOD
M1
FDS6298
R
LD
OSC
100kΩ
C
VREG
1µF
RT
VREG
PGND
GND
SYNC
EN/SS
COMP
R
TOP
10kΩ
1%
C
22nF
SS
FB
R
BOT
2.21kΩ
1%
C
C_EA
R
C_EA
49.9kΩ
1000pF
C
CP_EA
2.2pF
Figure 36. Design Example Schematic
Rev. 0 | Page 21 of 28
ADP2380
Data Sheet
RECOMMENDED EXTERNAL COMPONENTS
Table 11. Recommended External Components for Typical Applications with Compensation Network Between COMP and GND Pins,
4 A Output Current
fSW (kHz)
VIN (V)
12
12
12
12
12
12
12
5
VOUT (V)
L (µH)
3.3
3.3
4.7
4.7
6.8
6.8
10
COUT (µF)1
680 + 2 × 100
680
RTOP (kΩ)
RBOT (kΩ)
RC (kΩ)
CC (pF)
3900
3900
3900
3900
3900
3900
3900
3900
3900
3900
3900
3900
3900
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
CCP (pF)
150
100
100
100
10
250
1
10
15
47
1.2
1.5
1.8
2.5
3.3
5
10
10
47
680
15
10
60.4
51
470
20
10
3 × 100
2 × 100
100 + 47
680 + 2 × 100
680
47.5
10
15
28
2.21
3
24
10
22
29.4
47
6.8
150
100
100
15
1
3.3
3.3
3.3
3.3
4.7
3.3
2.2
2.2
2.2
3.3
4.7
4.7
1.5
1.5
2.2
2.2
2.2
2.2
1.5
1.5
2.2
2.2
1
10
15
5
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5
10
10
47
5
470
15
10
39
5
3 × 100
2 × 100
2 × 100
470
20
10
20
5
47.5
10
15
18.2
24
10
5
2.21
10
10
500
12
12
12
12
12
12
5
10
68
68
3 × 100
2 × 100
2 × 100
2 × 100
100
15
10
33
10
20
10
26.7
37.4
47
10
47.5
10
15
6.8
4.7
3.3
68
2.21
3
22
37.4
56
1
470
10
15
5
1.2
1.5
1.8
2.5
3.3
1.8
2.5
3.3
5
3 × 100
3 × 100
2 × 100
2 × 47
100 + 47
2 × 100
100
10
10
26.7
33
10
5
15
10
10
5
20
10
26.7
21
10
5
47.5
10
15
6.8
4.7
4.7
3.3
2.2
1
5
2.21
10
37.4
51
1000
12
12
12
12
5
20
47.5
10
15
37.4
47
100
2.21
3
100
22
69
1
3 × 100
2 × 100
100 + 47
2 × 47
100
10
15
43.2
33
8.2
6.8
4.7
4.7
3.3
2.2
5
1.2
1.5
1.8
2.5
3.3
1
10
10
5
1
15
10
33
5
1
20
10
30
5
1
47.5
10
15
37.4
47
5
1
100
2.21
1 680 μF: 4 V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. 0 | Page 22 of 28
Data Sheet
ADP2380
Table 12. Recommended External Components for Typical Applications with Compensation Network Between COMP and FB Pins,
4 A Output Current
fSW (kHz)
VIN (V)
12
12
12
12
12
12
12
5
VOUT (V)
L (µH)
3.3
3.3
4.7
4.7
6.8
6.8
10
COUT (µF)1
680 + 2 × 100
680
RTOP (kΩ)
RBOT (kΩ)
RC_EA (kΩ)
191
169
237
220
187
47
CC_EA (pF)
1000
1200
1000
1000
680
CCP_EA (pF)
47
33
22
22
1
250
1
10
15
1.2
1.5
1.8
2.5
3.3
5
10
10
680
15
10
470
20
10
3 × 100
2 × 100
100 + 47
680 + 2 × 100
680
47.5
10
15
2.21
3
2200
1800
1000
1200
1000
1000
680
4.7
2.2
39
39
22
3.9
2.2
15
22
2.2
2.2
1
22
69.8
191
169
169
88.7
124
47
1
3.3
3.3
3.3
3.3
4.7
3.3
2.2
2.2
2.2
3.3
4.7
4.7
1.5
1.5
2.2
2.2
2.2
2.2
1.5
1.5
2.2
2.2
1
10
15
5
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5
10
10
5
470
15
10
5
3 × 100
2 × 100
2 × 100
470
20
10
5
47.5
10
15
5
2.21
10
2200
680
500
12
12
12
12
12
12
5
10
237
130
110
249
95.3
86.6
220
95.3
130
110
147
75
3 × 100
2 × 100
2 × 100
2 × 100
100
15
10
470
20
10
470
47.5
10
15
330
2.21
3
1000
820
2.2
1
22
1
470
10
15
470
22
3.3
2.2
2.2
1
5
1.2
1.5
1.8
2.5
3.3
1.8
2.5
3.3
5
3 × 100
3 × 100
2 × 100
2 × 47
100 + 47
2 × 100
100
10
10
680
5
15
10
470
5
20
10
470
5
47.5
10
15
330
5
2.21
10
1000
220
1
1000
12
12
12
12
5
20
232
232
95.3
169
180
127
140
137
249
93.1
1
47.5
10
15
150
1
100
2.21
3
470
1
100
22
470
1
1
3 × 100
2 × 100
100 + 47
2 × 47
100
10
15
270
2.2
2.2
1
5
1.2
1.5
1.8
2.5
3.3
1
10
10
330
5
1
15
10
270
5
1
20
10
270
1
5
1
47.5
10
15
150
1
5
1
100
2.21
470
1
1 680 μF: 4V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. 0 | Page 23 of 28
ADP2380
Data Sheet
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential for obtaining the best
performance from the ADP2380. Poor printed circuit board
(PCB) layout degrades the output regulation as well as the
electromagnetic interface (EMI) and electromagnetic
In addition, ensure that the high current path from the
power ground plane through the external MOSFET,
inductor, and output capacitor back to the power ground
plane is as short as possible by tying the MOSFET source
node to the PGND plane as close as possible to the input
and output capacitors.
compatibility (EMC) performance. Figure 38 shows a PCB
layout example. For optimum layout, use the following guidelines:
•
Make the low-side driver path from the LD pin of the
ADP2380 to the external MOSFET gate node and back to
the PGND pin of the ADP2380 as short as possible, and
use a wide trace for better noise immunity.
Connect the exposed pad of the ADP2380 to a large copper
plane to maximize its power dissipation capability for
better thermal dissipation.
Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Try to
minimize the length of the trace that connects the top of
the feedback resistor divider to the output while keeping
the trace away from the high current traces and the
switching node to avoid noise pickup. To further reduce
noise pickup, place an analog ground plane on either side
of the FB trace and ensure that the trace is as short as
possible to reduce parasitic capacitance pickup.
•
Use separate analog ground and power ground planes.
Connect the ground reference of sensitive analog circuitry,
such as output voltage divider components, to analog
ground. In addition, connect the ground reference of
power components, such as input and output capacitors
and a low-side MOSFET, to power ground. Connect both
ground planes to the exposed pad of the ADP2380.
Place the input capacitor, inductor, low-side MOSFET, and
output capacitor as close to the IC as possible, and use
short traces.
Ensure that the high current loop traces are as short and
as wide as possible. Make the high current path from the
input capacitor through the inductor, the output capacitor,
and the power ground plane back to the input capacitor as
short as possible. To accomplish this, ensure that the input
and output capacitors share a common power ground plane.
•
•
•
•
V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PVIN
PVIN
BST
L
C
V
BST
OUT
C
IN
SW
SW
C
OUT
UVLO ADP2380
PGOOD
FET
LD
C
RT
VREG
PGND
GND
VREG
R
OSC
SYNC
EN/SS
COMP
R
R
TOP
BOT
C
SS
FB
C
C_EA
R
C_EA
C
CP_EA
Figure 37. High Current Path in the PCB Circuit
Rev. 0 | Page 24 of 28
Data Sheet
ADP2380
POWER GROUND PLANE
VIN
INPUT
BULK CAP
OUTPUT
CAPACITOR
INPUT
BYPASS
CAP
LOW-SIDE
MOSFET
PVIN
PVIN
UVLO
BST
SW
C
BST
INDUCTOR
VOUT
SW
SW
PULL UP
PGOOD
RT
LD
VREG
PGND
GND
FB
C
VREG
SYNC
EN/SS
COMP
C
R
C_EA
C_EA
R
C
TOP
SS
R
OSC
R
C
BOT
CP_EA
ANALOG GROUND PLANE
VIA
BOTTOM LAYER TRACE
COPPER PLANE
Figure 38. Recommended PCB Layout
Rev. 0 | Page 25 of 28
ADP2380
Data Sheet
TYPICAL APPLICATIONS CIRCUITS
V
= 12V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L1
2.2µH
C
0.1µF
PVIN
BST
BST
V
= 1.2V
OUT
C
10µF
25V
IN
PVIN
SW
SW
C
OUT
470µF
6.3V
UVLO ADP2380
PGOOD
M1
FDS6298
R
LD
OSC
100kΩ
C
VREG
1µF
RT
VREG
PGND
GND
SYNC
EN/SS
COMP
R
TOP
10kΩ
1%
C
SS
FB
22nF
R
10kΩ
1%
BOT
R
68kΩ
C
C
CP
C
C
68pF
2.2nF
Figure 39. Compensation Network Between COMP and GND, VIN = 12 V, VOUT = 1.2 V, IOUT = 4 A, fSW = 500 kHz
V
= 12V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L1
C
0.1µF
PVIN
PVIN
BST
BST
2.2µH
V
= 1.8V
OUT
R1
C
IN
SW
SW
7.32kΩ
10µF
25V
C
C
OUT2
OUT1
1%
100µF
6.3V
100µF
6.3V
UVLO ADP2380
PGOOD
M1
FDS6298
R2
LD
1kΩ
R
OSC
1%
100kΩ
C
VREG
1µF
RT
VREG
PGND
GND
SYNC
EN/SS
COMP
R
TOP
20kΩ
1%
C
22nF
SS
FB
R
BOT
10kΩ
1%
C
470pF
C_EA
R
C_EA
110kΩ
C
CP_EA
2.2pF
Figure 40. Programming Input Voltage UVLO Rising Threshold at 10 V, VIN = 12 V, VOUT = 1.8 V, IOUT = 4 A, fSW = 500 kHz
V
= 12V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L1
4.7µH
PVIN
PVIN
BST
C
0.1µF
BST
C
V
= 5V
OUT
IN
OUT
10µF
25V
SW
SW
C
UVLO ADP2380
PGOOD
100µF
6.3V
M1
FDS6298
R
LD
OSC
82kΩ
RT
VREG
PGND
GND
C
VREG
1µF
SYNC
EN/SS
COMP
R
TOP
22kΩ
1%
FB
R
SOT
3kΩ
1%
C
820pF
C_EA
R
C_EA
100kΩ
C
CP_EA
1pF
Figure 41. Using Internal Soft Start, Programming Switching Frequency at 600 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 4 A, fSW = 600 kHz
Rev. 0 | Page 26 of 28
Data Sheet
ADP2380
OUTLINE DIMENSIONS
5.10
5.00
4.90
2.31
1.75
16
9
8
9
8
16
4.50
4.40
4.30
2.46
1.75
EXPOSED
PAD
1
6.40 BSC
1
PIN 1
FOR PROPER CONNECTION OF
INDICATOR
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
TOP VIEW
BOTTOM VIEW
0.95
0.90
0.85
SECTION OF THIS DATA SHEET.
0.20
0.09
1.10 MAX
0.25
8°
0°
0.70
0.60
0.50
SEATING
PLANE
0.15 MAX
0.05 MIN
0.30
0.19
0.65 BSC
COPLANARITY
0.076
COMPLIANT TO JEDEC STANDARDS MO-153-ABT
Figure 42. 16-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP_EP]
(RE-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
ADP2380AREZ-R7
ADP2380AREZ
ADP2380-EVALZ
16-Lead TSSOP_EP, 7”Tape and Reel
16-Lead TSSOP_EP, Tube
Evaluation Board
RE-16-3
RE-16-3
1 Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
ADP2380
NOTES
Data Sheet
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09939-0-12/12(0)
Rev. 0 | Page 28 of 28
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