ADP2384ACPZN-R7 [ADI]
20 V, 4 A, Synchronous Step-Down DC-to-DC Regulator;
| 型号： | ADP2384ACPZN-R7 |
| 厂家： | 
ADI |
| 描述： | 20 V, 4 A, Synchronous Step-Down DC-to-DC Regulator 开关 输出元件 |
| 文件： | 总25页 (文件大小：753K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
20 V, 4 A, Synchronous, Step-Down
DC-to-DC Regulator
Data Sheet
ADP2384
FEATURES
TYPICAL APPLICATIONS CIRCUIT
Input voltage: 4.5 V to 20 V
Integrated MOSFET: 44 mΩ/11.6 mΩ
Reference voltage: 0.6 V 1%
ADP2384
BST
V
PVIN
EN
IN
C
BST
L
C
IN
SW
V
OUT
Continuous output current: 4 A
C
OUT
PGOOD
SYNC
RT
R
TOP
Programmable switching frequency: 200 kHz to 1.4 MHz
Synchronizes to external clock: 200 kHz to 1.4 MHz
180° out-of-phase clock synchronization
Precision enable and power good
FB
COMP
SS
R
T
R
C
R
VREG
BOT
C
C
VREG
GND PGND
C
C
SS
External compensation
Internal soft start with external adjustable option
Startup into a precharged output
Supported by ADIsimPower design tool
Figure 1.
APPLICATIONS
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point-of-load applications
GENERAL DESCRIPTION
The ADP2384 is a synchronous, step-down dc-to-dc regulator
with an integrated 44 mΩ, high-side power MOSFET and
an 11.6 mΩ, synchronous rectifier MOSFET to provide a high
efficiency solution in a compact 4 mm × 4 mm LFCSP package.
This device uses a peak current mode, constant frequency pulse-
width modulation (PWM) control scheme for excellent stability
and transient response. The switching frequency of the ADP2384
can be programmed from 200 kHz to 1.4 MHz. To minimize
system noise, the synchronization function allows the switching
frequency to be synchronized to an external clock.
Other key features include undervoltage lockout (UVLO),
overvoltage protection (OVP), overcurrent protection (OCP),
short-circuit protection (SCP), and thermal shutdown (TSD).
The ADP2384 operates over the −40°C to +125°C junction
temperature range and is available in a 24-lead, 4 mm × 4 mm
LFCSP package.
100
95
90
85
80
75
70
65
60
The ADP2384 requires minimal external components and operates
from an input voltage of 4.5 V to 20 V. The output voltage can be
adjusted from 0.6 V to 90% of the input voltage and delivers up to
4 A of continuous current. Each IC draws less than 120 μA current
from the input source when it is disabled.
This regulator targets high performance applications that require
high efficiency and design flexibility. External compensation and an
adjustable soft start function provide design flexibility. The power-
good output and precision enable input provide simple and reliable
power sequencing.
V
V
V
= 1.2V
= 3.3V
= 5V
OUT
OUT
OUT
55
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current, VIN = 12 V, fSW = 300 kHz
Rev. A
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ADP2384* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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REFERENCE MATERIALS
Press
• Analog Devices Introduces the Most Efficient Switching
Regulators in Their Class
EVALUATION KITS
• ADA4961 & AD9680 Analog Signal Chain Evaluation and
Technical Articles
AD9528 Converter Synchronization
• MS-2437: Convert a Buck Regulator into a Smart LED
Driver
• ADP2384/ADP2386 Evaluation Board
• Powering GSPS or RF Sampling ADCs: Switcher vs LDO
• Two Channels, 2400MHz TDD Application
DESIGN RESOURCES
• ADP2384 Material Declaration
• PCN-PDN Information
DOCUMENTATION
Application Notes
• AN-1168: Designing an Inverting Power Supply Using the
ADP2384/ADP2386 Synchronous Step-Down DC-to-DC
Regulators
• Quality And Reliability
• Symbols and Footprints
Data Sheet
• ADP2384: 20 V, 4 A, Synchronous, Step-Down DC-to-DC
Regulator Data Sheet
DISCUSSIONS
View all ADP2384 EngineerZone Discussions.
User Guides
• UG-466: Evaluation Board for the ADP2384/ADP2386, 20
V, 4 A/6 A Synchronous Step-Down DC-to-DC Regulators
SAMPLE AND BUY
Visit the product page to see pricing options.
TOOLS AND SIMULATIONS
• ADIsimPower™ Voltage Regulator Design Tool
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• ADP238x Buck Regulator Design Tool
• ADP238x Inverting Buck-Boost Regulator Design Tool
DOCUMENT FEEDBACK
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ADP2384
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Shutdown .................................................................... 14
Applications Information .............................................................. 15
Input Capacitor Selection.......................................................... 15
Output Voltage Setting .............................................................. 15
Voltage Conversion Limitations............................................... 15
Inductor Selection...................................................................... 15
Output Capacitor Selection....................................................... 16
Programming the Input Voltage UVLO.................................. 17
Compensation Design ............................................................... 17
ADIsimPower Design Tool ....................................................... 18
Design Example.............................................................................. 19
Output Voltage Setting (Design Example).............................. 19
Frequency Setting....................................................................... 19
Inductor Selection (Design Example) ..................................... 19
Output Capacitor Selection (Design Example)...................... 20
Compensation Components..................................................... 20
Soft Start Time Program ........................................................... 20
Input Capacitor Selection (Design Example)......................... 20
Recommended External Components .................................... 21
Circuit Board Layout Recommendations ................................... 22
Typical Applications Circuits........................................................ 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Functional Block Diagram ............................................................ 11
Theory of Operation ...................................................................... 12
Control Scheme .......................................................................... 12
Precision Enable/Shutdown ...................................................... 12
Internal Regulator (VREG)....................................................... 12
Bootstrap Circuitry .................................................................... 12
Oscillator ..................................................................................... 12
Synchronization.......................................................................... 12
Soft Start ...................................................................................... 13
Power Good................................................................................. 13
Peak Current-Limit and Short-Circuit Protection................. 13
Overvoltage Protection (OVP)................................................. 14
Undervoltage Lockout (UVLO) ............................................... 14
REVISION HISTORY
7/14—Rev. 0 to Rev. A
Changes to Table 2 and Table 3....................................................... 5
Changes to Inductor Selection Section........................................ 15
Changes to Compensation Components Section....................... 20
Updated Outline Dimensions....................................................... 24
8/12—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADP2384
SPECIFICATIONS
VPVIN = 12 V, T J = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
PVIN
PVIN Voltage Range
Quiescent Current
Shutdown Current
PVIN Undervoltage Lockout Threshold
VPVIN
IQ
ISHDN
UVLO
4.5
2.1
45
20
V
No switching
EN = GND
PVIN rising
PVIN falling
2.9
80
4.3
3.8
3.6
120
4.5
mA
µA
V
3.5
V
FB
FB Regulation Voltage
VFB
IFB
0°C < TJ < 85°C
−40°C < TJ < 125°C
0.594
0.591
0.6
0.6
0.01
0.606
0.609
0.1
V
V
µA
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
EA Sink Current
gm
ISOURCE
ISINK
340
40
40
470
60
60
600
80
80
µS
µA
µA
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
VVREG
VPVIN = 12 V, IVREG = 50 mA
VPVIN = 12 V, IVREG = 50 mA
7.6
65
8
340
100
8.4
V
mV
mA
Regulator Current Limit
135
SW
High-Side On Resistance1
Low-Side On Resistance1
High-Side Peak Current Limit
VBST − VSW = 5 V
VVREG = 8 V
44
11.6
70
20
mΩ
mΩ
4.8
4.5
6.1
20
7.4
A
mV
Low-Side Negative Current-Limit
Threshold Voltage2
SW Minimum On Time
SW Minimum Off Time
BST
Bootstrap Voltage
OSCILLATOR (RT PIN)
Switching Frequency
Switching Frequency Range
SYNC
tMIN_ON
tMIN_OFF
125
200
168
260
ns
ns
VBOOT
5
5.5
V
fSW
fSW
RT = 100 kΩ
530
200
600
670
1400
kHz
kHz
Synchronization Range
SYNC Minimum Pulse Width
SYNC Minimum Off Time
SYNC Input High Voltage
SYNC Input Low Voltage
SS
200
100
100
1.3
1400
kHz
ns
ns
V
0.4
3.9
V
Internal Soft Start
SS Pin Pull-Up Current
1600
3.2
Clock cycles
µA
ISS_UP
2.5
Rev. A | Page 3 of 24
ADP2384
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
PGOOD
Power-Good Range
FB Rising Threshold
FB Rising Hysteresis
FB Falling Threshold
FB Falling Hysteresis
Power-Good Deglitch Time
PGOOD from low to high
PGOOD from high to low
PGOOD from low to high
PGOOD from high to low
PGOOD from low to high
PGOOD from high to low
VPGOOD = 5 V
95
5
%
%
%
%
105
11.7
1024
16
0.01
125
Clock cycle
Clock cycle
µA
Power-Good Leakage Current
Power-Good Output Low Voltage
EN
0.1
200
IPGOOD = 1 mA
mV
EN Rising Threshold
EN Falling Threshold
EN Source Current
1.17
1.07
5
1.28
V
V
µA
µA
0.97
EN voltage below falling threshold
EN voltage above rising threshold
1
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
150
25
°C
°C
1 Pin-to-pin measurement.
2 Guaranteed by design.
Rev. A | Page 4 of 24
Data Sheet
ADP2384
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a 4-layer, JEDEC standard circuit board for surface-
mount packages.
Parameter
Rating
PVIN, SW, EN, PGOOD
SW 10 ns Transient
SW 100 ns Transient
BST
FB, SS, CO M P, SYNC, RT
VREG
−0.3 V to +22 V
−2.5 V to +22 V
−1 V to +22 V
Table 3. Thermal Resistance
VSW + 6 V
Package Type
θJA
θJC
Unit
−0.3 V to +6 V
−0.3 V to +12 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
24-Lead LFCSP_WQ
42.6
6.8 (EP, SW)
2.3 (EP, GND)
°C/W
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 5 of 24
ADP2384
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
18
17
16
15
14
13
COMP
FB
PVIN
PVIN
PVIN
BST
SW
25
GND
VREG
GND 4
26
SW
5
6
SW
SW
PG
ND
ADP2384
TOP VIEW
NOTES
1. THE EXPOSED GND PAD MUST BE SOLDERED
TO A LARGE, EXTERNAL, COPPER GND PLANE
TO REDUCE THERMAL RESISTANCE.
2. THE EXPOSED SW PAD MUST BE CONNECTED
TO THE SW PINS OF THE ADP2384 BY USING
SHORT, WIDE TRACES, OR ELSE SOLDERED
TO A LARGE, EXTERNAL, COPPER SW PLANE
TO REDUCE THERMAL RESISTANCE.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
COMP
FB
VREG
Error Amplifier Output. Connect an RC network from COMP to GND.
Feedback Voltage Sense Input. Connect to a resistor divider from the output voltage, VOUT
Output of the Internal 8 V Regulator. The control circuits are powered from this voltage. Place a 1 µF, X7R
or X5R ceramic capacitor between this pin and GND.
.
4
GND
SW
Analog Ground. Return of internal control circuit.
Switch Node Output. Connect to the output inductor.
5, 6, 7, 14
8, 9, 10, 11, 12, 13 PGND
Power Ground. Return of low-side power MOSFET.
15
BST
PVIN
EN
Supply Rail for the High-Side Gate Drive. Place a 0.1 µF, X7R or X5R capacitor between SW and BST.
Power Input. Connect to the input power source and connect a bypass capacitor between this pin and PGND.
Precision Enable Pin. An external resistor divider can be used to set the turn-on threshold. To enable the
part automatically, connect the EN pin to the PVIN pin.
16,17,18,19
20
21
22
PGOOD
RT
Power-Good Output (Open Drain). A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
Frequency Setting. Connect a resistor between RT and GND to program the switching frequency from 200 kHz
to 1.4 MHz.
23
24
SYNC
SS
Synchronization Input. Connect this pin to an external clock to synchronize the switching frequency from
200 kHz and 1.4 MHz. See the Oscillator section and Synchronization section for more information.
Soft Start Control. Connect a capacitor from SS to GND to program the soft start time. If this pin is open,
the regulator uses the internal soft start time.
25
26
E P, G N D
E P, S W
The exposed GND pad must be soldered to a large, external, copper GND plane to reduce thermal resistance.
The exposed SW pad must be connected to the SW pins of the ADP2384, using short, wide traces, or else
soldered to a large, external, copper SW plane to reduce thermal resistance.
Rev. A | Page 6 of 24
Data Sheet
ADP2384
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12 V, VOUT = 3.3 V, L = 3.3 µH, COUT = 47 µF × 2, fSW = 600 kHz, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
INDUCTOR: FDVE1040-6R8M
INDUCTOR: FDVE1040-3R3M
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 4. Efficiency at VIN = 12 V, fSW = 600 kHz
Figure 7. Efficiency at VIN = 12 V, fSW = 300 kHz
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V
V
V
V
V
V
= 1.0V
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
= 1.8V
OUT
OUT
OUT
OUT
= 2.5V
= 3.3V
= 5V
INDUCTOR: FDVE1040-3R3M
INDUCTOR: FDVE1040-1R5M
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 8. Efficiency at VIN = 5 V, fSW = 600 kHz
Figure 5. Efficiency at VIN = 18 V, fSW = 600 kHz
100
90
80
70
60
50
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
T
T
T
= –40°C
= +25°C
= +125°C
T
T
T
= –40°C
= +25°C
= +125°C
J
J
J
J
J
J
4
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
20
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 6. Shutdown Current vs. VIN
Figure 9. Quiescent Current vs. VIN
Rev. A | Page 7 of 24
ADP2384
Data Sheet
4.5
1.25
1.20
4.4
RISING
RISING
4.3
4.2
4.1
4.0
3.9
3.8
1.15
1.10
1.05
FALLING
FALLING
1.00
0.95
3.7
3.6
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. UVLO Threshold vs. Temperature
Figure 13. EN Threshold vs. Temperature
3.30
606
604
3.25
3.20
3.15
3.10
3.05
3.00
2.95
2.90
602
600
598
596
594
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. SS Pin Pull-Up Current vs. Temperature
Figure 14. FB Voltage vs. Temperature
8.4
8.3
8.2
8.1
8.0
7.9
7.8
630
620
610
600
590
580
570
R
= 100kΩ
T
7.7
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. VREG Voltage vs. Temperature
Figure 12. Frequency vs. Temperature
Rev. A | Page 8 of 24
Data Sheet
ADP2384
65
7.0
6.5
55
HIGH-SIDE R
DSON
45
35
25
15
5
6.0
5.5
5.0
4.5
4.0
LOW-SIDE R
DSON
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. MOSFET RDSON vs. Temperature
Figure 19. Current-Limit Threshold vs. Temperature
V
(AC)
OUT
EN
1
3
I
L
V
OUT
1
2
PGOOD
SW
4
2
I
OUT
4
B
B
CH1 2.00V
CH3 10.0V
CH2 5.00V
CH4 5.00A Ω
M2.00ms
27.00%
A CH3
8.60V
CH1 10mV
CH2 10.0V
CH4 2.00A Ω
M2.00µs
50.00%
A CH2
5.00V
W
W
T
T
Figure 17. Working Mode Waveform
Figure 20. Soft Start with Full Load
SYNC
SW
EN
3
2
V
OUT
1
2
PGOOD
4
I
L
4
B
M1.00µs
50.00%
A CH2
3.40V
CH1 2.00V
CH3 10.0V
CH2 5.00V
CH4 2.00A Ω
M2.00ms
50.20%
A CH2
3.90V
W
CH2 5.00V
CH4 10.0V
T
T
Figure 18. Voltage Precharged Output
Figure 21. External Synchronization
Rev. A | Page 9 of 24
ADP2384
Data Sheet
V
(AC)
V
V
(AC)
OUT
OUT
1
1
IN
SW
3
2
I
OUT
4
B
B
CH2 10.0V B
M1.00ms
30.00%
A CH3
12.0V
CH1 100mV
M200µs
70.40%
A CH4
2.52A
W
CH1 20.0mV
W
W
B
CH4 2.00A Ω
T
CH3 5.00V
T
W
Figure 22. Load Transient Response, 1 A to 4 A
Figure 25. Line Transient Response, VIN from 8 V to 14 V, IOUT = 4 A
V
OUT
V
OUT
1
2
4
1
2
4
SW
SW
I
L
I
L
CH1 2.00V B
CH2 10.0V
CH4 5.00A Ω
M4.00ms
30.40%
A CH1
1.48V
W
B
M4.00ms
78.80%
A CH1
1.72V
CH1 2.00V
CH2 10.0V
CH4 5.00A Ω
W
T
T
Figure 23. Output Short Entry
Figure 26. Output Short Recovery
5
4
3
5
4
3
2
2
V
V
V
V
V
V
= 1V
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
OUT
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
1
1
0
45
0
45
55
65
75
85
95
105
55
65
75
85
95
105
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 27. Output Current vs. Ambient Temperature at VIN = 12 V,
SW = 300 kHz
Figure 24. Output Current vs. Ambient Temperature at VIN = 12 V,
SW = 600 kHz
f
f
Rev. A | Page 10 of 24
Data Sheet
ADP2384
FUNCTIONAL BLOCK DIAGRAM
VREG
CLK
BIAS AND DRIVER
REGULATOR
RT
PVIN
OSC
SLOPE RAMP
SYNC
UVLO
EN
EN_BUF
BOOST
REGULATOR
1.17V
1µA
4µA
A
CS
+
HICCUP
MODE
OCP
–
V
SLOPE RAMP
I_MAX
Σ
BST
SW
COMP
0.6V
+
NFET
NFET
+
CMP
–
I
DRIVER
SS
SS
FB
+
AMP
–
CONTROL
LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
VREG
OVP
PROTECTION
DRIVER
CLK
PGND
0.7V
–
NEG CURRENT
CMP
–
+
+
–
V
I_NEG
0.54V
+
PGOOD
GND
DEGLITCH
Figure 28. Functional Block Diagram
Rev. A | Page 11 of 24
ADP2384
Data Sheet
THEORY OF OPERATION
The ADP2384 is a synchronous step-down, dc-to-dc regulator
that uses a current mode architecture with an integrated high-
side power switch and a low-side synchronous rectifier. The
regulator targets high performance applications that require
high efficiency and design flexibility.
BOOTSTRAP CIRCUITRY
The ADP2384 includes a regulator to provide the gate drive
voltage for the high-side N-MOSFET. It uses differential sensing to
generate a 5 V bootstrap voltage between the BST and SW pins.
It is recommended that a 0.1 µF, X7R or X5R ceramic capacitor
be placed between the BST pin and the SW pin.
The ADP2384 operates from an input voltage that ranges from
4.5 V to 20 V and regulates the output voltage from 0.6 V to 90%
of the input voltage. Additional features that maximize design
flexibility include the following: programmable switching
frequency, programmable soft start, external compensation,
precision enable, and a power-good output.
OSCILLATOR
The ADP2384 switching frequency is controlled by the RT pin.
A resistor from RT to GND can program the switching frequency
according to the following equation:
CONTROL SCHEME
69,120
f
SW (kHz) =
The ADP2384 uses a fixed frequency, peak current mode PWM
control architecture. At the start of each oscillator cycle, the
high-side N-MOSFET is turned on, putting a positive voltage
across the inductor. When the inductor current crosses the peak
inductor current threshold, the high-side N-MOSFET is turned
off and the low-side N-MOSFET is turned on. This puts a negative
voltage across the inductor, causing the inductor current to
decrease. The low-side N-MOSFET stays on for the rest of the
cycle (see Figure 17).
RT (kΩ) + 15
A 100 kΩ resistor sets the frequency to 600 kHz, and a 42.2 kΩ
resistor sets the frequency to 1.2 MHz. Figure 29 shows the
typical relationship between fSW and RT.
1400
1200
1000
800
600
400
200
0
PRECISION ENABLE/SHUTDOWN
The EN input pin has a precision analog threshold of 1.17 V
(typical) with 100 mV of hysteresis. When the enable voltage
exceeds 1.17 V, the regulator turns on; when it falls below 1.07 V
(typical), the regulator turns off. To force the regulator to auto-
matically start when input power is applied, connect EN to PVIN.
The precision EN pin has an internal pull-down current source
(5 µA) that provides a default turn-off when the EN pin is open.
20
60
100
140
180
(kΩ)
220
260
300
R
T
When the EN pin voltage exceeds 1.17 V (typical), the ADP2384
is enabled and the internal pull-down current source at the EN
pin decreases to 1 µA, which allows users to program the PVIN
UVLO and hysteresis.
Figure 29. Switching Frequency vs. RT
SYNCHRONIZATION
To synchronize the ADP2384, connect an external clock to the
SYNC pin. The frequency of the external clock can be in the range
of 200 kHz to 1.4 MHz. During synchronization, the regulator
operates in continuous conduction mode (CCM), and the rising
edge of the switching waveform runs 180° out of phase to the rising
edge of the external clock.
INTERNAL REGULATOR (VREG)
The on-board regulator provides a stable supply for the internal
circuits. It is recommended that a 1 µF ceramic capacitor be placed
between the VREG pin and GND. The internal regulator includes
a current-limit circuit to protect the output if the maximum
external load current is exceeded.
When the ADP2384 operates in synchronization mode,
a resistor must be connected from the RT pin to GND to
program the internal oscillator to run at 90% to 110% of the
external synchronization clock.
Rev. A | Page 12 of 24
Data Sheet
ADP2384
V
RISING
V
FALLING
OUT
OUT
SOFT START
116.7%
The ADP2384 has integrated soft start circuitry to limit the output
voltage rising time and reduce inrush current at startup. The
internal soft start time is calculated using the following equation:
105%
100%
95
%
90%
1600
tSS_INT
=
(ms)
fSW (kHz)
PGOOD
A slower soft start time can be programmed by using the SS pin.
When a capacitor is connected between the SS pin and GND, an
internal current charges the capacitor to establish the soft start
ramp. The soft start time is calculated using the following equation:
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
Figure 30. PGOOD Rising and Falling Thresholds
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
0.6V ×CSS
tSS_EXT
=
The ADP2384 has a peak current-limit protection circuit to
prevent current runaway. During the initial soft start, the
ADP2384 uses frequency foldback to prevent output current
runaway. The switching frequency is reduced according to the
voltage on the FB pin, which allows more time for the inductor
to discharge. The correlation between the switching frequency
and the FB pin voltage is shown in Table 5.
ISS _UP
where:
CSS is the soft start capacitance.
SS_UP is the soft start pull-up current (3.2 µA).
I
The internal error amplifier includes three positive inputs: the
internal reference voltage, the internal digital soft start voltage,
and the SS pin voltage. The error amplifier regulates the FB
voltage to the lowest of the three voltages.
Table 5. FB Pin Voltage and Switching Frequency
FB Pin Voltage
Switching Frequency
If the output voltage is charged prior to turn-on, the ADP2384
prevents reverse inductor current that would discharge the output
capacitor. This function remains active until the soft start
voltage exceeds the voltage on the FB pin.
VFB ≥ 0.4 V
0.4 V > VFB ≥ 0.2 V
VFB < 0.2 V
fSW
fSW/2
fSW/4
For protection against heavy loads, the ADP2384 uses a hiccup
mode for overcurrent protection. When the inductor peak current
reaches the current-limit value, the high-side MOSFET turns off
and the low-side MOSFET turns on until the next cycle. The over-
current counter increments during this process. If the overcurrent
counter reaches 10 or the FB pin voltage falls to 0.4 V after the
soft start, the regulator enters hiccup mode. The high-side and
low-side MOSFETs are both turned off. The regulator remains
in hiccup mode for 4096 clock cycles and then attempts to restart.
If the current-limit fault has cleared, the regulator resumes normal
operation. Otherwise, it reenters hiccup mode.
POWER GOOD
The power-good pin (PGOOD) is an active high, open-drain
output that requires an external resistor to pull it up to a voltage.
A logic high on the PGOOD pin indicates that the voltage on
the FB pin (and, therefore, the output voltage) is within regulation.
The power-good circuitry monitors the output voltage on the FB
pin and compares it to the rising and falling thresholds that are
specified in Table 1. If the rising output voltage exceeds the target
value, the PGOOD pin is held low. The PGOOD pin continues
to be held low until the falling output voltage returns to the
target value.
The ADP2384 also provides a sink current limit to prevent the
low-side MOSFET from sinking a lot of current from the load.
When the voltage across the low-side MOSFET exceeds the sink
current-limit threshold, which is typically 20 mV, the low-side
MOSFET turns off immediately for the rest of the cycle. Both high-
side and low-side MOSFETs turn off until the next clock cycle.
If the output voltage falls below the target output voltage, the
PGOOD pin is held low. The PGOOD pin continues to be held
low until the rising output voltage returns to the target value.
The power-good rising and falling thresholds are shown in
Figure 30. There is a 1024-cycle waiting period before the PGOOD
pin is pulled from low to high, and there is a 16-cycle waiting
period before the PGOOD pin is pulled from high to low.
In some cases, the input voltage (VPVIN) ramp rate is too slow or
the output capacitor is too large for the output to reach regulation
during the soft start process, which causes the regulator to enter
the hiccup mode. To avoid such occurrences, use a resistor
divider at the EN pin to program the input voltage UVLO,
or use a longer soft start time.
Rev. A | Page 13 of 24
ADP2384
Data Sheet
OVERVOLTAGE PROTECTION (OVP)
THERMAL SHUTDOWN
The ADP2384 includes an overvoltage protection feature
to protect the regulator against an output short to a higher
voltage supply or when a strong load disconnect transient
occurs. If the feedback voltage increases to 0.7 V, the internal
high-side and low-side MOSFETs are turned off until the
voltage at the FB pin decreases to 0.63 V. At that time, the
ADP2384 resumes normal operation.
If the ADP2384 junction temperatures rises above 150°C, the
internal thermal shutdown circuit turns off the regulator for self-
protection. Extreme junction temperatures can be the result of
high current operation, poor circuit board thermal design,
and/or high ambient temperature. A 25°C hysteresis is included
in the thermal shutdown circuit so that, if an overtemperature
event occurs, the ADP2384 does not return to normal operation
until the on-chip temperature falls below 125°C. Upon recovery, a
soft start is initiated before normal operation begins.
UNDERVOLTAGE LOCKOUT (UVLO)
Undervoltage lockout circuitry is integrated in the ADP2384 to
prevent the occurrence of power-on glitches. If the VPVIN voltage
falls below 3.8 V typical, the part shuts down and both the
power switch and synchronous rectifier turn off. When the
VPVIN voltage rises above 4.3 V typical, the soft start period
is initiated and the part is enabled.
Rev. A | Page 14 of 24
Data Sheet
ADP2384
APPLICATIONS INFORMATION
The maximum output voltage for a given input voltage and
INPUT CAPACITOR SELECTION
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is typically
200 ns, and the maximum duty cycle of the ADP2384 is
typically 90%.
The input capacitor reduces the input voltage ripple caused by
the switch current on PVIN. Place the input capacitor as close
as possible to the PVIN pin. A ceramic capacitor in the 10 μF to
47 μF range is recommended. The loop that is composed of this
input capacitor, the high-side N-MOSFET, and the low-side
N-MOSFET must be kept as small as possible.
The maximum output voltage, limited by the minimum off time
at a given input voltage and frequency, can be calculated using
the following equation:
The voltage rating of the input capacitor must be greater than
the maximum input voltage. The rms current rating of the input
capacitor should be larger than the value calculated from the
following equation:
V
OUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) ×
OUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT_MAX (2)
where:
OUT_MAX is the maximum output voltage.
MIN_OFF is the minimum off time.
I
V
ICIN RMS = IOUT
×
D ×(1 − D)
_
t
I
OUT_MAX is the maximum output current.
OUTPUT VOLTAGE SETTING
The output voltage of the ADP2384 is set by an external
resistive divider. The resistor values are calculated using
The maximum output voltage, limited by the maximum duty
cycle at a given input voltage, can be calculated by using the
following equation:
RTOP
RBOT
OUT = 0.6 × 1 +
V
VOUT_MAX = DMAX × VIN
(3)
where DMAX is the maximum duty cycle.
To limit output voltage accuracy degradation due to FB bias
current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT < 30 kΩ.
As shown in Equation 1 to Equation 3, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.
Table 6 lists the recommended resistor divider values for
various output voltages.
INDUCTOR SELECTION
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor value leads to a faster transient response but
degrades efficiency, due to a larger inductor ripple current;
using a large inductor value leads to smaller ripple current
and better efficiency but results in a slower transient response.
Table 6. Resistor Divider Values for Various Output Voltages
VOUT (V)
RTOP 1% (kΩ)
RBOT 1% (kΩ)
1.0
1.2
1.5
1.8
2.5
3.3
5.0
10
10
15
20
47.5
10
22
15
10
10
10
15
2.21
3
As a guideline, the inductor ripple current, ΔIL, is typically set
to one-third of the maximum load current. The inductor value
is calculated using the following equation:
(VIN −VOUT )× D
L =
VOLTAGE CONVERSION LIMITATIONS
∆IL × fSW
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2384 is typically 125 ns. The
minimum output voltage for a given input voltage and switching
frequency can be calculated using the following equation:
where:
VIN is the input voltage.
V
OUT is the output voltage.
D is the duty cycle (D = VOUT/VIN).
ΔIL is the inductor current ripple.
V
I
OUT_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) ×
OUT_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT_MIN
where:
OUT_MIN is the minimum output voltage.
MIN_ON is the minimum on time.
SW is the switching frequency.
fSW is the switching frequency.
(1)
The ADP2384 uses adaptive slope compensation in the current
loop to prevent subharmonic oscillations when the duty cycle is
larger than 50%. The internal slope compensation limits the
minimum inductor value.
V
t
f
R
R
DSON_HS is the high-side MOSFET on resistance.
DSON_LS is the low-side MOSFET on resistance.
I
OUT_MIN is the minimum output current.
RL is the series resistance of the output inductor.
Rev. A | Page 15 of 24
ADP2384
Data Sheet
KUV × ∆ISTEP2 × L
For a duty cycle that is larger than 50%, the minimum inductor
value is determined using the following equation:
COUT_UV
=
2 ×(VIN −VOUT )× ∆VOUT _UV
VOUT
×
(
1− D
)
L (Minimum) =
where:
UV is a factor, with a typical setting of KUV = 2.
ΔISTEP is the load step.
2×ΔIL × fSW
K
The peak inductor current is calculated by
ΔVOUT_UV is the allowable undershoot on the output voltage.
∆IL
IPEAK = IOUT +
Another example occurs when a load is suddenly removed from
the output, and the energy stored in the inductor rushes into
the output capacitor, causing the output to overshoot.
2
The saturation current of the inductor must be larger than the peak
inductor current. For ferrite core inductors with a quick saturation
characteristic, the saturation current rating of the inductor should
be higher than the current-limit threshold of the switch. This
prevents the inductor from reaching saturation.
The output capacitance that is required to meet the overshoot
requirement can be calculated using the following equation:
KOV × ∆ISTEP2 × L
COUT_OV
=
2
2
The rms current of the inductor is calculated as follows:
(VOUT + ∆VOUT _OV ) −VOUT
2
where:
ΔVOUT_OV is the allowable overshoot on the output voltage.
OV is a factor, with a typical setting of KOV = 2.
∆IL
2
IRMS
=
IOUT
+
12
K
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 7 lists some recommended inductors.
The output ripple is determined by the ESR and the value of the
capacitance. Use the following equation to select a capacitor
that can meet the output ripple requirements:
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects the output ripple voltage
load step transient and the loop stability of the regulator.
∆IL
COUT_RIPPLE
=
8 × fSW × ∆VOUT _ RIPPLE
For example, during a load step transient where the load is
suddenly increased, the output capacitor supplies the load until
the control loop can ramp up the inductor current. The delay
caused by the control loop causes output undershoot. The
output capacitance that is required to satisfy the voltage droop
requirement can be calculated using the following equation:
∆VOUT _ RIPPLE
RESR
=
∆IL
where:
ΔVOUT_RIPPLE is the allowable output ripple voltage.
ESR is the equivalent series resistance of the output capacitor
R
in ohms (Ω).
Table 7. Recommended Inductors
Vendor
Part No.
Value (µH)
1.5
2.2
3.3
4.7
ISAT (A)
13.7
11.4
9.8
8.2
7.1
IRMS (A)
14.6
11.6
9.0
8.0
7.1
5.2
17.5
15
12
10
9.5
8.0
6.8
20
DCR (mΩ)
4.6
6.8
10.1
13.8
20.2
34.1
4.1
Toko
FDVE1040-1R5M
FDVE1040-2R2M
FDVE1040-3R3M
FDVE1040-4R7M
FDVE1040-6R8M
FDVE1040-100M
IHLP4040DZ-1R0M-01
IHLP4040DZ-1R5M-01
IHLP4040DZ-2R2M-01
IHLP4040DZ-3R3M-01
IHLP4040DZ-4R7M-01
IHLP4040DZ-6R8M-01
IHLP4040DZ-100M-01
744325120
6.8
10
6.1
Vishay
1.0
1.5
2.2
3.3
4.7
6.8
10
36
27.5
25.6
18.6
17
13.5
12
5.8
9
14.4
16.5
23.3
36.5
1.8
Wurth Elektronik
1.2
25
744325180
1.8
18
16
3.5
744325240
744325330
2.4
3.3
17
15
14
12
4.75
5.9
744325420
4.2
14
11
7.1
744325550
5.5
12
10
10.3
Rev. A | Page 16 of 24
Data Sheet
ADP2384
Select the largest output capacitance given by COUT_UV, COUT_OV
and COUT_RIPPLE to meet both load transient and output ripple
performance.
,
where:
AVI = 8.7 A/V.
R is the load resistance.
C
OUT is the output capacitance.
The selected output capacitor voltage rating must be greater than
the output voltage. The rms current rating of the output capacitor
must be larger than the value that is calculated by
RESR is the equivalent series resistance of the output capacitor.
The ADP2384 uses a transconductance amplifier for the error
amplifier and to compensate the system. Figure 32 shows the
simplified, peak current mode control, small signal circuit.
∆IL
ICOUT
=
_RMS
12
V
V
OUT
OUT
PROGRAMMING THE INPUT VOLTAGE UVLO
R
TOP
The ADP2384 has a precision enable input that can be used to
program the UVLO threshold of the input voltage (see Figure 31).
V
C
COMP
C
OUT
ESR
–
gm
+
–
A
VI
+
R
R
BOT
R
C
PVIN
CP
R
ADP2384
C
C
R
TOP_EN
EN CMP
EN
Figure 32. Simplified Peak Current Mode Control, Small Signal Circuit
1.17V
4µA
The compensation components, RC and CC, contribute a zero,
and RC and the optional CCP contribute an optional pole.
R
BOT_EN
1µA
The closed-loop transfer equation is as follows:
RBOT
−gm
TV (s) =
×
×
Figure 31. Programming the Input Voltage UVLO
Use the following equation to calculate RTOP_EN and RBOT_EN
1.07V ×VIN _ RISING −1.17V ×VIN _ FALLING
RBOT + RTOP CC + CCP
:
1 + RC × CC × s
×GVD (s)
RTOP_EN
=
RC × CC × CCP
CC + CCP
1.07 V × 5μA −1.17V ×1μA
1.17V× RTOP _ EN
s × 1 +
× s
RBOT_EN
where:
=
The following design guideline shows how to select the RC, CC,
and CCP compensation components for ceramic output capacitor
applications:
VIN _ RISING − RTOP _ EN × 5μA −1.17 V
V
V
IN_RISING is the VIN rising threshold.
IN_FALLING is the VIN falling threshold.
1. Determine the cross frequency, fC. Generally, fC is between
fSW/12 and fSW/6.
2. Calculate RC using the following equation:
COMPENSATION DESIGN
For peak current mode control, the power stage can be simplified
as a voltage controlled current source supplying current to the
output capacitor and load resistor. It is composed of one domain
pole and a zero that is contributed by the output capacitor ESR.
The control-to-output transfer function is based on the following:
2 × π ×VOUT ×COUT × fC
RC =
0.6V × gm × AVI
3. Place the compensation zero at the domain pole, fP; then
determine CC by using the following equation:
s
(R + RESR )×COUT
CC =
1+
1+
2×π× fZ
RC
G
VD (s) = VOUT (s)/VCOMP (s) = AVI × R ×
s
4. CCP is optional. It can be used to cancel the zero caused by
the ESR of the output capacitor.
2×π× fP
R
ESR ×COUT
1
CCP
=
fZ =
fP =
RC
2 × π × RESR ×COUT
1
2 × π ×(R + RESR )×COUT
Rev. A | Page 17 of 24
ADP2384
Data Sheet
can optimize designs for cost, area, efficiency, and part count,
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For more
information about theADIsimPower design tools, refer to
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can request an unpopulated board.
ADIsimPower DESIGN TOOL
The ADP2384 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs that are optimized for a specific design goal. The
tools enable the user to generate a full schematic and bill of
materials and calculate performance in minutes. ADIsimPower
Rev. A | Page 18 of 24
Data Sheet
ADP2384
DESIGN EXAMPLE
ADP2384
V
= 12V
IN
PVIN
EN
BST
SW
C
10µF
25V
IN
C
BST
0.1µF
L1
3.3µH
V
= 3.3V
OUT
PGOOD
SYNC
RT
C
47µF
C
OUT2
47µF
6.3V
OUT1
R
10kΩ
TOP
6.3V
R
1%
T
100kΩ
FB
R
BOT
COMP
2.21kΩ
1%
VREG
SS
C
R
VREG
1µF
C
31.6kΩ
C
C
CP
3.9pF
C
22nF
GND PGND
C
SS
1500pF
Figure 33. Schematic for Design Example
This section describes the procedures for selecting the external
components, based on the example specifications that are listed
in Table 8. See Figure 33 for the schematic of this design example.
∆IL = 1.2 A.
SW = 600 kHz.
f
This calculation results in L = 3.323 μH. Choose the standard
inductor value of 3.3 μH.
Table 8. Step-Down DC-to-DC Regulator Requirements
The peak-to-peak inductor ripple current can be calculated
using the following equation:
Parameter
Specification
VIN = 12.0 V 10%
VOUT = 3.3 V
Input Voltage
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
(VIN −VOUT )× D
ΔIL =
IOUT = 4 A
L × fSW
∆VOUT_RIPPLE = 33 mV
5%, 1 A to 4 A, 2 A/μs
fSW = 600 kHz
This calculation results in ∆IL = 1.21 A.
Switching Frequency
Use the following equation to calculate the peak inductor
current:
OUTPUT VOLTAGE SETTING (DESIGN EXAMPLE)
∆IL
Choose a 10 kΩ resistor as the top feedback resistor (RTOP),
and calculate the bottom feedback resistor (RBOT) by using the
following equation:
I
PEAK = IOUT +
2
This calculation results in IPEAK = 4.605 A.
Use the following equation to calculate the rms current flowing
through the inductor:
0.6
RBOT = RTOP ×
VOUT − 0.6
2
∆IL
2
To set the output voltage to 3.3 V, the resistors values are as
follows: RTOP = 10 kΩ, and RBOT = 2.21 kΩ.
IRMS
=
IOUT
+
12
FREQUENCY SETTING
This calculation results in IRMS = 4.015 A.
Connect a 100 kΩ resistor from the RT pin to GND to set the
switching frequency to 600 kHz.
Based on the calculated current value, select an inductor with
a minimum rms current rating of 4.02 A and a minimum
saturation current rating of 4.61 A.
INDUCTOR SELECTION (DESIGN EXAMPLE)
However, to protect the inductor from reaching its saturation
point under the current-limit condition, the inductor should be
rated for at least a 6 A saturation current for reliable operation.
The peak-to-peak inductor ripple current, ∆IL, is set to 30% of
the maximum output current. Use the following equation to
estimate the inductor value:
Based on the requirements described previously, select a 3.3 μH
inductor, such as the FDVE1040-3R3M from Toko, which has
a 10.1 mΩ DCR and a 9.8 A saturation current.
(VIN −VOUT )× D
L =
∆IL × fSW
where:
VIN = 12 V.
VOUT = 3.3 V.
D = 0.275.
Rev. A | Page 19 of 24
ADP2384
Data Sheet
(0.825Ω + 0.002Ω)× 2 × 32μF
32.5kΩ
OUTPUT CAPACITOR SELECTION (DESIGN
EXAMPLE)
CC =
= 1629 pF
The output capacitor is required to meet both the output voltage
ripple and load transient response requirements.
0.002 Ω × 2 × 32 μF
CCP
=
= 3.9 pF
32.5kΩ
To meet the output voltage ripple requirement, use the following
equation to calculate the ESR and capacitance value of the output
capacitor:
Choose standard components, as follows: RC = 31.6 kΩ,
CC = 1500 pF, and CCP = 3.9 pF.
∆IL
Figure 34 shows the bode plot at 4 A. The cross frequency is
59 kHz, and the phase margin is 55°.
COUT_RIPPLE
=
8 × fS × ∆VOUT _ RIPPLE
60
180
144
108
72
∆VOUT _ RIPPLE
48
RESR
=
∆IL
36
24
This calculation results in COUT_RIPPLE = 7.6 μF, and RESR = 27 mΩ.
12
36
To meet the 5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
0
0
–12
–24
–36
–48
–36
–72
–108
–144
KOV × ∆ISTEP2 × L
COUT_OV
=
2
2
(VOUT + ∆VOUT _OV ) −VOUT
KUV × ∆ISTEP2 × L
–60
1k
–180
COUT_UV
=
10k
100k
1M
2 ×(VIN −VOUT )× ∆VOUT _UV
FREEQUENCY (Hz)
Figure 34. Bode Plot at 4 A
where:
OV = KUV = 2 are the coefficients for estimation purposes.
∆ISTEP = 3 A is the load transient step.
∆VOUT_OV = 5%VOUT is the overshoot voltage.
∆VOUT_UV = 5%VOUT is the undershoot voltage.
K
SOFT START TIME PROGRAM
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
This calculation results in COUT_OV = 53.2 μF, and COUT_UV = 20.7 μF.
According to the calculation, the output capacitance must be
greater than 53 μF, and the ESR of the output capacitor must be
smaller than 27 mΩ. It is recommended that two pieces of
47 μF/X5R/6.3 V ceramic capacitors be used, such as the
GRM32ER60J476ME20 from Murata, with an ESR of 2 mΩ.
tSS _ EXT × ISS _
4ms × 3.2μA
UP
CSS =
=
= 21.3 nF
0.6
0.6V
Choose a standard component value, as follows: CSS = 22 nF.
INPUT CAPACITOR SELECTION (DESIGN
EXAMPLE)
COMPENSATION COMPONENTS
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this case, fSW is running at 600 kHz;
therefore, the fC is set to 60 kHz.
A minimum 10 μF ceramic capacitor must be placed near the
PVIN pin. In this application, it is recommended that one 10 μF,
X5R, 25 V ceramic capacitor be used.
The 47 µF ceramic output capacitor has a derated value of 32 µF.
2×π×3.3 V×2×32 μF×60 kHz
RC =
= 32.5 kΩ
0.6 V×470 μS×8.7 A/V
Rev. A | Page 20 of 24
Data Sheet
ADP2384
RECOMMENDED EXTERNAL COMPONENTS
Table 9. Recommended External Components for Typical Applications with 4 A Output Current
fSW (kHz)
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
VOUT (V)
L (µH)
2.2
3.3
3.3
4.7
4.7
6.8
10
2.2
2.2
3.3
3.3
3.3
3.3
2.2
2.2
2.2
3.3
4.7
1
COUT (µF)1
680
680
470
RTOP (kΩ)
RBOT (kΩ)
RC (kΩ)
CC (pF)
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
1000
1000
1000
1000
1000
1000
1000
1000
1000
CCP (pF)
150
100
100
68
300
1
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
15
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
10
15
2.21
3
15
10
10
10
15
2.21
15
2.21
3
15
10
47
59
47
60.4
22
29.4
34
47
39
47
24
22
29.4
39
31.6
24
31.6
44.2
26.7
21
26.7
24
1.2
1.5
1.8
2.5
3.3
5
470
2 × 100
2 × 100
100 + 47
680
470
470
3 × 100
2 × 100
2 × 100
3 × 100
2 × 100
2 × 47
2 × 47
100
3 × 100
2 × 100
2 × 100
100 + 47
100
10
8.2
4.7
150
100
100
15
10
8.2
10
8.2
4.7
4.7
2.2
10
1
1.2
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
5
5
600
12
12
12
12
12
5
5
5
5
5
15
20
47.5
10
22
10
10
15
20
1
1.2
1.5
1.8
2.5
3.3
2.5
3.3
5
1
10
10
1.5
1.5
1.5
1.5
1.5
2.2
2.2
1
1
1
1
1
8.2
4.7
4.7
3.3
2.2
1
8.2
6.8
4.7
4.7
3.3
2.2
47.5
10
22
28
5
100
1000
12
12
12
5
5
5
5
5
5
100
100
100
3 × 100
2 × 100
100 + 47
2 × 47
100
47.5
10
22
10
10
15
20
47.5
10
37.4
47
69
43.2
33
33
30
37.4
47
1
1.2
1.5
1.8
2.5
3.3
10
10
15
2.21
1
100
1 680 μF: 4 V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. A | Page 21 of 24
ADP2384
Data Sheet
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good printed circuit board (PCB) layout is essential for obtaining
the best performance from the ADP2384. Poor PCB layout can
degrade the output regulation, as well as the electromagnetic
interference (EMI) and electromagnetic compatibility (EMC)
performance. Figure 36 shows an example of a good PCB layout
for the ADP2384. For optimum layout, refer to the following
guidelines:
•
•
Connect the exposed GND pad of the ADP2384 to a large,
external copper ground plane to maximize its power
dissipation capability and minimize junction temperature.
In addition, connect the exposed SW pad to the SW pins
of the ADP2384 using short, wide traces; or connect the
exposed SW pad to a large copper plane of the switching
node for high current flow.
Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Minimize
the length of the trace that connects the top of the feedback
resistor divider to the output while keeping the trace away
from the high current traces and the switching node to
avoid noise pickup. To further reduce noise pickup, place
an analog ground plane on either side of the FB trace and
ensure that the trace is as short as possible to reduce the
parasitic capacitance pickup.
•
Use separate analog ground planes and power ground
planes. Connect the ground reference of sensitive analog
circuitry, such as output voltage divider components, to
analog ground. In addition, connect the ground reference
of power components, such as input and output capacitors,
to power ground. Connect both ground planes to the exposed
GND pad of the ADP2384.
•
•
Place the input capacitor, inductor, and output capacitor as
close as possible to the IC, and use short traces.
Ensure that the high current loop traces are as short and as
wide as possible. Make the high current path from the input
capacitor through the inductor, the output capacitor, and the
power ground plane back to the input capacitor as short as
possible. To accomplish this, ensure that the input and output
capacitors share a common power ground plane.
ADP2384
V
PVIN
EN
BST
SW
IN
C
C
IN
BST
V
L
OUT
PGOOD
SYNC
C
OUT
R
TOP
FB
•
In addition, ensure that the high current path from the power
ground plane through the inductor and output capacitor
back to the power ground plane is as short as possible by
tying the PGND pins of the ADP2384 to the PGND plane
as close as possible to the input and output capacitors.
R
RT
COMP
SS
BOT
R
C
VREG
R
T
C
GND PGND
VREG
C
C
C
SS
Figure 35. High Current Path in the PCB Circuit
ANALOG GROUND PLANE
R
BOT
PVIN
COMP
FB
PVIN
PVIN
R
TOP
INPUT INPUT
BYPASS BULK
GND
SW
VREG
CAP
CAP
PVIN
BST
C
VREG
GND
SW
+
C
BST
SW
SW
PGND
SW
INDUCTOR
POWER GROUND PLANE
OUTPUT
CAPACITOR
VOUT
VIA
BOTTOM LAYER TRACE
COPPER PLANE
Figure 36. Recommended PCB Layout
Rev. A | Page 22 of 24
Data Sheet
ADP2384
TYPICAL APPLICATIONS CIRCUITS
ADP2384
V
= 12V
IN
BST
SW
PVIN
EN
C
10µF
25V
IN
C
BST
0.1µF
L1
1.5µH
V
= 1.2V
OUT
PGOOD
SYNC
RT
C
100µF
C
100µF
C
OUT3
100µF
6.3V
OUT1
OUT2
R
10kΩ
TOP
6.3V
6.3V
R
1%
T
124kΩ
FB
R
BOT
10kΩ
1%
COMP
VREG
SS
C
R
VREG
1µF
C
27.4kΩ
C
C
2.2nF
CP
10pF
GND PGND
C
C
SS
22nF
Figure 37. Typical Applications Circuit, VIN = 12 V, VOUT = 1.2 V, IOUT = 4 A, fSW = 500 kHz
ADP2384
V
= 12V
IN
BST
SW
PVIN
EN
C
10µF
25V
IN
C
BST
0.1µF
L1
2.2µH
V
= 1.8V
OUT
PGOOD
SYNC
RT
C
100µF
C
OUT2
100µF
6.3V
OUT1
R
20kΩ
TOP
6.3V
R
1%
T
100kΩ
FB
R
BOT
10kΩ
1%
COMP
VREG
SS
C
1µF
R
VREG
C
31.6kΩ
C
C
1.5nF
CP
8.2pF
GND PGND
C
Figure 38. Typical Applications Circuit Using Internal Soft Start, VIN = 12 V, VOUT = 1.8 V, IOUT = 4 A, fSW = 600 kHz
ADP2384
V
= 12V
IN
BST
SW
PVIN
EN
C
10µF
25V
IN
C
BST
0.1µF
L1
4.7µH
V
= 5V
OUT
PGOOD
SYNC
RT
C
100µF
6.3V
OUT
R
22kΩ
1%
TOP
R
T
124kΩ
FB
R
3kΩ
1%
BOT
COMP
VREG
SS
R
C
C
1µF
VREG
44.2kΩ
C
C
1.5nF
CP
2.2pF
GND PGND
C
C
22nF
SS
Figure 39. Typical Applications Circuit with Programming Switching Frequency at 500 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 4 A, fSW = 500 kHz
Rev. A | Page 23 of 24
ADP2384
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
2.80
2.70
2.60
0.20
MIN
0.20 MIN
PIN 1
PIN 1
INDICATOR
INDICATOR
1.50
0.20
MIN
19
24
18
1.40
1
1.30
0.45
EXPOSED
PAD
0.35
0.25
0.50
BSC
EXPOSED
PAD
1.05
0.95
0.85
6
13
7
12
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
0.20
MIN
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD .
Figure 40. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option
ADP2384ACPZN-R7 −40°C to +125°C
ADP2384-EVALZ
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7”Tape and Reel
Evaluation Board
CP-24-12
1 Z = RoHS Compliant Part.
©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10725-0-7/14(A)
Rev. A | Page 24 of 24
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