ADMV4420ACPZ [ADI]
K Band Downconverter with Integrated Fractional-N PLL and VCO;
| 型号： | ADMV4420ACPZ |
| 厂家： | 
ADI |
| 描述： | K Band Downconverter with Integrated Fractional-N PLL and VCO |
| 文件： | 总61页 (文件大小：1041K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K Band Downconverter with Integrated
Fractional-N PLL and VCO
ADMV4420
Data Sheet
FEATURES
GENERAL DESCRIPTION
RF front end with integrated RF balun and LNA
The ADMV4420 is a highly integrated, double balanced, active
Double balanced, active mixer with high dynamic range IF
amplifier
mixer with an integrated fractional-N synthesizer, ideally suited
for next generation K band satellite communications.
Fractional-N synthesizer with low phase noise, multicore VCO
5 V supply operation with integrated LDO regulators
Output P1dB: 7 dBm
Output IP3: 16 dBm
Conversion gain: 36 dB
The RF front end consists of an integrated RF balun and low
noise amplifier (LNA) for an optimal, 7 dB, single-sideband
noise figure while minimizing external components. Additionally,
the high dynamic range IF output amplifier provides a nominal
conversion gain of 36 dB.
Noise figure: 7 dB
An integrated low phase noise, fractional-N, phase-locked loop
(PLL) with a multicore voltage controlled oscillator (VCO) and
internal 2× multiplier generate the necessary on-chip LO signal
for the double balanced mixer, eliminating the need for external
frequency synthesis. The multicore VCO uses an internal
autocalibration routine that allows the PLL to select the
necessary settings and lock in approximately 400 µs.
RF input frequency range: 16.95 GHz to 22.05 GHz
Internal LO frequency range: 16.35 GHz to 21.15 GHz
IF frequency range: 900 MHz to 2500 MHz
Single-ended 50 Ω input impedance and 75 Ω IF output
impedance
Programmable via 4-wire SPI
32-lead, 5 mm × 5 mm LFCSP
The reference input to the PLL employs a differentially excited
50 MHz crystal oscillator. Alternatively, the reference input can
be driven by an external, singled-ended, 50 MHz source. The
phase frequency detector (PFD) comparison frequency of the
PLL operates up to 50 MHz.
APPLICATIONS
Satellite communication
Point to point microwave communication
The ADMV4420 is fabricated on a silicon germanium (SiGe),
bipolar complementary metal-oxide semiconductor (BiCMOS)
process, and is available in a 32-lead, RoHS compliant, 5 mm ×
5 mm LFCSP package with an exposed pad. The device is
specified over the −40°C to +85°C temperature range on a 5 V
power supply.
Rev. A
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Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved.
Technical Support
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ADMV4420
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
IF Output—External Inductor/Biasing ................................... 40
SPI Configuration ...................................................................... 40
VCO Autocalibration and Automatic Level Control............. 40
Programming Sequence ............................................................ 40
Control Registers............................................................................ 41
Register Details ............................................................................... 42
Address 0x000, Reset: 0x00, Name: ADI_SPI_CONFIG_1.. 42
Address 0x001, Reset: 0x00, Name: ADI_SPI_CONFIG_2.. 43
Address 0x003, Reset: 0x01, Name: CHIPTYPE.................... 44
Address 0x004, Reset: 0x03, Name: PRODUCT_ID_L ........ 44
Address 0x005, Reset: 0x00, Name: PRODUCT_ID_H ....... 44
Address 0x00A, Reset: 0x00, Name: SCRATCHPAD............ 44
Address 0x00B, Reset: 0x00, Name: SPI_REV........................ 44
Address 0x103, Reset: 0x6F, Name: ENABLES....................... 45
Address 0x108, Reset: 0x05, Name: SDO_LEVEL................. 45
Address 0x200, Reset: 0xA7, Name: INT_L ........................... 46
Address 0x201, Reset: 0x00, Name: INT_H ........................... 46
Address 0x202, Reset: 0x02, Name: FRAC_L......................... 46
Address 0x203, Reset: 0x00, Name: FRAC_M ....................... 46
Address 0x204, Reset: 0x00, Name: FRAC_H........................ 46
Address 0x208, Reset: 0x04, Name: MOD_L ......................... 47
Address 0x209, Reset: 0x00, Name: MOD_M........................ 47
Address 0x20A, Reset: 0x00, Name: MOD_H........................ 47
Address 0x20C, Reset: 0x01, Name: R_DIV_L ...................... 48
Address 0x20D, Reset: 0x00, Name: R_DIV_H ..................... 48
Address 0x20E, Reset: 0x00, Name: REFERENCE................ 48
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Interface Schematics..................................................................... 9
Typical Performance Characteristics ........................................... 10
IF = 900 MHz, Low-Side Injection LO Performance ............ 10
IF = 900 MHz, High-Side Injection LO Performance........... 12
IF = 1700 MHz, Low-Side Injection LO Performance .......... 14
IF = 1700 MHz, High-Side Injection LO Performance......... 16
IF = 2500 MHz, Low-Side Injection LO Performance .......... 18
IF = 2500 MHz, High-Side Injection LO Performance......... 20
LO = 16.75 GHz, Low-Side Injection Performance............... 22
LO = 16.75 GHz, High-Side Injection Performance ............. 24
LO = 18.95 GHz, Low-Side Injection Performance............... 26
LO = 18.95 GHz, High-Side Injection Performance ............. 28
LO = 21.15 GHz, Low-Side Injection Performance............... 30
LO = 21.15 GHz, High-Side Injection Performance ............. 32
Phase Noise Performance.......................................................... 34
Return Loss and Isolation.......................................................... 35
Spurious and Harmonics Performance ................................... 36
Theory of Operation ...................................................................... 37
Reference Input Stage................................................................. 37
Reference Doubler, R Counter, and RDIV2............................ 37
N Counter.................................................................................... 38
INT, FRAC, MOD, and Reference Path Relationship............ 38
Integer-N Mode .......................................................................... 38
Phase Frequency Detector and Charge Pump........................ 38
Loop Filter ................................................................................... 39
CP Current Setup ....................................................................... 39
Bleed Current (CP_BLEED) Setup .......................................... 39
MUXOUT.................................................................................... 39
Digital Lock Detect .................................................................... 40
Enables ......................................................................................... 40
Address 0x211, Reset: 0x00, Name:
VCO_DATA_READBACK1..................................................... 49
Address 0x212, Reset: 0x00, Name:
VCO_DATA_READBACK2..................................................... 49
Address 0x213, Reset: 0x01, Name: PLL_MUX_SEL............ 50
Address 0x214, Reset: 0x98, Name: LOCK_DETECT.......... 50
Address 0x215, Reset: 0x00, Name: VCO_BAND_SELECT 51
Address 0x216, Reset: 0x00, Name: VCO_ALC_TIMEOUT51
Address 0x217, Reset: 0x01, Name: VCO_MANUAL........... 51
Address 0x219, Reset: 0x13, Name: ALC ................................ 51
Address 0x21C, Reset: 0x90, Name: VCO_TIMEOUT1 ...... 52
Address 0x21D, Reset: 0x01, Name: VCO_TIMEOUT2 ...... 52
Address 0x21E, Reset: 0x4B, Name: VCO_BAND_DIV ...... 52
Address 0x21F, Reset: 0x18, Name: VCO_READBACK_SEL
....................................................................................................... 52
Rev. A | Page 2 of 61
Data Sheet
ADMV4420
Address 0x226, Reset: 0x02, Name: AUTOCAL.....................53
Address 0x22C, Reset: 0x07, Name: CP_STATE ....................54
Address 0x22D, Reset: 0x01, Name: CP_BLEED_EN............54
Address 0x22E, Reset: 0x03, Name: CP_CURRENT .............54
Address 0x22F, Reset: 0x0C, Name: CP_BLEED....................54
Applications Information...............................................................55
Evaluation Board.........................................................................55
Outline Dimensions........................................................................60
Ordering Guide ...........................................................................60
REVISION HISTORY
4/2019—Rev. 0 to Rev. A
Change to Features Section..............................................................1
Changes to Local Oscillator (LO) Internal Frequency Range
Parameter, VCO Frequency Range Parameter, and Conversion
Gain Parameter, Table 1....................................................................5
Changes to IF = 900 MHz, Low-Side Injection LO Performance
Section ..............................................................................................10
Changes to IF = 1700 MHz, Low-Side Injection LO
Performance Section.......................................................................14
Changes to IF = 2500 MHz, Low-Side Injection LO
Performance Section.......................................................................18
10/2018—Revision 0: Initial Version
Rev. A | Page 3 of 61
ADMV4420
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
PLL LOOP FILTER
27 26 25
32
31
30
29
28
GND
1
SPI/
LOGIC
ADMV4420
24 SDO
23 GND
GND
GND
RFIN
GND
GND
2
3
4
5
6
16.75GHz TO 21.15GHz
×2
CPOUT
CALIBRATION
SWITCH
22
21 VPOS3_CP
20 ENBL1
19 ENBL0
18 GND
VCO
VCO
INTEGER
REGISTER
FRACTION
REGISTER
MODULUS
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
8.375GHz TO 10.575GHz
CHARGE
PUMP
PHASE
FREQUENCY
DETECTOR
17 GND
BLEED
CURRENT
DECL1_VCO1
DECL2_VCO2
7
8
3.3V
VCO
LDO
÷1 OR ÷2
÷1
×1 OR ×2
3.3V
PLL
LDO
1.8V
SDM
LDO
REFERENCE REFERENCE REFERENCE
DIVIDE-BY-2 DIVIDER DOUBLER
9
10
11
12
13
14
15
16
Figure 1.
Rev. A | Page 4 of 61
Data Sheet
ADMV4420
SPECIFICATIONS
The measurements are performed at TA = 25°C with 0 dBm external reference at 50 MHz when VVPOS1_VCO = VVPOS2_PLL = VVPOS3_CP
=
V
VPOS4_IF = 5 V, RF input power = −40 dBm, and PLL loop filter bandwidth = 60 kHz with 45° of phase margin, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF INPUT
Frequency Range
Input Return Loss
Input Impedance
16.95
22.05
GHz
dB
Ω
−8.5
50
Single-ended
LOCAL OSCILLATOR (LO) INTERNAL
FREQUENCY RANGE
16.35
21.15
GHz
VCO
Frequency Range
Tuning Sensitivity (kVCO
VTUNE
8.175
0
10.575 GHz
MHz/V
)
50
Calculated with fVCO/VTUNE
3
V
IF OUTPUT
IF Frequency Range
Conversion Gain
IF = 900 MHz
900
2500
MHz
Low-Side Injection
LO = 16.75 GHz
LO = 18.95 GHz
LO = 21.15 GHz
High-Side Injection
LO = 17.85 GHz
LO = 18.95 GHz
LO = 21.15 GHz
IF = 950 MHz
31
33
35
39
32
dB
dB
dB
RF = 17.65 GHz
RF = 19.85GHz
RF = 22.05 GHz
28.5
32.5
29
33
37
40
dB
dB
dB
RF = 16.95 GHz
RF = 18.05 GHz
RF = 20.25 GHz
Low-Side Injection
LO = 16.35 GHz
IF = 2500 MHz
29
32
dB
RF = 17.30 GHz
Low-Side Injection
LO = 16.75 GHz
LO = 17.95 GHz
LO = 19.55 GHz
High-Side Injection
LO = 19.45 GHz
LO = 20.45 GHz
LO = 21.15 GHz
28.5
36
38
30
dB
dB
dB
RF = 19.25 GHz
RF = 20.45 GHz
RF = 22.05 GHz
27
31
35
37
7
dB
dB
dB
dBm
RF = 16.95 GHz
RF = 17.95 GHz
RF = 18.65 GHz
Output 1 dB Compression Point
(Output P1dB)
Output Third-Order Intercept
(Output IP3)
Noise Figure
Gain Flatness
16
7
dBm
dB
Single sideband with appropriate filtering
1
2
dB
dB
Across any 250 MHz bandwidth for an IF of 900 MHz to
2000 MHz
Across any 250 MHz bandwidth for an IF of 2000 MHz to
2500 MHz
Output Impedance
Output Return Loss
75
−6.5
Ω
dB
Single-ended
Rev. A | Page 5 of 61
ADMV4420
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY VOLTAGE
VVPOS1_VCO, VVPOS2_PLL, VVPOS3_CP, VVPOS4_IF
TOTAL POWER CONSUMPTION
Active Mode
4.75
5.00
5.25
V
1900
80
mW
mW
Sleep Mode
All blocks powered down
EXTERNAL PLL REFERENCE
Frequency
50
MHz
Amplitude
0.3
2.5
V p-p
Single-ended input, high impedance
Fundamental mode
CRYSTAL REFERENCE
Crystal Frequency
Capacitance
50
10
50
MHz
pF
PHASE FREQUENCY DETECTOR (PFD)
FREQUENCY
MHz
Compare frequency
REFERENCE SPURS
−70
400
dBm
μs
FREQUENCY SETTLING
CLOSED-LOOP PHASE NOISE
After frequency change programmed; within 50 kHz resolution
LO frequency = 16.75 GHz to 21.15 GHz
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
−80
−85
−116
−125
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
LOGIC
(ENBL0, ENBL1, SDO, SDI, SCLK, CS)
Logic Low
Logic High
−0.3
1.2
0
3.3
+0.5
3.6
V
V
Rev. A | Page 6 of 61
Data Sheet
ADMV4420
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Supply Voltage (VVPOS1_VCO, VVPOS2_PLL
VVPOS3_CP, and VVPOS4_IF
Digital Input/Output Signal (SCLK, SDI,
SDO, CS, ENBL1, and ENBL0)
,
5.5 V
3.6 V
θ
JA is the natural convection junction to ambient measured in a
one cubic foot sealed enclosure. θJC is the junction to case
thermal resistance.
RFIN
0 dBm
300 µA
125°C
260°C
−40°C to +85°C
−65°C to +150°C
Source and Sink Current (MUXOUT)
Maximum Junction Temperature
Peak Reflow Temperature
Operating Temperature Range
Storage Temperature Range
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
Table 3. Thermal Resistance
1
1
Package Type
θJC
θJA
39.6
Unit
CP-32-12
7.25
°C/W
1 The θJA and θJC values are determined by measuring the thermally
designed PCB with a heat sink.
500 V1
2000 V2
1500 V3
500 V
ESD CAUTION
Field Induced Charged Device Model
(FICDM)1
1 Applies to all pins of the ADMV4420.
2 Applies to all pins except the MUXOUT, ENBL0, ENBL1, SDO, SDI, SCLK, and
CS
pins.
Applies to the MUXOUT, ENBL0, ENBL1, SDO, SDI, SCLK, and pins.
3
CS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
60 SECONDS
TO
150 SECONDS
RAMP UP
3°C/SEC MAX
260°C –5°C/+0°C
217°C
150°C TO 200°C
RAMP DOWN
6°C/SEC MAX
TIME (Seconds)
60 SECONDS
20 SECONDS
TO 40 SECONDS
TO 180 SECONDS
480 SECONDS MAX
Figure 2. Pb-Free Reflow Solder Profile
Rev. A | Page 7 of 61
ADMV4420
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
GND
GND
GND
RFIN
GND
1
2
3
4
5
6
7
8
24 SDO
23
22 CPOUT
GND
ADMV4420
TOP VIEW
(Not to Scale)
21 VPOS3_CP
20
19
ENBL1
ENBL0
GND
DECL1_VCO1
DECL2_VCO2
18 GND
17 GND
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 3, 5, 6,
16, 17, 18,
23, 31
GND
Ground. Connect these pins and package bottom to RF and dc ground. See Figure 4 for the GND interface
schematic.
4
RFIN
RF Input Pin. This pin has a 50 Ω input impedance.
7, 8
DECL1_VCO1, LDO Regulator Decoupling Pin. Place a 10 µF capacitor close to this pin.
DECL2_VCO2
9
VPOS1_VCO
5 V Power Supply Pin. Place 0.1 µF and 100 pF decoupling capacitors close to this pin.
LDO Decoupling Pin. Place a 10 µF capacitor close to this pin.
10, 11, 32
DECL3_PLL,
DECL4_SDM,
DECL5_RF
12
13
VPOS2_PLL
XTAL2/NC
5 V Power Supply. Place the 0.1 µF and 100 pF decoupling capacitor close to this pin.
Crystal Input or No Connect. When using an external crystal, place the crystal between the REF/XTAL1 and
XTAL2/DNC pins. When an external reference input signal is applied through the REF/XTAL1 pin, this pin is
used as a No Connect pin. Connect this pin to ground with a 1 nF capacitor (ac ground) when an external
reference input signal is applied through the REF/XTAL1 pin.
14
REF/XTAL1
External Reference Input or Crystal Input. When using an external crystal, place the crystal between the
XTAL1 and XTAL2 pins. When using as external reference input, apply an external reference signal to this
pin with a 0.01 µF, dc blocking capacitor. Refer to Figure 121 for the external reference input configuration.
This pin is internally biased to 1.65 V.
15
19
20
21
22
24
25
26
27
28
29
30
MUXOUT
ENBL0
ENBL1
VPOS3_CP
CPOUT
SDO
PLL Multiplexer Output.
Device Enable 0. For nominal operation, keep this pin tied to 3.3 V.
Device Enable 1. For nominal operation, keep this pin tied to 3.3 V
5 V Power Supply. Place the 0.1 µF and 100 pF decoupling capacitor close to this pin.
Synthesizer Charge Pump Output. Connect this pin to VTUNE (Pin 28) through the loop filter
Serial Peripheral Interface (SPI) Data Output. 3.3 V logic.
SPI Data Input. 3.3 V logic.
SDI
SCLK
SPI Clock. 3.3 V logic.
SPI Chip Select. 3.3 V logic. Active low.
CS
VTUNE
VPOS4_IF
IFOUT
VCO Tuning Voltage. This pin is driven by the output of the loop filter.
5 V Power Supply. Place 0.1 µF and 100 pF decoupling capacitors close to this pin.
IF Output. This pin has a 75 Ω output impedance. The output stage of the IF amplifier is an open-collector
configuration and requires a dc bias of 5 V. Use a bias choke inductor. See the IF Output—External
Inductor/Biasing section for more details.
EPAD
Exposed Pad. The exposed pad must be connected to GND.
Rev. A | Page 8 of 61
Data Sheet
ADMV4420
INTERFACE SCHEMATICS
GND
VPOS3_CP
Figure 4. GND Interface Schematic
CPOUT
DECL1_VCO1,
DECL2_VCO2,
DECL3_PLL,
DECL4_SDM,
DECL5_RF
Figure 11. CPOUT Interface Schematic
ESD
CLAMP
VPOS4_IF
Figure 5. DECL1_VCO1, DECL2_VCO2, DECL3_PLL, DECL4_SDM, and
DECL5_RF Interface Schematic
SDO
ESD
RFIN
ESD
Figure 12. SDO Interface Schematic
Figure 6. RFIN Interface Schematic
VPOS4_IF
VPOS1_VCO,
VPOS2_PLL,
VPOS3_CP,
SDI,
SCLK,
CS
500Ω
VPOS4_IF
ESD
CLAMP
ESD
CLAMP
Figure 7. VPOS1_VCO, VPOS2_PLL, VPOS3_CP, and VPOS4_IF Interface
Schematic
CS
Figure 13. SDI, SCLK, and Interface Schematic
XTAL2/NC
REF/XTAL1
VTUNE
ESD
CLAMP
ESD
CLAMP
Figure 14. VTUNE Interface Schematic
Figure 8. XTAL2/NC and REF/XTAL1 Interface Schematic
VPOS4_IF
VPOS2_PLL
IFOUT
ESD
MUXOUT
ESD
CLAMP
Figure 15. IFOUT Interface Schematic
Figure 9. MUXOUT Interface Schematic
VPOS4_IF
ENBL0
ENBL1
500Ω
ESD
CLAMP
Figure 10. ENBL0 and ENBL1 Interface Schematic
Rev. A | Page 9 of 61
ADMV4420
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
A 0 dBm external reference at 50 MHz is used with VVPOS1_VCO = VVPOS2_PLL = VVPOS3_CP = VVPOS4_IF = 5 V, RF input power = −40 dBm, and
the PLL loop filter bandwidth = 60 kHz with 45° of phase margin, unless otherwise noted.
IF = 900 MHz, LOW-SIDE INJECTION LO PERFORMANCE
RF minimum and maximum frequencies are limited by the LO frequency = 16.75 GHz to 21.15 GHz.
50
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
+85°C
+25°C
–40°C
5.25V
5.00V
4.75V
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 16. Conversion Gain vs. RF Frequency at Various Temperatures
Figure 18. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
20
+85°C
18
5.25V
5.00V
4.75V
18
16
14
12
10
8
+25°C
–40°C
16
14
12
10
8
6
6
4
4
2
2
NO FILTERING APPLIED
NO FILTERING APPLIED
0
0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 17. Noise Figure vs. RF Frequency at Various Temperatures
Figure 19. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 10 of 61
Data Sheet
ADMV4420
30
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
28
26
24
22
20
18
16
14
12
10
5.25V
5.00V
4.75V
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 20. Output IP3 vs. RF Frequency at Various Temperatures
Figure 22. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
12
10
8
6
6
5.25V
+85°C
5.00V
4
4
+25°C
4.75V
–40°C
2
2
0
0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 21. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Figure 23. Output P1dB vs. RF Frequency at Various Temperatures
Rev. A | Page 11 of 61
ADMV4420
Data Sheet
IF = 900 MHz, HIGH-SIDE INJECTION LO PERFORMANCE
The RF minimum frequency is limited at 16.95 GHz for optimal performance and the RF maximum frequency is limited at the maximum
LO frequency (21.15 GHz).
50
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
5.25V
5.00V
4.75V
+85°C
+25°C
–40°C
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 24. Conversion Gain vs. RF Frequency at Various Temperatures
Figure 27. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
20
18
16
14
12
10
8
+85°C
+25°C
–40°C
18
16
14
12
10
8
6
6
4
2
0
5.25V
5.00V
4.75V
4
2
NO FILTERING APPLIED
NO FILTERING APPLIED
0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 25. Noise Figure vs. RF Frequency at Various Temperatures
Figure 28. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
12
10
8
6
6
5.25V
5.00V
4.75V
+85°C
4
4
2
0
+25°C
–40°C
2
0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 26. Output P1dB vs. RF Frequency at Various Temperatures
Figure 29. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 12 of 61
Data Sheet
ADMV4420
30
28
26
24
22
20
18
16
14
12
10
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
5.25V
5.00V
4.75V
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 30. Output IP3 vs. RF Frequency at Various Temperatures
Figure 31. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 13 of 61
ADMV4420
Data Sheet
IF = 1700 MHz, LOW-SIDE INJECTION LO PERFORMANCE
The RF minimum frequency is limited at the LO frequency of 16.75 GHz and the RF maximum frequency is limited at 22.05 GHz for
optimal performance.
50
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
+85°C
+25°C
–40°C
5.25V
5.00V
4.75V
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 32. Conversion Gain vs. RF Frequency at Various Temperatures
Figure 35. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
20
+85°C
+25°C
–40°C
18
16
14
12
10
8
18
5.25V
5.00V
16
4.75V
14
12
10
8
6
6
4
4
2
2
NO FILTERING APPLIED
NO FILTERING APPLIED
0
0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 33. Noise Figure vs. RF Frequency at Various Temperatures
Figure 36. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
5.25V
5.00V
4.75V
12
10
8
6
6
+85°C
4
4
+25°C
–40°C
2
2
0
0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 34. Output P1dB vs. RF Frequency at Various Temperatures
Figure 37. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 14 of 61
Data Sheet
ADMV4420
30
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
28
26
24
22
20
18
16
14
12
10
5.25V
5.00V
4.75V
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 38. Output IP3 vs. RF Frequency at Various Temperatures
Figure 39. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 15 of 61
ADMV4420
Data Sheet
IF = 1700 MHz, HIGH-SIDE INJECTION LO PERFORMANCE
The RF minimum frequency is limited at 16.95 GHz for optimum performance and the RF maximum frequency is limited at the
maximum LO frequency (21.15 GHz).
50
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
+85°C
+25°C
–40°C
5.25V
5.00V
4.75V
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 40. Conversion Gain vs. RF Frequency at Various Temperatures
Figure 43. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
20
+85°C
+25°C
–40°C
18
16
14
12
10
8
18
16
14
12
10
8
5.25V
5.00V
4.75V
6
6
4
4
2
2
NO FILTERING APPLIED
NO FILTERING APPLIED
0
0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 41. Noise Figure vs. RF Frequency at Various Temperatures
Figure 44. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
12
10
8
6
6
+85°C
5.25V
4
4
+25°C
5.00V
–40°C
4.75V
2
2
0
0
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 42. Output P1dB vs. RF Frequency at Various Temperatures
Figure 45. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 16 of 61
Data Sheet
ADMV4420
30
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
28
26
24
22
20
18
16
14
12
10
5.25V
5.00V
4.75V
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 46. Output IP3 vs. RF Frequency at Various Temperatures
Figure 47. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 17 of 61
ADMV4420
Data Sheet
IF = 2500 MHz, LOW-SIDE INJECTION LO PERFORMANCE
In this configuration, the RF minimum frequency is limited at the LO frequency of 16.75 GHz and the RF maximum frequency is limited
at 22.05 GHz for optimal performance.
50
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
+85°C
+25°C
–40°C
5.25V
5.00V
4.75V
19.25
19.65
20.05
20.45
20.85
21.25
21.65
22.05
19.25
19.65
20.05
20.45
20.85
21.25
21.65
22.05
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 48. Conversion Gain vs. RF Frequency at Various Temperatures
Figure 51. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
20
+85°C
+25°C
–40°C
18
16
14
12
10
8
18
5.25V
5.00V
4.75V
16
14
12
10
8
6
6
4
4
2
2
NO FILTERING APPLIED
NO FILTERING APPLIED
0
0
19.25
19.65
20.05
20.45
20.85
21.25
21.65
22.05
19.25
19.65
20.05
20.45
20.85
21.25
21.65
22.05
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 49. Noise Figure vs. RF Frequency at Various Temperatures
Figure 52. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
5.25V
5.00V
4.75V
12
10
8
6
6
+85°C
4
4
+25°C
–40°C
2
2
0
0
19.25
19.65
20.05
20.45
20.85
21.25
21.65
22.05
19.25
19.65
20.05
20.45
20.85
21.25
21.65
22.05
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 50. Output P1dB vs. RF Frequency at Various Temperatures
Figure 53. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 18 of 61
Data Sheet
ADMV4420
30
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
28
26
24
22
20
18
16
14
12
10
5.25V
5.00V
4.75V
19.25
19.65
20.05
20.45
20.85
21.25
21.65
22.05
19.25
19.65
20.05
20.45
20.85
21.25
21.65
22.05
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 54. Output IP3 vs. RF Frequency at Various Temperatures
Figure 55. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 19 of 61
ADMV4420
Data Sheet
IF = 2500 MHz, HIGH-SIDE INJECTION LO PERFORMANCE
The RF minimum frequency is limited at 16.95 GHz for optimal performance and the RF maximum frequency is limited at the maximum
LO frequency (21.15 GHz).
50
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
+85°C
+25°C
–40°C
5.25V
5.00V
4.75V
16.95
17.29
17.63
17.97
18.31
18.65
16.95
17.29
17.63
17.97
18.31
18.65
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 56. Conversion Gain vs. RF Frequency at Various Temperatures
Figure 59. Conversion Gain vs. RF Frequency at Various Supply Voltages,
TA = 25°C
20
20
+85°C
+25°C
–40°C
18
16
14
12
10
8
18
16
14
12
10
8
5.25V
5.00V
4.75V
6
6
4
4
2
2
NO FILTERING APPLIED
17.97 18.31 18.65
NO FILTERING APPLIED
17.97 18.31 18.65
0
0
16.95
17.29
17.63
16.95
17.29
17.63
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 57. Noise Figure vs. RF Frequency at Various Temperatures
Figure 60. Noise Figure vs. RF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
12
10
8
6
6
+85°C
5.25V
4
4
+25°C
5.00V
–40°C
4.75V
2
2
0
0
16.95
17.29
17.63
17.97
18.31
18.65
16.95
17.29
17.63
17.97
18.31
18.65
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 58. Output P1dB vs. RF Frequency at Various Temperatures
Figure 61. Output P1dB vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 20 of 61
Data Sheet
ADMV4420
30
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
28
26
24
22
20
18
16
14
12
10
5.25V
5.00V
4.75V
16.95
17.29
17.63
17.97
18.31
18.65
16.95
17.29
17.63
17.97
18.31
18.65
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 62. Output IP3 vs. RF Frequency at Various Temperatures
Figure 63. Output IP3 vs. RF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 21 of 61
ADMV4420
Data Sheet
LO = 16.75 GHz, LOW-SIDE INJECTION PERFORMANCE
50
50
45
40
35
30
25
20
15
10
45
40
35
30
25
+85°C
5.25V
5.00V
4.75V
20
+25°C
–40°C
15
10
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 64. Conversion Gain vs. IF Frequency at Various Temperatures
Figure 67. Conversion Gain vs. IF Frequency at Various Supply Voltages,
TA = 25°C
20
20
+85°C
+25°C
–40°C
18
16
14
12
10
8
18
16
14
12
10
8
5.25V
5.00V
4.75V
6
6
4
4
2
2
NO FILTERING APPLIED
NO FILTERING APPLIED
0
900
0
900
1100
1300
1500
1700
1900
2100
2300
2500
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 65. Noise Figure vs. IF Frequency at Various Temperatures
Figure 68. Noise Figure vs. IF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
12
10
8
6
6
+85°C
5.25V
4
4
+25°C
5.00V
–40°C
4.75V
2
2
0
900
0
900
1100
1300
1500
1700
1900
2100
2300
2500
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 66. Output P1dB vs. IF Frequency at Various Temperatures
Figure 69. Output P1dB vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 22 of 61
Data Sheet
ADMV4420
30
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
28
26
24
22
20
18
16
14
12
10
5.25V
5.00V
4.75V
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 70. Output IP3 vs. IF Frequency at Various Temperatures
Figure 71. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 23 of 61
ADMV4420
Data Sheet
LO = 16.75 GHz, HIGH-SIDE INJECTION PERFORMANCE
50
50
45
40
35
30
25
20
15
10
5.25V
5.00V
4.75V
+85°C
+25°C
–40°C
45
40
35
30
25
20
15
10
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 72. Conversion Gain vs. IF Frequency at Various Temperatures
Figure 75. Conversion Gain vs. IF Frequency at Various Supply Voltages,
TA = 25°C
30
30
+85°C
+25°C
–40°C
5.25V
5.00V
4.75V
25
25
20
15
10
5
20
15
10
5
NO FILTERING APPLIED
NO FILTERING APPLIED
0
900
0
900
1100
1300
1500
1700
1900
2100
2300
2500
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 73. Noise Figure vs. IF Frequency at Various Temperatures
Figure 76. Noise Figure vs. IF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
12
10
8
6
6
+85°C
5.25V
4
4
+25°C
5.00V
–40°C
4.75V
2
2
0
900
0
900
1100
1300
1500
1700
1900
2100
2300
2500
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 74. Output P1dB vs. IF Frequency at Various Temperatures
Figure 77. Output P1dB vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 24 of 61
Data Sheet
ADMV4420
30
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
28
26
24
22
20
18
16
14
12
10
5.25V
5.00V
4.75V
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 78. Output IP3 vs. IF Frequency at Various Temperatures
Figure 79. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 25 of 61
ADMV4420
Data Sheet
LO = 18.95 GHz, LOW-SIDE INJECTION PERFORMANCE
50
50
45
40
35
30
25
20
15
10
45
40
35
30
25
+85°C
5.25V
5.00V
4.75V
20
+25°C
–40°C
15
10
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 80. Conversion Gain vs. IF Frequency at Various Temperatures
Figure 83. Conversion Gain vs. IF Frequency at Various Supply Voltages,
TA = 25°C
20
20
+85°C
+25°C
–40°C
18
16
14
12
10
8
18
16
14
12
10
8
5.25V
5.00V
4.75V
6
6
4
4
2
2
NO FILTERING APPLIED
NO FILTERING APPLIED
1900 2100 2300 2500
IF FREQUENCY (MHz)
0
900
0
900
1100
1300
1500
1700
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
Figure 81. Noise Figure vs. IF Frequency at Various Temperatures
Figure 84. Noise Figure vs. IF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
12
10
8
6
6
+85°C
5.25V
4
4
+25°C
5.00V
–40°C
4.75V
2
2
0
900
0
900
1100
1300
1500
1700
1900
2100
2300
2500
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 82. Output P1dB vs. IF Frequency at Various Temperatures
Figure 85. Output P1dB vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 26 of 61
Data Sheet
ADMV4420
30
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
28
26
24
22
20
18
16
14
12
10
5.25V
5.00V
4.75V
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 86. Output IP3 vs. IF Frequency at Various Temperatures
Figure 87. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 27 of 61
ADMV4420
Data Sheet
LO = 18.95 GHz, HIGH-SIDE INJECTION PERFORMANCE
50
50
45
40
35
30
25
20
15
10
45
40
35
30
25
+85°C
5.25V
5.00V
4.75V
20
+25°C
–40°C
15
10
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 88. Conversion Gain vs. IF Frequency at Various Temperatures
Figure 91. Conversion Gain vs. IF Frequency at Various Supply Voltages,
TA = 25°C
20
20
+85°C
+25°C
–40°C
18
16
14
12
10
8
18
16
14
12
10
8
5.25V
5.00V
4.75V
6
6
4
4
2
2
NO FILTERING APPLIED
NO FILTERING APPLIED
0
0
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 89. Noise Figure vs. IF Frequency at Various Temperatures
Figure 92. Noise Figure vs. IF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
12
10
8
6
6
+85°C
5.25V
4
4
+25°C
5.00V
–40°C
4.75V
2
2
0
900
0
900
1100
1300
1500
1700
1900
2100
2300
2500
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 90. Output P1dB vs. IF Frequency at Various Temperatures
Figure 93. Output P1dB vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 28 of 61
Data Sheet
ADMV4420
30
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
28
26
24
22
20
18
16
14
12
10
5.25V
5.00V
4.75V
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 94. Output IP3 vs. IF Frequency at Various Temperatures
Figure 95. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 29 of 61
ADMV4420
Data Sheet
LO = 21.15 GHz, LOW-SIDE INJECTION PERFORMANCE
50
50
45
40
35
30
25
20
15
10
45
+85°C
+25°C
–40°C
40
35
30
25
20
15
10
5.25V
5.00V
4.75V
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 96. Conversion Gain vs. IF Frequency at Various Temperatures
Figure 99. Conversion Gain vs. IF Frequency at Various Supply Voltages,
TA = 25°C
30
30
+85°C
+25°C
–40°C
5.25V
5.00V
25
25
4.75V
20
15
10
5
20
15
10
5
NO FILTERING APPLIED
NO FILTERING APPLIED
0
900
0
900
1100
1300
1500
1700
1900
2100
2300
2500
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 97. Noise Figure vs. IF Frequency at Various Temperatures
Figure 100. Noise Figure vs. IF Frequency at Various Supply Voltages,
TA = 25°C
16
14
12
10
8
16
14
12
10
8
6
6
+85°C
5.25V
4
4
+25°C
5.00V
–40°C
4.75V
2
2
0
900
0
900
1100
1300
1500
1700
1900
2100
2300
2500
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 98. Output P1dB vs. IF Frequency at Various Temperatures
Figure 101. Output P1dB vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 30 of 61
Data Sheet
ADMV4420
30
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
28
26
24
22
20
18
16
14
12
10
5.25V
5.00V
4.75V
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 102. Output IP3 vs. IF Frequency at Various Temperatures
Figure 103. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 31 of 61
ADMV4420
Data Sheet
LO = 21.15 GHz, HIGH-SIDE INJECTION PERFORMANCE
50
50
45
40
35
30
25
20
15
10
45
40
35
30
25
+85°C
5.25V
5.00V
4.75V
+25°C
–40°C
20
15
10
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 107. Conversion Gain vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Figure 104. Conversion Gain vs. IF Frequency at Various Temperatures
20
20
+85°C
+25°C
–40°C
18
18
16
14
12
10
8
5.25V
5.00V
4.75V
16
14
12
10
8
6
6
4
4
2
2
NO FILTERING APPLIED
NO FILTERING APPLIED
0
900
0
900
1100
1300
1500
1700
1900
2100
2300
2500
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 108. Noise Figure vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Figure 105. Noise Figure vs. IF Frequency at Various Temperatures
16
14
12
10
8
16
14
12
10
8
6
6
5.25V
+85°C
4
4
5.00V
+25°C
4.75V
–40°C
2
2
0
900
0
900
1100
1300
1500
1700
1900
2100
2300
2500
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 109. Output P1dB vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Figure 106. Output P1dB vs. IF Frequency at Various Temperatures
Rev. A | Page 32 of 61
Data Sheet
ADMV4420
30
28
26
24
22
20
18
16
14
12
10
30
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
5.25V
5.00V
4.75V
900
1100
1300
1500
1700
1900
2100
2300
2500
900
1100
1300
1500
1700
1900
2100
2300
2500
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 110. Output IP3 vs. IF Frequency at Various Temperatures
Figure 111. Output IP3 vs. IF Frequency at Various Supply Voltages,
TA = 25°C
Rev. A | Page 33 of 61
ADMV4420
Data Sheet
PHASE NOISE PERFORMANCE
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
–110
–120
–130
–140
LO = 16.75GHz LOW-SIDE INJECTION
LO = 18.95GHz HIGH-SIDE INJECTION
LO = 18.95GHz LOW-SIDE INJECTION
LO = 21.15GHz HIGH-SIDE INJECTION
+85°C
+25°C
–40°C
–110
–120
–130
–140
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
Figure 112. Closed-Loop Phase Noise vs. Offset Frequency at Various
Temperatures, IF = 900 MHz, Low-Side Injection LO = 18.95 GHz
Figure 114. Closed-Loop Phase Noise vs. Offset Frequency at Various LO
Frequencies, TA = 25°C GHz
–40
–50
–60
–70
–80
–90
–100
0
8375MHz
8805MHz
9270MHz
9720MHz
10570MHz
10740MHz
–20
–40
–60
–80
+85°C
+25°C
–40°C
–110
–120
–130
–140
–100
–120
–140
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
Figure 113. Closed-Loop Phase Noise vs. Offset Frequency at Various
Temperatures, IF = 900 MHz, High-Side Injection LO = 18.95 GHz
Figure 115. Free Running Phase Noise vs. Offset Frequency at Various
VCO Frequencies, TA = 25°C
Rev. A | Page 34 of 61
Data Sheet
ADMV4420
RETURN LOSS AND ISOLATION
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+85°C
+85°C
+25°C
–40°C
+25°C
–40°C
–5
–10
–15
–20
–25
–30
–35
FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 116. RF Return Loss vs. Frequency at Various Temperatures,
LO = 18.95 GHz
Figure 119. LO to IF Leakage vs. LO Frequency at Various Temperatures for
Low-Side Injection LO, IF = 900 MHz
0
0
–10
–20
–30
–40
–50
–60
+85°C
–2
+25°C
–40°C
–4
–6
–8
–70
–80
+85°C
+25°C
–40°C
–10
–90
–100
–12
16.95 17.59 18.23 18.86 19.50 20.14 20.78 21.41 22.05
0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00
RF FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 120. RF to IF Leakage vs. RF Frequency at Various Temperatures for
LO = 21.15 GHz
Figure 117. IF Return Loss vs. Frequency at Various Temperatures,
LO = 18.95 GHz, Based on 75 Ω Output System
0
+85°C
+25°C
–40°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
LO FREQUENCY (GHz)
Figure 118. LO to RF Leakage vs. LO Frequency at Various Temperatures for
Low-Side Injection LO, IF = 900 MHz
Rev. A | Page 35 of 61
ADMV4420
Data Sheet
Downconverter Spurious Outputs
SPURIOUS AND HARMONICS PERFORMANCE
Mixer spurious products are measured in dBc from the IF
output power level, unless otherwise specified. Trace and
connector losses are de-embedded. N/A means not applicable.
LO Harmonics
All values are in dBm and are measured at the IF output. Trace
and connector losses are de-embedded.
RF = 19.85 GHz, LO = 18.95 GHz, IF = 0.9 GHz, RF power =
−40 dBm. Spur frequencies are the absolute value of (M × RF) +
(N × LO/2)
Table 5. LO Harmonics at IF Output
LO Harmonics (dBm)
LO Frequency (GHz) 0.25
0.5
1
1.5
2
N × LO
16.75
18.95
21.15
−110
−113
−111
−49
−41
−34
−58
−45
−58
−71
−63
−85
−66
−62
−69
0
1
2
3
4
−95
−78
N/A
−78
−95
−99
−77
−46
−98
−88
−101
0
−91
−81
−65
−88
N/A
−37
−90
−56
N/A
N/A
−2
−1
0
Reference Input (REFIN) Harmonics
−50
−80
N/A
M × RF
All values are in dBm and measured at the IF output. Trace and
connector losses are de-embedded. Reference frequency is at
50 MHz.
+1
+2
RF = 18.05 GHz, LO = 18.95 GHz, IF = 0.9 GHz, RF power =
−40 dBm. Spur frequencies are the absolute value of (M × RF) +
(N × LO/2).
Table 6. REFIN Harmonics at the IF Output
REFIN
REFIN Harmonics (dBm)
Frequency
(MHz)
N × LO
1
2
3
4
5
6
7
8
0
1
2
3
4
50
−78 −46 −60 −47 −57 −56 −61 −59
−77
−95
N/A
−77
−95
−70
−98
−45
−98
−89
0
−82
−96
−64
−89
N/A
−87
−41
−55
N/A
N/A
−2
−1
0
IF Harmonics
−103
−49
−93
N/A
All values are in dBm and are measured at the IF output. Trace
and connector losses are de-embedded. The downconverted IF
frequency is at 900 MHz.
M × RF
+1
+2
Table 7. IF Harmonics at the IF Output
IF Harmonics (dBm)
IF Frequency (MHz)
1
2
3
4
5
900
−7
−42
−58
−89
−90
Rev. A | Page 36 of 61
Data Sheet
ADMV4420
THEORY OF OPERATION
REFERENCE INPUT STAGE
REFERENCE DOUBLER, R COUNTER, AND RDIV2
The reference input stage is shown in Figure 121 and employs a
differentially excited, 50 MHz crystal oscillator. Alternatively,
the reference input can be driven by an external singled-ended
50 MHz source. Use the REF_IN_MODE bit (Register 0x20E,
Bit 1) to select the input configuration. To select crystal
oscillator mode, set this bit to 0 to close the SW1 switch and
open the SW2 switch. To select single-ended mode, set this bit
to 1 to close the SW2 switch and open the SW1 switch.
Following the reference input stage as shown in Figure 121,
there is an internal reference multiply by 2 block (×2 doubler)
that allows generation of higher phase frequency detector
frequencies (fPFD). A higher fPFD is useful for improving overall
system phase noise performance. Typically, doubling the fPFD
improves the inband phase noise performance by up to
3 dBc/Hz. Use the EN_REF_X2 bit (Register 0x20E, Bit 2) to
enable the reference doubler, which toggles the SW3 switch, as
shown in Figure 121.
The selection of a crystal oscillator must be such that the
electrical series resistance (ESR) and the load capacitance are
well defined. For worst case demonstration purposes, the
crystal oscillator selected for the evaluation board uses a
maximum ESR of 100 Ω. To ensure the crystal oscillation
startup over all temperature and process variations, a maximum
ESR of 40 Ω is recommended. The nominal crystal load
capacitance (CLOAD) = 10 pF, which is computed from series
combination of the C5 and C6 capacitors. It is recommended to
keep CLOAD between 8 pF and 12 pF. Additionally, ensure that
C21 is not installed for crystal oscillator mode, as this can
impact capacitive loading on the crystal, which can in turn
prevent the oscillation from starting up.
Following the reference doubler block, there are two frequency
dividers: a 10-bit R counter (1 to 1023 allowed) and a divide
by 2 block. These dividers allow the input reference frequency
(fREF) to be divided down to produce lower fPFD, which helps to
minimize fractional-N integer boundary spurs at the output.
The R counter is set using the R_DIV bits in Register 0x20C
and Register 0x20D. If the R_DIV = 1, the SW4 switch is in the
position shown in Figure 121. Otherwise, the SW4 switch
toggles to use the R counter.
The reference divide by 2 block is enabled by using the RDIV2_
SEL bit (Register 0x20E, Bit 0), which toggles the SW5 switch,
as shown in Figure 121.
×2
DOUBLER
10-BIT
R COUNTER
SW1
TO
PFD
÷2
SW3
SW4
SW5
SW2
XTAL2/NC
C6
REF/XTAL1
C21
Y1
EXTERNAL
REFERENCE
R1
C5
Figure 121. Reference Input Path Block Diagram
Rev. A | Page 37 of 61
ADMV4420
Data Sheet
The N counter value is defined as:
FRAC fLO
N COUNTER
The N counter allows a division ratio in the PLL feedback path
from the VCO. Note that the VCO signal is multiplied by 2 to
achieve the LO frequency at the double balanced mixer. The
division ratio is determined using the integer-N (INT),
fractional-N (FRAC), and modulus (MOD) values that this
counter comprises. The applicable registers for setting the INT,
FRAC, and MOD values are Register 0x200 to Register 0x20A.
fVCO
N = INT +
=
=
(3)
MOD 2 fPFD fPFD
where:
INT is the 16-bit integer value (75 to 65,535).
FRAC is the numerator of the 24-bit primary modulus value
(0 to 16,777,215).
MOD is the denominator of the 24-bit primary modulus value
(1 to 16,777,215).
N = INT + FRAC/MOD
TO PFD
To obtain the INT portion of the N counter value, round down
using the mathematical floor function,
FROM VCO
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT = FLOOR(N)
(4)
where FLOOR is the mathematical floor function.
INT
VALUE
MOD
VALUE
FRAC
VALUE
To determine the value of the MOD parameter, a channel
spacing step size (fCHSP) and the fPFD must be selected first.
The MOD parameter is then computed with the fPFD and the
greatest common denominator (GCD),
Figure 122. N Counter Functional Diagram
INT, FRAC, MOD, AND REFERENCE PATH
RELATIONSHIP
fPFD
MOD =
(5)
(6)
GCD( fCHSP , fPFD
)
The INT, FRAC, and MOD values, in conjunction with the
reference path, make it possible to generate VCO frequencies
The FRAC value can be computed for a given an N counter
value, INT value, and MOD value,
spaced by fractions of the fPFD
.
FRAC = FLOOR(MOD × (N –INT))
The fPFD can be calculated from the reference frequency (fREF
)
and the reference path configuration parameters,
INTEGER-N MODE
When the FRAC value is equal to zero, the synthesizer operates
in integer-N mode.
1 + D
R ×(1 + T)
fPFD = fREF
where:
×
(1)
PHASE FREQUENCY DETECTOR AND CHARGE
PUMP
D is the reference doubler bit (0 or 1).
R is the reference divide ratio of the binary, 10-bit
programmable counter (1 to 1023).
The PFD takes inputs from the R counter and N counter to
produce an output that is proportional to the phase and
frequency differences between them. This proportional
information is then output to a charge pump (CP) circuit that
generates current to drive an external loop filter, which is then
used to appropriately increase or decrease the VTUNE tuning
voltage.
T is the reference divide by 2 bit (0 or 1).
The VCO frequency (fVCO) is calculated with the following
equation:
fLO
2
fVCO
=
= fPFD × N
(2)
Figure 123 shows a simplified schematic of the PFD and CP.
Note that the PFD includes a fixed delay element, which is used
to ensure there is no dead zone in the PFD transfer function for
consistent reference spur levels.
where:
LO is the frequency of the LO driving the mixer.
N is the desired value of the N counter.
f
Rev. A | Page 38 of 61
Data Sheet
ADMV4420
UP
To change the fPFD, if no change has been made to the existing
loop filter components, it is recommended to scale the ICP using
the following equation:
HIGH
D1
Q1
U1
CLR1
+IN
ICP(DEFAULT ) × fPFD(DEFAULT )
1.25 mA × 50 MHz
(8)
ICP(NEW )
=
=
CHARGE
PUMP
CPOUT
U3
DELAY
fPFD(NEW )
fPFD(NEW )
where:
CLR2
D2 Q2
I
I
CP(NEW) is the new desired ICP.
CP(DEFAULT) is the default ICP.
DOWN
HIGH
U2
fPFD(DEFAULT) is the default fPFD
.
–IN
fPFD(NEW) is the new desired fPFD.
Figure 123. PFD and CP Simplified Schematic
When ICP(NEW) is obtained, the CP_CURRENT value in
Register 0x22E can be updated using the round function,
LOOP FILTER
Defining a loop filter for a PLL is dependent on several dynamics,
such as the PFD frequency, the N counter value, the tuning
sensitivity characteristics (kVCO) of the VCO, and the selected
CP current. A higher fPFD has the advantage of lowering inband
phase noise performance at the expense of integer boundary spur
levels when operating in fractional-N mode. Consequently, a
lower fPFD can allow the PLL to operate in integer-N mode,
which can eliminate integer boundary spurs at the expense of
higher inband phase noise performance. Given the trade-offs,
care must be taken with frequency planning and fPFD selection
to ensure the appropriate inband phase noise performance is
met with acceptable spur levels for the end application.
ICP(NEW)
312.5 μA
(9)
CP _CURRENT = ROUND
−1
where ROUND is the mathematical round function.
BLEED CURRENT (CP_BLEED) SETUP
The charge pump includes a binary scaled bleed current (IBLEED),
which is set by using the CP_BLEED value in Register 0x22F.
The bleed current introduces a slight phase offset in the PFD to
improve integer boundary spurs when operating in fractional-N
mode.
Generally, the bleed current follows Equation 10 and provides a
value that can be applicable for most applications, but there can
be additional spur level improvement by empirically
determining the appropriate bleed current value from actual
measurements for the intended application. The applicable
range is 0 µA to 956.25 µA, with 3.75 µA steps.
The loop filter, as implemented in the ADMV4420-EVALZ
evaluation board, is a third-order passive filter, as shown in
Figure 124. The filter is designed with the following simulation
input parameters: fPFD = 50 MHz, kVCO = 80 MHz/V, f VCO = 9.4 GHz
and ICP = 1.25 mA. The resulting loop filter bandwidth and
phase margin are 60 kHz and 45°, respectively.
4 × ICP
IBLEED = CP _ BLEED × 3.75 μA =
(10)
For additional guidance with loop filter simulations on the
ADMV4420, contact Analog Devices, Inc., for technical
support.
N
where CP_BLEED is an integer value (0 to 255).
When IBLEED is obtained, the CP_BLEED value in Register 0x22F
can be updated using the round function,
R2
R3
1.5kΩ
0Ω
CPOUT
VTUNE
R1
680Ω
IBLEED
3.75 μA
C1
470pF
C2
6.8nF
C3
220pF
C2
DNI
(11)
CP _ BLEED = ROUND
Figure 124. Recommended Loop Filter Schematic
where IBLEED is the desired charge pump bleed current.
CP CURRENT SETUP
MUXOUT
For a specifically designed loop filter, the CP current (ICP) must
be set by adjusting the CP_CURRENT value in Register 0x22E.
The on-chip multiplexer output (MUXOUT) allows access to
various internal signals, in addition to providing a digital lock
detect function. A representative diagram is shown in
Figure 125. The state of the MUXOUT pin is determined from
the PLL_MUX_SEL value in Register 0x213. See Table 31 for
full details.
The CP current follows the equation,
ICP = (CP_CURRENT + 1) × 312.5 μA
(7)
where CP_CURRENT is an integer value (0 to 15).
Note that the default value of CP_CURRENT is 3, which yields
a current of 1.25 mA. The applicable range is 312.5 µA to 5 mA,
with 312.5 µA steps.
Rev. A | Page 39 of 61
ADMV4420
Data Sheet
on the falling edge of SCLK. The output logic level for a read
cycle is 3.3 V. The output drivers of the SDO are enabled after
the last rising edge of SCLK of the instruction cycle and remain
active until the end of the read cycle. In a read operation, when
OUTPUT LOW
DIGITAL LOCK DETECT
R COUNTER/2
MUX
MUXOUT
N COUNTER/2
OUTPUT HIGH
is deasserted, SDO returns to high impedance until the next
CS
read transaction. The
is active low and must be deasserted at
CS
the end of the write or read sequence.
An active low input on starts and gates a communication
Figure 125. Multiplexer Output Diagram
DIGITAL LOCK DETECT
CS
pin allows more than one device to be used on the
The digital lock detect function that is output on the MUXOUT
pin has two adjustable settings in Register 0x214. LD_BIAS
adjusts an internal precision window and LD_COUNT adjusts
the consecutive cycle count to declare PLL lock. It is recom-
mended to keep the 20 µA and 8192 PFD cycle count factory
settings. For special applications, contact Analog Devices
technical support for guidance on adjusting these settings.
cycle. The
CS
same serial communications lines. The SDO pin goes to a high
impedance state when the input is high. During the
CS
communication cycle, the chip select must stay low.
The SPI communications protocol follows the Analog Devices
SPI standard. For more information, see the ADI-SPI Serial
Control Interface Standard (Rev 1.0).
ENABLES
VCO AUTOCALIBRATION AND AUTOMATIC LEVEL
CONTROL
Register 0x103 has individual circuit block enables. Setting this
register to 0 disables all circuit blocks, resulting in approximately
80 mW of power dissipation. For nominal operation, keep all
enables in this register set to 1 (register value of 0x6F). Note that
Bit 4 and Bit 7 are reserved and must be set to 0.
The multicore VCO uses an internal autocalibration
(AUTOCAL) and automatic level control (ALC) routine that
optimizes the VCO settings for a particular frequency and
allows the PLL to lock in approximately 400 µs after the lower
portion of the N counter integer value (INT_L) has been
programmed. For nominal applications, maintain the
AUTOCAL and ALC default values in the register map (see
Table 8).
IF OUTPUT—EXTERNAL INDUCTOR/BIASING
The IF amplifier output is an open-collector configuration and
requires an external biasing inductor pulled up to the
VPOS4_IF supply. The recommended value of the inductor is
approximately 50 nH, which requires a current carrying
capability of at least 150 mA. Because this configuration is
dc-coupled, it is necessary to place a series capacitor between
the IF output and the next stage in the end application. A
recommended minimum value for the series capacitor is 1 nF.
PROGRAMMING SEQUENCE
A number of double buffered registers that take effect only after
a write to the lower portion of the N counter integer value
(INT_L). The INT_L register applies any changes to these
double registers and initiate the autocalibration routine.
Additionally, it is recommended to allow 16 SPI clock cycles
after writing to the INT_L register.
SPI CONFIGURATION
The SPI of the ADMV4420 allows configuration of the device
for specific functions or operations via the 4-pin SPI port. This
interface provides users with added flexibility and customization.
The following describes the recommended programming
sequence:
The SPI consists of four control lines: SCLK, SDI, SDO, and
.
CS
The ADMV4420 protocol consists of a write/read bit followed
by 15 register address bits and 8 data bits. The address field and
data field are organized MSB first and end with the LSB.
1. Program the CP_CURRENT register (Register 0x22E).
2. Program the FRAC_H register (Register 0x204).
3. Program the FRAC_M register (Register 0x203).
4. Program the FRAC_L register (Register 0x202).
5. Program the MOD_H register (Register 0x20A).
6. Program the MOD_M register (Register 0x209).
7. Program the MOD_L register (Register 0x208).
8. Program the INT_H register (Register 0x201).
9. Program the INT_L register (Register 0x200).
10. Program 16 SPI clock cycles.
For a write operation, set the MSB to 0, and for a read
operation, set the MSB to 1. The write cycle sampling must be
done on the rising edge of SCLK. The 24 bits of the serial write
address and data are shifted in on the SDI control line, MSB to
LSB. The ADMV4420 input logic level for the write cycle
supports a 3.3 V interface.
For a read cycle, the R/W bit and the 15 bits of address shift in
on the rising edge of SCLK on the SDI control line. Then, 8 bits
of serial read data shift out on the SDO control line, MSB first,
Rev. A | Page 40 of 61
Data Sheet
ADMV4420
CONTROL REGISTERS
Table 8. Control Register Map
Register
Address
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x000
ADI_SPI_
[7:0]
SOFTRESET_
LSB_
ENDIAN_
SDOACTIVE_
SDOACTIVE
ENDIAN
LSB_FIRST
SOFTRESET
0x00
R/W
CONFIG_1
FIRST_
0x001
ADI_SPI_
CONFIG_2
[7:0]
SINGLE_
INSTRUCTION
CSB_
STALL
MASTER_
SLAVE_RB
RESERVED
MASTER_SLAVE_
TRANSFER
0x00
R/W
0x003
0x004
CHIPTYPE
[7:0]
[7:0]
CHIPTYPE
0x01
0x03
R
R
PRODUCT_
ID_L
PRODUCT_ID_L
0x005
PRODUCT_
ID_H
[7:0]
PRODUCT_ID_H
0x00
R
0x00A
0x00B
0x103
0x108
0x200
0x201
0x202
0x203
0x204
0x208
0x209
0x20A
0x20C
0x20D
0x20E
SCRATCHPAD
SPI_REV
ENABLES
SDO_LEVEL
INT_L
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
SCRATCHPAD
SPI_REV
0x00
0x00
0x6F
0x05
0xA7
0x00
0x02
0x00
0x00
0x04
0x00
0x00
0x01
0x00
0x00
R/W
R
RESERVED
EN_PLL
EN_LO
RESERVED
EN_VCO
EN_IFAMP
EN_MIXER
EN_LNA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESERVED
SDO_LEVEL
RESERVED
INT[7:0]
INT[15:8]
INT_H
FRAC_L
FRAC[7:0]
FRAC[15:8]
FRAC[23:16]
MOD[7:0]
MOD[15:8]
MOD[23:16]
R_DIV[7:0]
FRAC_M
FRAC_H
MOD_L
MOD_M
MOD_H
R_DIV_L
R_DIV_H
REFERENCE
RESERVED
R_DIV[9:8]
RDIV2_SEL
RESERVED
END_REF_
X2
REF_IN_
MODE
0x211
0x212
0x213
0x214
0x215
0x216
0x217
VCO_DATA_
READBACK1
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
VCO_DATA_READBACK[7:0]
0x00
0x00
0x01
0x98
0x00
0x00
0x01
R
VCO_DATA_
READBACK2
RESERVED
VCO_DATA_READBACK[10:8]
RESERVED
R
PLL_
MUX_SEL
PLL_MUX_SEL
LD_COUNT
R/W
R/W
R/W
R/W
R/W
LOCK_
DETECT
LD_BIAS
VCO_BAND_
SELECT
VCO_BAND_SELECT
VCO_ALC_
TIMEOUT
RESERVED
VCO_ALC_TIMEOUT
VCO_BIAS_ADJUST
RESERVED
VCO_
MANUAL
RESERVED
RESERVED
VCO_CORE_SELECT
EN_ALC
0x219
0x21C
ALC
[7:0]
[7:0]
0x13
0x90
R/W
R/W
VCO_
VCO_TIMEOUT[7:0]
TIMEOUT1
0x21D
0x21E
0x21F
0x226
VCO_
TIMEOUT2
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
VCO_TIMEOUT[9:8]
0x01
0x4B
0x18
0x02
R/W
R/W
R/W
R/W
VCO_BAND_
DIV
VCO_BAND_DIV
VCO_
READBACK_SEL
RESERVED
RESERVED
RESERVED
VCO_READBACK_SEL
AUTOCAL
EN_
RESERVED
AUTOCAL
0x22C
2x22D
0x22E
0x22F
CP_STATE
[7:0]
[7:0]
[7:0]
[7:0]
CP_STATE
EN_BLEED
0x07
0x01
0x03
0x0C
R/W
R/W
R/W
R/W
CP_BLEED_EN
CP_CURRENT
CP_BLEED
RESERVED
RESERVED
CP_CURRENT
BICP
Rev. A | Page 41 of 61
ADMV4420
Data Sheet
REGISTER DETAILS
ADDRESS 0x000, RESET: 0x00, NAME: ADI_SPI_CONFIG_1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SOFTRESET_ (R/W)
SoftReset
[0] SOFTRESET (R/W)
SoftReset
0: Reset Asserted.
1: Reset not Asserted.
0: Reset Asserted.
1: Reset not Asserted.
[6] LSB_FIRST_ (R/W)
LSB_First
[1] LSB_FIRST (R/W)
LSB_First
0: LSB First.
1: MSB First.
0: LSB First.
1: MSB First.
[5] ENDIAN_ (R/W)
Endian
[2] ENDIAN (R/W)
Endian
0: Little Endian.
1: Big Endian.
0: Little Endian.
1: Big Endian.
[4] SDOACTIVE_ (R/W)
SDOActive
[3] SDOACTIVE (R/W)
SDOActive
0: SDO Inactive.
1: SDO Active.
0: SDO Inactive.
1: SDO Active.
Table 9. ADI_SPI_CONFIG1 Bit Descriptions
Bit
Bit Name
Description
Reset
Access
7
SOFTRESET_
Soft reset bit
0x0
R/W
0: Reset asserted
1: Reset not asserted
LSB first bit
0: LSB first
6
5
4
3
2
1
0
LSB_FIRST_
ENDIAN_
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1: MSB first
Endian bit
0: Little endian
1: Big endian
SDO active bit
0: SDO inactive
1: SDO active
SDO active bit
0: SDO inactive
1: SDO active
Endian bit
0: Little endian
1: Big endian
LSB first bit
0: LSB first
1: MSB first
SDOACTIVE_
SDOACTIVE
ENDIAN
LSB_FIRST
SOFTRESET
Soft reset
0: Reset asserted
1: Reset not asserted
Rev. A | Page 42 of 61
Data Sheet
ADMV4420
ADDRESS 0x001, RESET: 0x00, NAME: ADI_SPI_CONFIG_2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SINGLE_INSTRUCTION (R/W)
Single Instruction
[0] MASTER_SLAVE_TRANSFER (R/W)
Master Slave Transfer
0: Enable Streaming.
1: Disable Streaming Regardless of
CSB.
[4:1] RESERVED
[6] CSB_STALL (R/W)
CSB Stall
[5] MASTER_SLAVE_RB (R/W)
Master Slave RB
Table 10. ADI_SPI_CONFIG_2 Bit Descriptions
Bit
Bit Name
Description1
Reset
Access
7
SINGLE_INSTRUCTION
Single instruction bit
0: Enable streaming
0x0
R/W
1: Disable streaming regardless of CSB
CSB stall bit
6
CSB_STALL
0x0
0x0
0x0
0x0
R/W
R/W
R
5
MASTER_SLAVE_RB
RESERVED
Master slave readback bit
Reserved
[4:1]
0
MASTER_SLAVE_TRANSFER
Master slave transfer bit
R/W
1
CS
Note that corresponds to CSB.
Rev. A | Page 43 of 61
ADMV4420
Data Sheet
ADDRESS 0x003, RESET: 0x01, NAME: CHIPTYPE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:0] CHIPTYPE (R)
Chip Type (Read Only)
Table 11. CHIPTYPE Bit Descriptions
Bits
Bit Name
Description
Chip type bits, read only.
Reset
Access
[7:0]
CHIPTYPE
0x01
R
ADDRESS 0x004, RESET: 0x03, NAME: PRODUCT_ID_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7:0] PRODUCT_ID_L (R)
Product_ID_L, Lower 8 Bits
Table 12. PRODUCT_ID_L Bit Descriptions
Bits
Bit Name
Description
Reset
0x03
Access
[7:0]
PRODUCT_ID_L
PRODUCT_ID_L bits, lower 8 bits.
R
ADDRESS 0x005, RESET: 0x00, NAME: PRODUCT_ID_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PRODUCT_ID_H (R)
Product_ID_H, Higher 8 Bits
Table 13. PRODUCT_ID_H Bit Descriptions
Bits
Bit Name
Description
Reset
0x00
Access
[7:0]
PRODUCT_ID_H
PRODUCT_ID_H bits, higher 8 bits.
R
ADDRESS 0x00A, RESET: 0x00, NAME: SCRATCHPAD
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] SCRATCHPAD (R/W)
ScratchPad
Table 14. SCRATCHPAD Bit Descriptions
Bits
Bit Name
Description
Scratch pad bits
Reset
Access
R/W
[7:0]
SCRATCHPAD
0x00
ADDRESS 0x00B, RESET: 0x00, NAME: SPI_REV
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] SPI_REV (R)
SPI Register Map Revision
Table 15. SPI_REV Bit Descriptions
Bits
Bit Name
Description
SPI register map revision bits
Reset
0x00
Access
[7:0]
SPI_REV
R
Rev. A | Page 44 of 61
Data Sheet
ADMV4420
ADDRESS 0x103, RESET: 0x6F, NAME: ENABLES
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
1
[7] RESERVED
[0] EN_LNA (R/W)
LNA Enable
0: Power Down LNA.
1: Power Up LNA.
[6] EN_PLL (R/W)
PLL Enable
0: Power Down PLL.
1: Power Up PLL.
[1] EN_MIXER (R/W)
Mixer Enable
0: Power Down Mixer.
1: Power Up Mixer.
[5] EN_LO (R/W)
LO Enable
0: Power Down LO.
1: Power Up LO.
[2] EN_IFAMP (R/W)
IF Amp Enable
0: Power Down IF Amplifier.
1: Power Up IF Amplifier.
[4] RESERVED
[3] EN_VCO (R/W)
VCO Enable
0: Power Down VCO.
1: Power Up VCO.
Table 16. ENABLES Bit Descriptions
Bits
Bit Name
RESERVED
EN_PLL
Description
Reset
0x0
Access
R
7
Reserved
6
PLL enable bit
0x1
R/W
0: Power down PLL
1: Power up PLL
LO enable bit
5
EN_LO
0x1
R/W
0: Power down LO
1: Power up LO
Reserved
4
3
RESERVED
EN_VCO
0x0
0x1
R
VCO enable bit
R/W
0: Power down VCO
1: Power up VCO
2
1
0
EN_IFAMP
EN_MIXER
EN_LNA
IF amplifier enable bit
0x1
0x1
0x1
R/W
R/W
R/W
0: Power down IF amplifier
1: Power up IF amplifier
Mixer enable bit
0: Power down mixer
1: Power up mixer
LNA enable bit
0: Power down LNA
1: Power up LNA
ADDRESS 0x108, RESET: 0x05, NAME: SDO_LEVEL
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
1
[7:3] RESERVED
[1:0] RESERVED
[2] SDO_LEVEL (R/W)
SPI Supply Control
0: 1.8V Read Back.
1: 3.3V Read Back.
Table 17. SDO_LEVEL Bit Descriptions
Bits
[7:3]
2
Bit Name
RESERVED
SDO_LEVEL
Description
Reset
Access
R
Reserved
0x0
0x1
SPI supply control bit
0: 1.8 V readback
1: 3.3 V readback
Reserved
R/W
[1:0]
RESERVED
0x1
R/W
Rev. A | Page 45 of 61
ADMV4420
Data Sheet
ADDRESS 0x200, RESET: 0xA7, NAME: INT_L
7
6
5
4
3
2
1
0
1
0
1
0
0
1
1
1
[7:0] INT[7:0] (R/W)
Integer-N Word (16-Bit)
Table 18. INT_L Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
INT[7:0]
Integer-N word (16-bit)
0xA7
R/W
ADDRESS 0x201, RESET: 0x00, NAME: INT_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] INT[15:8] (R/W)
Integer-N Word (16-Bit)
Table 19. INT_H Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
INT[15:8]
Integer-N word (16-bit)
0x0
R/W
ADDRESS 0x202, RESET: 0x02, NAME: FRAC_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
[7:0] FRAC[7:0] (R/W)
Fractional-N Word (24-Bit)
Table 20. FRAC_L Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
FRAC[7:0]
Fractional-N word (24-bit)
0x2
R/W
ADDRESS 0x203, RESET: 0x00, NAME: FRAC_M
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] FRAC[15:8] (R/W)
Fractional-N Word (24-Bit)
Table 21. FRAC_M Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
FRAC[15:8]
Fractional-N word (24-bit)
0x0
R/W
ADDRESS 0x204, RESET: 0x00, NAME: FRAC_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] FRAC[23:16] (R/W)
Fractional-N Word (24-Bit)
Table 22. FRAC_H Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
FRAC[23:16]
Fractional-N word (24-bit)
0x0
R/W
Rev. A | Page 46 of 61
Data Sheet
ADMV4420
ADDRESS 0x208, RESET: 0x04, NAME: MOD_L
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
[7:0] MOD[7:0] (R/W)
Fractional-N Modulus (24-Bit)
Table 23. MOD_L Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
MOD[7:0]
Fractional-N modulus (24-bit)
0x4
R/W
ADDRESS 0x209, RESET: 0x00, NAME: MOD_M
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] MOD[15:8] (R/W)
Fractional-N Modulus (24-Bit)
Table 24. MOD_M Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
MOD[15:8]
Fractional-N modulus (24-bit)
0x0
R/W
ADDRESS 0x20A, RESET: 0x00, NAME: MOD_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] MOD[23:16] (R/W)
Fractional-N Modulus (24-Bit)
Table 25. MOD_H Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
MOD[23:16]
Fractional-N modulus (24-bit)
0x0
R/W
Rev. A | Page 47 of 61
ADMV4420
Data Sheet
ADDRESS 0x20C, RESET: 0x01, NAME: R_DIV_L
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:0] R_DIV[7:0] (R/W)
R-Divider Word (10-Bit)
Table 26. R_DIV_L Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
R_DIV[7:0]
R divider word (10-bit)
0x1
R/W
ADDRESS 0x20D, RESET: 0x00, NAME: R_DIV_H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:2] RESERVED
[1:0] R_DIV[9:8] (R/W)
R-Divider Word (10-Bit)
Table 27. R_DIV_H Bit Descriptions
Bits
[7:2]
[1:0]
Bit Name
RESERVED
R_DIV[9:8]
Description
Reset
0x0
Access
R
Reserved
R divider word (10-bit)
0x0
R/W
ADDRESS 0x20E, RESET: 0x00, NAME: REFERENCE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:3] RESERVED
[2] EN_REF_X2 (R/W)
Reference Doubler Enable
0: Disable.
[0] RDIV2_SEL (R/W)
Reference Divide by 2
0: Reference Divide by 2 Disabled.
1: Reference Divide by 2 Enabled.
1: Enable.
[1] REF_IN_MODE (R/W)
Reference Input Mode
0: XTAL Oscillator Mode.
1: Single-Ended Mode.
Table 28. REFERENCE Bit Descriptions
Bits
[7:3]
2
Bit Name
RESERVED
EN_REF_X2
Description
Reset
0x0
Access
R
Reserved
Reference doubler enable bit
0: Disable
0x0
R/W
1: Enable
1
0
REF_IN_MODE
RDIV2_SEL
Reference input mode bit
0: Crystal (XTAL) oscillator mode
1: Single-ended mode
0x0
0x0
R/W
R/W
Reference divide by 2 bit
0: Reference divide by 2 disabled
1: Reference divide by 2 enabled
Rev. A | Page 48 of 61
Data Sheet
ADMV4420
ADDRESS 0x211, RESET: 0x00, NAME: VCO_DATA_READBACK1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VCO_DATA_READBACK[7:0] (R)
VCO Data Readback
Table 29. VCO_DATA_READBACK1 Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
VCO_DATA_READBACK[7:0] VCO data readback
0x0
R
ADDRESS 0x212, RESET: 0x00, NAME: VCO_DATA_READBACK2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:3] RESERVED
[2:0] VCO_DATA_READBACK[10:8] (R)
VCO Data Readback
Table 30. VCO_DATA_READBACK2 Bit Descriptions
Bits
[7:3]
[2:0]
Bit Name
Description
Reset
0x0
Access
RESERVED
Reserved
R
R
VCO_DATA_READBACK[10:8] VCO data readback bits
0x0
Rev. A | Page 49 of 61
ADMV4420
Data Sheet
ADDRESS 0x213, RESET: 0x01, NAME: PLL_MUX_SEL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:0] PLL_MUX_SEL (R/W)
PLL Mux Select
00000000: Output Logic Low.
00000001: Digital Lock Detect.
00000100: RDiv-by-2 to Mux Out, Frequency =
REFIN/(2 x R)
00000101: NDiv-by-2 to Mux Out, Frequency =
VCO/(2 x N)
00001000: Output Logic High.
Table 31. PLL_MUX_SEL Bit Descriptions
Bits
Bit Name
Description
Reset
0x1
Access
[7:0]
PLL_MUX_SEL
PLL mux select bits
R/W
00000000: Output logic low
00000001: Digital lock detect
00000100: R divide by 2 to mux out, frequency = REFIN /2 × R)
00000101: N divide by 2 to mux out, frequency = VCO/(2 × N)
00001000: Output logic high
ADDRESS 0x214, RESET: 0x98, NAME: LOCK_DETECT
7
6
5
4
3
2
1
0
1
0
0
1
1
0
0
0
[7:6] LD_BIAS (R/W)
Lock Detect Bias
00: 40uA.
[2:0] RESERVED
01: 30uA.
10: 20uA.
11: 10uA.
[5:3] LD_COUNT (R/W)
Lock Detect Count
000: 1024 Consecutive PFD Cycles to
Declare Lock.
001: 2048 Consecutive PFD Cycles to
Declare Lock.
010: 4096 Consecutive PFD Cycles to
Declare Lock.
011: 8192 Consecutive PFD Cycles to
Declare Lock.
Table 32. LOCK_DETECT Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:6]
LD_BIAS
Lock detect bias bits
00: 40 μA
01: 30 μA
10: 20 μA
11: 10 μA
0x2
0x3
0x0
R/W
R/W
R/W
[5:3]
[2:0]
LD_COUNT
RESERVED
Lock detect count bits
000: 1024 consecutive PFD cycles to declare lock
001: 2048 consecutive PFD cycles to declare lock
010: 4096 consecutive PFD cycles to declare lock
011: 8192 consecutive PFD cycles to declare lock
Reserved
Rev. A | Page 50 of 61
Data Sheet
ADMV4420
ADDRESS 0x215, RESET: 0x00, NAME: VCO_BAND_SELECT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VCO_BAND_SELECT (R/W)
Manually Programmed VCO Band
Table 33. VCO_BAND_SELECT Bit Descriptions
Bits
Bit Name
Description
Reset
Access
[7:0]
VCO_BAND_SELECT Manually programmed VCO band
0x0
R/W
ADDRESS 0x216, RESET: 0x00, NAME: VCO_ALC_TIMEOUT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[3:0] VCO_ALC_TIMEOUT (R/W)
VCO ALC Timeout Divide
Table 34. VCO_ALC_TIMEOUT Bit Descriptions
Bits
[7:4]
[3:0]
Bit Name
Description
Reset
0x0
Access
R
RESERVED
Reserved
VCO_ALC_TIMEOUT
VCO ALC timeout divide
0x0
R/W
ADDRESS 0x217, RESET: 0x01, NAME: VCO_MANUAL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:6] RESERVED
[3:0] VCO_BIAS_ADJUST (R/W)
Manually Control VCO Bias
[5:4] VCO_CORE_SELECT (R/W)
Manually Control VCO Core
01: Core#1.
10: Core#2.
Table 35. VCO_MANUAL Bit Descriptions
Bits
[7:6]
[5:4]
Bit Name
Description
Reset
Access
RESERVED
Reserved
0x0
0x0
R
VCO_CORE_SELECT
Manual control of VCO core
01: Core 1
R/W
10: Core 2
[3:0]
VCO_BIAS_ADJUST
Manual control of VCO bias
0x1
R/W
ADDRESS 0x219, RESET: 0x13, NAME: ALC
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
1
[7:5] RESERVED
[3:0] RESERVED
[4] EN_ALC (R/W)
VCO ALC Enable
0: Disable.
1: Enable.
Table 36. ALC Bit Descriptions
Bits
[7:5]
4
Bit Name
RESERVED
EN_ACL
Description
Reset
0x0
Access
R
Reserved
VCO ALC enable bit
0: Disable
0x1
R/W
1: Enable
[3:0]
RESERVED
Reserved
0x3
R/W
Rev. A | Page 51 of 61
ADMV4420
Data Sheet
ADDRESS 0x21C, RESET: 0x90, NAME: VCO_TIMEOUT1
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
[7:0] VCO_TIMEOUT[7:0] (R/W)
Main VCO Calibration Timeout
Table 37. VCO_TIMEOUT1 Bit Descriptions
Bits
Bit Name
Description
Reset
0x90
Access
[7:0]
VCO_TIMEOUT[7:0] Main VCO calibration timeout
R/W
ADDRESS 0x21D, RESET: 0x01, NAME: VCO_TIMEOUT2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:2] RESERVED
[1:0] VCO_TIMEOUT[9:8] (R/W)
Main VCO Calibration Timeout
Table 38. VCO_TIMEOUT2 Bit Descriptions
Bits
[7:2]
[1:0]
Bit Name
Description
Reset
0x0
Access
RESERVED
Reserved
R
VCO_TIMEOUT[9:8]
Main VCO calibration timeout
0x1
R/W
ADDRESS 0x21E, RESET: 0x4B, NAME: VCO_BAND_DIV
7
6
5
4
3
2
1
0
0
1
0
0
1
0
1
1
[7:0] VCO_BAND_DIV (R/W)
VCO Band Select Divide
Table 39. VCO_BAND_DIV Bit Descriptions
Bits
[7:0]
Bit Name
VCO_BAND_DIV
Description
VCO band select divide
Reset
0x4B
Access
R/W
ADDRESS 0x21F, RESET: 0x18, NAME: VCO_READBACK_SEL
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
[7:3] RESERVED
[2:0] VCO_READBACK_SEL (R/W)
VCO Read Back Select
000: Read Back Checkered Board (Functionality
Test)
001: Read Back Core & Band.
011: Read Back Bias Code.
100: Read Back Core.
101: Read Back Low (Zeros)
Table 40. VCO_READBACK_SEL Bit Descriptions
Bits
[7:3]
[2:0]
Bit Name
Description
Reset
Access
RESERVED
Reserved
0x3
0x0
R
VCO_READBACK_SEL
VCO read back select
R/W
000: Read back checkered board (functionality test)
001: Read back core and band
011: Read back bias code
100: Read back core
101: Read back low (zeros)
Rev. A | Page 52 of 61
Data Sheet
ADMV4420
ADDRESS 0x226, RESET: 0x02, NAME: AUTOCAL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
[7:2] RESERVED
[0] RESERVED
[1] EN_AUTOCAL (R/W)
Enable VCO Auto Cal and Lock PLL
0: Disable.
1: Enable.
Table 41. AUTOCAL Bit Descriptions
Bits
[7:2]
1
Bit Name
RESERVED
EN_AUTOCAL
Description
Reserved
Reset
0x0
Access
R
Enable VCO autocalibration and lock PLL
0x1
R/W
0: Disable
1: Enable
Reserved
0
RESERVED
0x0
R
Rev. A | Page 53 of 61
ADMV4420
Data Sheet
ADDRESS 0x22C, RESET: 0x07, NAME: CP_STATE
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
[7:2] RESERVED
[1:0] CP_STATE (R/W)
Charge Pump State
0: Tri-State (Hi-Z)
1: Force Up.
2: Force Down.
3: Normal Operation.
Table 42. CP_STATE Bit Descriptions
Bits
[7:2]
[1:0]
Bit Name
RESERVED
CP_STATE
Description
Reset
0x1
Access
Reserved
R
Charge pump state
0: Tristate (high-Z)
1: Force up
0x3
R/W
2: Force down
3: Normal operation
ADDRESS 0x22D, RESET: 0x01, NAME: CP_BLEED_EN
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:1] RESERVED
[0] EN_BLEED (R/W)
Bleed CP Current Enable
0: Disable.
1: Enable.
Table 43. CP_BLEED_EN Bit Descriptions
Bits
[7:1]
0
Bit Name
RESERVED
EN_BLEED
Description
Reserved
Reset
0x0
Access
R
Bleed CP current enable
0: Disable
0x1
R/W
1: Enable
ADDRESS 0x22E, RESET: 0x03, NAME: CP_CURRENT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7:4] RESERVED
[3:0] CP_CURRENT (R/W)
Main Charge Pump Current
Table 44. CP_CURRENT Bit Descriptions
Bits
[7:4]
[3:0]
Bit Name
Description
Reset
0x0
Access
R
RESERVED
CP_CURRENT
Reserved
Main charge pump current bit
0x3
R/W
ADDRESS 0x22F, RESET: 0x0C, NAME: CP_BLEED
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
0
[7:0] BICP (R/W)
Binary Scaled Bleed Current
Table 45. CP_BLEED Bit Descriptions
Bits
Bit Name
Description
Binary scaled bleed current
Reset
0xC
Access
[7:0]
BICP
R/W
Rev. A | Page 54 of 61
Data Sheet
ADMV4420
APPLICATIONS INFORMATION
The ADMV4420-EVALZ evaluation board layout consists of
four layers. Layer 1 contains the charge pump, IF supplies
(VPOS3_CP and VPOS4_IF), and the multiplexer output signal
(MUXOUT) trace, which are routed together with the
peripheral component placements. Layer 2 is arranged to
provide the ground plane for the board. Layer 3 includes the
VCO (VPOS1_VCO) supply, the PLL (VPOS2_PLL) supply,
EVALUATION BOARD
The ADMV4420-EVALZ evaluation board can be used to
evaluate the performance of the ADMV4420. The top and cross
sectional layout views of the ADMV4420-EVALZ evaluation
board are shown in Figure 126 and Figure 127, respectively. The
RF transmission lines were designed using a coplanar waveguide
(CPWG) model with a line width (W) of 16 mil and 13 mil of
ground spacing for a characteristic impedance of 50Ω for the
RF input (RFIN) and the external reference input (REF/XTAL1).
The line width and ground spacing for the IF output (IFOUT)
are 9 mil and 15 mil, respectively. The PCB is made with Rogers
4350B dielectric material, which offers low loss performance,
and isola 370HR dielectric material, which achieves the
required thickness of the PCB.
and digital SPI control signal ( , SDI, SDO, and SCLK) traces,
CS
and Layer 4 includes the chip enable (ENBL0 and ENBL1) traces
on the bottom side of the board. Note that on the evaluation
board,
is indicated by CSB. Figure 128 to Figure 130 show
CS
the routing details of Layer 2 to Layer 4. For optimal RF and
thermal grounding place as many plated through vias as possible
around the RF transmission lines, underneath the exposed pad
and throughout the entire PCB (See Figure 128).
Figure 126. ADMV4420-EVALZ Evaluation Board Layout, Top View (Layer 1)
Rev. A | Page 55 of 61
ADMV4420
Data Sheet
W = 16mil FOR 50Ω W = 13mil FOR 50Ω
W = 9mil FOR 75Ω
W = 15mil FOR 75Ω
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
LAYER 1
10mil ROGERS 4350B
1oz Cu (1.4mil)
ISOLA 370HR
LAYER 2
1oz Cu (1.4mil) – POWER LINES
0.5oz Cu (0.7mil) – SIGNAL LINES
LAYER 3
LAYER 4
ISOLA 370HR
0.5oz Cu (0.7mil)
Figure 127. ADMV4420-EVALZ PCB, Cross Sectional View
Figure 128. ADMV4420-EVALZ Evaluation Board, Layer 2
Figure 129. ADMV4420-EVALZ Evaluation Board, Layer 3
Rev. A | Page 56 of 61
Data Sheet
ADMV4420
Figure 130. ADMV4420-EVALZ Evaluation Board, Layer 4 (Bottom Side)
Figure 126 shows the ADMV4420-EVALZ evaluation board
with component placement. The decoupling capacitors on the
LDO decoupling pin and power supply traces to minimize noise
effects. The schematic and Pb-free reflow solder profile of the
evaluation board are shown in and Figure 2 and Figure 132,
respectively.
There are two different options to apply an external reference
input to the ADMV4420, as shown in Figure 132. The required
configurations for these options are described in Table 46.
When using the Case 1 option, the external reference input is
applied through the J2 connector with a signal generator. When
using the Case 2 option, the external reference input is provided
by the crystal (Y1).
There are two options to power up the evaluation board. The
first option is to apply a 5 V supply to the VPOS1, VPOS2,
VPOS3, and VPOS4 test points for the VCO, PLL, CP, and IF
blocks (VPOS1_VCO, VPOS2_PLL, VPOS3_CP, and
VPOS4_IF pins) respectively, and connect a 0 V supply to one
of the GND1, GND2, or GND3 ground test points. In this
option, remove the R13, R14, R15, and R16 resistors from the
evaluation board. This option allows the user to monitor the
currents of each block separately.
A loop filter circuit generates the VCO control voltage (VTUNE)
by applying the CP current output of the ADMV4420 from the
charge pump output pin (CPOUT) to obtain the target LO
frequency. Figure 131 shows the recommended schematic and
Table 47 describes the loop filter components when the phase
frequency detector frequency is 50 MHz. Table 48 describes the
complete list of materials, which includes the loop filter
components. For details about the evaluation board, see the
ADMV4420-EVALZ user guide.
The second option to power up the board requires the power
supply to be applied through the VCC5P0 test point with the
appropriate ground connection. Only the total current of the
ADMV4420 can be monitored with this option. After powering
up the evaluation board, program the required digital settings
for the target configuration through the SDP-S controller board
by using the Analysis, Control, Evaluation (ACE) software,
which can be downloaded from the Analysis, Control,
Evaluation (ACE) product page. See the ADMV4420-EVALZ
user guide for details.
Table 46. External Reference Input Configurations
Option
Component Configuration
Case 1
Populate C21. Replace C6 with 1 nF capacitor.
Remove C5 and Y1.
Case 2 (Default) C5 = 20 pF, C6 = 20 pF. Do not populate C21.
Rev. A | Page 57 of 61
ADMV4420
Data Sheet
R5
R11
CPOUT
VTUNE
Table 47. Recommended Integer Mode Loop Filter
Components for Phase Frequency Detector = 50 MHz
1.5kΩ
0Ω
R4
680Ω
C24
470pF
C26
220pF
Component
Value
C25
C24
C25
C26
R4
R5
R11
470 pF (0402)
6800 pF (0402)
220 pF (0402)
680 Ω (0402)
1.5 kΩ (0402)
0 Ω (0402)
6800pF
AGND
Figure 131. Recommended Integer Mode Loop Filter Schematic
Table 48. Bill of Materials for ADMV4420-EVALZ
Reference Designator
Description
C1, C3, C14, C32, C33, C35
Power supply decoupling and LDO decoupling capacitor, 10 μF, 0603
Power supply decoupling and LDO decoupling capacitor, 10 pF, 0402
Crystal loading capacitors
C2, C10, C16, C18, C30
C5, C6
C7, C8, C11, C12, C13, C22, C27
C15, C19, C20, C23, C29
C4, C34
C9
C17, C21
C24
Power supply decoupling and LDO decoupling capacitor, 0.1 μF, 0402
Power supply decoupling and LDO decoupling capacitor, 100 pF, 0402)
Power supply decoupling and LDO decoupling capacitor, 10 μF, 0402
Power supply decoupling and LDO decoupling capacitor, 4.7 μF, 0402
AC coupling capacitor, 0.01 μF, 0402
Loop filter capacitor, 470 pF, 0402
C25
C26
Loop filter capacitor, 6800 pF, 0402
Loop filter capacitor, 220 pF, 0402
Test point, yellow
CS, ENBL0, ENBL1, MUXOUT, SCLK, SDI, SDO
DS1
LED, green
GND1, GND2, GND3
Test point, black
J1
RF connector, SRI, K type, female
J2
J3
J4
RF connector, subminiature version a (SMA), female
System demonstration platform (SDP) connector
RF connector, F type, female
L1
Choke inductor, 51 nH, 0402
M1
Heat sink
R1
External reference input matching, 49.9 Ω, 0402
Resistor, 0 Ω, 0402
R11, R13, R14, R15, R16
R19, R29
Resistor, 1 kΩ, 0402
R25, R27
Resistor, pull-down, 100 kΩ, 0402
R4
Resistor, loop filter, 680 Ω, 0402
R5
Resistor, loop filter,1.5 kΩ, 0402
U1
U2
K band downconverter with integrated fractional-N PLL and VCO, ADMV4420
Serial EEPROM, 32-bit
VCC5P0, VPOS1, VPOS2, VPOS3, VPOS4
Y1
Test point, red
Crystal
Rev. A | Page 58 of 61
Data Sheet
ADMV4420
I D S
K L C S
S C
5 2
6 2
7 2
8 2
9 2
0 3
1 3
2 3
D N G
T U O X U M
1 L A T X / F E R
C N / 2 L A T X
L L P 2 _ S O V P
M D S 4 _ L C E D
L L P 3 _ L C E D
O C V 1 _ S O V P
6 1
5 1
4 1
3 1
2 1
1 1
0 1
9
E
U T N V
F I 4 _ S O V P
T U O F I
D N G
F R 5 _ L C E D
D A P
Figure 132. ADMV4420-EVALZ Evaluation Board Schematic
Rev. A | Page 59 of 61
ADMV4420
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
AREA
PIN 1
25
32
IONS
INDICATOR AR EA OP T
(SEE DETAIL A)
24
1
0.50
BSC
3.75
EXPOSED
PAD
3.60 SQ
3.55
17
8
16
9
0.50
0.40
0.30
0.20 MIN
TOP VIEW
TOP VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
Figure 133. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
(NOTE 2)
1.60
Ø 1.55
1.50
(NOTE 1)
4.10
4.00
3.90
2.05
2.00
1.95
(NOTE 3)
1.85
1.75
1.65
0.35
0.30
0.25
A
5.60
5.50
Ø 1.50 MIN
5.40
5.30
12.30
12.00
11.70
5.40
(NOTE 1)
3° BSC
5.20
(NOTE 6)
1.35
1.25
TOP VIEW
A
DETAIL A
8.00
R 0.50
R 0.50
1.15
0.50
0.40
0.30
(NOTE 8)
DIRECTION OF FEED
SECTION A-A
DETAIL A
NOTES:
1. MEASURED FROM THE CENTERLINE OF SPROCKET HOLE TO CENTERLINE OF THE
POCKET HOLE
2. 10 SPROCKET HOLE PITCH CUMUL ATIVE TOLERANCE IS ± 0.20
3. THICKNESS IS APPLICABLE AS MEASURED AT EDGE OF TAPE
4. BLACK POLYSTYRENE MATERIAL
5. ALLOWABLE CAMBER TO BE 1 mm PER 100 mm IN LENGHT, NON-CUMULATIVE OVER 250 mm
6. MEASUREMENT POINT TO BE 0.3 mm FROM BOTTOM POCKET
5
11
7. SURFACE RESISTIVITY FROM 10 TO 10 Ω/SQ
8. KO MEASUREMENT POINT SHOULD NOT BE REFERED ON POCKET RIDGE
Figure 134. 32-Lead Lead Frame Chip Scale Package [LFCSP] Tape and Reel Outline Dimensions
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Moisture Sensitivity
Model1
Level (MSL) Rating2 Package Description
Package Option
ADMV4420ACPZ
ADMV4420ACPZ-R2
ADMV4420ACPZ-RL7
ADMV4420-EVALZ
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
MSL3
MSL3
MSL3
32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12
32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12
32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12
1 Z = RoHS Compliant Part.
2 See Table 2 and Figure 2 for the peak reflow temperature.
Rev. A | Page 60 of 61
Data Sheet
NOTES
ADMV4420
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16995-0-4/19(A)
Rev. A | Page 61 of 61
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