ADMC330 [ADI]
Single Chip DSP Motor Controller; 单芯片DSP电机控制器
| 型号： | ADMC330 |
| 厂家： | 
ADI |
| 描述： | Single Chip DSP Motor Controller |
| 文件： | 总20页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Chip DSP
Motor Controller
a
ADMC330
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Seven Analog Input Channels
Acquisition Synchronized to PWM Sw itching Frequency
Three-Phase 12-Bit PWM Generator
Program m able Deadtim e and Narrow Pulse Deletion
2.5 kHz Minim um Sw itching Frequency
ECM Control Mode
ADSP-2100 BASE
ARCHITECTURE
PROGRAM
ROM
2K
؋
24 MEMORY
DATA
ADDRESS
GENERATORS
DATA
MEMORY
1K
؋
16 WATCH-
DOG
TIMER
PROGRAM
RAM
2K
؋
24 8-BIT
PIO
PROGRAM
SEQUENCER
DAG 1 DAG 2
Output Control for Space Vector Modulation
Gate Drive Block (Pulsed PWM Output Capability)
Hardw ired Output Polarity Control
External Trip Input
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
Tw o 8-Bit Auxiliary PWM Tim ers
Synthesized Analog Output
DATA MEMORY DATA
39 kHz Frequency
0 to 99.6% Duty Cycle
ARITHMETIC UNITS
ALU SHIFTER
12-BIT
3-PHASE
PWM
2
؋
8-BIT AUX
PWM
SERIAL PORTS
SPORT 0 SPORT 1
ANALOG
INPUTS
TIMER
MAC
Eight Bits of Digital I/ O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
20 MIPS Fixed Point DSP Core
Pow erful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Independent Com putational Units
ALU
GENERAL D ESCRIP TIO N
T he ADMC330 is a low cost single chip DSP microcontroller
optimized for stand alone ac motor control applications. T he
device is based on a 20 MHz fixed-point DSP core (ADSP-
2171) and a set of motor control peripherals including seven
analog input channels and a 12-bit three-phase PWM generator.
T he device has two auxiliary 8-bit PWM channels and adds
expansion capability through the serial ports and an 8-bit digital
I/O port. T he ADMC330 has internal 2K words program RAM,
and 1K words data RAM, which can be loaded from an external
device via the serial port. T here are also 2K words of internal
program ROM, which includes a monitor that adds software
debugging features through the serial port.
Multiplier/ Accum ulator
Barrel Shifter
Multifunction Instructions
Single-Cycle Instruction Execution (50 ns)
Single-Cycle Context Sw itch
ADSP-2100 Fam ily Code and Function Com patible w ith
Instruction Set Enhancem ents
16-Bit Watchdog Tim er
Program m able 16-Bit Interval Tim er w ith Prescaler
Tw o Synchronous Serial Ports
Full Debugger Interface
2 Bootstrap Protocols via Sport 1, Serial and UART
Mem ory Configuration
2K
؋
24-Bit Word Program RAM 1K
؋
16-Bit Word Data RAM T he ADMC330 core combines the ADSP-2100 base architec-
ture (three computational units, data address generators and a
program sequencer) with two serial ports, a programmable
timer, extensive interrupt capabilities and on-chip program and
data memory.
In addition, the ADMC330 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding and global interrupt masking, for increased
flexibility.
2K
؋
24-Bit Word Program ROM REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
(V = 5 V ؎ 10%, GND = SGND = 0 V, T = –40؇C to +85؇C, unless otherwise noted)
ADMC330–SPECIFICATIONS
DD
A
P aram eter
Min
Typ
Max
Units
Conditions/Com m ents
ANALOG-T O-DIGIT AL CONVERT ER
Charging Capacitor = 1000 pF
2.5 kHz Sample Frequency
Signal Input
Resolution
Converter Linearity
Zero Offset
Channel-to-Channel Comparator Match
Comparator Delay
Current Source
0.3
9.5
3.21
12
4
200
25
V
Bits
Bits
mV
mV
ns
No Missing Codes
2
50
600
11
13.5
3
µA
%
Current Source Linearity
ELECT RICAL CHARACT ERIST ICS
VIL Logic Low
0.8
V
VIH Logic High
2
4
V
V
V
V
µA
µA
mA
mA
VOL Low-Level Output Voltage
VOL Low-Level Output Voltage (XT AL)
VOH High-Level Output Voltage
IIL Low-Level Input Current
IIH High-Level Input Current
IDD Supply Current (Power-Down Mode)
IDD Supply Current (Static)
0.4
0.5
IOL = 2 mA
IOL = 2 mA
IOH = 0.5 mA
VIN = 0 V
–10
10
5
60
VIN = VDD
CLOCK
Input Clock (tCK
DSP Clock (tCK/2)
)
100
50
ns
ns
10 MHz Clock Input (CLKIN)
20 MHz DSP Clock (CLKOUT )
REFERENCE VOLT AGE OUT PUT
Voltage Level
Output Voltage Change TMIN to TMAX
2.2
2.55
20
2.9
V
mV
100 µA Load
12-BIT PWM T IMER
Counter Resolution
122
Bits
ns
µs
ns
µs
ns
kHz
µs
Edge Resolution
100
200
100
2
10 MHz CLKIN
10 MHz CLKIN
10 MHz CLKIN
10 MHz CLKIN
10 MHz CLKIN
10 MHz CLKIN
10 MHz CLKIN
10 MHz CLKIN
Programmable Deadtime Range
Programmable Deadtime Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
0
12.5
12.5
0
2.5
0.08
PWMSYNC Pulsewidth (T CRST
Gate Drive Chop Frequency Range
)
5
MHz
AUXILIARY PWM T IMERS
Resolution
PWM Frequency
8
39
Bits
kHz
1/256 of 10 MHz CLKIN Clock
NOT ES
1Signal input max V = 3.5 if VDD = 5 V ± 5%.
2Resolution varies with PWM switching frequency (10 MHz Clock), 25 kHz = 8 bits, 2.5 kHz = 12 bits.
Specifications subject to change without notice.
–2–
REV. 0
ADMC330
ABSO LUTE MAXIMUM RATINGS*
Supply Voltage (VDD . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
)
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Input Voltage . . . . . . . . . . . . –0.3 V to VDD
Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Output Swing . . . . . . . . . . . . –0.3 V to VDD
Operating T emperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. T hese are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
O RD ERING GUID E
Tem perature
Range
Instruction
Rate
P ackage
D escription
P ackage
O ption
Model
ADMC330BST –40°C to +85°C
20 MHz
80-Lead Plastic T hin Quad Flatpack (T QFP)
ST -80
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC330 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
ADMC330
P IN FUNCTIO N D ESCRIP TIO NS
P in P in
No. Type
P in
Nam e
P in P in
No. Type
P in
Nam e
Pin
No.
P in
Type
P in
Nam e
P in P in
No. Type
P in
Nam e
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
21
NC
VDD
GND
NC
PWMSYNC
CL
CH
BL
BH
AL
AH
NC
VDD
GND
GND
GND
GND
GND
NC
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
NC
NC
41
NC
GND
GND
XT AL
CLKIN
PWMPOL
RESET
GND
VDD
CLKOUT
GND
DT 1
T FS1
RFS1
DR1A
DR1B
SCLK1
DT 0
I/P
O/P
SUP
VAUX3
REFOUT
VDD
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SUP
GND
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
GND
GND
I/P
I/P
I/P
BIDIR
BIDIR
BIDIR
BIDIR
SUP
GND
GND
I/P
O/P
GND
I/P
I/P
I/P
T FS0
RFS0
DR0
SCLK0
VDD
GND
AGND
CAPIN
ICONST
SGND
V1
V2
V3
VAUX0
VAUX1
VAUX2
NC
O/P
O/P
O/P
O/P
O/P
O/P
O/P
GND
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
O/P
GND
PIO7
PIO6
PIO5
PIO4
PIO3
PIO2
PIO1
PIO0
AUX1
AUX0
VDD
I/P
GND
SUP
O/P
GND
O/P
BIDIR
BIDIR
I/P
SUP
GND
GND
GND
GND
GND
O/P
SUP
I/P
GND
I/P
I/P
I/P
I/P
BIDIR
BIDIR
PWMTRIP
GND
NC
NC
NC
NC
NC
NC
P IN CO NFIGURATIO N
80-Lead P lastic Thin Q uad Flatpack (TQ FP )
(ST-80)
61
62
63
64
65
66
67
68
69
NC
NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
NC
TFS0
RFS0
DR0
GND
GND
GND
GND
GND
SCLK0
V
DD
GND
V
DD
AGND
NC
AH
AL
BH
BL
CH
CL
ADMC330
TOP VIEW
CAPIN 70
ICONST
71
(Not to Scale)
SGND 72
V1 73
V2 74
V3 75
VAUX0
VAUX1
76
77
PWMSYNC
NC
VAUX2 78
GND
V
NC
NC
79
80
DD
PIN 1
IDENTIFIER
21 NC
NC = NO CONNECT
–4–
REV. 0
ADMC330
T he ADMC330 operates with a 50 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
an executable file. T he simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
MAKEPROM utility splitter generates PROM programmer
compatible files. T he C Compiler, based on the Free Software
Foundation’s GNU C Compiler, generates ADMC330 assem-
bly source code. T he runtime library includes over 100 ANSI-
standard mathematical and DSP-specific functions.
T he flexible architecture and comprehensive instruction set of
the ADMC330 allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADMC330 can:
• generate the next program address
• fetch the next instruction
• perform one or two data moves
• update one or two data address pointers
• perform a computational operation
Low cost, easy-to-use hardware development tools include an
ADMC330-EVAL board and a windows based software debugger.
T his debugger can be run with either the ADMC330-EVAL
board or the target system by communicating over a two-wire
asynchronous link to a PC.
T his takes place while the processor continues to:
• receive and transmit data through the two serial ports
• decrement the timer
Independently the peripheral blocks can:
FUNCTIO NAL D ESCRIP TIO N
AD MC330 P er ipher als O ver view
• generate three-phase PWM waveforms for a power inverter
• generate two signals using the 8-bit auxiliary PWM timers
• acquire four analog signals
• control eight digital I/O lines
• decrement the watchdog timer
T he ADMC330 set of peripherals was specifically developed to
address the requirements of variable speed control of ac induc-
tion motors (ACIM) and electronically commutated synchro-
nous motors (ECM). T hey are memory mapped to a block in
the DSP data memory space allowing single cycle read and/or
write to all peripheral registers. T he operation of the peripherals
is synchronized to the DSP core by a clock HCLK, which is
derived from half of the DSP system clock.
RO M Code Functions
The ADMC330 has a 2K Boot ROM that contains the
following:
• Monitor Program:
Serial Boot Loader for OT P ROM or EEPROM
UART Debugger Interface and Loader
Thr ee-P hase P WM Gener ator
• 12-bit center-based PWM generator including program-
mable deadtime and narrow pulse deletion.
• ECM crossover block.
• Output enable block.
• Hardwired output polarity control.
• External trip input.
• Math Utilities/T ables:
Sine, cosine, tangent, inverse tangent, log, inverse log,
square root, 1/X, 1/(sine rms), unsigned division, Cartesian
to polar conversion, interpolation
T he ADMC330 is similar to an ADSP-2172 in its booting se-
quence. T he MMAP and BMODE pins are tied high, which
enables the on-chip ROM and starts execution of the monitor
program on power-up or reset. T he monitor program first at-
tempts to boot load through SPORT 1 from a serial memory
device. T he loader uses a two-wire (data and clock) serial proto-
col. T he ADMC330 provides a serial clock to the device equal
to 1/20 of CLKOUT . Default input is from a Xilinx XC1765D
OT P ROM or Atmel AT 17C65 EEPROM; other devices are
possible as long as they adhere to the loader protocol. If the
serial load is successful, the code that was downloaded is ex-
ecuted at the start of user memory space.
• Pulsed PWM output capability for transformer coupled gate.
Analog I/O
• Two 8-bit PWM Output T imers—(Synthesized Analog
Output).
• Comparator based Analog Input Acquisition. Analog-to-digital
conversion is accomplished via 4-channel single slope ADC.
D igital I/O
• Eight bits of programmable digital I/O configurable as
interrupt sources.
TH REE-P H ASE P WM GENERATO R
T he ADMC330 PWM controller is a self-contained program-
mable waveform generator that produces PWM switching sig-
nals for a three-phase power inverter. It includes a waveform
timing edge calculation unit which allows the generation of six
center based PWM signals based on only three duty cycle regis-
ter updates every switching cycle. T his minimizes the DSP
software required to service the PWM controller and frees up
processor time for the motor control law implementation. In the
default configuration it produces the three-phase center based
PWM waveforms required for three phase sinusoidal inverter.
However, it can also be configured for space vector modulation
schemes, or for controlling brushless dc motors (sometimes
known as electronically commutated motors). It also has func-
tions which simplify the interface to the power inverter gate
drive and protection circuits.
Failing a synchronous boot load, the ADMC330 monitor switches
over to debug mode and waits for commands over SPORT 1
from a UART . Debug mode uses a standard RS-232 protocol in
which only the data receive and transmit lines are used by the
ADMC330. This interface is used by the Visual DSP® Debugger,
but can also be used by UART devices for boot loading programs.
In addition to the monitor program, the ROM contains the
previously listed math utilities. T hese routines can be called
from user applications.
D evelopm ent System
T he ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADMC330. T he system builder provides a high level
method for defining the architecture of systems under develop-
ment. T he assembler has an algebraic syntax that is easy to
program and debug. T he linker combines object files into
T he PWM controller is synchronized to the DSP core by the
HCLK which runs at half the DSP clock frequency giving wave-
form resolution of 100 ns with a 20 MHz DSP clock. T here are
Visual DSP is a registered trademark of Analog Devices, Inc.
REV. 0
–5–
ADMC330
four configuration registers (PWMT M, PWMDT , PWMPD
and PWMGAT E), which define basic waveform parameters
such as the master switching frequency, deadtime, minimum
pulsewidth, and gate drive chopping. T here PWM output sig-
nals on the pins AH through CL are controlled by the input
registers (PWMCHA, PWMCHB, PWMCHC and PWMSEG)
and the control pins PWMTRIP and PWMPOL.
dead time and the duty cycle for each inverter phase. T here is
no extra DSP software overhead once the duty cycle for each
phase has been calculated and loaded into the PWM channel
registers.
T he PWM T iming Unit produces three pairs of complemented
variable duty cycle waveforms symmetrical about common axes
of the form shown in Figure 2. T hey are complemented wave-
forms, which means that for any pair of PWM waveforms (AH
and AL), they can never both be ON at the same time. T hey are
deadtime adjusted, which means that for any pair of PWM
waveforms, there is a delay between switching from being ON in
one waveform to being ON in the complemented waveform. A
pulse deletion function is implemented, which means that very
narrow PWM pulses will not be generated.
P WM Contr oller O ver view
T he PWM controller consists of three units: the center-based
timing unit, output control unit and the gate drive unit as shown
in Figure 1.
• T he center-based PWM timing unit is the core of the PWM
controller and produces three pairs of complemented and
deadtime adjusted PWM waveforms as required for ac motor
control.
It is important to note that the deadtime compensation does not
take place on the boundary between consecutive PWM cycles.
T hus both the low side and high side devices can switch on
during the transition from a full-ON state to any other state.
T his potentially volatile condition can be avoided by:
• Ensuring that the device never enters to the full-ON or full-
OFF states, that is,
• T he output control unit is a signal switching unit that selects
the appropriate PWM signals to be connected to the output
pins based on the bits set in the segment register (PWMSEG)
as may be required for ECM control or some space vector
modulation schemes.
• T he gate drive block sets the logic polarity of the PWM “on”
signal according to the polarity of the PWMPOL pin to match
the gate drive circuit requirement. It can also modulate the
PWM “on” signal with a high frequency carrier (0.08 MHz–
5 MHz) if required for a transformer coupled gate drive circuit.
PWMCHx ≤ PWMTM –2 × (PWMDT + 1), with PWMPD = 0
• Using an external deadtime compensation circuit.
T here is an active high PWMSYNC pulse produced at the be-
ginning of each PWM cycle to synchronize the operation of
other peripherals with the switching of the power inverter. T his
signal is also internally connected to the ADC block to initiate
conversions, and to the DSP core to generate an interrupt.
Figure 2 shows the center-based PWM operation.
T he DSP-based control algorithm can be synchronized to the
PWM generator by a hardware interrupt signal that is generated
at the end of every PWM switching cycle. This same PWMSYNC
signal is internally connected to the internal analog-to-digital
converter and is also available at an output pin. Finally, the
hardware PWMTRIP pin can be used to shut down the PWM
controller in the event of a fault.
T he master switching frequency can range from 2.5 kHz to
25 kHz and is an integral fraction of HCLK clock frequency. It
is set by the value in the 12-bit PWMT M period register, which
sets the total number of clock cycles in a PWM cycle. The
required PWM period as a function of the desired master
switching frequency (fPWM) and peripheral system clock fre-
quency (fHCLK) is given by:
Center -Based P WM Tim ing Unit
T he center-based PWM timing unit is a programmable timer
that generates three pairs of fixed frequency PWM waveforms
suitable for controlling a three-phase power inverter. T he unit
contains arithmetic circuits that calculate the PWM signal tim-
ing edges from waveform parameters such as the PWM period,
f HCLK
PWMTM =
f PWM
TIMING CONTROL
REGISTERS
CHANNEL
REGISTERS
PWMTM
PWMDT
PWMPD
PWMCHA
PWMCHB
PWMCHC
OUTPUT CONTROL
GATE CONTROL
REGISTER
REGISTER
PWMSEG
PWMGATE
AH
AL
BH
BL
CH
CL
OUTPUT
CONTROL
UNIT
GATE
DRIVE
UNIT
CENTER-BASED
PWM TIMING
UNIT
CLK
SYNC
RESET
SYNC
CLK
PWMPOL
HCLK
PWMSYNC
PWMSYNC
INTERRUPT
SIGNALS
PWMTRIP
Figure 1. PWM Controller Overview
–6–
REV. 0
ADMC330
O utput Contr ol Unit
For example, the H CLK clock is 10 MH z. If 8 kH z PWM
waveforms are required, then PWMT M should be loaded
with 10 MH z/8 kH z = 1250. A value must be written to the
PWMT M register before the PWM block can be used.
T he Output Control Unit contains special features that allow
the ADMC330 to be easily applied for the control of electroni-
cally commutated motors (ECM) or brushless dc motors
(BDCM). In these machines, only two motor phases are required
to conduct simultaneously so that at most two power switches are
turned on at any time. In order to build up current in the motor
phases, it is necessary to turn on the upper switch in one phase and
the lower switch in another phase of the inverter.
The ON time of each pair of PWM waveforms, e.g., AH and AL,
is set by the integer value in the duty cycle registers PWMCHA,
PWMCHB and PWMCHC. T he deadtime between the active
portions of complementary waveforms is set by the value in the
deadtime register PWMDT and is subtracted from the value in
the duty cycle register. T he final deadtime adjusted fractional
duty cycle for Channel A for example is given by:
T he PWMSEG register of the ADMC330 PWM block allows
modification of the pulsewidth modulation signals from the
center-based block in order to meet the requirements for ECM
control. T hree bits of the PWMSEG register (Bits 6, 7 and 8)
permit individual crossover of the three PWM signal pairs. For
example, setting Bit 8 will crossover the signals for Phase A such
that the high-side signal from the center-based block will ulti-
mately appear at the low-side output pin (AL). Conversely, the
low-side signal from the center-based block will appear at Pin AH.
tAon
PWMCHA – PWMDT
dA
=
=
T PWM
PWMTM
T he minimum pulsewidth delivered is set by the value in the
pulse deletion register PWMPD. When the calculated high or
low pulsewidth for any channel is less than PWMPD, the
switching pulse is eliminated and the outputs are saturated one
to 100% high, and the other to 100% low.
START
END
PWMCHA
AH
AL
PWMDT
PWMDT
PWMCHB
PWMCHC
PWMTM
BH
BL
PWMDT
PWMDT
CH
CL
PWMDT
PWMDT
PWMSYNC
Figure 2. Three-Phase Center-Based Active Low PWM Waveform s
REV. 0
–7–
ADMC330
Gate D r ive Unit
Similar modifications can be made to Phases B and C using Bits
7 and 6, respectively, of the PWMSEG register. Six bits of the
PWMSEG register (Bits 0 . . . 5) are used to independently
enable/disable any individual PWM output pins. For example,
setting Bits 0 and 1 high disables PWM outputs CH and CL,
which keeps these outputs off over the full PWM period regard-
less of the value in the PWMCHC register. T his feature is not
only useful for ECM control, but is also required in some space
vector modulation schemes. Modifications to the PWMSEG
register only become effective at the start of each PWM cycle. In
the transparent (default) mode, all bits in PWMSEG are set low.
T he Gate Drive Unit adds features that simplify the interface to
a variety of gate drive circuits for PWM inverters. If a trans-
former coupled power device gate drive amplifier is used, the
active PWM signal must be chopped at a high frequency of up
to 5 MHz. T he chopped active PWM signals may be required
for the high side drivers only or for both high side and low side.
T he gate drive chopping feature is enabled by Bits 8 and 9 of the
PWMGAT E register. Setting Bit 8 enables a chopped PWM
signal on all high side output pins AH , BH and CH , setting
Bit 9 enables a chopped PWM signal on all low side output pins
AL, BL and CL. The gate chopping frequency is programmed
using Bits 0–5 of the PWMGATE register. The gate drive chop-
ping frequency is given by the following equation:
Consider the situation shown in Figure 3 for operation of an
ECM with the AH and BL power devices active. T he PWM
duty cycle registers, PWMCHA and PWMCHB, are programmed
with the appropriate on-time value. Since all three PWM regis-
ters must be written to trigger an update of the PWM, it is neces-
sary to write also to PWMCHC. For this example, the particular
value written to this register is unimportant. Subsequently,
crossover bit of the PWMSEG register for Phase B (Bit 7) is set
to enable crossover of the Phase B signals. T he PWM outputs
for Phase C high and low, Phase B high and Phase A low are
disabled by setting Bits 0, 1, 2 and 5 of the PWMSEG register.
In this example, the appropriate value for the PWMSEG register
is 0x00A7. In addition, high side chopping of the signal AH is
enabled by setting Bit 8 of the PWMGAT E register.
f HCLK
fchop
=
2 ×(GATETM +1)
where GATETM is the 6-bit value in Bits 0 . . . 5 of the
PWM G AT E register.
Depending on the type of power device gate drive circuit used,
either active high or active low, PWM signals will be required,
so an external PWM polarity pin is provided. T he polarity of the
PWMPOL pin determines the active polarity of the PWM out-
put signals (i.e., a low PWMPOL pin means active low PWM).
T his must be set by hardware because even though the ADMC330
will power up with all PWM outputs off, the correct polarity of
an off PWM signal is a function of the gate drive circuit only.
T he level on the PWMPOL pin is available in Bit 2 of the
SYSST AT register.
START
MIDPOINT
END
PWMCHA
PWMCHB
PWMDT
CENTER-
BASED
OUTPUTS
Exter nal P WM Tr ip
PWMDT
In fault conditions the power devices must be switched off as soon
as possible after the fault has been detected, hence an external
hardware PWM trip input is provided. A low going PWMTRIP
pulse will reset the PWM block which will disable all PWM
outputs. T his will also generate a PWMTRIP interrupt signal
and cause a DSP interrupt. T he PWMTRIP pin is accessible
through Bit 0 of SYSST AT so that the DSP can determine
when the external fault has been cleared. At this point, a full
initialization of the PWM controller will be required to restart
the PWM.
AH
AL
BH
BL
CH
CL
AD C O VERVIEW
T he analog input block is a 12-bit resolution analog data acqui-
sition system. A single slope type ADC is implemented by timing
the crossover between the analog input and a sawtooth refer-
ence ramp. A simple voltage comparator is used to latch the output
of a reference counter timer circuit when the crossover is detected.
Figure 3. PWM Output Waveform s for an ECM with
Inverter Devices AH and BL Active
Known limitation of the ECM block. Modifying the PWMSEG
register while the PWM duty cycle transitions from a full-ON
state to any other state will cause both the high side and low
side devices to switch on for 50 ns. T his potentially volatile
condition can be avoided by:
T here are seven input channels to the ADC of which three (V1,
V2 and V3) have dedicated comparators. T he remaining four
inputs (VAUX0, VAUX1, VAUX2 and VAUX3) are multi-
plexed into the fourth comparator channel. T his allows four
conversions per PWM period to be performed by the ADC. T he
particular input signal that is fed to the fourth comparator input
is selected using the ADCMUX0 and ADCMUX1 bits of the
peripheral control register, MODECT RL. T he settings of these
two control bits in order to select the appropriate auxiliary ana-
log input is shown in T able I.
• Disabling the PWM channel outputs during the transition
from full-ON to any other state.
• Preventing the full-ON condition namely limiting PWMCHx to:
PWMCHx ≤ PWMTM –2 × (PWMDT + 1), with PWMPD = 0.
• Preventing a PWMSEG update operation during the transi-
tion from full-ON to any other state.
–8–
REV. 0
ADMC330
PWMGATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GATETM
LOW SIDE GATE CHOPPING
HIGH SIDE GATE CHOPPING
1 = ENABLE
0 = DISABLE
GATE DRIVE CHOPPING FREQUENCY
(f )/(2(GATETM+1))
HCLK
PWMSEG
15
14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
CH OUTPUT DISABLE
CL OUTPUT DISABLE
BH OUTPUT DISABLE
BL OUTPUT DISABLE
AH OUTPUT DISABLE
AL OUTPUT DISABLE
A CHANNEL CROSSOVER
B CHANNEL CROSSOVER
C CHANNEL CROSSOVER
1 = CROSSOVER
0 = NO CROSSOVER
1 = DISABLE
0 = ENABLE
Figure 4. Configuration of PWMSEG and PWMGATE Registers
Table I. AD C Auxiliary Channel Selection
appropriate 12-bit ADC register. T here are four ADC registers
(ADC1, ADC2, ADC3 and ADCAUX) corresponding to each
of the four comparators. At the end of the reference voltage
ramp, all four registers should have been loaded with new values
so that new conversion data is available to the controller after a
PWMSYNC interrupt.
MO D ECTRL (1)
AD CMUX1
MO D ECTRL (0)
AD CMUX0
Select
VAUX0
VAUX1
VAUX2
VAUX3
0
0
1
1
0
1
0
1
T he first set of values loaded into the output registers after the
first PWMSYNC interrupt will be invalid since the latched value
is indeterminate. For very low analog inputs, less than the mini-
mum reference value, the comparator output will be perma-
nently high and the output register will contain the code 0x000.
Also, if the input analog voltage exceeds the peak capacitor
ramp voltage, the comparator output will be permanently low
and a 0xFFF code will be produced. T his indicates an input
overvoltage condition.
Analog Block
T he operation of the ADC block may be explained by reference
to Figures 5 and 6. T he reference ramp is tied to one input of
each of the four comparators. T his reference ramp is generated
by charging an external timing capacitor with a constant current
source. T he timing capacitor is connected between pins CAPIN
and SGND. T he capacitor voltage is reset at the start of each
PWM cycle using the PWMSYNC pulse, which is held high for
20 CLKIN cycles (TCRST = 2 µs for a 10 MHz CLKIN). On the
falling edge of PWMSYNC, the capacitor begins to charge at a
rate determined by the capacitor and the current source values.
An internal current source is made available for connection to
the external timing capacitor on the ICONST pin. An external
current source could also be used, if required. T he four input
comparators of the ADC block continuously compare the values
of the four analog inputs with the capacitor voltage. Each com-
parator output will go high when the capacitor voltage exceeds
the respective analog input voltage.
REFOUT
ICONST
CAPIN
PWMSYNC
C
ADC REGISTERS
ADC1
SGND
V1
ADC2
ADC3
ADC
TIMER
BLOCK
V2
V3
AD C Tim er Block
T he ADC timer block consists of a 12-bit counter clocked at a
constant rate of HCLK, equal to half the DSP clock rate. T his
gives a timer resolution of 100 ns at the maximum CLKIN
frequency of 10 MHz. T he counter is reset on the falling edge of
the PWMSYNC pulse so that the counter commences at the
beginning of the reference voltage ramp. When the output of a
given comparator goes high, the counter value is latched into the
ADCAUX
VAUX0
VAUX1
VAUX2
VAUX3
4-1
MUX
ADMUX0
ADMUX1
HCLK
Figure 5. ADC Overview
REV. 0
–9–
ADMC330
As a result, assuming ±10% variations in both the capacitance
and current source, the nominal capacitance value required at a
given PWM period is:
V
C
V
CMAX
(0.9 × ICONST )(T PWM –TCRST
)
V1
CNOM
=
(1.1)(3.5)
T he largest standard value capacitor that is less than this calcu-
lated value is chosen. T able III shows the appropriate standard
capacitor value to use for various PWM switching frequencies
assuming ±10% variations in both the current source and ca-
pacitor tolerances. If required, more precise control of the ramp
voltage is possible by using higher precision capacitor compo-
nents, an external current source and/or series or parallel timing
capacitor combinations.
V
VIL
t
tVIL
T
CRST
T
– T
CRST
PWM
PWMSYNC
Table III. Tim ing Capacitor Selection
COMPARATOR
OUTPUT
P WM Frequency
(kH z)
Tim ing Capacitor
(pF)
Figure 6. Analog Input Block Operation
AD C Resolution
2.5–3.0
3.0–3.6
3.6–4.3
4.3–5.2
5.2–6.2
6.2–7.3
7.3–9.0
9.0–10.9
10.9–13.2
13.2–15.8
15.8–19.6
19.6–23.4
23.4–28.2
820
680
560
470
390
330
270
220
180
150
120
100
82
Because the operation of the ADC is intrinsically linked to the
PMW block, the effective resolution of the ADC is a function of
the PMW switching frequency. T he effective ADC resolution is
determined by the rate at which the counter timer is clocked.
For a CLKIN period of tCK and a PWM period of TPWM , the
maximum count of the ADC is given by
T PWM
Max Count =
tCK
For an assumed CLKIN frequency of 10 MHz, the effective
resolution of the ADC block is tabulated for various PWM
switching frequencies in T able II.
Table II. AD C Resolution Exam ples
AUXILIARY P WM TIMERS O VERVIEW
T he two auxiliary PWM timers can be used to produce analog
signal outputs when configured as PWM DACs. T his allows the
ADMC330 to generate a reference for power factor correction
and supply an analog reference for other systems in the applica-
tion. T hey can also be used as supplementary PWM outputs for
other control circuits.
P WM Frequency
(kH z)
Effective Resolution
(Bits)
Max Count
2.5
4
8
18
25
3980
2480
1230
535
≈12
>11
>10
>9
T he PWM timers generate two fixed frequency edge-based
variable duty cycle PWM signals. T he PWM frequency is
1/256 times HCLK, or 39 kHz. T he duty cycle is based on a
user-supplied 8-bit value loaded into the AUX0 and AUX1
registers.
380
>8
Exter nal Tim ing Capacitor
In order to maximize the useful input voltage range and effective
resolution of the ADC, it is necessary to carefully select the
value of the external timing capacitor. For a given capacitance
value, CNOM, the peak ramp voltage is given by:
T he timer output can range from 0% to 99.6%, where the num-
ber written to the register represents the high time. T he values
are updated as soon as new values are written in the registers: if
the value is smaller than the present counter value the output
goes low, otherwise it stays high.
ICONST
T
– TCRST
PWM
(
)
VC max =
CNOM
On RESET, the AUX0 and AUX1 registers are cleared to zero
and remain at zero until a new value is written.
where ICONST is the nominal current source value of 10.5 µA and
TCRST is the PWMSYNC pulsewidth. In selecting the capacitor
value, however, it is necessary to take into account the tolerance
of the capacitor and the variation of the current source value.
T o ensure that the full input range of the ADC is utilized, it is
necessary to select the capacitor so that at the maximum capaci-
tance value and the minimum current source output, the ramp
voltage will charge to at least 3.5 V.
P WM D AC Equation
T he PWM output must be filtered in order to produce a low
frequency analog signal between 0 V to 4.98 V dc. For example,
a 2-pole filter with a 1.2 kHz cut off frequency will sufficiently
attenuate the PWM carrier. Figure 7 shows how the filter would
be applied.
–10–
REV. 0
ADMC330
WATCH D O G TIMER O VERVIEW
PWMDAC
R1
R2
R1 = R2 = 13k⍀
T he watchdog timer can be used to reset the DSP and peripher-
als in the event of a software error hanging the processor. T he
watchdog timer is enabled by writing a value to the watchdog
timer register. In the event of the code “hanging” the counter
will count down from its initial value to zero and the watchdog
timer hardware will force a DSP and peripheral reset. In normal
operation a section of DSP code will write to the timer register
to reset the counter to its initial value preventing it from reach-
ing zero.
C1 = C2 = 10nF
C2
C1
Figure 7. Auxiliary PWM Output Filter
P RO GRAMMABLE D IGITAL INP UT/O UTP UT
T he ADMC330 has eight programmable digital I/O (PIO) pins:
PIO0–PIO7. Each pin can be individually configurable as either
an input or an output. Input pins can also be used to generate
interrupts.
D SP CO RE ARCH ITECTURE O VERVIEW
Figure 9 is a block diagram of the ADMC330 processor core
and system peripherals. T he processor contains three indepen-
dent computational units: T he ALU, the multiplier/accumulator
(MAC) and the shifter. T he computational units process 16-bit
data directly and have provisions to support multiprecision
computations. T he ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. T he
MAC performs single-cycle multiply, multiply/add and multiply/
subtract operations with 40 bits of accumulation. T he shifter
performs logical and arithmetic shifts, normalization, denormali-
zation and derive exponent operations. The shifter can be used to
efficiently implement numeric format control including multi-
word and block floating-point representations.
T he PIO pins are configured as input or output by setting the
appropriate bits in the PIODIR register, as shown in Figure 8.
T he read/write register PIODAT A is used to set the state of an
output pin or read the state of an input pin. Writing to PIODATA
affects only the pins configured as outputs. The default state,
after an ADMC330 reset, is that all PIO are configured as inputs.
Any pin can be configured as an independent edge triggered
interrupt source. T he pin must first be configured as an input
and then the appropriate bit must be set in the PIOINT EN
register. A peripheral interrupt is generated when the input level
changes on any PIO pin configured as an interrupt source. A
PIO interrupt sets the appropriate bit in the PIOFLAG register.
T he DSP peripheral interrupt service routine (ISR) must read
the PIOFLAG registers to determine which PIO pin was the
source of the PIO interrupt. Reading the PIOFLAG register will
clear it.
T he internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
PIODIR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 = OUTPUT
0 = INPUT
PIODATA
(READ/WRITE)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 = HI
0 = LOW
PIOINTEN
(WRITE-ONLY)
9
15 14 13 12 11 10
8
7
6
5
4
3
2
1
0
1 = ENABLE INTERRUPT
0 = DISABLE INTERRUPT
PIOFLAG
(READ-ONLY)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 = INTERRUPT FLAGGED
0 = NO INTERRUPT
PIO0
PIO7
Figure 8. Configuration of PIO Registers
REV. 0
–11–
ADMC330
INSTRUCTION
REGISTER
PROGRAM ROM
2K
؋
24 DATA
SRAM
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
1K
؋
16 PROGRAM SRAM
FLAGS
PROGRAM
SEQUENCER
2K
؋
24 PMA BUS
14
14
24
DMA BUS
PMD BUS
BUS
EXCHANGE
DMD BUS
16
COMPANDING
CIRCUITRY
CONTROL
LOGIC
TIMER
INPUT REGS
SHIFTER
INPUT REGS
ALU
INPUT REGS
MAC
OUTPUTREGS
16
TRANSMIT REG
TRANSMIT REG
RECEIVE REG
RECEIVE REG
OUTPUTREGS
OUTPUTREGS
SERIAL
PORT 0
SERIAL
PORT 1
R BUS
5
5
Figure 9. DSP Core Block Diagram
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. T he sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMC330 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
T he ADMC330 can respond to interrupts. T here can be
internal interrupts generated by the T imer, the Serial Ports
(SPORT s), and software or peripheral interrupts generated by
the PIO or PWM. T here is also a master RESET signal.
T he two serial ports provide a complete synchronous serial
interface with optional companding in hardware and a wide
variety of framed or frameless data transmit and receive modes
of operation. Each port can generate an internal programmable
serial clock or accept an external serial clock.
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Boot circuitry provides for automatically loading on-chip pro-
gram memory from the data input and output pins on SPORT 1.
SPORT 1 can be alternatively configured as an input flag, output
flag or two additional interrupt sources.
A programmable interval timer generates periodic interrupts. A
16-bit count register (T COUNT ) is decremented every n pro-
cessor cycles, where n-l is a scaling value stored in an 8-bit regis-
ter (T SCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (T PERIOD).
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
T he ADMC330 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. T he ADMC330 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Program memory can store both instructions and data, permit-
ting the ADMC330 to fetch two operands in a single cycle,
one from program memory and one from data memory. T he
ADMC330 can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
–12–
REV. 0
ADMC330
Ser ial P or ts
PIOFLAG register for a PIO interrupt, and the IRQ2 line is
pulled low. T he IRQ2 line is held low until all pending periph-
eral interrupts are acknowledged. Execution then begins at the
IRQ2 (or peripheral) interrupt vector location (0x004). Soft-
ware at this location further determines if the source of the
interrupt was a PWM trip, PWYMSYNC, or PIO, by reading
the IRQFLAG register, and vectors to the appropriate interrupt
vector location. If more than one interrupt occurs simultaneously,
the higher priority interrupt service routine is executed. T he
software at location 0x004 is provided in a default interrupt
vector table that is created by the on-chip boot ROM code.
T herefore, a user need only put the interrupt service routine
for the given interrupt at the interrupt vector location shown in
T able IV. Reading the IRQFLAG register clears the PWMTRIP
and PWMSYNC bits and acknowledges the interrupt, thus
allowing further interrupts when the interrupt service routine
exits. When the IRQFLAG register is read, it is saved in a data
memory variable so the user interrupt service routines can check
to see if there were simultaneous PWMTRIP and PWMSYNC
interrupts.
T he ADMC330 incorporates two complete synchronous serial
ports (SPORT 0 and SPORT 1) for serial communications and
multiprocessor communication.
Following is a brief list of the capabilities of the ADMC330
SPORT s. Refer to the ADSP-2100 Family User’s Manual for
further details.
• SPORT s are bidirectional and have a separate, double-buff-
ered transmit and receive section.
• SPORT s can use an external serial clock or generate their
own serial clock internally.
• SPORT s have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
• SPORT s support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCIT T recommendation G.711.
A user’s PIO interrupt service routine must read the PIOFLAG
register to determine which PIO port is the source of the inter-
rupt. Reading the PIOFLAG register clears all bits in the
register and acknowledges the interrupt, thus allowing further
interrupts when the interrupt service routine exits.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORT s can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
All interrupts are internally prioritized and individually maskable
(except for power-down). T he interrupt vector locations and
priorities for all interrupts are listed in T able IV. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the higher priority unmasked interrupt is then selected. T he
software forced power-down interrupt is nonmaskable. T he
ADMC330 masks all interrupts for one instruction cycle follow-
ing the execution of an instruction that modifies the IMASK
register. T his does not affect autobuffering.
• SPORT 0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bit stream.
• SPORT 1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. T he
internally generated serial clock may still be used in this
configuration.
• SPORT 1 has two multiplexed data receive pins DR1A and
DR1B. DR1A is automatically selected at boot up and is the
default input for the serial ROM. For UART communication
DR1B is selected.
Table IV. Interrupt P riority and Interrupt Vector Addresses
Interrupt
A full description of the SPORT timing parameters is given in
Figure 14.
Source of Interrupt
Vector Location (H ex)
Inter r upts
T he interrupt controller allows the processor core to respond to
nine possible interrupts with the minimum of overhead. T he
ADMC330 supports eight internal interrupts from the timer,
the two serial ports, the software interrupts, and the software
forced power-down interrupt. T he ninth interrupt, IRQ2 on the
2171 core, is actually wired internally to the ADMC330 periph-
eral interrupt sources. T his peripheral interrupt is generated on
a PWM trip, PWMSYNC (once each PWM cycle), or from any
of the eight PIO ports. T he PWMSYNC interrupt is triggered
by a low to high transition on the PWMSYNC pulse.
Reset
0x0000 (Reserved)
0x002C (Highest Priority)
0x000C
0x0008
0x0010
0x0014
0x0018
0x001C
0x0020
PWMTRIP and Power-Down*
PWMSYNC*
PIO*
SPORT 0 T ransmit
SPORT 0 Receive
Software Interrupt 1
Software Interrupt 0
SPORT 1 T ransmit or IRQ1
SPORT 1 Receive or IRQ0
T imer
0x0024
0x0028 (Lowest Priority)
T he PWMTRIP interrupt is triggered on a high-to-low transi-
tion on the PWMTRIP pin. A PIO interrupt is detected on any
change of state (high-to-low or low-to-high) on the PIO line.
When a peripheral interrupt is detected, a flag bit is set in the
IRQFLAG register for PWMSYNC and PWMTRIP or in the
*Peripheral interrupt (IRQ2) starts execution at 0x004, software further vector
to 0x002C, 0x000C or 0x0008 as appropriate.
REV. 0
–13–
ADMC330
T he interrupt control register, ICNT L, allows the external inter-
rupts to be either edge- or level-sensitive. Since the IRQ2 line is
a combination of all peripheral interrupt sources, they will all be
set to edge- or level-sensitive. Level-sensitive is recommended
when using both PIO and PWM interrupts together. When
simultaneous PIO and PWM interrupts occur, the IRQ2 line is
brought low and held low until both the PIO and PWM inter-
rupts are acknowledged. If interrupts are set to edge-sensitive
only, one IRQ2 interrupt will occur for simultaneous interrupts
and it is incumbent on the interrupt service routine to check for
simultaneous interrupts. If, however, interrupts are set to level-
sensitive, all simultaneous interrupts are detected because IRQ2
is held low until all interrupts are acknowledged.
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADMC330 includes an on-chip oscillator circuit,
an external crystal may be used. T he crystal should be con-
nected across the CLKIN and XT AL pins, with two capacitors
connected as shown in Figure 10. A parallel-resonant, funda-
mental frequency, microprocessor-grade crystal should be used.
10M⍀
CLKIN
XTAL
T he ICNT L register also allows interrupts to be sequentially
processed or nested with higher priority interrupts taking prece-
dence. Since the peripheral interrupts are all on the same level
(IRQ2), they can only be nested by manually unmasking them
with the IMASK register from inside the interrupt service routine.
Figure 10. External Crystal Connections
A clock output (CLKOUT ) signal is generated by the processor
at the processor’s cycle rate.
T he IFC register is a write-only register, which is used to force
and clear interrupts from software.
Reset
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. T he stacks are 12
levels deep to allow interrupt nesting. A set of shadow registers
are provided for single context switching.
T he RESET signal initiates a master reset of the ADMC330.
T he RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
P ower -D own
T he ADMC330 can be put in a lower power state from software
control by setting the PDFORCE bit in the SPORT1 Autobuffer/
Power-Down register. T his causes a power-down interrupt;
execution then continues at the power-down interrupt vector
location 0x002C. T he power-down interrupt vector location is
shared with the PWMTRIP interrupt, thus if a different inter-
rupt service routine is required, the vector must be changed
prior to setting the PDFORCE bit. T he power-down interrupt
service routine must perform a peripheral reset prior to entering
power-down to shut down the PWM signals to the motor. T he
interrupt service routine can then perform any housekeeping
operations prior to executing an IDLE instruction, after which
the ADMC330 is in power-down mode. T he only way out of
power-down is to perform a hardware reset of the ADMC330.
T he power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low.
T he RESET input contains some hysteresis; however, if you
use an RC circuit to generate your RESET signal, the use of an
external Schmitt trigger is recommended.
T he master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MST AT
register. When RESET is released, the DSP starts running from
the internal ROM and the boot loading sequence is performed.
If an SROM (serial ROM) or Serial EEPROM is connected to
SPORT 1 with valid program data, this code is then loaded and
execution starts. If a valid device is not detected, then the pro-
gram defaults to debug mode with SPORT 1 configured as a
UART running at 9600 baud.
Clock Signals
T he ADMC330 can be clocked by either a crystal or a T T L-
compatible clock signal.
T he CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal operation.
If an external clock is used, it should be a T T L-compatible
signal running at half the instruction rate. T he signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XT AL input must be left unconnected.
T he ADMC330 uses an input clock with a frequency equal to
half the instruction rate; a 10 MHz input clock yields a 50 ns
processor cycle (which is equivalent to 20 MHz). Normally,
instructions are executed in a single processor cycle. All device
–14–
REV. 0
ADMC330
A software controlled full peripheral reset (including the watch-
dog timer) is achieved by toggling the DSP FL2 flag from 1 to 0
to 1 again.
This mode only has an effect when the MR0 register contains
0x8000; all other rounding operation work normally. This mode
was added to allow more efficient implementation of bit speci-
fied algorithms that specify biased rounding, such as the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
MEMO RY MAP
T he ADMC330 has two types of memory: data memory and
program memory. Program RAM starts at 0x0000, while the
program ROM area starts at 0x800. T he data RAM starts at
0x3800 while the peripherals are mapped to a data memory
block starting at 0x2000.
Note: BIASRND bit is Bit 12 of the SPORT 0 Autobuffer
Control register.
INSTRUCTIO N SET D ESCRIP TIO N
T he ADMC330 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
Table V. P rogram Mem ory
0x0000–0x002F
0x0030–0x07FF
0x0800–0x0BFF
0x0C00–0x0FFF
Interrupt Vector T able
User Program Space
ROM Monitor
• T he algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical arith-
metic add instruction, such as AR = AX0 + AY0, resembles a
simple equation.
ROM Math Utilities
Table VI. D ata Mem ory
• Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.
0x2000–0x201F
0x3800–0x3B8F
0x3B90–0x3BFF
Peripherals
User Data Space
Reserved for ROM Monitor Use
• T he syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members.
AD MC330 Register s
• Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
Some registers store values. For example, AX0 stores an ALU
operand; I4 stores a DAG2 pointer. Other registers consist of
control bits and fields, or status flags. For example, AST AT
contains status flags from arithmetic operations, and fields in
DWAIT control the numbers of wait states for different zones of
data memory.
• Multifunction instructions allow parallel execution of an arith-
metic instruction with up to two fetches or one write to pro-
cessor memory space during a single instruction cycle.
A secondary set of registers in all computational units allows a
single-cycle context switch.
Consult the ADSP-2100 Family User’s Manual for a complete
description of the syntax and an instruction set reference with
particular reference to the ADSP-2171 device.
T he bit and field definitions for control and status registers are
given in the rest of this section, except for IMASK, ICNT L and
IFC, which are defined earlier in this data sheet. T he system
control register, timer registers and SPORT control registers are
all mapped into data memory; that is, registers are accessed by
reading and writing data memory locations rather than register
names. T he particular data memory address is shown with each
memory-mapped register.
Inter r upt Enable
T he ADMC330 supports an interrupt enable instruction. Inter-
rupts are enabled by default at reset. T he instruction source
code is specified as follows:
Syntax:
ENA INT S;
D escr iption:
Executing the ENA INT S instruction allows
all unmasked interrupts to be serviced again.
Biased Rounding
A new mode allows biased rounding in addition to the normal
unbiased rounding. When the BIASRND bit is set to 0, the
normal unbiased rounding operations occur. When the BIASRND
bit is set to 1, biased rounding occurs instead of the normal unbi-
ased rounding. When operating in biased rounding mode all
rounding operations with MR0 set to 0x8000 will round up,
rather than only rounding odd MR1 values up. For example:
Inter r upt D isable
T he ADMC330 supports an interrupt disable instruction. T he
instruction source code is specified as follows:
Syntax:
DIS INT S;
D escr iption:
Reset enables interrupt servicing. Executing
the DIS INT S instruction causes all inter-
rupts to be masked without changing the
contents of the IMASK register. Disabling
interrupts does not affect the autobuffer cir-
cuitry, which will operate normally whether
or not interrupts are enabled. T he disable
interrupt instruction masks all user interrupts
including the power-down interrupt.
MR value before RND biased RND result unbiased RND result
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
REV. 0
–15–
ADMC330
ICNTL
IMASK
4
3
2
1
0
15 14 13 12 11 10
9
0
8
7
6
0
5
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1 = ENABLE, 0 = DISABLE
IRQ2
TIMER
IRQ0 SENSITIVITY
IRQ1 SENSITIVITY
IRQ2 SENSITIVITY
1 = EDGE
0 = LEVEL
IRQ0 OR SPORT1 RECEIVE
IRQ1 OR SPORT1 TRANSMIT
SOFTWARE 0
SOFTWARE 1
SPORT0 TRANSMIT
SPORT0 RECEIVE
INTERRUPT NESTING
1 = ENABLE, 0 = DISABLE
IFC
15 14 13 12 11 10
9
0
8
7
6
0
5
0
4
0
3
0
2
1
0
0
0
0
0
0
0
0
0
0
0
0
INTERRUPT FORCE
INTERRUPT CLEAR
IRQ2
SPORT0 TRANSMIT
SPORT0 RECEIVE
SOFTWARE 1
TIMER
SPORT1 RECEIVE OR IRQ0
SPORT1 TRANSMIT OR IRQ1
SOFTWARE 0
SOFTWARE 1
SOFTWARE 0
SPORT1 TRANSMIT OR IRQ1
SPORT1 RECEIVE OR IRQ0
TIMER
SPORT0 RECEIVE
SPORT0 TRANSMIT
IRQ2
Figure 11. Interrupt Registers
D SP INTERFACE AND MEMO RY MAP
SYSTEM CO NTRO LLER O VERVIEW
All data transferred between the DSP core and the peripherals is
controlled by the System Controller.
T he System Controller has a number of functions:
1. It decodes the DSP address bus and selects the appropriate
peripheral registers.
T he peripheral registers, with the exception of the ADC read
registers, are right justified, i.e., the LSB of each register is
connected to the LSB of the 16-bit DSP DM data bus DSPD
[15:0]. Any unused MSBs are connected to zeros. T he ADMC
peripheral registers are memory mapped to 32 words on the
DSP address space, starting at DSP memory location 0x2000:
2. It controls the ADC multiplexer select lines.
3. It can enable PWMTRIP and PWMSYNC interrupts.
4. It controls the SPORT 0 multiplexer select lines.
5. It resets the peripherals and control registers on hardware,
software or watchdog initiated resets.
1. ADC read registers (0–3)
2. PIO Registers (4–7)
3. PWM Set-Up Registers (8–11)
4. PWM Data Registers (12–15)
5. AUX PWM Data Registers (16, 17)
6. System Registers (21–24)
6. It handles interrupts generated by the peripherals and
generates a DSP core interrupt signal IRQ1 (IRQ2).
7. It can be used to control the peripheral test modes.
–16–
REV. 0
ADMC330
Table VII. P eripheral Register Map
Address
(H EX)
O ffset
(D ecim al)
Nam e
Bits Used
Function
0x2000
0x2001
0x2002
0x2003
0x2004
0x2005
0x2006
0x2007
0x2008
0x2009
0x200A
0x200B
0x200C
0x200D
0x200E
0x200F
0x2010
0x2011
0x2012
0x2013
0x2014
0x2015
0x2016
0x2017
0x2018
0x2019..F
0
1
2
3
4
5
6
7
ADC1
ADC2
ADC3
ADCAUX
PIODIR
PIODAT A
PIOINT EN
PIOFLAG
PWMT M
PWMDT
PWMPD
PWMGAT E
PWMCHA
PWMCHB
PWMCHC
PWMSEG
AUX0
[4..15]
[4..15]
[4..15]
[4..15]
[0..7]
[0..7]
[0..7]
[0..7]
[0..11]
[0..6]
[0..6]
[0..8]
[0..11]
[0..11]
[0..11]
[0..8]
ADC Results for V1
ADC Results for V2
ADC Results for V3
ADC Results for VAUX
PIO Pins Direction Setting
PIO Pins Input/Output Data
PIO Pins Interrupt Enable
PIO Pins Interrupt Status
PWM Period
8
9
PWM Deadtime
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25..31
PWM Pulse Deletion T ime
PWM Gate Drive Configuration
PWM Channel A Pulsewidth
PWM Channel B Pulsewidth
PWM Channel C Pulsewidth
PWM Segment Select
AUX PWM Output 1
AUX PWM Output 2
Not Used
Not Used
Not Used
System Control Register
System Status
Interrupt Status
[0..7]
[0..7]
AUX1
MODECT RL
SYSST AT
IRQFLAG
[0..15]
[0..1]
[0..2]
WDT IMER
[0..15]
Watchdog T imer
Not Used
Multiplexer , P WM Inter r upts and SP O RT1 Contr ol
T he ADC, the SPORT 1 peripherals and the PWM interrupts
are configured using the MODECT RL register.
The D SP and P er ipher al Reset Functions
A full system reset of the ADMC330 is achieved by pulling the
RESET pin low (for > 5 clock cycles when running, or > 2000
clock cycles on power-up). This resets the DSP core and all
peripherals including the watchdog timer.
1. T wo bits control the ADC aux channel selection:
ADCMUX0..1.
The SYSSTAT register indicates the fault status of the ADMC330
after a PWMTRIP interrupt or a watchdog reset:
2. T wo bits can enable/disable the PWMTRIP and PWMSYNC
interrupts.
1. The status of the PWMTRIP pin (active low).
3. Two bits control the SPORT1 UART and DR1A/B multiplexer.
2. The status of the watchdog flag register (this is not reset on a
The PWM interrupt enable bits are masking bits rather than
set/reset bits. Therefore, before enabling these interrupts any
pending interrupts can be cleared by reading the IRQFLAG
register.
DSP RESET).
3. The status of the PWMPOL pin.
When one of the peripherals generates an interrupt, the DSP
IRQ2 line is pulled low and a flag bit is set in the IRQFLAG
register for PWMSYNC and PWMTRIP or in the PIOFLAG
register for a PIO interrupt. The DSP can read these registers to
determine the source of the interrupt. When the IRQFLAG
register is read, the PWMSYNC and PWMTRIP bits are
cleared to zero. Reading the PIOFLAG register clears all the bits
in this register to zero. When both registers are cleared, the IRQ2
line is set high again. The reset condition for all bits in this regis-
ter is zero.
Setting the UART EN bit connects DR1 to the RFS1 input,
which allows SPORT1 to be used as a UART port. The DR1SEL
bit selects either pins DR1A or DR1B. The reset condition for
all bits in this register is zero.
DT1
DT1
DR1A
DR1
DR1B
ADMC330
SPORT1
TFS1
TFS1
RFS1
RFS1
SCLCK1
SCLCK1
UART
ENABLE SELECT
DR1B
DEFAULT SWITCH
POSITION SHOWN
Figure 12. Internal Multiplexing of SPORT1 Pins
REV. 0
–17–
ADMC330
MODECTRL
(READ/WRITE)
9
15 14 13 12 11 10
8
7
6
5
4
3
2
1
0
ADC MUX CONTROL
00 = VAUX0
01 = VAUX1
10 = VAUX2
11 = VAUX3
PWMTRIP INTERRUPT ENABLE
1 = ENABLE
0 = DISABLE
PWMSYNC INTERRUPT ENABLE
1 = DR1B
0 = DR1A
SPORT1 DATA RECEIVE SELECT
SPORT1 MODE SELECT
1 = UART
0 = SPORT
SYSSTAT
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 = HI
0 = LO
PWMTRIP PIN STATUS
WATCHDOG STATUS
PWMPOL PIN STATUS
1 = RESET OCCURRED
0 = NORMAL
1 = HI
0 = LO
IRQFLAG
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PWMTRIP INTERRUPT STATUS
1 = PENDING
0 = CLEARED
PWMSYNC INTERRUPT STATUS
Figure 13. Configuration of MODECTRL, SYSSTAT and IRQFLAG Registers
–18–
REV. 0
ADMC330
TIMING PARAMETERS
SERIAL P O RTS
Frequency
12.5 MH z
Min Max
13.0 MH z
Min Max
13.824 MH z*
Min Max
D ependency
P aram eter
Min
Max
Unit
Timing Requirement:
tSCK
tSCS
tSCH
tSCP
SCLK Period
80
8
10
30
76.9
8
10
28
72.3
8
10
28
100
15
20
ns
ns
ns
ns
DR/T FS/RFS Setup before SCLK Low
DR/T FS/RFS Hold after SCLK Low
SCLKIN Width
40
Switching Characteristic:
tCC
CLKOUT High to SCLKOUT
20
0
35
20
20
19.2 34.2
0
18.1 33.1
0
0.25 tCK 0.25 tCK + 20 ns
0
tSCDE SCLK High to DT Enable
tSCDV SCLK High to DT Valid
tRH
tRD
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
20
30
30
T FS/RFSOUT Hold after SCLK High
T FS/RFSOUT Delay from SCLK High
0
0
0
0
tSCDH DT Hold after SCLK High
tT DE T FS (Alt) to DT Enable
tT DV T FS (Alt) to DT Valid
tSCDD SCLK High to DT Disable
tRDV RFS (Multichannel, Frame Delay Zero)
to DT Valid
0
0
0
0
0
0
0
0
18
25
20
18
25
20
18
25
20
25
40
30
*Maximum serial port operating frequency is 13.824 MHz for all processor speed grades except the 12.5 MHz ADSP-2101 and 13.0 MH z ADSP-2111.
CLKOUT
tCC
tCC
tSCK
SCLK
tSCP
tSCS tSCH
tSCP
DR
RFS
IN
TFS
IN
tRD
tRH
RFS
OUT
OUT
TFS
tSCDV
tSCDD
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
(ALTERNATE
FRAME MODE)
tRDV
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 (MFD = 0))
Figure 14. Serial Ports
REV. 0
–19–
ADMC330
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
80-Lead P lastic Thin Q uad Flatpack (TQ FP )
(ST-80)
0.640 (16.25)
0.620 (15.75)
0.553 (14.05)
0.549 (13.95)
0.063 (1.60)
MAX
0.486 (12.35) TYP
0.030 (0.75)
0.020 (0.50)
41
40
60
61
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.004
(0.10)
MAX
80
21
20
1
0.006 (0.15)
0.014 (0.35)
0.010 (0.25)
0.029 (0.73)
0.022 (0.57)
0.002 (0.05)
0.057 (1.45)
0.053 (1.35)
–20–
REV. 0
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