ADMC331-ADVEVALKIT [ADI]
Single Chip DSP Motor Controller; 单芯片DSP电机控制器
| 型号： | ADMC331-ADVEVALKIT |
| 厂家： | 
ADI |
| 描述： | Single Chip DSP Motor Controller |
| 文件： | 总36页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Chip DSP
Motor Controller
a
ADMC331
TARGET APPLICATIONS
Edge Resolution to 38.5 ns
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives
198 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Suitable for AC Induction and Synchronous Motors
Special Signal Generation for Switched Reluctance
Motors
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for all PWM Outputs
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
Hardwired Polarity Control
External PWMTRIP Pin
Seven Analog Input Channels
Acquisition Synchronized to PWM Switching
Frequency
FEATURES
26 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (38.5 ns)
ADSP-2100 Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generator
Memory Configuration
2K ꢀ 24-Bit Program Memory RAM
2K ꢀ 24-Bit Program Memory ROM
1K ꢀ 16-Bit Data Memory RAM
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Deadtime and Narrow Pulse Deletion
Conversion Speed Control
24 Bits of Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synchronized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
(Continued on page 7)
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
PROGRAM
ROM
2K ꢀ 24
MEMORY
DATA
ADDRESS
WATCH-
DOG
TIMER
PROGRAM
RAM
2K ꢀ 24
DATA
RAM
1K ꢀ 16
GENERATORS
24-BIT
PIO
PROGRAM
SEQUENCER
DAG 1 DAG 2
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
16-BIT
3-PHASE
PWM
7
2 ꢀ 8 BIT
AUX
PWM
SERIAL PORTS
ARITHMETIC UNITS
MAC
ANALOG
INPUTS
TIMER
SPORT 0 SPORT 1
ALU
SHIFTER
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(V = +5 V ꢁ 10%, GND = SGND = 0 V, T = –40ꢂC to +85ꢂC, unless otherwise noted)
ADMC331–SPECIFICATIONS
DD
A
Parameter
Min
Typ Max
Units
Conditions/Comments
ANALOG-TO-DIGITAL CONVERTER
Charging Capacitor = 1000 pF
2.5 kHz Sample Frequency
Signal Input
Resolution
Converter Linearity
Zero Offset
Channel-to-Channel Comparator Match
Comparator Delay
Current Source
0.3
3.31
122
12
50
22
V
Bits
LSBs
mV
mV
ns
µA
%
No Missing Codes
2
5
600
10.16
2
12.7 15.24
2
Current Source Linearity
ELECTRICAL CHARACTERISTICS
VIL
Logic Low
0.8
V
V
VIH Logic High
VOL Low Level Output Voltage
VOL Low Level Output Voltage (XTAL)
VOH High Level Output Voltage
0.4
0.5
V
V
V
IOL = 2 mA
IOL = 2 mA
IOH = 0.5 mA
4
IIL
Low Level Input Current
High Level Input Current
Hi-Level PWMTRIP, PIO0–PIO23 Current
Hi-Level PWMPOL/PWMSR Current
Lo-Level PWMTRIP, PIO0–PIO23 Current
Lo-Level PWMPOL/PWMSR Current
Supply Current (Dynamic)
–10
µA
µA
µA
µA
µA
µA
mA
mA
VIN = 0 V
VIN = VDD
IIH
IIH
IIH
IIL
IIL
IDD
IDD
10
100
10
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
13 MHz DSP Clock
13 MHz DSP Clock
10
100
120
60
Supply Current (Idle)
REFERENCE VOLTAGE OUTPUT
Voltage Level
Output Voltage Change TMIN to TMAX
2.2
2.55 2.9
20
V
mV
100 µA Load
16-BIT PWM TIMER
Counter Resolution
16
76.9
38.5
78
Bits
ns
ns
µs
ns
µs
ns
kHz
Edge Resolution (Single Update Mode)
Edge Resolution (Double Update Mode)
Programmable Deadtime Range
Programmable Deadtime Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
13 MHz CLKIN
0
0
76.9
78
76.9
0.198
0.077
0.02
PWMSYNC Pulsewidth (TCRST
Gate Drive Chop Frequency Range
)
9.8
6.5
µs
MHz
AUXILIARY PWM TIMERS
Resolution
8
Bits
PWM Frequency
0.051
6.5
MHz
13 MHz CLKIN
NOTES
1Signal input max V = 3.5 V if VDD = 5 V 5%.
2Resolution varies with PWM switching frequency (13 MHz Clock in Double Update mode), 50.7 kHz = 9 bits, 6.3 kHz = 12 bits.
Specifications subject to change without notice.
–2–
REV. B
ADMC331
TIMING PARAMETERS
Parameter
Min
Max
Unit
Clock Signals
tCK is defined as 0.5 tCKI. The ADMC331 uses an input clock with a frequency equal
to half the instruction rate; a 13 MHz input clock (which is equivalent to 76.9 ns)
yields a 38.5 ns processor cycle (equivalent to 26 MHz). tCK values within the range
of 0.5 tCKI period should be substituted for all relevant timing parameters to obtain
specification value.
Example: tCKH = 0.5 tCK – 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.
Timing Requirements:
tCKI
CLKIN Period
76.9
20
20
150
20
ns
ns
ns
tCKIL
tCKIH
CLKIN Width Low
CLKIN Width High
Switching Characteristics:
tCKL
CLKOUT Width Low
0.5 tCK – 10
0.5 tCK – 10
0
ns
ns
ns
tCKH
tCKOH
CLKOUT Width High
CLKIN High to CLKOUT High
Control Signals
Timing Requirement:
1
tRSP
RESET Width Low
5 tCK
ns
ns
PWM Shutdown Signals
Timing Requirement:
tPWMTPW
PWMTRIP Width Low
2 tCK
NOTE
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
Figure 1. Clock Signals
REV. B
–3–
ADMC331
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
tSCK
tSCS
tSCH
tSCP
SCLK Period
100
15
20
ns
ns
ns
ns
DR/TFS/RFS Setup before SCLK Low
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
40
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
0.25 tCK
0
0.25 tCK + 20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCDE
tSCDV
tRH
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
SCLK High to DT Disable
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
RFS (Multichannel, Frame Delay Zero) to DT Valid
30
30
30
0
0
0
tRD
tSCDH
tSCDD
tTDE
tTDV
tRDV
25
30
CLKOUT
tCC
tCC
tSCK
SCLK
tSCP
tSCS tSCH
tSCP
DR
RFS
TFS
IN
IN
tRD
tRH
RFS
TFS
OUT
OUT
tSCDV
tSCDD
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
(ALTERNATE
FRAME MODE)
tRDV
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
Figure 2. Serial Ports
–4–
REV. B
ADMC331
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
)
Supply Voltage (AVDD) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . .+280°C
ORDERING GUIDE
Temperature
Range
Instruction
Rate
Package
Description
Package
Option
Model
ADMC331BST
ADMC331-ADVEVALKIT
ADMC331-PB
–40°C to +85°C
26 MHz
80-Lead Plastic Thin Quad Flatpack (TQFP)
Development Tool Kit
Evaluation/Processor Board
ST-80
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC331 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
ADMC331
PIN FUNCTION DESCRIPTIONS
Pin Pin
No. Type
Pin
Name
Pin Pin
No. Type
Pin
Name
Pin Pin
No. Type
Pin
Name
Pin Pin
No. Type
Pin
Name
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SUP
GND
BIDIR PIO12
BIDIR PIO13
O/P
O/P
O/P
O/P
O/P
O/P
O/P
BIDIR PIO14
BIDIR PIO15
BIDIR PIO16
SUP
GND
BIDIR PIO17
GND GND
BIDIR PIO18
GND GND
VDD
GND
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
GND
GND
O/P
I/P
I/P
GND
GND
XTAL
CLKIN
PWMPOL
RESET
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
O/P
SUP
VREF
AVDD
GND
PIO9
PIO8
PIO7
PIO6
PIO5
PIO4
PIO3
PIO2
PIO1
PIO0
AUX1
AUX0
PIO10
PIO11
VDD
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
BIDIR TFS0
BIDIR RFS0
GND
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
O/P
I/P
DR0
BIDIR SCLK0
BIDIR PIO21
BIDIR PIO22
BIDIR PIO23
PWMSYNC
CL
CH
BL
BH
AL
AH
I/P
GND
SUP
BIDIR
BIDIR
O/P
GND
O/P
BIDIR
BIDIR
I/P
VDD
SUP
GND
GND
I/P
O/P
GND
I/P
VDD
GND
AGND
CAPIN
ICONST
SGND
V1
PIO19
PIO20
CLKOUT
GND
DT1
TFS1
RFS1/SROM
DR1A
DR1B
SCLK1
O/P
VDD
GND
I/P
I/P
V2
V3
BIDIR
BIDIR
SUP
I/P
GND
I/P
BIDIR
O/P
I/P
I/P
I/P
I/P
I/P
VAUX0
VAUX1
VAUX2
VAUX3
DT0
PWMSR
PWMTRIP
GND
PIN CONFIGURATION
80-Lead Plastic Thin Quad Flatpack (TQFP)
(ST-80)
VREF
AV
60
59
58
57
56
55
54
1
2
PWMSR
PIN 1
IDENTIFIER
DT0
DD
GND
PIO9
SCLK1
DR1B
3
4
PIO8
DR1A
5
PIO7
PIO6
6
RFS1/ SROM
TFS1
7
PIO5
PIO4
53 DT1
GND
8
52
9
ADMC331
TOP VIEW
(Not to Scale)
PIO3
51 CLKOUT
50 PIO20
10
11
12
13
PIO2
PIO1
PIO19
49
PIO0
V
48
47
46
45
44
43
42
DD
GND
AUX1 14
AUX0 15
PIO10 16
RESET
PWMPOL
CLKIN
PIO11
17
18
19
V
XTAL
GND
DD
PWMTRIP
GND
GND 20
41
–6–
REV. B
ADMC331
(Continued from page 1)
GENERAL DESCRIPTION
The ADMC331 is a low cost, single-chip DSP-based controller,
suitable for ac induction motors, permanent magnet synchro-
nous motors, brushless dc motors, and switched reluctance
motors. The ADMC331 integrates a 26 MIPS, fixed-point DSP
core with a complete set of motor control peripherals that per-
mits fast, efficient development of motor controllers.
Two Programmable Operational Modes
Independent Mode
Offset Mode
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Two Double Buffered Synchronous Serial Ports
Four Boot Load Protocols via SPORT1
E2PROM/SROM Booting
UART Booting (SCI Compatible) with Autobaud
Feature
Synchronous Master Booting with Autobaud Feature
Synchronous Slave Booting with Autobaud Feature
Debugger Interface via SPORT1 with Autobaud (UART
and Synchronous Supported)
The DSP core of the ADMC331 is the ADSP-2171, which is
completely code compatible with the ADSP-2100 DSP family
and combines three computational units, data address genera-
tors and a program sequencer. The computational units com-
prise an ALU, a multiplier/accumulator (MAC) and a barrel
shifter. The ADSP-2171 adds new instructions for bit manipula-
tion, multiplication (X squared), biased rounding and global
interrupt masking. In addition, two flexible, double-buffered,
bidirectional, synchronous serial ports are included in the
ADMC331.
ROM Utilities
Full Debugger for Program Development
Preprogrammed Math Functions
Preprogrammed Motor Control Functions—Vector
Transformations
80-Lead TQFP Package
Industrial Temperature Range –40ꢂC to +85ꢂC
The ADMC331 provides 2K × 24-bit program memory RAM,
2K × 24-bit program memory ROM and 1K × 16-bit data
memory RAM. The program and data memory RAM can be
boot loaded through the serial port from a Serial ROM (SROM),
E2PROM, asynchronous (UART) connection or synchronous
connection. The program memory ROM includes a monitor
that adds software debugging features through the serial port. In
addition, a number of preprogrammed mathematical and motor
control functions are included in the program memory ROM.
The motor control peripherals of the ADMC331 include a
16-bit center-based PWM generation unit that can be used to
produce high accuracy PWM signals with minimal processor
overhead and seven analog input channels. The device also
contains two auxiliary 8-bit PWM channels, a 16-bit watch-
dog timer and expanded capability through the serial ports
and 24-bit digital I/O ports.
REV. B
–7–
ADMC331
INSTRUCTION
REGISTER
PM ROM
2K ꢀ 24
DM RAM
1K ꢀ 16
DATA
DATA
ADDRESS
GENERATOR
#2
PM RAM
2K ꢀ 24
ADDRESS
GENERATOR
#1
PROGRAM
SEQUENCER
14
14
PMA BUS
DMA BUS
PMD BUS
DMD BUS
24
BUS
EXCHANGE
16
COMPANDING
CIRCUITRY
CONTROL
LOGIC
TIMER
INPUT REGS
ALU
INPUT REGS
SHIFTER
INPUT REGS
MAC
TRANSMIT REG
TRANSMIT REG
RECEIVE REG
RECEIVE REG
OUTPUT REGS
16
OUTPUT REGS
OUTPUT REGS
SERIAL
PORT 0
SERIAL
PORT 1
R BUS
5
6
Figure 3. DSP Core Block Diagram
DSP CORE ARCHITECTURE OVERVIEW
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
Figure 3 is an overall block diagram of the DSP core of the
ADMC331, which is based on the fixed-point ADSP-2171. The
flexible architecture and comprehensive instruction set of the
ADSP-2171 allows the processor to perform multiple operations
in parallel. In one processor cycle (38.5 ns with a 13 MHz
CLKIN) the DSP core can:
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa-
tional units. The sequencer supports conditional jumps and
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMC331 executes looped code
with zero overhead; no explicit jump instructions are required
to maintain the loop.
• Generate the next program address.
• Fetch the next instruction.
• Perform one or two data moves.
• Update one or two data address pointers.
• Perform a computational operation.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and
program memory. Each DAG maintains and updates four ad-
dress pointers (I registers). Whenever the pointer is used to
access data (indirect addressing), it is post-modified by the
value in one of four modify (M registers). A length value may
be associated with each pointer (L registers) to implement auto-
matic modulo addressing for circular buffers. The circular buff-
ering feature is also used by the serial ports for automatic data
transfers to and from on-chip memory. DAG1 generates only
data memory address but provides an optional bit-reversal
capability. DAG2 may generate either program or data memory
addresses, but has no bit-reversal capability.
This all takes place while the processor continues to:
• Receive and transmit through the serial ports.
• Decrement the interval timer.
• Generate three-phase PWM waveforms for a power inverter.
• Generate two signals using the 8-bit auxiliary PWM timers.
• Acquire four analog signals.
• Decrement the watchdog timer.
The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC) and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision com-
putations. The ALU performs a standard set of arithmetic and
logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, multiply/
subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denormalization
and derive exponent operations. The shifter can be used to effi-
ciently implement numeric format control including floating-
point representations.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
–8–
REV. B
ADMC331
• SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated. Frame
synchronization signals are active high or inverted, with either of
two pulsewidths and timings.
Program memory can store both instructions and data, permit-
ting the ADMC331 to fetch two operands in a single cycle—
one from program memory and one from data memory. The
ADMC331 can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
• SPORTs support serial data word lengths from 3 bits to 16
bits and provide optional A-law and µ-law companding ac-
cording to ITU (formerly CCITT) recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
The ADMC331 writes data from its 16-bit registers to the 24-bit
program memory using the PX register to provide the lower
eight bits. When it reads data (not instructions) from 24-bit
program memory to a 16-bit data register, the lower eight bits
are placed in the PX register.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24-word or 32-word, time-division multi-
plexed, serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1), and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this con-
figuration.
• SPORT1 is the default input for program and data memory
boot loading. The RFS1 pin can be configured internal to the
ADMC331 as an SROM/E2PROM reset signal.
• SPORT1 has two data receive pins (DR1A and DR1B). The
DR1A pin is intended for synchronous boot loading from the
external SROM/E2PROM. The DR1B pin can be used as the
data receive pin for boot loading from an external asynchro-
nous (UART) connection (SCI compatible), an external
synchronous connection as the data receive pin for an external
device communicating over the debugger interface, or as the
data receive pin for a general purpose SPORT after booting.
These two pins are internally multiplexed onto the one DR1
port of the SPORT. The particular data receive pin selected is
determined by a bit in the MODECTRL register.
The ADMC331 can respond to a number of distinct DSP core
and peripheral interrupts. The DSP core interrupts include
serial port receive and transmit interrupts, timer interrupts,
software interrupts and external interrupts. The motor control
peripherals also produce interrupts to the DSP core.
The two serial ports (SPORTs) provide a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed and unframed data transmit and receive
modes of operation. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Boot loading of both the program and data memory RAM of the
ADMC331 is through the serial port SPORT1.
A programmable interval counter is also included in the DSP
core and can be used to generate periodic interrupts. A 16-bit
count register (TCOUNT) is decremented every n processor
cycle, where n–1 is a scaling value stored in the 8-bit TSCALE
register. When the value of the counter reaches zero, an interrupt is
generated and the count register is reloaded from a 16-bit pe-
riod register (TPERIOD).
The ADMC331 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation) instruc-
tions. Each instruction is executed in a single 38.5 ns processor
cycle (for a 13 MHz CLKIN). The ADMC331 assembly lan-
guage uses an algebraic syntax for ease of coding and readabil-
ity. A comprehensive set of development tools support program
development. For further information on the DSP core, refer to
the ADSP-2100 Family User’s Manual, Third Edition, with par-
ticular reference to the ADSP-2171.
Serial Ports
The ADMC331 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communication and
multiprocessor communication. Following is a brief list of capa-
bilities of the ADMC331 SPORTs. Refer to the ADSP-2100
Family User’s Manual, Third Edition, for further details.
• SPORTs are bidirectional and have a separate, double-buffered
transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
REV. B
–9–
ADMC331
PIN FUNCTION DESCRIPTION
Memory Map
The ADMC331 is available in an 80-lead TQFP package. Table I
contains the pin descriptions.
The ADMC331 has two distinct memory types: program
memory and data memory. In general, program memory contains
user code and coefficients, while the data memory is used to store
variables and data during program execution. Both program
memory RAM and ROM are provided on the ADMC331. Pro-
gram memory RAM is arranged as one contiguous 2K × 24-bit
block, starting at address 0x0000. Program memory ROM is
located at address 0x0800. Data memory is arranged as a 1K ×
16-bit block starting at address 0x3800. The motor control
peripherals are memory mapped into a region of the data
memory space starting at 0x2000. The complete program and
data memory maps are given in Tables II and III, respectively.
Table I. Pin List
Pin
#
Group
Name
of
Input/
Pins Output Function
RESET
1
5
I/P
Processor Reset Input.
SPORT0
I/P, O/P Serial Port 0 Pins (TFS0, RFS0,
DT0, DR0, SCLK0).
SPORT1
6
I/P, O/P Serial Port 1 Pins (TFS1, RFS1,
DT1, DR1A, DR1B, SCLK1).
Table II. Program Memory Map
CLKOUT
1
2
O/P
Processor Clock Output.
Memory
Type
CLKIN, XTAL
I/P, O/P External Clock or Quartz Crystal
Connection Point.
Address Range
Function
0x0000–0x002F
0x0030–0x071F
0x0720–0x07EC
0x07ED–0x07FF
0x0800–0x0DEC
0x0DED–0x0FEA
RAM
RAM
RAM
RAM
ROM
ROM
Interrupt Vector Table
User Program Space
Reserved by Debugger
Reserved by Monitor
ROM Monitor
ROM Math and Motor
Control Utilities
PIO0–PIO23
AUX0–AUX1
AH–CL
24
2
I/P, O/P Digital I/O Port Pins.
O/P
O/P
I/P
Auxiliary PWM Outputs.
PWM Outputs.
6
PWMTRIP
PWMPOL
PWMSYNC
PWMSR
1
PWM Trip Signal.
1
I/P
PWM Polarity Pin.
1
O/P
I/P
PWM Synchronization Pin.
Switch Reluctance Mode Pin.
Analog Inputs.
0x0FEB–0x0FFF
ROM
Reserved
1
V1–V3,
3
I/P
Table III. Data Memory Map
Memory
VAUX0–VAUX3 4
I/P
Auxiliary Analog Input
ADC Capacitor Input.
ADC Constant Current Source.
Voltage Reference Output.
Analog Power Supply.
Analog Ground.
CAPIN
ICONST
VREF
AVDD
1
I/P
Address Range
Type
Function
1
O/P
O/P
0x0000–0x1FFF
0x2000–0x20FF
0x2100–0x37FF
0x3800–0x3B5F
0x3B60–0x3BFF
0x3C00–0x3FFF
Reserved
Memory Mapped Registers
Reserved
User Data Space
Reserved by Monitor
Memory Mapped Registers
1
1
AGND
SGND
VDD
1
RAM
RAM
1
Analog Signal Ground
Digital Power Supply.
Digital Ground.
5
GND
11
ROM Code
The 2K × 24-bit block of program memory ROM starting at ad-
dress 0x0800 contains a monitor function that is used to download
and execute user programs via the serial port. In addition, the
monitor function supports an interactive mode in which commands
are received and processed from a host. An example of such a host
is the Windows®-based Motion Control Debugger, which is part of
the software development system for the ADMC331. In the inter-
active mode, the host can access both the internal DSP and periph-
eral motor control registers of the ADMC331, read and write to
both program and data memory, implement breakpoints and per-
form single-step and run/halt operation as part of the program
debugging cycle.
INTERRUPT OVERVIEW
The ADMC331 can respond to 34 different interrupt sources
with minimal overhead, 8 of which are internal DSP core
interrupts and 26 interrupts from the motor control peripherals.
The 8 DSP core interrupts are SPORT0 receive and transmit,
SPORT1 receive (or IRQ0) and transmit (or IRQ1), the internal
timer and two software interrupts. The motor control peripheral
interrupts are the 24 peripheral I/Os and two from the PWM
(PWMSYNC pulse and PWMTRIP). All motor control inter-
rupts are multiplexed into the DSP core through the peripheral
IRQ2 interrupt. The interrupts are internally prioritized and indi-
vidually maskable. A detailed description of the entire inter-
rupt system of the ADMC331 is given later, following a more
detailed description of each peripheral block.
In addition to the monitor function, the program memory ROM
contains a number of useful mathematical and motor control util-
ities that can be called as subroutines from the user code. A com-
plete list of these ROM functions is given in Table IV. The start
address of the function in the program memory ROM is also given.
Refer to the ADMC331 DSP Motor Controller Developer’s Reference
Manual for more details of the ROM functions.
Windows is a registered trademark of Microsoft Corporation.
–10–
REV. B
ADMC331
Table IV. ROM Utilities
Clock Signals
The ADMC331 can be clocked by either a crystal or a TTL-
compatible clock signal. The CLKIN input cannot be halted,
changed during operation nor operated below the specified
minimum frequency during normal operation. If an external
clock is used, it should be a TTL-compatible signal running at
half the instruction rate. The signal is connected to the CLKIN
pin of the ADMC331. In this mode, with an external clock
signal, the XTAL pin must be left unconnected. The ADMC331
uses an input clock with a frequency equal to half the instruc-
tion rate; a 13 MHz input clock yields a 38.5 ns processor cycle
(which is equivalent to 26 MHz). Normally, instructions are
executed in a single processor cycle. All device timing is
relative to the internal instruction rate, which is indicated by
the CLKOUT signal.
Utility
Address
Function
PER_RST
UMASK
0x07F1
0x0DED
Reset Peripherals.
Limits Unsigned Value to
Given Range.
Facilitates User Setup of
Vector Table.
Limits Signed Value to Given
Range.
PUT_VECTOR
SMASK
0x0DF4
0x0E06
ADMC_COS
ADMC_SIN
ARCTAN
RECIPROCAL
SQRT
LN
LOG
FLTONE
FIXONE
FPA
FPS
FPM
FPD
FPMACC
PARK
0x0E26
0x0E2D
0x0E43
0x0E65
0x0E7B
0x0EB5
0x0EB8
0x0ED4
0x0ED9
0x0EDD
0x0EEC
0x0EFC
0x0F05
0x0F26
0x0F48
Cosine Function.
Sine Function.
Arctangent Function.
Reciprocal (1/×) Function.
Square Root Function.
Natural Logarithm Function.
Logarithm (Base 10) Function.
Fixed Pt. to Float Conversion.
Float to Fixed Pt. Conversion.
Floating Pt. Addition.
Floating Pt. Subtraction.
Floating Pt. Multiplication.
Floating Pt. Division.
Floating Pt. Multiply/Accumulate.
Forward/Reverse Park
Transformation.
Reverse Clark Transformation.
Forward Clark Transformation.
64 Pt. COS Table.
16 Pt. 1/× Table.
Unsigned Single Precision
Division (Integer).
Because the ADMC331 includes an on-chip oscillator feedback
circuit, an external crystal may be used instead of a clock
source, as shown in Figure 4. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors as
shown in Figure 4. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. A clock output
signal (CLKOUT) is generated by the processor at the processor’s
cycle rate of twice the input frequency. This output can be
enabled and disabled by the CLKODIS bit of the SPORT0
Autobuffer Control Register, DM[0x3FF3]. However, extreme
care must be exercised when using this bit since disabling
CLKOUT effectively disables all motor control peripherals,
except the watchdog timer.
REV_CLARK
FOR_CLARK
COS64
ONE_BY_X
SDIVQINT
0x0F5C
0x0F72
0x0F80
0x0FCO
0x0FD0
Reset
The RESET signal initiates a master reset of the ADMC331.
The RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
SDIVQ
0x0FD9
Unsigned Single Precision
Division (Fractional).
SYSTEM INTERFACE
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence, the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
Figure 4 shows a basic system configuration for the ADMC331,
with an external crystal and serial E2PROM for boot loading of
program and data memory RAM.
XTAL
CLKOUT
13 MHz
CLKIN
mum pulsewidth specification, tRSP
.
ADMC331
DATA
If an RC circuit is used to generate the RESET signal, the use of
DR1A
an external Schmitt trigger is recommended.
SERIAL
E PROM
CLK
SCLK1
2
RESET
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, initializes DSP core regis-
ters and performs a full reset of all of the motor control periph-
erals. When the RESET line is released, the first instruction is
fetched from internal program memory ROM at location 0x0800.
The internal monitor code at this location then commences the
boot-loading sequence over the serial port, SPORT1. A soft-
ware controlled full peripheral reset is achieved by toggling the
DSP FL2 flag from 1 to 0 to 1 again.
RESET
RFS1/SROM
Figure 4. Basic System Configuration
REV. B
–11–
ADMC331
Boot Loading
control of the electronically commutated motor (ECM) or
brushless dc motor (BDCM).
On power-up or reset, the ADMC331 is configured so that
execution begins at the internal PM ROM at address 0x0800.
This starts execution of the internal monitor function that first
performs some initialization functions and copies a default inter-
rupt vector table to addresses 0x0000–0x002F of program memory
RAM. The monitor next attempts to boot load from an external
SROM or E2PROM on SPORT1 using the three wire connec-
tion of Figure 4. The monitor program first toggles the RFS1/
SROM pin of the ADMC331 to reset the serial memory device.
If an SROM or E2PROM is connected to SPORT1, data is
clocked into the ADMC331 at a rate CLKOUT/20. Both pro-
gram and data memory RAM can be loaded from the SROM or
E2PROM. After the boot load is complete, program execution
begins at address 0x0030. This is where the first instruction of
the user code should be placed.
The PWM generator produces three pairs of PWM signals on
the six PWM output pins (AH, AL, BH, BL, CH and CL). The
six PWM output signals consist of three high side drive signals
(AH, BH and CH) and three low side drive signals (AL, BL and
CL). The polarity of the generated PWM signals may be
programmed by the PWMPOL pin, so that either active HI or
active LO PWM patterns can be produced by the ADMC331.
The switching frequency, dead time and minimum pulsewidths
of the generated PWM patterns are programmable using respec-
tively the PWMTM, PWMDT and PWMPD registers. In addi-
tion, three duty cycle control registers (PWMCHA, PWMCHB
and PWMCHC) directly control the duty cycles of the three
pair of PWM signals.
When the PWMSR pin is pulled low, the PWM generator trans-
forms the six PWM output signals into six waveforms for
switched reluctance gate drive signals. The low side PWM
signals from the three-phase timing unit assume permanently
ON states, independent of the value written to the duty-cycle
registers. The duty cycles of the high side PWM signals from the
timing unit are still determined by the three duty-cycle registers.
If boot loading from an E2PROM is unsuccessful, the monitor
code reconfigures SPORT1 as a UART and attempts to receive
commands from an external device on this serial port. The
monitor then waits for a byte to be received over SPORT1,
locks onto the baud rate of the external device (autobaud fea-
ture) and takes in a header word that tells it with what type of
device it is communicating. There are six alternatives:
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low
side output and the signal destined for the low side switch is
diverted to the corresponding high side output signal.
• A UART boot loader such as a Motorola 68HC11SCI port.
• A synchronous slave boot loader (the clock is external).
• A synchronous master boot loader (the ADMC331 provides the
clock).
• A UART debugger interface.
• A synchronous master debugger interface.
• A synchronous slave debugger interface.
With the debugger interface, the monitor enters an interactive
mode in which it processes commands received from the exter-
nal device.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation
techniques, optical isolation using opto-couplers, and trans-
former isolation using pulse transformers. The PWM controller
of the ADMC331 permits mixing of the output PWM signals
with a high frequency chopping signal to permit easy interface to
such pulse transformers. The features of this gate-drive chop-
ping mode can be controlled by the PWMGATE register. There
is an 8-bit value within the PWMGATE register that directly con-
trols the chopping frequency. In addition, high frequency chopping
can be independently enabled for the high side and the low side
outputs using separate control bits in the PWMGATE register.
DSP Control Registers
The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT0 is enabled when Bit 12 is
set, disabled when this bit is cleared. SPORT1 is enabled when
Bit 11 is set, disabled when this bit is cleared. SPORT1 is con-
figured as a serial port when Bit 10 is set, or as flags and inter-
rupt lines when this bit is cleared. For proper operation of the
ADMC331, all other bits in this register must be cleared (which
is their default).
The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). For proper operation of the
ADMC331, this register must always contain the value 0x8000
(which is the default).
The PWM generator is capable of operating in two distinct
modes, single update mode or double update mode. In single
update mode, the duty cycle values are programmable only once
per PWM period, so that the resultant PWM patterns are sym-
metrical about the midpoint of the PWM period. In the double
update mode, a second updating of the PWM duty cycle values
is implemented at the midpoint of the PWM period. In this
mode, it is possible to produce asymmetrical PWM patterns,
that produce lower harmonic distortion in three-phase PWM
inverters. This technique also permits the closed loop controller
to change the average voltage applied to the machine winding at
a faster rate and so permits fast closed loop bandwidths to be
achieved. The operating mode of the PWM block (single or
double update mode) is selected by a control bit in MODECTRL
register.
The configuration of both the SYSCNTL and MEMWAIT
registers of the ADMC331 is shown at the end of the data sheet.
THREE-PHASE PWM CONTROLLER
Overview
The PWM generator block of the ADMC331 is a flexible, pro-
grammable, three-phase PWM waveform generator that can be
programmed to generate the required switching patterns to drive
a three-phase voltage source inverter for ac induction (ACIM),
or permanent magnet synchronous (PMSM) or a switched or
variable reluctance (SRM) motor control. In addition, the
PWM block contains special functions that considerably sim-
plify the generation of the required PWM switching patterns for
–12–
REV. B
ADMC331
PWM CONFIGURATION PWM DUTY CYCLE
REGISTERS
REGISTERS
PWMTM (15 . . . 0)
PWMDT (9 . . . 0)
PWMPD (9 . . . 0)
PWMSYNCWT (7 . . . 0)
MODECTRL (6)
PWMCHA (15 . . . 0)
PWMCHB (15 . . . 0)
PWMCHC (15 . . . 0)
PWMSEG
PWMGATE
AH
THREE-PHASE
PWM TIMING
UNIT
AL
BH
BL
CH
CL
SWITCHED
RELUCTANCE
CONTROL
UNIT
OUTPUT
CONTROL
UNIT
GATE
DRIVE
UNIT
CLK
RESET
SYNC
SR
SYNC
CLK
POL
CLKOUT
PWMSYNC
PWMSYNC
PWMPOL
TO INTERRUPT
CONTROLLER
PWMSR
PWMTRIP
PWMTRIP
OR
PWMSWT (0)
Figure 5. Overview of the PWM Controller of the ADMC331
The PWM generator of the ADMC331 also provides an output
pulse on the PWMSYNC pin that is synchronized to the PWM
switching frequency. In single update mode, a PWMSYNC
pulse is produced at the start of each PWM period. In double
update mode, an additional PWMSYNC pulse is produced at
the midpoint of each PWM period. The width of the PWM-
SYNC pulse is programmable through the PWMSYNCWT
register.
• The Switched Reluctance Control Unit transforms the three-
phase outputs into six PWM wave forms for switched reluc-
tance gate drive signals.
• The Output Control Unit allows the redirection of the out-
puts of the Three-Phase Timing Unit for each channel to
either the high side or the low side output. In addition, the
Output Control Unit allows individual enabling/disabling of
each of the six PWM output signals.
The PWM signals produced by the ADMC331 can be shut-off
in two different ways. Firstly there is a dedicated asynchronous
PWM shutdown pin, PWMTRIP, that when brought LO, in-
stantaneously places all six PWM outputs in the OFF state (as
determined by the state of the PWMPOL pin). This hardware
shutdown mechanism is asynchronous so that the associated
PWM disable circuitry does not go through any clocked logic,
thereby ensuring correct PWM shutdown even in the event of a
loss of DSP clock. In addition to the hardware shutdown fea-
ture, the PWM system may be shutdown in software by writing
to the PWMSWT register.
• The GATE Drive Unit provides the correct polarity output
PWM signals based on the state of the PWMPOL pin. The
Gate Drive Unit also permits the generation of the high fre-
quency chopping frequency and its subsequent mixing with
the PWM signals.
The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, CLKOUT, and is capable of gener-
ating two interrupts to the DSP core. One interrupt is gener-
ated on the occurrence of a PWMSYNC pulse and the other is
generated on the occurrence of any PWM shutdown action.
Three-Phase Timing Unit
Status information about the PWM system of the ADMC331 is
available to the user in the SYSSTAT register. In particular,
the state of the PWMTRIP, PWMPOL and PWMSR pins is
available, as well as a status bit that indicates whether operation
is in the first half or the second half of the PWM period.
The 16-bit three-phase timing unit is the core of the PWM
controller and produces three pair of pulsewidth modulated
signals with high resolution and minimal processor overhead.
The outputs of this timing unit are active LO such that a low
level is interpreted as a command to turn ON the associated
power device. There are four main configuration registers
(PWMTM, PWMDT, PWMPD and PWMSYNCWT) that
determine the fundamental characteristics of the PWM outputs.
In addition, the operating mode of the PWM (single or double
update mode) is selected by Bit 6 of the MODECTRL register.
A functional block diagram of the PWM controller is shown in
Figure 5. The generation of the six output PWM signals on
pins AH to CL is controlled by four important blocks:
• The Three-Phase PWM Timing Unit, which is the core of the
PWM controller, generates three pairs of complemented and
dead time adjusted center based PWM signals.
REV. B
–13–
ADMC331
These registers, in conjunction with the three 16-bit duty-cycle
registers (PWMCHA, PWMCHB and PWMCHC), control the
output of the three-phase timing unit.
(=1023) corresponding to a maximum programmed dead time
of:
T
D,max = 1023 × 2 × tCK = 1023 × 2 × 38.46 × 10–9 = 78.69 µs
PWM Switching Frequency, PWMTM Register
for a CLKOUT rate of 26 MHz. Obviously, the deadtime can
be programmed to be zero by writing 0 to the PWMDT register.
The PWM switching frequency is controlled by the 16-bit read/
write PWM period register, PWMTM. The fundamental timing
unit of the PWM controller is tCK (DSP instruction rate).
Therefore, for a 26 MHz CLKOUT, the fundamental time
increment is 38.5 ns. The value written to the PWMTM regis-
ter is effectively the number of tCK clock increments in half a
PWM period. The required PWMTM value is a function of the
desired PWM switching frequency (fPWM) and is given by:
PWM Operating Mode, MODECTRL and SYSSTAT Registers
The PWM controller of the ADMC331 can operate in two
distinct modes: single update mode and double update mode.
The operating mode of the PWM controller is determined by
the state of Bit 6 of the MODECTRL register. If this bit is
cleared, the PWM operates in the single update mode. Setting
Bit 6 places the PWM in the double update mode. By default,
following either a peripheral reset or power on, Bit 6 of the
MODECTRL register is cleared so that the default operating
mode is in single update mode.
fCLKOUT fCLKIN
2× fPWM fPWM
PWMTM =
=
Therefore, the PWM switching period, TS, can be written as:
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle and is used to latch new values from
the PWM configuration registers (PWMTM, PWMDT, PWMPD
and PWMSYNCWT) and the PWM duty-cycle registers
(PWMCHA, PWMCHB and PWMCHC) into the three-phase
timing unit. In addition, the PWMSEG register is also latched
into the output control unit on the rising edge of the PWMSYNC
pulse. In effect, this means that the characteristics and resultant
duty cycles of the PWM signals can be updated only once per
PWM period at the start of each cycle. The result is that PWM
patterns that are symmetrical about the midpoint of the switch-
ing period are produced.
TS = 2× PWMTM ×tCK
For example, for a 26 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (TS = 100 µs), the correct value
to load into the PWMTM register is:
26 ×106
2×10 ×103
PWMTM =
=1300
The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535 which corresponds to a minimum
PWM switching frequency of:
26 ×106
2×65,535
In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The rising
edge of this new PWMSYNC pulse is again used to latch new
values of the PWM configuration registers, duty-cycle registers
and the PWMSEG register. As a result it is possible to alter
both the characteristics (switching frequency, dead time, minimum
pulsewidth and PWMSYNC pulsewidth) as well as the output
duty cycles at the midpoint of each PWM cycle. Consequently, it is
possible to produce PWM switching patterns that are no longer
symmetrical about the midpoint of the period (asymmetrical
PWM patterns).
fPWM,min
=
=198.4 Hz
PWM Switching Dead Time, PWMDT Register
The second important parameter that must be set up in the
initial configuration of the PWM block is the switching dead
time. That is a short delay time introduced between turning off
one PWM signal (AH) and turning on the complementary sig-
nal, AL. This short time delay is introduced to permit the
power switch being turned off (AH in this case) to completely
recover its blocking capability before the complementary switch
is turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link ca-
pacitor of a typical voltage source inverter.
In the double update mode, it may be necessary to know whether
operation at any point in time is in either the first half or the
second half of the PWM cycle. This information is provided by
Bit 3 of the SYSSTAT register, which is cleared during opera-
tion in the first half of each PWM period (between the rising
edge of the original PWMSYNC pulse and the rising edge of
the new PWMSYNC pulse introduced in double update mode).
Bit 3 of the SYSSTAT register is set during operation in the
second half of each PWM period. This status bit allows the user
to make a determination of the particular half-cycle during
implementation of the PWMSYNC interrupt service routine, if
required.
The dead time is controlled by the 10-bit, read/write PWMDT
register. There is only one dead time register that controls the
dead time inserted into the three pairs of PWM output signals.
The dead time, TD, is related to the value in the PWMDT regis-
ter by:
TD = PWMTM ×2×tCK
Therefore, a PWMDT value of 0x00A (= 10), introduces a
769.2 ns delay between the turn-off on any PWM signal (AH)
and the turn-on of its complementary signal (AL). The amount
of the dead time can therefore be programmed in increments of
2 tCK (or 76.92 ns for a 26 MHz CLKOUT). The PWMDT
register is a 10-bit register so that its maximum value is 0x3FF
The advantage of the double update mode is that lower har-
monic voltages can be produced by the PWM process and faster
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Since new duty cycle values
must be computed in each PWMSYNC interrupt service rou-
tine, there is a larger computational burden on the DSP in the
double update mode.
–14–
REV. B
ADMC331
PWMCHA
PWMCHA
Width of the PWMSYNC Pulse, PWMSYNCWT Register
The PWM controller of the ADMC331 produces an output
PWM synchronization pulse at a rate equal to the PWM switch-
ing frequency in single update mode and at twice the PWM
frequency in the double update mode. This pulse is available
for external use at the PWMSYNC pin. The width of this
PWMSYNC pulse is programmable by the 8-bit read/write
PWMSYNCWT register. The width of the PWMSYNC pulse,
TPWMSYNC, is given by:
AH
2 ꢀ PWMDT
2 ꢀ PWMDT
AL
PWMSYNCWT + 1
PWMSYNC
SYSSTAT (3)
T
PWMSYNC = tCK × (PWMSYNCWT + 1)
PWMTM
PWMTM
so that the width of the pulse is programmable from tCK to 256 tCK
(corresponding to 38.5 ns to 9.84 µs for a CLKOUT rate of
26 MHz). Following a reset, the PWMSYNCWT register con-
tains 0x27 (= 39) so that the default PWMSYNC width is
1.54 µs, again for a 26 MHz CLKOUT.
Figure 6. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode (Active LO Waveforms)
The resultant on-times of the PWM signals in Figure 6 may be
written as:
PWM Duty Cycles, PWMCHA, PWMCHB, PWMCHC
Registers
T
AH = 2 × (PWMCHA – PWMDT) × tCK
TAL = 2 × (PWMTM–PWMCHA–PWMDT) × tCK
The duty cycles of the six PWM output signals on pins AH to
CL are controlled by the three 16-bit read/write duty-cycle
registers, PWMCHA, PWMCHB, and PWMCHC. The integer
value in the register PWMCHA controls the duty cycle of the
signals on AH and AL, in PWMCHB, controls the duty cycle of
the signals on BH and BL and in PWMCHC, controls the duty
cycle of the signals on CH and CL. The duty-cycle registers are
programmed in integer counts of the fundamental time unit,
tCK, and define the desired on-time of the high side PWM signal
produced by the three-phase timing unit over half the PWM
period. The switching signals produced by the three-phase
timing unit are also adjusted to incorporate the programmed
dead time value in the PWMDT register. The three-phase
timing unit produces active LO signals so that a LO level corre-
sponds to a command to turn on the associated power device.
and the corresponding duty cycles are:
TAH PWMCHA – PWMDT
dAH
=
=
TS
PWMTM
TAL PWMTM – PWMCHA – PWMDT
dAL
=
=
TS
PWMTM
The output signals from the timing unit for operation in double
update mode are shown in Figure 7. This illustrates a com-
pletely general case where the switching frequency, dead time
and duty cycle are all changed in the second half of the PWM
period. Of course, the same value for any or all of these quanti-
ties could be used in both halves of the PWM cycle. However,
it can be seen that there is no guarantee that symmetrical PWM
signal will be produced by the timing unit in this double update
mode. Additionally, it is seen that the dead time is inserted into
the PWM signals in the same way as in the single update mode.
A typical pair of PWM outputs (in this case for AH and AL)
from the timing unit are shown in Figure 6 for operation in
single update mode. All illustrated time values indicate the
integer value in the associated register and can be converted to
time simply by multiplying by the fundamental time increment,
PWMCHA
PWMCHA
1
2
t
CK. Firstly, it is noted that the switching patterns are perfectly
symmetrical about the midpoint of the switching period in
this single update mode since the same values of PWMCHA,
PWMTM and PWMDT are used to define the signals in both
half cycles of the period. It can be seen how the programmed
duty cycles are adjusted to incorporate the desired dead time
into the resultant pair of PWM signals. Clearly, the dead time is
incorporated by moving the switching instants of both PWM
signals (AH and AL) away from the instant set by the PWMCHA
register. Both switching edges are moved by an equal amount
(PWMDT × tCK) to preserve the symmetrical output patterns.
Also shown is the PWMSYNC pulse whose width is set by the
PWMSYNCWT register and Bit 3 of the SYSSTAT register,
which indicates whether operation is in the first or second half
cycle of the PWM period.
AH
2 ꢀ PWMDT
2 ꢀ PWMDT
2
1
AL
PWMSYNC
PWMSYNCWT + 1
1
PWMSYNCWT + 1
2
SYSSTAT (3)
PWMTM
1
PWMTM
2
Figure 7. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode (Active LO Waveforms)
In general, the on-times of the PWM signals in double update
mode can be defined as:
Obviously negative values of TAH and TAL are not permitted and
the minimum permissible value is zero, corresponding to a 0%
duty cycle. In a similar fashion, the maximum value is TS,
corresponding to a 100% duty cycle.
TAH = PWMCHA1 + PWMCHA2 − PWMDT1 − PWMDT2 × tCK
(
)
TAL = (PWMTM1 + PWMTM2 – PWMCHA1 – PWMCHA2
–PWMDT1 – PWMDT2 ) × tCLK
REV. B
–15–
ADMC331
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
power semiconductor devices. Therefore, if the width of any of
the PWM signals goes below some minimum value, it may be
desirable to completely eliminate the PWM switching for that
particular cycle.
TAH (PWMCHA1 + PWMCHA2 – PWMDT1 – PWMDT2)
dAL
=
=
TS
(PWMTM1 + PWMTM2)
The allowable minimum on-time for any of the six PWM out-
puts over half a PWM period that can be produced by the PWM
controller may be programmed using the 10-bit read/write
PWMPD register. The minimum on-time is programmed in
increments of tCK so that the minimum on-time that will be
produced over any half PWM period, TMIN, is related to the
value in the PWMPD register by:
TAL (PWMTM1 + PWMTM2 – PWMCHA1 – PWMCHA2 – PWMDT1 – PWMDT2)
dAL
=
=
TS
(PWMTM1 + PWMTM2)
since for the completely general case in double update mode,
the switching period is given by:
TS =(PWMTM1 + PWMTM2)×tCK
Again, the values of TAH and TAL are constrained to lie between
zero and TS.
TMIN = PWMPD ×tCK
so that a PWMPD value of 0x002 defines a permissible mini-
mum on-time of 76.9 ns for a 26 MHz CLKOUT.
Similar PWM signals to those illustrated in Figure 6 and Fig-
ure 7 can be produced on the BH, BL, CH and CL outputs by
programming the PWMCHB and PWMCHC registers in a man-
ner identical to that described for PWMCHA.
In each half cycle of the PWM, the timing unit checks the on-
time of each of the six PWM signals. If any of the times are
found to be less than the value specified by the PWMPD regis-
ter, the corresponding PWM signal is turned OFF for the entire
half period and its complementary signal is turned completely
ON.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB and PWMCHC
registers have been written to at least once. Once these registers
have been written, internal counting of the timers in the three-
phase timing unit is enabled.
Consider the example where PWMTM = 200, PWMCHA = 5,
PWMDT = 3, PWMPD = 10 with a CLKOUT of 26 MHz
and operation in single update mode. In this case, the PWM
switching frequency is 65 kHz and the dead time is 230 ns.
The permissible on-time of any PWM signal over one half of
any period is 384.6 ns. Clearly, for this example, the dead
time adjusted on-time of the AH signal over half a PWM
period is (5–3) × 38.5 ns = 77 ns. This is less than the permis-
sible value, so the timing unit will output a completely OFF
(0% duty cycle) signal on AH. Additionally, the AL signal will
be turned ON for the entire half period (100% duty cycle).
Effective PWM Resolution
In single update mode, the same value of PWMCHA, PWM-
CHB and PWMCHC are used to define the on-times in both
half cycles of the PWM period. As a result, the effective resolu-
tion of the PWM generation process is 2 tCK (or 76.9 ns for a
26 MHz CLKOUT) since incrementing one of the duty-cycle
registers by 1 changes the resultant on-time of the associated
PWM signals by tCK in each half period (or 2 tCK for the full
period).
In double update mode, improved resolution is possible since
different values of the duty cycles registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of tCK. This corresponds to an effective
PWM resolution of tCK in double update mode (or 38.5 ns for a
26 MHz CLKOUT).
Switched Reluctance Mode
The PWM block of the ADMC331 contains a switched reluc-
tance mode that is controlled by the state of the PWMSR pin.
The switched reluctance (SR) mode is enabled by connecting
the PWMSR pin to GND. In this SR mode, the low side PWM
signals from the three-phase timing unit assume permanently
ON states, independent of the value written to the duty-cycle
registers. The duty cycles of the high side PWM signals from
the timing unit are still determined by the three duty-cycle regis-
ters. Using the crossover feature of the output control unit, it is
possible to divert the permanently ON PWM signals to either
the high side or the low side outputs. This mode is necessary
because in the typical power converter configuration for switched
or variable reluctance motors, the motor winding is connected
between the two power switches of a given inverter leg. There-
fore, in order to build up current in the motor winding, it is
necessary to turn on both switches at the same time. Typical
active LO PWM signals during operation in SR mode are shown
in Figure 8 for operation in double update mode. It is clear that
the three low side signals (AL, BL and CL) are permanently ON
and the three high side signals are modulated so that the corre-
sponding high side power switches are switched between the ON
and OFF states.
The achievable PWM switching frequency at a given PWM
resolution is tabulated in Table V.
Table V. Achievable PWM Resolution in Single and Double
Update Modes
Resolution Single Update Mode
Double Update Mode
PWM Frequency (kHz)
(Bit)
PWM Frequency (kHz)
8
9
10
11
12
50.7
25.4
12.7
6.3
101.5
50.7
25.4
12.7
6.3
3.2
Minimum Pulsewidth, PWMPD Register
In many power converter switching applications, it is desirable
to eliminate PWM switching signals below a certain width. It
takes a certain finite time to both turn on and turn off modern
–16–
REV. B
ADMC331
In a manner identical to the duty-cycle registers, the PWMSEG
is latched on the rising edge of the PWMSYNC signal so that
the changes to this register only become effective at the start of
each PWM cycle in single update mode. In double update mode,
the PWMSEG register can also be updated at the midpoint of
the PWM cycle.
PWMCHA
1
PWMCHA
2
AH
AL
PWMCHB
2
PWMCHB
1
BH
BL
In the control of an ECM, only two inverter legs are switched
at any time and often the high side device in one leg must be
switched ON at the same time as the low side driver in a second
leg. Therefore, by programming identical duty cycles values for
two PWM channels (i.e., PWMCHA = PWMCHB) and setting
Bit 7 of the PWMSEG register to crossover the BH/BL pair if
PWM signals, it is possible to turn ON the high side switch of
phase A and the low side switch of Phase B at the same time.
In the control of ECM, it is usual that the third inverter leg
(Phase C in this example) be permanently disabled for a number
of PWM cycles. This function is implemented by disabling both
the CH and CL PWM outputs by setting Bits 0 and 1 of the
PWMSEG register. This situation is illustrated in Figure 9
where it can be seen that both the AH and BL signals are identi-
cal, since PWMCHA = PWMCHB and the crossover bit for
Phase B is set. In addition, the other four signals (AL, BH, CH
and CL) have been disabled by setting the appropriate enable/
disable bits of the PWMSEG register. For the situation illus-
trated in Figure 9, the appropriate value for the PWMSEG
register is 0x00A7. In normal ECM operation, each inverter leg
is disabled for certain periods of time, so that the PWMSEG
register is changed based on the position of the rotor shaft
(motor commutation).
PWMCHC
PWMCHC
1
2
CH
CL
PWMTM
1
PWMTM
2
Figure 8. Active LO PWM signals in SR Mode (PWMPOL =
PWMSR = GND) for ADMC331 in double update mode.
The signals from the three-phase unit are not crossed over
(PWMSEG = 0) and the dead time is zero (PWMDT = 0).
The SR mode can only be enabled by connecting the PWMSR
pin to GND. There is no software means by which this mode
can be enabled. There is an internal pull-up resistor on the
PWMSR pin so that if this pin is left unconnected or becomes
disconnected the SR mode is disabled. Of course, the SR mode
is disabled when the PWMSR pin is tied to VDD. The state of
the PWMSR pin may be read from Bit 4 of the SYSSTAT
register.
Output Control Unit, PWMSEG Register
The operation of the Output Control Unit is controlled by the
9-bit read/write PWMSEG register that controls two distinct
features that are directly useful in the control of ECM or BDCM.
PWMCHA
= PWMCHB
PWMCHA
= PWMCHB
The PWMSEG register contains three crossover bits, one for
each pair of PWM outputs. Setting Bit 8 of the PWMSEG
register enables the crossover mode for the AH/AL pair of PWM
signals; setting Bit 7 enables crossover on the BH/BL pair of
PWM signals; setting Bit 6 enables crossover on the CH/CL
pair of PWM signals. If crossover mode is enabled for any pair
of PWM signals, the high side PWM signal from the timing unit
(i.e. AH) is diverted to the associated low side output of the
Output Control Unit so that the signal will ultimately appear at
the AL pin. Of course, the corresponding low side output of the
Timing Unit is also diverted to the complementary high side
output of the Output Control Unit so that the signal appears at
the AH pin. Following a reset, the three crossover bits are
cleared so that the crossover mode is disabled on all three pairs
of PWM signals.
AH
2 ꢀ PWMDT
2 ꢀ PWMDT
AL
BH
BL
CH
CL
PWMTM
PWMTM
Figure 9. Example active LO PWM signals suitable for
ECM control, PWMCHA = PWMCHB, crossover BH/BL pair
and disable AL, BH, CH and CL outputs. Operation is in
single update mode.
The PWMSEG register also contains six bits (Bits 0 to 5) that
can be used to individually enable or disable each of the six
PWM outputs. The PWM signal of the AL pin is enabled by
setting Bit 5 of the PWMSEG register while Bit 4 controls AH,
Bit 3 controls BL, Bit 2 controls BH, Bit 1 controls CL and
Bit 0 controls the CH output. If the associated bit of the
PWMSEG register is set, then the corresponding PWM output
is disabled irrespective of the value of the corresponding duty
cycle register. This PWM output signal will remain in the OFF
state as long as the corresponding enable/disable bit of the
PWMSEG register is set. The implementation of this output
enable function is implemented after the crossover function.
Following a reset, all six enable bits of the PWMSEG register
are cleared so that all PWM outputs are enabled by default.
Gate Drive Unit, PWMGATE Register
The Gate Drive Unit of the PWM controller adds features
that simplify the design of isolated gate drive circuits for
PWM inverters. If a transformer-coupled power device gate
driver amplifier is used, the active PWM signals must be
chopped at a high frequency. The 10-bit read/write PWMGATE
register allows the programming of this high frequency chopping
mode. The chopped active PWM signals may be required for
the high side drivers only, for the low side drivers only or for
both the high side and low side switches. Therefore, indepen-
dent control of this mode for both high and low side switches is
REV. B
–17–
ADMC331
included with two separate control bits in the PWMGATE
register.
The state of the PWMTRIP pin can be read from Bit 0 of the
SYSSTAT register.
Typical PWM output signals with high frequency chopping
enabled on both high side and low side signals are shown in
Figure 10. Chopping of the high side PWM outputs (AH, BH
and CH) is enabled by setting Bit 8 of the PWMGATE register.
Chopping of the low side PWM outputs (AL, BL and CL) is
enabled by setting Bit 9 of the PWMGATE register. The high
frequency chopping frequency is controlled by the 8-bit word
(GDCLK) placed in Bits 0 to 7 of the PWMGATE register.
The period of this high frequency carrier is:
In addition, it is possible to initiate a PWM shutdown in soft-
ware by writing to the 1-bit read/write PWMSWT register. The
act of writing to this register generates a PWM shutdown com-
mand in a manner identical to the PWMTRIP pin. It does not
matter which value is written to the PWMSWT register. How-
ever, following a PWM shutdown, it is possible to read the
PWMSWT register to determine if the shutdown was generated
by hardware or software. Reading the PWMSWT register auto-
matically clears its contents.
On the occurrence of a PWM shutdown command (either from
the PWMTRIP pin or the PWMSWT register), a PWMTRIP
interrupt will be generated. In addition, internal timing of the
three-phase timing unit of the PWM controller is stopped. Fol-
lowing a PWM shutdown, the PWM can only be re-enabled (in
a PWMTRIP interrupt service routine, for example) by writing
to all of the PWMTM, PWMCHA, PWMCHB and PWMCHC
registers. Provided the external fault has been cleared and the
PWMTRIP has returned to a HI level, internal timing of the
three-phase timing unit resumes and new duty cycle values are
latched on the next PWMSYNC boundary.
TCHOP =[4×(GDCLK +1)]×tCK
fCLKOUT
[4×(GDCLK +1)]
fCHOP
=
The GDCLK value may range from 0 to 255, corresponding to
a programmable chopping frequency rate from 25.39 kHz to
6.5 MHz for a 26 MHz CLKOUT rate. The gate drive features
must be programmed before operation of the PWM controller
and typically are not changed during normal operation of the
PWM controller. Following a reset, all bits of the PWMGATE
register are cleared so that high frequency chopping is disabled,
by default.
PWM Registers
The configuration of the PWM registers is described at the end
of the data sheet.
PWMCHA
PWMCHA
ADC OVERVIEW
The Analog Input Block of the ADMC331 is a 7-channel single
slope Analog Data Acquisition System with 12-bit resolution.
Data Conversion is performed by timing the crossover between
the Analog Input and Sawtooth Reference Ramp. A simple
voltage comparator detects the crossover and latches the timed
counter value into a channel-specific output register
2 ꢀ PWMDT
2 ꢀ PWMDT
[4 ꢀ (GDCLK+1) ꢀ t
]
CK
PWMTM
PWMTM
Figure 10. Typical Active LO PWM Signals with High Fre-
quency Gate Chopping Enabled on Both High Side and
Low Side Switches
The ADC system is comprised of seven input channels to the ADC
of which three (V1, V2, V3) have dedicated comparators. The
remaining four channels (VAUX0, VAUX1, VAUX2, VAUX3)
are multiplexed into the fourth comparator and are selected using
the ADCMUX0 and ADCMUX1 bits of the MODECTRL regis-
ter (Table VI). This allows four conversions to be performed by the
ADC between successive PWMSYNC pulses.
PWM Polarity Control, PWMPOL Pin
The polarity of the PWM signals produced at the output pins
AH to CL may be selected in hardware by the PWMPOL pin.
Connecting the PWMPOL pin to GND selects active LO PWM
outputs, such that a LO level is interpreted as a command to
turn on the associated power device. Conversely, connecting
VDD to PWMPOL pin selects active HI PWM and the associ-
ated power devices are turned ON by a HI level at the PWM
outputs. There is an internal pull-up on the PWMPOL pin, so
that if this pin becomes disconnected (or is not connected),
active HI PWM will be produced. The level on the PWMPOL
pin may be read from Bit 2 of the SYSSTAT register, where a
zero indicated a measure LO level at the PWMPOL pin.
Table VI. ADC Auxiliary Channel Selection
MODECTRL (1)
ADCMUX1
MODECTRL (0)
ADCMUX0
Select
VAUX0
VAUX1
VAUX2
VAUX3
0
0
1
1
0
1
0
1
PWM Shutdown
Analog Block
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down in a safe fashion. A
falling edge on the PWMTRIP pin provides an instantaneous,
asynchronous (independent of the DSP clock) shutdown of the
PWM controller. All six PWM outputs are placed in the OFF
state (as defined by the PWMPOL pin). In addition, the PWM-
SYNC pulse is disabled and the associated interrupt is stopped.
The PWMTRIP pin has an internal pull-down resistor so that
if the pin becomes disconnected the PWM will be disabled.
The operation of the ADC block may be explained by reference
to Figures 11 and 12. The reference ramp is tied to one input of
each of the four comparators. This reference ramp is generated
by charging an external timing capacitor with a constant current
source. The timing capacitor is connected between pins CAPIN
and SGND. The capacitor voltage is reset at the start of each
PWMSYNC pulse, which by default is held high for 40 CLKOUT
cycles (TCRST = 1.54 µs for a 26 MHz CLKOUT). On the fall-
ing edge of PWMSYNC, the capacitor begins to charge at a rate
–18–
REV. B
ADMC331
determined by the capacitor and the current source values. An
internal current source is made available for connection to the
external timing capacitor on the ICONST pin. An external
current source could also be used, if required. The four input
comparators of the ADC block continuously compare the values
of the four analog inputs with the capacitor voltage. Each com-
parator output will go high when the capacitor voltage exceeds
the respective analog input voltage.
V
C
V
CMAX
V1
V
VIL
ADC Timer Block
t
The ADC timer block consists of a 12-bit counter clocked at a
rate determined by the ADCCNT bit in the MODECTRL
register. If ADCCNT is 0, the counter is clocked at twice the
CLKOUT period, or if ADCCNT is 1, the counter is clocked
at the CLKOUT period. Thus at the maximum CLKOUT
frequency of 26 MHz, this gives a timer resolution of 76.9 ns
when ADCCNT is 0, and 38.5 ns when ADCCNT is 1. The
counter is reset during the high PWMSYNC pulse so that the
counter commences at the beginning of the reference voltage
ramp. When the output of a given comparator goes high, the
counter value is latched into the appropriate 12-bit ADC regis-
ter. There are four pair of ADC registers (ADC1, ADC2,
ADC3 and ADCAUX) corresponding to each of the four com-
parators. Each comparator’s register pair is organized as master/
slave or master/shadow. At the end of the reference voltage ramp,
which is prior to the next PWMSYNC, all four master registers
have been loaded with the new conversion count. At the rising edge
of the PWMSYNC, the registered conversion count for each chan-
nel is loaded into the DSP readable shadow registers, ADC1,
ADC2, ADC3, and ADCAUX. The controller will then read
these shadow registers containing the previous PWM period
conversion count, while internally the master registers will be
loaded with the current PWM period conversion count.
tVIL
T
CRST
T
– T
CRST
PWM
PWMSYNC
COMPARATOR
OUTPUT
Figure 12. Analog Input Block Operation
ADC Resolution
Because the operation of the ADC is intrinsically linked to the
PWM block, the effective resolution of the ADC is a function of
the PWM switching frequency. The effective ADC resolution is
determined by the rate at which the counter timer is clocked,
which is selectable by the ADCCNT Bit 7 in MODECTRL
register. For a CLKOUT period of tCK and a PWM period of
T
PWM, the maximum count of the ADC is given by:
Max Count = min (4095, (TPWM – TCRST)/2 tCK
Max Count = min (4095, (TPWM – TCRST)/tCK
MODECTRL Bit 7 = 0
MODECTRL Bit 7 = 1
For an assumed CLKOUT frequency of 26 MHz and PWM-
SYNC pulsewidth of 1.54 µs, the effective resolution of the
ADC block is tabulated for various PWM switching frequencies
in Table VII.
The first set of values loaded into the output registers after the
first PWMSYNC interrupt will be invalid since the latched value
is indeterminate. Also, if the input analog voltage exceeds the
peak capacitor ramp voltage, the comparator output will be
permanently low and a 0xFFF0 code will be produced. This
indicates an input overvoltage condition.
Table VII. ADC Resolution Examples
PWM
Freq. Max
MODECTRL[7] = 0
MODECTRL[7] = 1
Effective
Max
Effective
(kHz) Count
Resolution Count
Resolution
VREF
ICONST
2.5
4
8
18
24
4095
3230
1605
702
12
4095
4095
3210
1404
1043
12
12
>11
>10
>10
CAPIN
>11
>10
>9
PWMSYNC
C
MODECTRL (7)
ADC
REGISTERS
SGND
521
>9
ADC1
ADC2
V1
V2
V3
External Timing Capacitor
ADC
TIMER
BLOCK
In order to maximize the useful input voltage range and effective
resolution of the ADC, it is necessary to carefully select the
value of the external timing capacitor. For a given capacitance
value, CNOM, the peak ramp voltage is given by:
ADC3
ADCAUX
VAUX0
VAUX1
VAUX2
VAUX3
4-1
MUX
ADMUX0
ADMUX1
I
CONST (TPWM –TCRST )
CLKOUT
VC max =
CNOM
Figure 11. ADC Overview
where ICONST is the nominal current source value of 13.5 µA and
CRST is the PWMSYNC pulsewidth. In selecting the capacitor
T
value, however, it is necessary to take into account the tolerance
of the capacitor and the variation of the current source value.
REV. B
–19–
ADMC331
To ensure that the full input range of the ADC is utilized, it is
necessary to select the capacitor so that at the maximum capaci-
tance value and the minimum current source output, the ramp
voltage will charge to at least 3.5 V.
independent mode. In this mode, the two auxiliary PWM gen-
erators are completely independent and separate switching fre-
quencies and duty cycles may be programmed for each auxiliary
PWM output. In this mode, the 8-bit AUXTM0 register sets
the switching frequency of the signal at the AUX0 output pin.
Similarly, the 8-bit AUXTM1 register sets the switching of the
signal at the AUX1 pin. The fundamental time increment for
the auxiliary PWM outputs is twice the DSP instruction rate (or
2 tCK) so that the corresponding switching periods are given by:
As a result, assuming 10% variations in both the capacitance
and current source, the nominal capacitance value required at a
given PWM period is:
(0.9× ICONST )(TPWM –TCRST
)
CNOM
=
TAUX0 = 2 × (AUXTM0 + 1) × tCK
TAUX1 = 2 × (AUXTM1 + 1) × tCK
(1.1)(3.5)
The largest standard value capacitor that is less than this calcu-
lated value is chosen. Table VIII shows the appropriate standard
capacitor value to use for various PWM switching frequencies
assuming 10% variations in both the current source and ca-
pacitor tolerances. If required, more precise control of the ramp
voltage is possible by using higher precision capacitor compo-
nents, an external current source and/or series or parallel timing
capacitor combinations.
Since the values in both AUXTM0 and AUXTM1 can range
from 0 to 0xFF, the achievable switching frequency of the auxil-
iary PWM signals may range from 50.8 kHz to 13 MHz for a
CLKOUT frequency of 26 MHz.
The on-time of the two auxiliary PWM signals is programmed
by the two 8-bit AUXCH0 and AUXCH1 registers, according
to:
TON
TON
,
,
AUX0 = 2 × (AUXCH0) × tCK
AUX1 = 2 × (AUXCH1) × tCK
Table VIII. Timing Capacitor Selection
PWM Frequency
(kHz)
PWM Frequency
(kHz)
Timing
Capacitor
(pF)
so that output duty cycles from 0% to 100% are possible. Duty
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in independent
mode are shown in Figure 13(a).
MODECTRL[6] = 0
MODECTRL[6] = 1
2.1–2.7
2.7–3.2
3.2–3.9
3.9–4.7
4.7–5.6
5.6–6.7
6.7–8.0
8.0–9.5
9.5–11.5
11.5–14.1
14.1–17.1
17.1–20.4
20.4–25.3
25.3–30.1
4.2–5.2
5.2–6.3
6.3–7.7
7.7–9.2
9.2–11.2
11.2–13.3
13.3–16.0
16.0–18.8
18.8–23.0
23.0–28.1
28.1–34.1
34.1–40.8
40.8–50.6
50.6–60.2
1500
1200
1000
820
680
560
470
390
330
270
220
180
150
120
When Bit 8 of the MODECTRL register is cleared, the auxiliary
PWM channels are placed in offset mode. In offset mode, the
switching frequency of the two signals on the AUX0 and AUX1
pins are identical and controlled by AUXTM0 in a manner
similar to that previously described for independent mode. In
addition, the on times of both the AUX0 and AUX1 signals are
controlled by the AUXCH0 and AUXCH1 registers as before.
However, in this mode the AUXTM1 register defines the offset
time from the rising edge of the signal on the AUX0 pin to that
on the AUX1 pin according to:
T
OFFSET = 2 × (AUXTM1 + 1) × tCK
For correct operation in this mode, the value written to the
AUXTM1 register must be less than the value written to the
AUXTM0 register. Typical auxiliary PWM waveforms in offset
mode are shown in Figure 13(b). Again, duty cycles from 0% to
100% are possible in this mode.
ADC Registers
The configuration of all registers of the ADC System is shown
at the end of the data sheet.
In both operating modes, the resolution of the auxiliary PWM
system is 8-bit only at the minimum switching frequency
(AUXTM0 = AUXTM1 = 255 in independent mode, AUXTM0
= 255 in offset mode). Obviously as the switching frequency is
increased the resolution is reduced.
AUXILIARY PWM TIMERS
Overview
The ADMC331 provides two variable-frequency, variable duty
cycle, 8-bit, auxiliary PWM outputs that are available at the
AUX1 and AUX0 pins. These auxiliary PWM outputs can be
used to provide switching signals to other circuits in a typical
motor control system such as power factor corrected front-end
converters or other switching power converters. Alternatively,
by addition of a suitable filter network, the auxiliary PWM out-
put signals can be used as simple single-bit digital-to-analog
converters.
Values can be written to the auxiliary PWM registers at any
time. However, new duty cycle values written to the AUXCH0
and AUXCH1 registers only become effective at the start of the
next cycle. Writing to the AUXTM0 or AUXTM1 registers
cause the internal timers to be reset to 0 and new PWM cycles
begin.
By default, following power on or a reset, Bit 8 of the
MODECTRL register is cleared so that offset mode is enabled.
In addition, the registers AUXTM0 and AUXTM1 default to
0xFF, corresponding to minimum switching frequency and zero
offset. In addition, the on-time registers AUXCH0 and AUXCH1
default to 0x00.
The auxiliary PWM system of the ADMC331 can operate in
two different modes, independent mode or offset mode. The
operating mode of the auxiliary PWM system is controlled
by Bit 8 of the MODECTRL register. Setting Bit 8 of the
MODECTRL register places the auxiliary PWM system in the
–20–
REV. B
ADMC331
(shorter than the programmed WDTIMER period value). On all
but the first write to WDTIMER, the particular value written to
the register is unimportant since writing to WDTIMER simply
reloads the first value written to this register. The WDTIMER
register is memory mapped to data memory at location 0x2018.
2 ꢀ (AUXTM0 + 1)
2 ꢀ AUXCH0
AUX0
AUX1
(A)
2 ꢀ (AUXTM1 + 1)
AUXCH1
PROGRAMMABLE DIGITAL INPUT/OUTPUT
The ADMC331 has 24 programmable digital I/O (PIO) pins:
PIO0–PIO23. Each pin can be individually configurable as
either an input or an output. Input pins can also be used to
generate interrupts. Each PIO pin includes an internal pull-
down resistor.
2 ꢀ AUXCH1
2 ꢀ (AUXTM0 + 1)
2 ꢀ AUXCH0
AUX0
AUX1
The PIO pins are configured as input or output by setting the
appropriate bits in the PIODIR0, PIODIR1 and PIODIR2
registers. The read/write registers PIODATA0, PIODATA1 and
PIODATA2 are used to set the state of an output pin or read the
state of an input pin. Writing to PIODATA0, PIODATA1 and
PIODATA2 affects only the pins configured as outputs. The
default state, after an ADMC331 reset, is that all PIOs are config-
ured as inputs.
(B)
2 ꢀ (AUXTM0 + 1)
2 ꢀ AUXCH1
2 ꢀ (AUXTM1 + 1)
Figure 13. Typical Auxiliary PWM Signals in (a) Independent
Any pin can be configured as an independent edge-triggered
interrupt source. The pin must first be configured as an input
and then the appropriate bit must be set in the PIOINTEN0, or
PIOINTEN1 or PIOINTEN2 registers. A peripheral interrupt
is generated when the input level changes on any PIO pin con-
figured as an interrupt source. A PIO interrupt sets the appro-
priate bit in the PIOFLAG0, or PIOFLAG1 or PIOFLAG2
registers. The DSP peripheral interrupt service routine (ISR)
must read the PIOFLAG0, PIOFLAG1 and PIOFLAG2 regis-
ters to determine which PIO pin was the source of the PIO
interrupt. Reading the PIOFLAG0, PIOFLAG1 and PIOFLAG2
registers will clear them.
Mode and (b) Offset Mode (All Times in Increments of tCK
)
Auxiliary PWM Interface, Registers and Pins
The registers of the auxiliary PWM system are summarized at
the end of the data sheet.
PWM DAC Equation
The PWM output can be filtered in order to produce a low
frequency analog signal between 0 V to 4.98 V dc. For example,
a 2-pole filter with a 1.2 kHz cutoff frequency will sufficiently
attenuate the PWM carrier. Figure 14 shows how the filter
would be applied.
PIO Registers
PWMDAC
R1
R2
R1 = R2 = 13kꢃ
The configuration of all registers of the PIO system is shown at
the end of the data sheet.
C1 = C2 = 10nF
C1
C2
INTERRUPT CONTROL
The ADMC331 can respond to 34 different interrupt sources
with minimal overhead. Eight of these interrupts are internal
DSP core interrupts and twenty six are from the Motor Control
Peripherals. The eight DSP core interrupts are SPORT0 re-
ceive and transmit, SPORT1 receive (or IRQ0) and transmit (or
IRQ1), the internal timer and two software interrupts. The
Motor Control interrupts are the 24 peripheral I/Os and two
from the PWM (PWMSYNC pulse and PWMTRIP). All mo-
tor control interrupts are multiplexed into the DSP core via the
peripheral IRQ2 interrupt. They are also internally prioritized
and individually maskable. The start address in the interrupt
vector table for the ADMC331 interrupt sources is shown in
Table VIII. The interrupts are listed from high priority to the
lowest priority.
Figure 14. Auxiliary PWM Output Filter
WATCHDOG TIMER
The ADMC331 incorporates a watchdog timer that can perform
a full reset of the DSP and motor control peripherals in the
event of software error. The watchdog timer is enabled by writ-
ing a timeout value to the 16-bit WDTIMER register. The
timeout value represents the number of CLKIN cycles required
for the watchdog timer to count down to zero. When the
watchdog timer reaches zero, a full DSP core and motor control
peripheral reset is performed. In addition, Bit 1 of the SYSSTAT
register is set so that after a watchdog reset the ADMC331 can
determine that the reset was due to the timeout of the watchdog
timer and not an external reset. Following a watchdog reset,
Bit 1 of the SYSSTAT register may be cleared by writing zero to
the WDTIMER register. This clears the status bit but does not
enable the watchdog timer.
The PWMSYNC interrupt is triggered by a low-to-high transi-
tion on the PWMSYNC pulse. The PWMTRIP interrupt is
triggered on a high-to-low transition on the PWMTRIP pin. A
PIO interrupt is detected on any change of state (high-to-low or
low-to-high) on the PIO lines.
On reset, the watchdog timer is disabled and is only enabled
when the first timeout value is written to the WDTIMER
register. To prevent the watchdog timer from timing out, the
user must write to the WDTIMER register at regular intervals
REV. B
–21–
ADMC331
The entire interrupt control system of the ADMC331 is config-
ured and controlled by the IFC, IMASK and ICNTL registers
of the DSP core and the IRQFLAG register for the PWMSYNC
and PWMTRIP interrupts and PIOFLAG0, PIOFLAG1 and
PIOFLAG2 registers for the PIO interrupts.
On the occurrence of an interrupt, the program sequencer en-
sures that there is no latency (beyond synchronization delay)
when processing unmasked interrupts. In the case of the timer,
SPORT0, SPORT1 and software interrupts, the interrupt con-
troller automatically jumps to the appropriate location in the
interrupt vector table. At this point, a JUMP instruction to the
appropriate ISR is required.
Table IX. Interrupt Vector Addresses
Interrupt Vector
In the event of a motor control peripheral interrupt, the opera-
tion is slightly different. When a peripheral interrupt is de-
tected, a bit is set in the IRQFLAG register for PWMSYNC
and PWMTRIP or in the PIOFLAG0, or PIOFLAG1 or
PIOFLAG2 registers for a PIO interrupt, and the IRQ2 line is
pulled low until all pending interrupts are acknowledged. For
any of the twenty six peripheral interrupts, the interrupt control-
ler automatically jumps to location 0x0004 in the interrupt
vector table. Code loaded at location 0x0004 by the monitor on
reset subsequently reads the IRQFLAG register to determine if
the source of the interrupt was a PWM trip, PWMSYNC or
PIOs and vectors to the appropriate interrupt vector location.
Interrupt Source
Address
Reset
PWMTRIP
Peripheral Interrupt (IRQ2)
PWMSYNC
0x0000 (Reserved)
0x002C (Highest Priority)
0x0004
0x000C
PIO
0x0008
SPORT0 Transmit
SPORT0 Receive
Software Interrupt 1
Software Interrupt 0
SPORT1 Transmit Interrupt or IRQ1
SPORT1 Receive Interrupt or IRQ0
Timer
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028 (Lowest Priority)
The code located at location 0x0004 by the monitor on reset is
as follows:
0x0004: ASTAT = DM(IRQFLAG);
DM(IRQFLAG_SAVE) = ASTAT;
IF EQ JUMP 0x002C
Interrupt Masking
Interrupt masking (or disabling) is controlled by the IMASK
register of the DSP core. This register contains individual bits
that must be set to enable the various interrupt sources. If any
peripheral interrupt is to be enabled, the IRQ2 interrupt enable
bit (Bit 9) of the IMASK register must be set. The configuration
of the IMASK register of the ADMC331 is shown at the end of
the data sheet.
IF LT JUMP 0x000C;
At this point, a JUMP instruction to the appropriate ISR, at the
interrupt vector location shown in Table IX, is required. If
more than one interrupt occurs simultaneously, the higher prior-
ity interrupt service routine is executed. Reading the IRQFLAG
register clears the PWMTRIP and PWMSYNC bits and ac-
knowledges the interrupt, thus allowing further interrupts when
the ISR exits. When the IRQFLAG register is read, it is saved
in a data memory variable so the user ISR can check to see if
there are simultaneous PWMSYNC and PWMTRIP interrupts.
Interrupt Configuration
The IFC and ICNTL registers of the DSP core control and
configure the interrupt controller of the DSP core. The IFC
register is a 16-bit register that may be used to force and/or clear
any of the eight DSP interrupts. Bits 0 to 7 of the IFC register
may be used to clear the DSP interrupts while Bits 8 to 15 can be
used to force a corresponding interrupt. Writing to Bits 11 and 12
in IFC is the only way to create the two software interrupts.
A user’s PIO interrupt service routine must read the PIOFLAG0,
PIOFLAG1 and PIOFLAG2 registers to determine which PIO
port is the source of the interrupt. Reading PIOFLAG0,
PIOFLAG1 and PIOFLAG2 registers clear all bits in the regis-
ters and acknowledge the interrupt, thus allowing further inter-
rupts when the ISR exits.
The ICNTL register is used to configure the sensitivity (edge-
or level-) of the IRQ0, IRQ1 and IRQ2 interrupts and to enable/
disable interrupt nesting. Setting Bit 0 of ICNTL configures the
IRQ0 as edge-sensitive, while clearing the bit configures it for
level-sensitive. Bit 1 is used to configure the IRQ1 interrupt
and Bit 2 is used to configure the IRQ2 interrupt. It is recom-
mended that the IRQ2 interrupt always be configured for level-
sensitive as this ensures that no peripheral interrupts are lost.
Setting Bit 4 of the ICNTL register enables interrupt nesting.
The configuration of both IFC and ICNTL registers is shown at
the end of the data sheet.
The configuration of all these registers is shown at the end of
the data sheet.
SYSTEM CONTROLLER
The system controller block of the ADMC331 performs a num-
ber of distinct functions:
1. Manages the interface and data transfer between the DSP
core and the motor control peripherals.
2. Handles interrupts generated by the motor control periph-
Interrupt Operation
erals and generates a DSP core interrupt signal IRQ2.
Following a reset, the ROM code monitor of the ADMC331
copies a default interrupt vector table into program memory
RAM from address 0x0000 to 0x002F. Since each interrupt
source has a dedicated four-word space in this vector table, it is
possible to code short interrupt service routines (ISR) in place.
Alternatively, it may be required to insert a JUMP instruction to
the appropriate start address of the interrupt service routine if
more memory is required for the ISR.
3. Controls the ADC multiplexer select lines.
4. Enables PWMTRIP and PWMSYNC interrupts.
5. Controls the multiplexing of the SPORT1 pins to select
either DR1A or DR1B data receive pins. It also allows
configuration of SPORT1 as a UART interface.
–22–
REV. B
ADMC331
6. Controls the PWM single/double update mode.
7. Controls the ADC conversion time modes.
8. Controls the AUXPWM mode.
the RFS1/SROM pin. This is accomplished by toggling the FL1
flag using the following code segment:
SROMRESET: SET FL1;
TOGGLE FL1;
TOGGLE FL1;
RTS;
9. Contains a status register (SYSSTAT) that indicates the
state of the PWMTRIP, PWMPOL and PWMSR pins, the
watchdog timer and the PWM timer.
If successful, data will be clocked from the external device in a
continuous stream. The start of the data stream is detected by
the serial port on the RFS1 pin, which is connected internally to
the DR1 pin in this mode. If the serial load is successful, code
is downloaded and execution begins at the start of user program
memory (address 0x0030). Following a SROM/E2PROM boot
load, SPORT1 could be configured for normal synchronous
serial mode by setting the DR1SEL pin to select the DR1B data
receive pin and by clearing the UARTEN bit to return to SPORT
mode.
Failing a SROM/E2PROM boot load, the ADMC331 monitor
automatically sets the DR1SEL bit to select the DR1B pin and
remains in UARTEN mode. The monitor code then waits for a
header byte that tells it with which of the other interfaces it is to
communicate. Obviously, if a debugger interface is required on
SPORT1, it is not possible to use SPORT1 as a general purpose
synchronous serial port. If such a serial port is required, it is
recommended that SPORT0 be used.
10. Performs a reset of the motor control peripherals and con-
trol registers following a hardware, software or watchdog
initiated reset.
ADMC331
DT1
DT1
DR1
DR1A
DR1B
TFS1
TFS1
RFS1
DSP
CORE
SPORT1
RFS1/SROM
SCLK1
FL1
SCLK1
Flag Pins
UARTEN
DR1SEL
The ADMC331 provides flag pins. The alternate configuration
of SPORT1 includes a Flag In (FI) and Flag Out (FO) pin.
This alternate configuration of SPORT1 is selected by Bit 10 of
the DSP system control register, SYSCNTL at data memory
address, 0x3FFF. In the alternate configuration, the DR1 pin
(either DR1A or DR1B depending on the state of the DR1SEL
bit) becomes the FI pin and the DT1 pin becomes the FO pin.
Additionally, RFS1 is configured as the IRQ0 interrupt input
and TFS1 is configured as the IRQ1 interrupt. The serial port
clock, SCLK1, is still available in the alternate configuration.
Following boot loading from a serial memory device, it is pos-
sible to reconfigure the SPORT1 to this alternate configuration.
However, if a debugger interface is used, this configuration is
not possible as the normal serial port pins are required for
debugger communications.
MODECTRL (5 . . . 4)
Figure 15. Internal Multiplexing of SPORT1 Pins
SPORT1 Control
The ADMC331 uses SPORT1 as the default serial port for boot
loading and as the interface to the development environment.
There are two data receive pins, DR1A and DR1B, on the
ADMC331. This permits DR1A to be used as the data receive
pin when interfacing to serial ROM or E2PROM for boot load-
ing. Alternatively, if connecting through another external device
for either boot loading or interface to the development environ-
ment, the DR1B pin can be used. Both data receive pins are
multiplexed internally into the single data receive input of
SPORT1. Two control bits in the MODECTRL register control
the state of the SPORT1 pins by manipulating internal multi-
plexers in the ADMC331. The configuration of SPORT1 is
illustrated in Figure 15.
The ADMC331 also contains two software flags, FL1 and FL2.
These flags may be controlled in software and perform specific
functions on the ADMC331. The FL1 pin has already been
described and is used to perform a reset of the external memory
device via the RFS1/SROM pin. The FL2 flag is used specifi-
cally to perform a full peripheral reset of the chip (including the
watchdog timer). This is accomplished by toggling the FL2 flag
in software using the following code segment:
Bit 4 of the MODECTRL register (DR1SEL) selects between
the two data receive pins. Setting Bit 4 of MODECTRL con-
nects the DR1B pin to the internal data receive port DR1 of
SPORT1. Clearing Bit 4 connects DR1A to DR1.
Setting Bit 5 of the MODECTRL register (UARTEN) config-
ures the serial port for UART mode. In this mode, the DR1 and
RFS1 pins of the internal serial port are connected together.
Additionally, setting the UARTEN bit connects the FL1 flag of
the DSP to the external RFS1/SROM pin. In this mode, this pin
is intended to be used to reset the external serial ROM device.
PRESET: SET FL2:
TOGGLE FL2;
TOGGLE FL2;
RTS;
The monitor code in ROM automatically configures the SPORT1
pins during the boot sequence. Initially, the DR1SEL bit is
cleared and the UARTEN bit is set so that the ADMC331 first
attempts to perform a reset of the external memory device using
REV. B
–23–
ADMC331
Table X. Peripheral Register Map
Bits Used
Address
(HEX)
Offset
(Decimal)
Name
Function
0x2000
0x2001
0x2002
0x2003
0x2004
0x2005
0x2006
0x2007
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADC1
ADC2
ADC3
[15 . . . 4]
[15 . . . 4]
[15 . . . 4]
[15 . . . 4]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
[15 . . . 0]
[9 . . . 0]
[9 . . . 0]
[9 . . . 0]
[15 . . . 0]
[15 . . . 0]
ADC Results for V1
ADC Results for V2
ADC Results for V3
ADC Results for VAUX
PIO0 . . . 7 Pins Direction Setting
PIO0 . . . 7 Pins Input/Output Data
PIO0 . . . 7 Pins Interrupt Enable
PIO0 . . . 7 Pins Interrupt Status
PWM Period
ADCAUX
PIODIR0
PIODATA0
PIOINTEN0
PIOFLAG0
PWMTM
PWMDT
PWMPD
PWMGATE
PWMCHA
PWMCHB
PWMCHC
PWMSEG
AUXCH0
AUXCH1
AUXTM0
AUXTM1
0x2008
0x2009
PWM Deadtime
0x200A
0x200B
0x200C
0x200D
0x200E
0x200F
0x2010
0x2011
0x2012
0x2013
0x2014
PWM Pulse Deletion Time
PWM Gate Drive Configuration
PWM Channel A Pulsewidth
PWM Channel B Pulsewidth
PWM Channel C Pulsewidth
PWM Segment Select
AUX PWM Output 0
AUX PWM Output 1
Auxiliary PWM Frequency Value
Auxiliary PWM Frequency Value/Offset
Reserved
[8 . . . 0]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
16
17
18
19
20
0x2015
0x2016
0x2017
0x2018
21
22
23
24
MODECTRL
SYSSTAT
IRQFLAG
[8 . . . 0]
[4 . . . 0]
[1 . . . 0]
[15 . . . 0]
System Control Register
System Status
Interrupt Status
Watchdog Timer
WDTIMER
0x2019 . . . 3F
0x2040 . . . 43
0x2044
0x2045
0x2046
0x2047
0x2048
0x2049
0x204A
0x204B
0x204C . . . 4F
0x2050 . . . 5F
0x2060
25 . . . 63
64 . . . 67
68
69
70
71
72
73
74
75
76 . . . 79
80 . . . 95
96
Reserved
Reserved
PIODIR1
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
[7 . . . 0]
PIO8 . . . 15 Pins Direction Setting
PIO8 . . . 15 Pins Input/Output Data
PIO8 . . . 15 Pins Interrupt Enable
PIO8 . . . 15 Pins Interrupt Status
PIO16 . . . 23 Pins Direction Setting
PIO16 . . . 23 Pins Input/Output Data
PIO16 . . . 23 Pins Interrupt Enable
PIO16 . . . 23 Pins Interrupt Status
Reserved
PIODATA1
PIOINTEN1
PIOFLAG1
PIODIR2
PIODATA2
PIOINTEN2
PIOFLAG2
Reserved
PWMSYNC Pulsewidth
PWM S/W Trip Bit
PWMSYNCWT
PWMSWT
[7 . . . 0]
[0]
0x2061
97
0x2062 . . . FF
98 . . . 255
Reserved
–24–
REV. B
ADMC331
Table XI. DSP Core Registers
Bits
Address
Name
Function
0x3FFF
0x3FFE
0x3FFD
0x3FFC
0x3FFB
0x3FFA
0x3FF9
0x3FF8
0x3FF7
0x3FF6
0x3FF5
0x3FF4
0x3FF3
0x3FF2
0x3FF1
0x3FF0
0x3FEF
SYSCNTL
MEMWAIT
TPERIOD
TCOUNT
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[7 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
[15 . . . 0]
System Control Register
Memory Wait State Control Register
Interval Timer Period Register
Interval Timer Count Register
TSCALE
Interval Timer Scale Register
SPORT0_RX_WORDS1
SPORT0_RX_WORDS0
SPORT0_TX_WORDS1
SPORT0_TX_WORDS0
SPORT0_CTRL_REG
SPORT0_SCLKDIV
SPORT0_RFSDIV
SPORT0_AUTOBUF_CTRL
SPORT1_CTRL_REG
SPORT1_SCLKDIV
SPORT0 Multichannel Word 1 Receive
SPORT0 Multichannel Word 0 Receive
SPORT0 Multichannel Word 1 Transmit
SPORT0 Multichannel Word 0 Transmit
SPORT0 Control Register
SPORT0 Clock Divide Register
SPORT0 Receive Frame Sync Divide
SPORT0 Autobuffer Control Register
SPORT1 Control Register
SPORT1 Clock Divide Register
SPORT1 Receive Frame Sync Divide
SPORT1 Autobuffer Control Register
SPORT1_RFSDIV
SPORT1_AUTOBUF_CTRL
REV. B
–25–
ADMC331
System Controller Registers
Register Memory Map
The system controller includes three registers, MODECTRL,
SYSSTAT and IRQFLAG registers. The format of these regis-
ters is shown at the end of the data sheet.
The address, name, used bits and function of all motor control
peripheral registers of the ADMC331 are tabulated in Table X.
In addition, the relevant DSP core registers are tabulated in
Table XI. Full details of the DSP core registers can be obtained
by referring to the ADSP-2171 sections of the ADSP-2100 Family
User’s Manual, Third Edition.
The MODECTRL register controls different multiplexing,
PWM interrupt and operating modes:
• Bit 0 and 1 control the multiplexing of the ADC auxiliary
channels.
Development Kit
To facilitate device evaluation and programming, an evaluation
kit (ADMC331-EVAL KIT) is available from Analog Devices.
The evaluation kit consists of an evaluation board and the
Motion Control Debugger software. The evaluation kit con-
tains latest programming and device information. It is recom-
mended that the evaluation kit be used for initial program
development.
• Bit 2 enables/disables the PWMTRIP interrupt: if the bit is
set the interrupt is enabled.
• Bit 3 enables/disables the PWMSYNC interrupt: if the bit is
set the interrupt is enabled.
• Bit 4 controls the multiplexing of the SPORT1 pins: if the bit
is set DR1B is selected.
• Bit 5 controls the configuration of SPORT1 as a UART inter-
face: if the bit is set UART mode is enabled.
• Bit 6 selected the PWM operating mode: single or double
duty cycle update modes. If the bit is set double update mode
is selected.
• Bit 7 selects the ADC counter frequency: if the bit is set full
DSP clkout frequency is selected.
• Bit 8 selects the Auxiliary PWM operating mode: offset or
independent modes: if the bit is set independent mode is
selected.
The SYSSTAT register displays various status information:
• Bit 0 indicates the status of the PWMTRIP pin: if this bit is
high, then PWMTRIP pin is high and no PWMTRIP is oc-
curring, if this bit is low, then the PWM is currently shut
down.
• Bit 1 indicates the status of the watchdog flag register: this bit
is set following a watchdog timeout.
• Bit 2 indicates the status of the PWMPOL pin: if this bit is
set, the PWMPOL pin is high and active high PWM outputs
will be produced.
• Bit 3 indicates the status of the PWM timer.
• Bit 4 indicates the status of the PWMSR pin: if this bit is set
to a logic one, the PWMSR pin is low and switched reluc-
tance mode is enabled.
The IRQFLAG register indicates the occurrence of PWM
interrupts:
• Bit 0 indicates that a PWMTRIP interrupt, either hardware of
software, has occurred.
• Bit 1 indicates that a PWMSYNC interrupt has occurred.
–26–
REV. B
ADMC331
PWMTM (R/W)
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
DM (0x2008)
PWMTM
f
CLKOUT
2 ꢀ PWMTM
f
=
PWM
PWMDT (R/W)
15 14 13 12
11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2009)
PWMDT
0
0
0
0
0
0
2 ꢀ PWMDT
SECONDS
T
D
=
f
CLKOUT
PWMSEG (R/W)
15 14 13 12
11 10
9
0
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x200F)
0
0
0
0
0
0
0
0
0
A CHANNEL CROSSOVER
B CHANNEL CROSSOVER
CH OUTPUT DISABLE
CL OUTPUT DISABLE
BH OUTPUT DISABLE
0 = NO CROSSOVER
1 = CROSSOVER
C CHANNEL CROSSOVER
0 = ENABLE
1 = DISABLE
BL OUTPUT DISABLE
AH OUTPUT DISABLE
AL OUTPUT DISABLE
PWMSYNCWT (R/W)
15 14 13 12 11 10
9
8
0
7
0
6
5
1
4
0
3
0
2
1
1
1
0
1
DM (0x2060)
0
0
0
0
0
0
0
0
PWMSYNCWT
PWMSYNCWT + 1
T
=
PWMSYNC,ON
f
CLKOUT
PWMSWT (R/W)
15 14 13 12
11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2061)
0
0
0
0
0
0
Figure 16. Configuration of ADMC331 Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. B
–27–
ADMC331
PWMPD (R/W)
15 14 13 12
11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x200A)
PWMPD
0
0
0
0
0
0
PWMPD
=
T
SECONDS
MIN
f
CLKOUT
PWMGATE (R/W)
15
14 13 12
11 10
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x200B)
GATETM
0
0
0
0
GATE DRIVE CHOPPING FREQUENCY
LOW SIDE GATE CHOPPING
HIGH SIDE GATE CHOPPING
f
CLKOUT
0 = DISABLE
1 = ENABLE
f
=
CHOP
4 ꢀ (GATETM + 1)
PWMCHA (R/W)
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
DM (0x200C)
PWM CHANNEL A
DUTY CYCLE
PWMCHB (R/W)
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
DM (0x200D)
PWM CHANNEL B
DUTY CYCLE
PWMCHC (R/W)
15
14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
DM (0x200E)
PWM CHANNEL C
DUTY CYCLE
Figure 17. Configuration of ADMC331 Registers
–28–
REV. B
ADMC331
PIODIR0 (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
DM (0x2004)
0
0
0
0 = INPUT
1 = OUTPUT
PIODIR1 (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2044)
0
0
0 = INPUT
1 = OUTPUT
PIODIR2 (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2048)
0
0
0 = INPUT
1 = OUTPUT
PIODATA0 (R/W)
15
14
13
12
11
0
10
0
9
8
7
6
5
4
4
4
3
3
3
2
1
0
DM (0x2005)
0
0
0
0
0
0
0 = LOW LEVEL
1 = HIGH LEVEL
PIODATA1 (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
2
1
0
DM (0x2045)
0
0
0 = LOW LEVEL
1 = HIGH LEVEL
PIODATA2 (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
2
1
0
0
0
DM (0x2049)
0 = LOW LEVEL
1 = HIGH LEVEL
Figure 18. Configuration of ADMC331 Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. B
–29–
ADMC331
PIOINTEN0 (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2006)
0
0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE
PIOINTEN1 (R/W)
15
0
14
0
13
0
12
0
11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2046)
0
0
0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE
PIOINTEN2 (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x204A)
0
0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE
PIOFLAG0 (R)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2007)
0
0 = NO INTERRUPT
1 = INTERRUPT FLAGGED
PIOFLAG1 (R)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DM (0x2047)
0
0
0 = NO INTERRUPT
1 = INTERRUPT FLAGGED
PIOFLAG2 (R)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x204B)
0 = NO INTERRUPT
1 = INTERRUPT FLAGGED
Figure 19. Configuration of ADMC331 Registers
–30–
REV. B
ADMC331
AUXCH0 (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2010)
0
0
T
= 2 ꢀ (AUXCH0) ꢀ t
ON, AUX0
CK
AUXCH1 (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2011)
T
= 2 ꢀ (AUXCH1) ꢀ t
ON, AUX1
CK
AUXTM0 (R/W)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
DM (0x2012)
0
1
AUX0 PERIOD = 2 ꢀ (AUXTM0 + 1) ꢀ t
CK
AUXTM1 (R/W)
15
0
14
0
13
0
12
0
11 10
9
0
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
DM (0x2013)
0
0
0
1
AUX1 PERIOD = 2 ꢀ (1 + AUXTM1) ꢀ t
CK
OFFSET = 2 ꢀ (1 + AUXTM1) ꢀ t
CK
Figure 20. Configuration of ADMC331 Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. B
–31–
ADMC331
ADC1 (R)
15 14 13 12
11 10
9
9
9
8
7
6
5
4
3
0
2
0
1
0
0
0
DM (0x2000)
ADC2 (R)
8
15 14 13 12 11 10
7
6
5
4
3
0
2
0
1
0
0
0
DM (0x2001)
ADC3 (R)
8
15 14 13 12 11 10
7
6
5
5
4
4
3
0
2
0
1
0
0
0
DM (0x2002)
ADCAUX (R)
9
15 14 13 12
11 10
8
7
6
3
0
2
0
1
0
0
0
DM (0x2003)
Figure 21. Configuration of ADMC331 Registers
–32–
REV. B
ADMC331
MODECTRL (R/W)
15 14 13 12
11 10
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2015)
0
0
0
0
0
0
0
0
0
0
AUXILIARY
ADC MUX CONTROL
0 = OFFSET MODE
PWM SELECT
00 VAUX0
01 VAUX1
10 VAUX2
11 VAUX3
1 = INDEPENDENT MODE
0 = 1/2 DSP CLOCKOUT
FREQUENCY
ADC
COUNTER
SELECT
PWMTRIP
INTERRUPT
0 = DISABLE
1 = ENABLE
1 = DSP CLOCKOUT
FREQUENCY
PWMSYNC
INTERRUPT
0 = DISABLE
1 = ENABLE
SPORT1 DATA
RECEIVE SELECT
0 = DR1A
1 = DR1B
SPORT1 MODE
SELECT
0 = SPORT
1 = UART
PWM UPDATE MODE
SELECT
0 = SINGLE UPDATE MODE
1 = DOUBLE UPDATE MODE
SYSSTAT (R)
15 14 13 12
11 10
9
8
7
6
0
5
0
4
3
2
1
0
DM (0x2016)
0
0
0
0
0
0
0
0
0
1 = SR MODE
0 = NORMAL
PWMTRIP
PIN STATUS
PWMSR
PIN STATUS
0 = LOW
1 = HIGH
0 = 1ST HALF OF PWM
CYCLE
1 = 2ND HALF OF PWM
CYCLE
PWM TIMER
STATUS
WATCHDOG
STATUS
0 = NORMAL
1 = WATCHDOG RESET
OCCURRED
PWMPOL PIN
STATUS
0 = LOW
1 = HIGH
IRQFLAG (R)
15 14 13 12
11 10
9
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
DM (0x2017)
0
0
0
0
0
0
0
0
0
0
PWMTRIP 1 = ACTIVE
PWMSYNC 1 = ACTIVE
WDTIMER (W)
15 14 13 12
11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2018)
0
0
0
0
0
0
Figure 22. Configuration of ADMC331 Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
REV. B
–33–
ADMC331
ICNTL
2
4
0
3
0
1
1
0
1
0
DSP REGISTER
0 = DISABLE
1 = ENABLE
INTERRUPT NESTING
IRQ0 SENSITIVITY
0 = LEVEL
1 = EDGE
IRQ1 SENSITIVITY
IRQ2 SENSITIVITY
IFC
15 14 13 12 11 10
9
0
8
0
7
6
0
5
0
4
3
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
DSP REGISTER
INTERRUPT FORCE
INTERRUPT CLEAR
IRQ2
TIMER
SPORT0 TRANSMIT
SPORT0 RECEIVE
SOFTWARE 1
SPORT1 RECEIVE OR IRQ0
SPORT1 TRANSMIT OR IRQ1
SOFTWARE 0
SOFTWARE 0
SOFTWARE 1
SPORT1 TRANSMIT OR IRQ1
SPORT1 RECEIVE OR IRQ0
TIMER
SPORT0 RECEIVE
SPORT0 TRANSMIT
IRQ2
IMASK (R/W)
15 14 13 12
11 10
9
0
8
7
6
5
0
4
3
0
2
1
1
0
DSP REGISTER
TIMER
0
0
0
0
0
0
0
0
0
0
1
0
PERIPHERAL (OR IRQ2)
SPORT1 RECEIVE
RESERVED (SET TO 0)
SPORT0 TRANSMIT
(OR IRQ0)
0 = DISABLE
(MASK)
0 = DISABLE
(MASK)
SPORT1 TRANSMIT
1 = ENABLE
1 = ENABLE
(OR IRQ1)
SPORT0 RECEIVE
SOFTWARE 1
SOFTWARE 0
Figure 23. Configuration of ADMC331 Registers
–34–
REV. B
ADMC331
SYSCNTL (R/W)
15 14 13 12 11 10
9
8
7
6
0
5
0
4
0
3
0
2
1
0
0
DM (0x3FFF)
0
0
0
0
1
1
0
0
0
0
0
0 = DISABLED
1 = ENABLED
0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SERIAL PORT
SPORT0 ENABLE
SPORT1 ENABLE
SPORT1 CONFIGURE
0 = DISABLED
1 = ENABLED
MEMWAIT (R/W)
15 14 13 12
11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x3FFE)
1
0
0
0
0
0
Figure 24. Configuration of ADMC331 Registers
REV. B
–35–
ADMC331
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
80-Lead Plastic Thin Quad Flatpack (TQFP)
(ST-80)
0.640 (16.25)
0.620 (15.75)
0.553 (14.05)
0.549 (13.95)
0.063 (1.60)
MAX
0.486 (12.35) TYP
0.030 (0.75)
0.020 (0.50)
80
1
61
60
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.004
(0.10)
MAX
20
41
40
21
0.006 (0.15)
0.002 (0.05)
0.014 (0.35)
0.010 (0.25)
0.029 (0.73)
0.022 (0.57)
0.057 (1.45)
0.053 (1.35)
–36–
REV. B
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