ADL5501_09 [ADI]
50 MHz to 6 GHz TruPwr Detector; 50 MHz至6 GHz的TruPwr检测器
| 型号： | ADL5501_09 |
| 厂家： | 
ADI |
| 描述： | 50 MHz to 6 GHz TruPwr Detector |
| 文件： | 总28页 (文件大小：2092K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50 MHz to 6 GHz
TruPwr Detector
ADL5501
5
1
FEATURES
True rms response
Excellent temperature stability
Up to 30 dB input dynamic range
50 Ω input impedance
1.25 V rms, 15 dBm, maximum input
Single-supply operation: 2.7 V to 5.5 V
Low power: 3.3 mW at 3 V supply
RoHS-compliant
0.1
APPLICATIONS
0.03
–25
Measurement of CDMA-, CDMA2000-, W-CDMA-, and QPSK-/
QAM-based OFDM, and other complex modulation
waveforms
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
Figure 1. Output vs. Input Level, Supply = 3 V, Frequency = 1.9 GHz
RF transmitter or receiver power measurement
GENERAL DESCRIPTION
The ADL5501 is a mean-responding TruPwr™ power detector
for use in high frequency receiver and transmitter signal chains
from 50 MHz to 6 GHz. It is easy to apply, requiring only a single
supply between 2.7 V and 5.5 V and a power supply decoupling
capacitor. The input is internally ac-coupled and has a nominal
input impedance of 50 Ω. The output is a linear-responding dc
voltage with a conversion gain of 6.3 V/V rms at 900 MHz.
The on-chip, 100 Ω series resistance at the output, combined
with an external shunt capacitor, creates a low-pass filter response
that reduces the residual ripple in the dc output voltage. For more
complex waveforms, an external capacitor at the FLTR pin can
be used for supplementary signal demodulation.
The ADL5501 offers excellent temperature stability across a
30 dB range and near 0 dB measurement error across temperature
over the top portion of the dynamic range. In addition to its
temperature stability, the ADL5501 offers low process variations
that further reduce calibration complexity.
The ADL5501 is intended for true power measurement of simple
and complex waveforms. The device is particularly useful for
measuring high crest factor (high peak-to-rms ratio) signals,
such as CDMA-, CDMA2000-, W-CDMA-, and QPSK-/QAM-
based OFDM waveforms. The on-chip modulation filter provides
adequate averaging for most waveforms.
The ADL5501 operates from −40°C to +85°C and is available in
a small 6-lead SC-70 package. It is fabricated on a proprietary
high fT silicon bipolar process.
FUNCTIONAL BLOCK DIAGRAM
VPOS
FLTR
ADL5501
INTERNAL FILTER
CAPACITOR
i
2
x
RFIN
TRANS-
CONDICTANCE
CELLS
ERROR
AMP
i
2
x
BUFFER
VRMS
100Ω
BAND-GAP
REFERENCE
ENBL
COMM
Figure 2.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2009 Analog Devices, Inc. All rights reserved.
ADL5501
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Coupling Using a Series Resistor................................... 19
Multiple RF Inputs ..................................................................... 19
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Circuit Description......................................................................... 17
Filtering........................................................................................ 17
Applications Information .............................................................. 18
Basic Connections...................................................................... 18
Output Swing .............................................................................. 18
Linearity....................................................................................... 18
Selecting the Square-Domain Filter and Output Low-Pass
Filter ............................................................................................. 19
Power Consumption, Enable, and Power-On/Power-Off
Response Time............................................................................ 20
Output Drive Capability and Buffering................................... 21
VRMS Output Offset ................................................................. 21
Device Calibration and Error Calculation.............................. 22
Calibration for Improved Accuracy......................................... 22
Drift over a Reduced Temperature Range .............................. 23
Operation Below 100 MHz ....................................................... 23
Evaluation Board........................................................................ 23
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
3/09—Rev. A to Rev. B
10/07—Rev. 0 to Rev. A
Change to Features ........................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Figure 4, Figure 5, Figure 7, and Figure 9 ............... 10
Deleted Figure 17 and Figure 21; Renumbered Sequentially ... 12
Changes to Figure 18 and Figure 21............................................. 13
Changes to Figure 36 and Figure 39............................................. 16
Changes to Figure 42...................................................................... 18
Changes to Operation Below 100 MHz Section......................... 23
Deleted Figure 56............................................................................ 22
Deleted Figure 57............................................................................ 23
Changes to General Description .....................................................1
Changes to Table 1.............................................................................3
Changes to Figure 30, Figure 32, and Figure 33......................... 14
Changes to Figure 35, Figure 37, and Figure 38......................... 15
Changes to Circuit Description Section...................................... 16
Changes to Layout and Operation Below 100 MHz and
Above 4.0 GHz Section.................................................................. 22
Inserted Figure 56........................................................................... 22
Inserted Figure 57........................................................................... 23
Changes to Figure 58...................................................................... 23
Deleted Figure 57 and Figure 58 .................................................. 24
Changes to Figure 59 and Figure 60............................................. 24
9/06—Revision 0: Initial Version
Rev. B | Page 2 of 28
ADL5501
SPECIFICATIONS
TA = 25°C, VS = 3.0 V, CFLTR = open, COUT = 100 nF, unless otherwise specified.
Table 1.
Parameter
Condition
Min
Typ
Max
Unit
FREQUENCY RANGE
RMS CONVERSION (f = 50 MHz)
Input Impedance
Input Return Loss
Dynamic Range1
1 dB Error2
Input RFIN
50
6000
MHz
Input RFIN to Output VRMS
87||6.9
11.0
Ω||pF
dB
CW input, −40°C < TA < +85°C
VS = 3 V
25
dB
VS = 5 V
VS = 3 V
26
32
dB
dB
2 dB Error2
VS = 5 V
35
dB
Maximum Input Level
Minimum Input Level
Conversion Gain
1 dB error2
1 dB error2
VOUT = (gain × VIN) + intercept
8
dBm
dBm
V/V rms
V
V
V
−18
4.5
0.03
1.81
0.11
Output Intercept3
Output Voltage—High Power In
Output Voltage—Low Power In
Temperature Sensitivity
PIN = 5 dBm, 400 mV rms
PIN = −21 dBm, 20 mV rms
PIN = −5 dBm
0.0039
dB/°C
dB/°C
25°C ≤ TA ≤ 85°C
−0.0037
−40°C ≤ TA ≤ +25°C
RMS CONVERSION (f = 100 MHz)
Input Impedance
Input Return Loss
Dynamic Range1
Input RFIN to Output VRMS
78||4.2
12.6
Ω||pF
dB
CW input, −40°C < TA < +85°C
Delta from 25°C, VS = 5 V
VS = 3 V
VS = 5 V
VS = 3 V
VS = 5 V
VS = 3 V
VS = 5 V
1 dB error2
1 dB error2
VOUT = (gain × VIN) + intercept
VS = 5 V
0.25 dB Error4
28
19
20
23
27
26
30
6
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
V/V rms
V/V rms
V
0.25 dB Error2
1 dB Error2
2 dB Error2
Maximum Input Level
Minimum Input Level
Conversion Gain
−18
6.1
5.6
7.8
Output Intercept3
0.03
VS = 5 V
−0.02
+0.1
V
Output Voltage—High Power In
Output Voltage—Low Power In
Temperature Sensitivity
PIN = 5 dBm, 400 mV rms
PIN = −21 dBm, 20 mV rms
PIN = −5 dBm
2.47
0.13
V
V
0.0028
dB/°C
dB/°C
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +25°C
−0.0018
Rev. B | Page 3 of 28
ADL5501
Parameter
Condition
Min
Typ
Max
Unit
RMS CONVERSION (f = 450 MHz)
Input Impedance
Input Return Loss
Dynamic Range1
0.25 dB Error4
Input RFIN to Output VRMS
63||1.4
16.0
Ω||pF
dB
CW input, −40°C < TA < +85°C
Delta from 25°C, VS = 5 V
VS = 3 V
32
20
dB
dB
0.25 dB Error2
VS = 5 V
VS = 3 V
VS = 5 V
VS = 3 V
24
25
29
28
dB
dB
dB
dB
1 dB Error2
2 dB Error2
VS = 5 V
33
5
dB
Maximum Input Level
Minimum Input Level
Conversion Gain
1 dB error2
dBm
dBm
V/V rms
V
V
V
1 dB error2
VOUT = (gain × VIN) + intercept
−20
7.1
0.03
2.81
0.15
Output Intercept3
Output Voltage—High Power In
Output Voltage—Low Power In
Temperature Sensitivity
PIN = 5 dBm, 400 mV rms
PIN = −21 dBm, 20 mV rms
PIN = −5 dBm
0.0016
dB/°C
dB/°C
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +25°C
−0.0002
RMS CONVERSION (f = 900 MHz)
Input Impedance
Input Return Loss
Dynamic Range1
Input RFIN to Output VRMS
52||0.9
17.5
Ω||pF
dB
CW input, −40°C < TA < +85°C
Delta from 25°C, VS = 5 V
VS = 3 V
0.25 dB Error4
33
20
dB
dB
0.25 dB Error2
VS = 5 V
VS = 3 V
VS = 5 V
VS = 3 V
23
24
27
27
dB
dB
dB
dB
1 dB Error2
2 dB Error2
VS = 5 V
30
6
dB
Maximum Input Level
Minimum Input Level
Conversion Gain
1 dB error2
dBm
dBm
V/V rms
V
V
V
1 dB error2
VOUT = (gain × VIN) + intercept
−18
6.3
0.03
2.53
0.14
Output Intercept3
Output Voltage—High Power In
Output Voltage—Low Power In
Temperature Sensitivity
PIN = 5 dBm, 400 mV rms
PIN = −21 dBm, 20 mV rms
PIN = −5 dBm
0.0019
dB/°C
dB/°C
25°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +25°C
−0.0002
Rev. B | Page 4 of 28
ADL5501
Parameter
Condition
Min
Typ
Max
Unit
RMS CONVERSION (f = 1900 MHz)
Input Impedance
Input Return Loss
Dynamic Range1
0.25 dB Error4
Input RFIN to Output VRMS
+33||−0.1
15
Ω||pF
dB
CW input, −40°C < TA < +85°C
Delta from 25°C, VS = 5 V
VS = 3 V
32
5
dB
dB
0.25 dB Error2
VS = 5 V
VS = 3 V
VS = 5 V
VS = 3 V
7
25
29
28
dB
dB
dB
dB
1 dB Error2
2 dB Error2
VS = 5 V
32
7
dB
Maximum Input Level
Minimum Input Level
Conversion Gain
1 dB error2
dBm
dBm
V/V rms
V
V
V
1 dB error2
VOUT = (gain × VIN) + intercept
−19
5.5
0.02
2.20
0.12
Output Intercept3
Output Voltage—High Power In
Output Voltage—Low Power In
Temperature Sensitivity
PIN = 5 dBm, 400 mV rms
PIN = −21 dBm, 20 mV rms
PIN = −5 dBm
0.0031
dB/°C
dB/°C
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +25°C
−0.0034
RMS CONVERSION (f = 2350 MHz)
Input Impedance
Input Return Loss
Dynamic Range1
Input RFIN to Output VRMS
+32||−0.3
13.6
Ω||pF
dB
CW input, −40°C < TA < +85°C
Delta from 25°C, VS = 5 V
VS = 3 V
0.25 dB Error4
8
4
dB
dB
0.25 dB Error2
VS = 5 V
VS = 3 V
VS = 5 V
VS = 3 V
7
dB
dB
dB
dB
1 dB Error2
2 dB Error2
25
29
29
32
8
−18
5.0
0.02
2.00
0.10
VS = 5 V
dB
Maximum Input Level
Minimum Input Level
Conversion Gain
1 dB error2
dBm
dBm
V/V rms
V
V
V
1 dB error2
VOUT = (gain × VIN) + intercept
Output Intercept3
Output Voltage—High Power In
Output Voltage—Low Power In
Temperature Sensitivity
PIN = 5 dBm, 400 mV rms
PIN = −21 dBm, 20 mV rms
PIN = −5 dBm
0.0032
dB/°C
dB/°C
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +25°C
−0.0044
Rev. B | Page 5 of 28
ADL5501
Parameter
Condition
Min
Typ
Max
Unit
RMS CONVERSION (f = 2700 MHz)
Input Impedance
Input Return Loss
Dynamic Range1
0.25 dB Error4
Input RFIN to Output VRMS
+35||−0.5
13
Ω||pF
dB
CW input, −40°C < TA < +85°C
Delta from 25°C, VS = 5 V
VS = 3 V
5
3
dB
dB
0.25 dB Error2
VS = 5 V
VS = 3 V
VS = 5 V
VS = 3 V
7
dB
dB
dB
dB
1 dB Error2
2 dB Error2
25
30
28
33
8
−17
4.6
0.02
1.84
0.09
VS = 5 V
dB
Maximum Input Level
Minimum Input Level
Conversion Gain
1 dB error2
dBm
dBm
V/V rms
V
V
V
1 dB error2
VOUT = (gain × VIN) + intercept
Output Intercept3
Output Voltage—High Power In
Output Voltage—Low Power In
Temperature Sensitivity
PIN = 5 dBm, 400 mV rms
PIN = –21 dBm, 20 mV rms
PIN = –5 dBm
0.0034
dB/°C
dB/°C
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +25°C
−0.0049
RMS CONVERSION (f = 4000 MHz)
Input Impedance
Input Return Loss
Dynamic Range1
Input RFIN to Output VRMS
+41||−0.1
20.8
Ω||pF
dB
CW input, −40°C < TA < +85°C
Delta from 25°C, VS = 5 V
VS = 3 V
0.25 dB Error4
5
4
dB
dB
0.25 dB Error2
VS = 5 V
VS = 3 V
VS = 5 V
VS = 3 V
5
28
31
30
dB
dB
dB
dB
1 dB Error2
2 dB Error2
VS = 5 V
33
10
dB
Maximum Input Level
Minimum Input Level
Conversion Gain
1 dB error2
dBm
dBm
V/V rms
V
V
V
1 dB error2
VOUT = (gain × VIN) + intercept
−18
3.8
0.01
1.53
0.07
Output Intercept3
Output Voltage—High Power In
Output Voltage—Low Power In
Temperature Sensitivity
PIN = 5 dBm, 400 mV rms
PIN = –21 dBm, 20 mV rms
PIN = –5 dBm
0.0019
dB/°C
dB/°C
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +25°C
−0.0043
Rev. B | Page 6 of 28
ADL5501
Parameter
Condition
Min
Typ
Max
Unit
RMS CONVERSION (f = 5000 MHz)
Input Impedance
Input Return Loss
Dynamic Range1
0.25 dB Error4
Input RFIN to Output VRMS
+51||−0.2
17
Ω||pF
dB
CW input, −40°C < TA < +85°C
Delta from 25°C, VS = 5 V
VS = 3 V
5
5
dB
dB
0.25 dB Error2
VS = 5 V
VS = 3 V
VS = 5 V
VS = 3 V
5
31
35
34
dB
dB
dB
dB
1 dB Error2
2 dB Error2
VS = 5 V
38
15
dB
Maximum Input Level
Minimum Input Level
Conversion Gain
1 dB error2
dBm
dBm
V/V rms
V
V
V
1 dB error2
VOUT = (gain × VIN) + intercept
−20
3.3
0.02
1.33
0.08
Output Intercept3
Output Voltage—High Power In
Output Voltage—Low Power In
Temperature Sensitivity
PIN = 5 dBm, 400 mV rms
PIN = –21 dBm, 20 mV rms
PIN = –5 dBm
0.0001
dB/°C
dB/°C
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +25°C
−0.0031
RMS CONVERSION (f = 6000 MHz)
Input Impedance
Input Return Loss
Dynamic Range1
Input RFIN to Output VRMS
+86||−0.1
10.1
Ω||pF
dB
CW input, −40°C < TA < +85°C
Delta from 25°C, VS = 5 V
VS = 3 V
0.25 dB Error4
25
20
dB
dB
0.25 dB Error2
VS = 5 V
VS = 3 V
VS = 5 V
VS = 3 V
20
31
31
35
dB
dB
dB
dB
1 dB Error2
2 dB Error2
VS = 5 V
35
14
dB
Maximum Input Level
Minimum Input Level
Conversion Gain
1 dB error2
dBm
dBm
V/V rms
V
V
V
1 dB error2
VOUT = (gain × VIN) + intercept
−17
2.4
0.02
0.97
0.07
Output Intercept3
Output Voltage—High Power In
Output Voltage—Low Power In
Temperature Sensitivity
PIN = 5 dBm, 400 mV rms
PIN = –21 dBm, 20 mV rms
PIN = –5 dBm
0.0017
dB/°C
dB/°C
25°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ +25°C
−0.0008
Rev. B | Page 7 of 28
ADL5501
Parameter
Condition
Min
Typ
Max
Unit
OUTPUT OFFSET
No signal at RFIN
50
150
mV
ENABLE INTERFACE
Pin ENBL
Logic Level to Enable Power, High Condition
Input Current when High
Logic Level to Disable Power, Low Condition
Power-Up Response Time5
2.7 V ≤ VS ≤ 5.5 V, −40°C < TA < +85°C
2.7 V at ENBL, –40°C ≤ TA ≤ +85°C
2.7 V ≤ VS ≤ 5.5 V, −40°C < TA < +85°C
CFLTR = COUT = open, 0 dBm at RFIN
CFLTR = 1 nF, COUT = open, 0 dBm at RFIN
CFLTR = open, COUT = 100 nF, 0 dBm at RFIN
1.8
VPOS
0.1
+0.5
V
μA
V
μs
μs
μs
0.05
–0.5
6
21
28
POWER SUPPLIES
Operating Range
Quiescent Current
Total Supply Current When Disabled
−40°C < TA < +85°C
2.7
5.5
<5
V
mA
μA
No signal at RFIN6
1.1
0.1
No signal at RFIN, ENBL input low
1 The available output swing and, therefore, the dynamic range are altered by the supply voltage; see Figure 8.
2 Error referred to best-fit line at 25°C.
3 Calculated using linear regression.
4 Error referred to delta from 25°C response; see Figure 13, Figure 14, Figure 15, Figure 19, Figure 20, and Figure 21.
5 The response time is measured from 10% to 90% of settling level; see Figure 30.
6 Supply current is input-level dependent; see Figure 6.
Rev. B | Page 8 of 28
ADL5501
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VS
VRMS
RFIN
Equivalent Power, re: 50 Ω
Internal Power Dissipation
θJA (SC-70)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
5.5 V
0 V, VS
1.25 V rms
15 dBm
80 mW
494°C/W
125°C
−40°C to +85°C
−65°C to +150°C
ESD CAUTION
Rev. B | Page 9 of 28
ADL5501
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
6
5
4
VPOS
FLTR
RFIN
VRMS
ENBL
COMM
ADL5501
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
VPOS
FLTR
Supply Voltage Pin. Operational range 2.7 V to 5.5 V.
Square-Domain Filter Pin. Connection for an external capacitor to lower the corner frequency of the square-
domain (or modulation) filter. Capacitor is connected between FLTR and VS and forms a low-pass filter with an
8 kΩ on-chip resistor. The on-chip capacitor provides filtering with an approximate 100 kHz corner frequency.
For simple waveforms, no further filtering of the demodulated signal is required.
3
4
5
RFIN
COMM
ENBL
Signal Input Pin. Internally ac-coupled after internal termination resistance. Nominal 50 Ω input impedance.
Device Ground Pin.
Enable Pin. Connect pin to VS for normal operation. Connect pin to ground for disable mode for a supply
current less than 1 μA.
6
VRMS
Output Pin. Rail-to-rail voltage output with limited 3 mA current drive capability. The output has an internal
100 Ω series resistance. High resistive loads are recommended to preserve output swing.
Rev. B | Page 10 of 28
ADL5501
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5.0 V, CFLTR = open, COUT = 100 nF, Colors: black = +25°C, blue = −40°C, red = +85°C, unless otherwise noted.
10
3
100MHz
450MHz
900MHz
1900MHz
2350MHz
2700MHz
4000MHz
5000MHz
6000MHz
2
1
1
0
100MHz
450MHz
900MHz
1900MHz
2350MHz
2700MHz
4000MHz
5000MHz
6000MHz
–1
–2
–3
0.1
0.03
–25
–20
–15
–10
–5
0
5
10
15
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 4. Output vs. Input Level; Frequencies = 100 MHz, 450 MHz, 900 MHz,
1900 MHz, 2350 MHz, 2700 MHz, 4000 MHz, 5000 MHz, and 6000 MHz;
Supply = 5.0 V
Figure 7. Linearity Error vs. Input Level; Frequencies = 100 MHz, 450 MHz, 900 MHz,
1900 MHz, 2350 MHz, 2700 MHz, 4000 MHz, 5000 MHz, and 6000 MHz;
Supply = 5.0 V
6
10
5.5V
100MHz
450MHz
5.0V
5
4
3
2
1
0
900MHz
1900MHz
2350MHz
2700MHz
4000MHz
5000MHz
6000MHz
3.0V
2.7V
1
0.1
0.03
–25
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–20
–15
–10
–5
0
5
10
15
INPUT (V rms)
INPUT (dBm)
Figure 5. Output vs. Input Level (Linear Scale); Frequencies = 100 MHz, 450 MHz,
900 MHz,1900 MHz, 2350 MHz, 2700 MHz, 4000 MHz, 5000 MHz, and 6000 MHz;
Supply = 5.0 V
Figure 8. Output vs. Input Level;
Supply = 2.7 V, 3.0 V, 5.0 V, and 5.5 V; Frequency = 900 MHz
12
11
10
30
25
20
15
10
5
9
8
7
6
5
4
3
2
1
0
5.0V
3.0V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0
1
2
3
4
5
6
INPUT (V rms)
FREQUENCY (GHz)
Figure 6. Supply Current vs. Input Level; Supplies = 3.0 V and 5.0 V;
Temperatures = −40°C, +25°C, and +85°C
Figure 9. Return Loss vs. Frequency
Rev. B | Page 11 of 28
ADL5501
3
3
2
2
1
1
0
0
–1
–2
–1
–2
–3
–3
–25
–20
–15
–10
–5
0
5
10
15
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 10. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 900 MHz; Supply = 5.0 V
Figure 13. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 900 MHz, Supply = 5.0 V
3
2
3
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
15
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 11. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 1900 MHz; Supply = 5.0 V
Figure 14. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 1900 MHz, Supply = 5.0 V
3
2
3
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
15
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 12. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 2350 MHz; Supply = 5.0 V
Figure 15. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 2350 MHz, Supply = 5.0 V
Rev. B | Page 12 of 28
ADL5501
3
2
3
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
15
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 16. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 2700 MHz; Supply = 5.0 V
Figure 19. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 2700 MHz, Supply = 5.0 V
3
2
3
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
15
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 17. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 4000 MHz; Supply = 5.0 V
Figure 20. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 4000 MHz, Supply = 5.0 V
3
3
2
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
15
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 18. Temperature Drift Distributions for 50 Devices at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference; Frequency = 6000 MHz; Supply = 5.0 V
Figure 21. Output Delta from +25°C Output Voltage for 50 Devices
at −40°C and +85°C, Frequency = 6000 MHz, Supply = 5.0 V
Rev. B | Page 13 of 28
ADL5501
5
3
2
CW
QPSK, 4.8dB CF
8PSK, 4.8dB CF
16QAM, 6.3dB CF
64QAM, 7.4dB CF
1
1
0
–1
–2
–3
CW
QPSK
8PSK
16QAM
64QAM
0.1
0.03
–25
–20
–15
–10
–5
0
5
10
–25
–20
–15
–10
–5
0
5
10
INPUT (dBm)
INPUT (dBm)
Figure 22. Output vs. Input Level with Different Waveforms, 10 MHz Signal BW
for All Modulated Signals, Supply = 5.0 V, Frequency = 1900 MHz
Figure 25. Error from CW Linear Reference vs. Input with Different Waveforms,
10 MHz Signal BW for All Modulated Signals, Supply = 5.0 V, Frequency = 1900 MHz
3
2
1
0
3
2
1
0
–1
–1
CW
CW
BPSK, 11dB CF
BPSK, 11dB CF
QPSK, 11dB CF
QPSK, 11dB CF
–2
–2
16QAM, 12dB CF
16QAM, 12dB CF
64QAM, 11dB CF
64QAM, 11dB CF
–3
–25
–3
–25
–20
–15
–10
–5
0
5
10
–20
–15
–10
–5
0
5
10
RFIN (dBm)
RFIN (dBm)
Figure 23. Error from CW Linear Reference vs. Input Level for Various
802.16 OFDM Waveforms at 2.35 GHz, 10 MHz Signal BW, and
256 Subcarriers for All Modulated Signals, Supply = 5.0 V
Figure 26. Error from CW Linear Reference vs. Input Level for Various
802.16 OFDM Waveforms at 3.5 GHz, 10 MHz Signal BW, and
256 Subcarriers for All Modulated Signals, Supply = 5.0 V
3
3
CW
CW
PICH, 4.7dB CF
PICH + FCH (9.6kbps), 4.8dB CF
PICH + FCH (9.6kbps) + DCCH, 6.3dB CF
12.2kbps, DPCCH (–5.46dB, 15kSPS) +
DPDCH (0dB, 60kSPS), 3.4dB CF
64kbps, DPCCH (–9.54dB, 15kSPS) +
DPDCH (0dB, 240kSPS), 3.4dB CF
2
1
2
144kbps, DPCCH (–11.48dB, 15kSPS) +
DPDCH (0dB, 480kSPS), 3.3dB CF
384kbps, DPCCH (–11.48dB, 15kSPS) +
DPDCH (0dB, 960kSPS), 3.3dB CF
PICH + FCH (9.6kbps) + SCH (153.6kbps), 6.7dB CF
PICH + FCH (9.6kbps) + DCCH +
SCH (153.6kbps), 7.6dB CF
1
768kbps, DPCCH (–11.48dB, 15kSPS) +
DPDCH1 + 2 (0dB, 960kSPS), 5.8dB CF
0
0
–1
–2
–3
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
–25
–20
–15
–10
–5
0
5
10
RFIN (dBm)
RFIN (dBm)
Figure 24. Error from CW Linear Reference vs. Input with Various
WCDMA Up Link Waveforms at 1900 MHz, CFLTR = Open, COUT = 100 nF
Figure 27. Error from CW Linear Reference vs. Input with Various
CDMA2000 Reverse Link Waveforms at 900 MHz, CFLTR = 1 nF, COUT = 100 nF
Rev. B | Page 14 of 28
ADL5501
3
2
3
2
CW
CW
TEST MODEL 1 w/ 16 DPCH, 1 CARRIER
TEST MODEL 1 w/ 32 DPCH, 1 CARRIER
TEST MODEL 1 w/ 64 DPCH, 1 CARRIER
TEST MODEL 1 w/ 64 DPCH, 2 CARRIERS
TEST MODEL 1 w/ 64 DPCH, 3 CARRIERS
TEST MODEL 1 w/ 64 DPCH, 4 CARRIERS
SR1, PILOT CHANNEL, 1 CARRIER
SR1, 9 CHANNEL, 1 CARRIER
SR1, 9 CHANNEL, 3 CARRIERS
SR1, 9 CHANNEL, 4 CARRIERS
1
1
0
0
–1
–2
–3
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
–25
–20
–15
–10
–5
0
5
10
RFIN (dBm)
INPUT (dBm)
Figure 28. Error from CW Linear Reference vs. Input with Various
Figure 31. Error from CW Linear Reference vs. Input with Various
WCDMA Down Link Waveforms at 2140 MHz, CFLTR = 1 nF, COUT = 100 nF
CDMA2000 Fwd Link Waveforms at 2140 MHz, CFLTR = 1 nF, COUT = 100 nF
PULSED
RFIN
OSCILLOSCOPE
C1
100pF
C2
0.1µF
400mV rms RF INPUT
FET PROBE
ADL5501
POWER
1
2
3
6
5
4
VPOS
VRMS
SUPPLY
C
R
OUT
OUT
C
FLTR
250mV rms
160mV rms
70mV rms
FLTR
RFIN
ENBL
RF PULSE
GENERATOR
COMM
40µs/DIV
Figure 29. Hardware Configuration for Output Response to RF Input Pulse
Figure 32. Output Response to Various RF Input Pulse Levels, Supply = 3 V,
Frequency = 900 MHz, CFLTR = 1 nF, COUT = Open, ROUT = Open
PULSED
RFIN
PULSED RFIN
400mV rms RF INPUT
400mV rms RF INPUT
250mV rms
160mV rms
70mV rms
250mV rms
160mV rms
70mV rms
10µs/DIV
100µs/DIV
Figure 33. Output Response to Various RF Input Pulse Levels, Supply = 3 V,
Frequency = 900 MHz, CFLTR = Open, COUT = 0.1 μF, ROUT = 1 kΩ
Figure 30. Output Response to Various RF Input Pulse Levels, Supply = 3 V,
Frequency = 900 MHz, CFLTR = Open, COUT = Open, ROUT = Open
Rev. B | Page 15 of 28
ADL5501
ENBL
OSCILLOSCOPE
FET PROBE
C1
100pF
C2
0.1µF
ADL5501
POWER
SUPPLY
1
2
3
6
5
4
VPOS
VRMS
400mV rms RF INPUT
C
R
OUT
OUT
C
FLTR
FLTR
RFIN
ENBL
250mV rms
160mV rms
70mV rms
RF SIGNAL
GENERATOR
COMM
AD811
PULSE
GENERATOR
50Ω
732Ω
40µs/DIV
Figure 34. Hardware Configuration for Output Response to
Enable Gating Measurements
Figure 37. Output Response to Enable Gating at Various RF Input Levels,
Supply = 3 V, Frequency = 900 MHz, CFLTR = 1 nF, COUT = Open, ROUT = Open
ENBL
ENBL
400mV rms RF INPUT
400mV rms RF INPUT
250mV rms
160mV rms
250mV rms
160mV rms
70mV rms
70mV rms
10µs/DIV
100µs/DIV
Figure 35. Output Response to Enable Gating at Various RF Input Levels,
Supply = 3 V, Frequency = 900 MHz, CFLTR = Open, COUT = Open, ROUT = Open
Figure 38. Output Response to Enable Gating at Various RF Input Levels,
Supply = 3 V, Frequency = 900 MHz, CFLTR = Open, COUT = 0.1 μF, ROUT = 1 kΩ
8
7
6
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
0
2000
4000
6000
0
2000
4000
6000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 36. Conversion Gain vs. Frequency, Supply 5 V
Figure 39. Intercept vs. Frequency, Supply = 5 V
Rev. B | Page 16 of 28
ADL5501
CIRCUIT DESCRIPTION
The ADL5501 is an rms-responding (mean power) detector that
provides an approach to the exact measurement of RF power that
is independent of waveform. It achieves this function by using
a proprietary technique in which the outputs of two identical
squaring cells are balanced by the action of a high gain error
amplifier.
The squaring cells have very wide bandwidth with an intrinsic
response from dc to microwave. However, the dynamic range of
such a system is small, due in part to the much larger dynamic
range at the output of the squaring cells. There are practical
limitations to the accuracy of sensing very small error signals at
the bottom end of the dynamic range, arising from small random
offsets that limit the attainable accuracy at small inputs.
The signal to be measured is applied to the input of the first
squaring cell through the input matching network. The input
is matched to offer a broadband 50 Ω input impedance from
50 MHz to 6 GHz. The input matching network has a high-pass
corner frequency of approximately 70 MHz.
On the other hand, the squaring cells in the ADL5501 have a
Class AB aspect; the peak input is not limited by its quiescent
bias condition but is determined mainly by the eventual loss of
square-law conformance. Consequently, the top end of their
response range occurs at a large input level (approximately
700 mV rms), while preserving a reasonably accurate square-law
response. The maximum usable range is, in practice, limited by
the output swing. The rail-to-rail output stage can swing from a
few millivolts above ground to within 100 mV below the supply.
An example of the output induced limit, given a conversion gain
of 6.3 V/V rms at 900 MHz and assuming a maximum output of
2.9 V with a 3 V supply, has a maximum input of 2.9 V rms/6.3 or
460 mV rms.
The ADL5501 responds to the voltage, VIN, at its input by squaring
this voltage to generate a current proportional to VIN . This current
is applied to an internal load resistor in parallel with a capacitor,
followed by a low-pass filter, which extracts the mean of VIN
Although essentially voltage responding, the associated input
impedance calibrates this port in terms of equivalent power.
Therefore, 1 mW corresponds to a voltage input of 224 mV rms
referenced to 50 Ω. Because both the squaring cell input impedance
and the input matching network are frequency dependent, the
conversion gain is a function of signal frequency.
2
2
.
FILTERING
The voltage across the low-pass filter, whose frequency can
be arbitrarily low, is applied to one input of an error-sensing
amplifier. A second identical voltage-squaring cell is used to
close a negative feedback loop around this error amplifier. This
second cell is driven by a fraction of the quasi-dc output voltage
of the ADL5501. When the voltage at the input of the second
squaring cell is equal to the rms value of VIN, the loop is in a stable
state, and the output then represents the rms value of the input.
An important aspect of rms-dc conversion is the need for
averaging (the function is root-mean-square). The on-chip
averaging in the square domain has a corner frequency of
approximately 100 kHz and is sufficient for common modu-
lation signals, such as CDMA-, CDMA2000-, WCDMA-, and
QPSK-/QAM-based OFDM (for example, WLAN and WiMAX).
For more complex RF waveforms (with modulation components
extending down into the kilohertz region), more filtering is
necessary to supplement the on-chip, low-pass filter. For this
reason, the FLTR pin is provided; a capacitor attached between
this pin and VPOS can extend the averaging time to very low
frequencies.
By completing the feedback path through a second squaring
cell, identical to the one receiving the signal to be measured,
several benefits arise. First, scaling effects in these cells cancel;
therefore, the overall calibration can be accurate, even though
the open-loop response of the squaring cells taken separately
need not be. Note that in implementing rms-dc conversion, no
reference voltage enters into the closed-loop scaling. Second,
the tracking in the responses of the dual cells remains very close
over temperature, leading to excellent stability of calibration.
Adequate filtering ensures the accuracy of the rms measurement;
however, some ripple or ac residual can still be present on the
dc output. To reduce this ripple, an external shunt capacitor can
be used at the output to form a low-pass filter with the on-chip,
100 Ω resistance (see the Selecting the Square-Domain Filter
and Output Low-Pass Filter section).
Rev. B | Page 17 of 28
ADL5501
APPLICATIONS INFORMATION
BASIC CONNECTIONS
LINEARITY
Because the ADL5501 is a linear-responding device, plots of
output voltage vs. input voltage result in a straight line. It is more
useful to plot the error on a logarithmic scale, as shown in
Figure 42. The deviation of the plot for the ideal straight-line
characteristic is caused by output clipping at the high end and
by signal offsets at the low end. However, it should be noted that
offsets at the low end can be either positive or negative; therefore,
this plot could also trend upwards at the low end. Figure 10
through Figure 12 and Figure 16 through Figure 18 show error
distributions for a large population of devices at specific
frequencies.
Figure 40 shows the basic connections for the ADL5501. The
device is powered by a single supply of between 2.7 V and 5.5 V,
with a quiescent current of 1.1 mA. The VPOS pin is decoupled
using 100 pF and 0.1 μF capacitors.
The ADL5501 RF input does not require external termination
components because it is internally matched for an overall
broadband input impedance of 50 Ω.
+V 2.7V TO 5.5V
S
100pF
0.1µF
ADL5501
VRMS
1
2
3
6
5
4
VPOS
VRMS
C
OUT
C
FLTR
3
FLTR
RFIN
ENBL
100MHz
450MHz
900MHz
1900MHz
2350MHz
2700MHz
4000MHz
5000MHz
6000MHz
2
1
RFIN
COMM
Figure 40. Basic Connections for the ADL5501
0
OUTPUT SWING
At 900 MHz, the output voltage is nominally 6.3 times the input
rms voltage (a conversion gain of 6.3 V/V rms). The output voltage
swings from near ground to 4.9 V on a 5.0 V supply.
–1
–2
–3
Figure 41 shows the output swing of the ADL5501 to a CW input
for various supply voltages. It is clear from Figure 41 that
operating the device at lower supply voltages reduces the
dynamic range as the output headroom decreases.
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
Figure 42. Representative Unit, Error in dB vs. Input Level, VS = 5.0 V
10
5.5V
It is also apparent in Figure 42 that the error plot tends to shift
to the right with increasing frequency. The squaring cell has an
input impedance that decreases with frequency. The matching
network compensates for the change and maintains the input
impedance at a nominal 50 Ω. The result is a decrease in the
actual voltage across the squaring cell as the frequency increases,
reducing the conversion gain. Similarly, conversion gain is less
at frequencies near 100 MHz because of the small on-chip
coupling capacitor.
5.0V
3.0V
2.7V
1
0.1
0.03
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
Figure 41. Output Swing for Supply Voltages of 2.7 V, 3.0 V, 5.0 V, and 5.5 V
Rev. B | Page 18 of 28
ADL5501
T-network sees a 50 Ω termination. Because there are only 6 dB
of isolation from one port of the combiner to the other ports,
only one band should be active at a time.
BAND 1
INPUT COUPLING USING A SERIES RESISTOR
Figure 43 shows a technique for coupling the input signal into
the ADL5501 that can be applicable where the input signal is
much larger than the input range of the ADL5501. A series
resistor combines with the input impedance of the ADL5501
to attenuate the input signal. Because this series resistor forms
a divider with the frequency dependent input impedance, the
apparent gain changes greatly with frequency. However, this
method has the advantage of very little power being tapped off
in RF power transmission applications. If the resistor is large
compared to the impedance of the transmission line, the VSWR
of the system is relatively unaffected.
DIRECTIONAL
COUPLER
50Ω
16.5Ω
16.5Ω
BAND 2
RFIN
DIRECTIONAL
COUPLER
50Ω
16.5Ω
ADL5501
Figure 44. Combining Multiple RF Input Signals
R
SERIES
RFIN
RFIN
SELECTING THE SQUARE-DOMAIN FILTER AND
OUTPUT LOW-PASS FILTER
ADL5501
The internal filter capacitor of the ADL5501 provides averaging
in the square domain but leaves some residual ac on the output.
Signals with high peak-to-average ratios, such as W-CDMA or
CDMA2000, can produce ac-residual levels on the ADL5501
dc output. To reduce the effects of these low frequency components
in the waveforms, some additional filtering is required.
Figure 43. Attenuating the Input Signal
The resistive tap or series resistance, RSERIES, can expressed as
R
SERIES = RIN (1 − 10ATTN/20)/(10ATTN/20
where:
IN is the input impedance of RFIN.
ATTN is the desired attenuation factor in dB.
)
(1)
R
The square-domain filter capacitance of the ADL5501 can be
augmented by connecting a capacitor between Pin 2 (FLTR) and
Pin 1 (VPOS). In addition, the output of the ADL5501 can be
filtered directly by placing a capacitor between VRMS (Pin 6)
and ground. The combination of the on-chip, 100 Ω output
series resistance and the external shunt capacitor forms a low-
pass filter to reduce the residual ac.
For example, if a power amplifier with a maximum output power
of +28 dBm is matched to the ADL5501 input at +5 dBm, then
a −23 dB attenuation factor is required. At 900 MHz, the input
resistance, RIN, is 55 Ω.
R
SERIES = (55 Ω) (1 − 10−23/20)/(10−23/20) = 722 Ω
Thus, for an attenuation of −23 dB, a series resistance of
approximately 722 Ω is needed.
Table 4 shows the effects of several capacitor values for various
communications standards with high peak-to-average ratios
along with the residual ripple at the output, in peak-to-peak and
rms volts. Note that large load capacitances increase the turn-on
and pulse response times (see Figure 30, Figure 32, Figure 33,
Figure 35, Figure 37, and Figure 38). For more information on
the effects of the filter capacitances on the response, see the
Power Consumption, Enable, and Power-On/Power-Off
Response Time section.
MULTIPLE RF INPUTS
Figure 44 shows a technique for combining multiple RF input
signals to the ADL5501. Some applications can share a single
detector for multiple bands. Three 16.5 Ω resistors in a T-network
combine the three 50 Ω terminations (including the ADL5501).
The broadband resistive combiner ensures that each port of the
Rev. B | Page 19 of 28
ADL5501
If the input of the ADL5501 is driven while the device is disabled
(ENBL = COMM), the leakage current of less than 1 μA increases
as a function of input level. When the device is disabled, the
output impedance increases to approximately 33.5 kΩ.
Table 4. Waveform and Output Filter Effects on Residual AC
Output
Residual AC
Waveform
64QAM
(7.4 dB CF)
CFILT, COUT V dc
mV p-p mV rms
1 nF,
0.5
1.0
2.0
0.5
1.0
2.0
0.5
1.0
2.0
0.5
1.0
2.0
0.5
1.0
2.0
0.5
1.0
2.0
0.5
1.0
2.0
0.5
1.0
2.0
0.5
1.0
2.0
0.5
1.0
2.0
0.5
1.0
2.0
0.5
1.0
2.0
83
11
The turn-on time and pulse response is strongly influenced by
the size of the square-domain filter and output shunt capacitor.
Figure 45 shows a plot of the output response to an RF pulse on
the RFIN pin, with a 0.1 μF output filter capacitor and no
square-domain filter capacitor. The falling edge is particularly
dependent on the output shunt capacitance, as shown in Figure 45.
open
175
394
49
21
47
Open,
0.1 μF
5.5
11
98
212
45
93
23
1 nF,
0.1 μF
5.5
11
PULSED RFIN
200
6.4
19
24
W-CDMA RL
(3.4 dB CF)
1 nF,
open
0.8
2.6
6.6
0.6
2.2
4.9
0.5
1.4
3.9
8.6
19
400mV rms RF INPUT
250mV rms
52
Open,
0.1 μF
4.5
16
36
160mV rms
70mV rms
1 nF,
0.1 μF
3.1
9.6
27
CDMA2000 DL 1 nF,
(6.7 dB CF)
67
2ms/DIV
open
148
339
28
56
119
26
Figure 45. Output Response to Various RF Input Pulse Levels,
Supply = 3 V, Frequency = 900 MHz,
43
Open,
0.1 μF
3.9
7.9
17
Square-Domain Filter Open, Output Filter = 0.1 μF
To improve the falling edge of the enable and pulse responses,
a resistor can be placed in parallel with the output shunt capacitor.
The added resistance helps to discharge the output filter capacitor.
Although this method reduces the power-off time, the added
load resistor also attenuates the output (see the Output Drive
Capability and Buffering section).
1 nF,
0.1 μF
3.7
7.7
17
52
116
204
396
840
60
W-CDMA UL
TM1-64, 1 CR open
1 nF,
32
64
140
11
PULSED RFIN
Open,
0.1 μF
400mV rms RF INPUT
112
227
56
21
42
1 nF,
0.1 μF
11
250mV rms
114
243
21
45
160mV rms
70mV rms
POWER CONSUMPTION, ENABLE, AND POWER-
ON/POWER-OFF RESPONSE TIME
The quiescent current consumption of the ADL5501 varies with
the size of the input signal from approximately 1.1 mA for no
signal up to 6.2 mA at an input level of 0.7 V rms (10 dBm,
re: 50 Ω). If the input is driven beyond this point, the supply
current increases sharply (as shown in Figure 6). There is little
variation in quiescent current with power supply voltage.
2ms/DIV
Figure 46. Output Response to Various RF Input Pulse Levels,
Supply = 3 V, Frequency = 900 MHz,
Square-Domain Filter Open, Output Filter = 0.1 μF with Parallel 1 kΩ
The square-domain filter improves the rms accuracy for high
crest factors (see the Selecting the Square-Domain Filter and
Output Low-Pass Filter section), but it can hinder the response
time. For optimum response time and low ac residual, both the
square-domain filter and the output filter should be used.
The ADL5501 can be disabled either by pulling ENBL (Pin 5) to
COMM (Pin 4) or by removing the supply power to the device.
Disabling the device via the ENBL function reduces the leakage
current to less than 1 μA.
Rev. B | Page 20 of 28
ADL5501
The square-domain filter at FLTR can be reduced to improve
response time, and the remaining ac residual can be decreased
by using the output filter, which has a smaller time constant.
VRMS OUTPUT OFFSET
The ADL5501 has a 1 dB error detection range of about 30 dB,
as shown in Figure 10 to Figure 12 and Figure 16 to Figure 18.
The error is referred to the best-fit line defined in the linear region
of the output response. Below an input power of −20 dBm, the
response is no longer linear and begins to lose accuracy. In addi-
tion, depending on the supply voltage, saturation of the output
limits the detection accuracy above 10 dBm. Calibration points
should be chosen in the linear region, avoiding the nonlinear
ranges at the high and low extremes.
OUTPUT DRIVE CAPABILITY AND BUFFERING
The ADL5501 is capable of sourcing an output current of approx-
imately 3 mA. The output current is sourced through the on-chip,
100 Ω series resistor; therefore, any load resistor forms a voltage
divider with this on-chip resistance.
It is recommended that the ADL5501 drive high resistive loads
to preserve output swing. If an application requires driving a low
resistance load, a simple buffering circuit can be used, as shown
in Figure 49. Similar circuits can be used to increase or decrease
the nominal conversion gain (see Figure 47 and Figure 48). In
Figure 48, the AD8031 buffers a resistive divider to give half of
the slope. In Figure 47, the op amp gain of two doubles the slope.
Using other resistor values, the slope can be changed to an arbitrary
value. The AD8031 rail-to-rail op amp, used in these examples,
can swing from 50 mV to 4.95 V on a single 5 V supply and
operates at supply voltages down to 2.7 V. If high output current
is required (>10 mA), the AD8051, which also has rail-to-rail
capability, can be used down to a supply voltage of 3 V. It can
deliver up to 45 mA of output current.
Figure 50 shows the distribution of the output response vs. the
input power for multiple devices. The ADL5501 loses accuracy at
low input powers as the output response begins to fan out. As the
input power is reduced, the spread of the output response increases
along with the error. Although some devices follow the ideal linear
response at very low input powers, not all devices continue the
ideal linear regression to a near 0 V y-intercept. Some devices
exhibit output responses that rapidly decrease, and some flatten
out. With no RF signal applied, the ADL5501 has a typical output
offset of 50 mV (with a maximum of 150 mV).
10
5V
0.1µF
100pF
1
0.01µF
VPOS
VRMS
12.6V/V rms
AD8031
ADL5501
0.1
COMM
5kΩ
5kΩ
0.01
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10
15
Figure 47. Output Buffering Options, Slope of 12.6 V/V rms at 900 MHz
INPUT (dBm)
5V
Figure 50. Output vs. Input Level Distribution of 50 Devices,
Frequency = 900 MHz, Supply = 5.0 V
0.1µF
100pF
VPOS
VRMS
0.01µF
4kΩ
5kΩ
ADL5501
3.2V/V rms
AD8031
COMM
Figure 48. Output Buffering Options, Slope of 3.2 V/V rms at 900 MHz
5V
0.1µF
100pF
0.01µF
VPOS
VRMS
6.3V/V rms
AD8031
ADL5501
COMM
Figure 49. Output Buffering Options, Slope of 6.3 V/V rms at 900 MHz
Rev. B | Page 21 of 28
ADL5501
DEVICE CALIBRATION AND ERROR CALCULATION
CALIBRATION FOR IMPROVED ACCURACY
Because slope and intercept vary from device to device, board-
level calibration must be performed to achieve high accuracy.
In general, calibration is performed by applying two input power
levels to the ADL5501 and measuring the corresponding output
voltages. The calibration points are generally chosen to be within
the linear operating range of the device. The best-fit line is char-
acterized by calculating the conversion gain (or slope) and intercept
using the following equations:
Another way of presenting the error function of the ADL5501
is shown in Figure 52. In this case, the dB error at hot and cold
temperatures is calculated with respect to the transfer function
at ambient. This is a key difference in comparison to the previous
plots. Up until now, the errors were calculated with respect to
the ideal linear transfer function at ambient. When this alterna-
tive technique is used, the error at ambient becomes equal to
zero by definition (see Figure 52).
3
Gain = (VRMS2 − VRMS1)/(VIN2 − VIN1
Intercept = VRMS1 − (Gain × VIN1
where:
)
(2)
(3)
)
2
V
V
IN is the rms input voltage to RFIN.
RMS is the voltage output at VRMS.
1
+85°C
+25°C
0
After gain and intercept are calculated, an equation can be
written that allows calculation of an (unknown) input power
based on the measured output voltage.
–40°C
–1
V
IN = (VRMS − Intercept)/Gain
(4)
–2
For an ideal (known) input power, the law conformance error of
the measured data can be calculated as
–3
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
ERROR (dB) =
Figure 52. Error from +25°C Output Voltage at −40°C, +25°C, and +85°C
After Ambient Normalization, Frequency = 1900 MHz, Supply = 5.0 V
20 × log [(VRMS, MEASURED − Intercept)/(Gain × VIN, IDEAL)] (5)
Figure 51 includes a plot of the error at 25°C, the temperature
at which the ADL5501 is calibrated. Note that the error is not
zero; this is because the ADL5501 does not perfectly follow the
ideal linear equation, even within its operating region. The
error at the calibration points is, however, equal to zero by
definition.
This plot is a useful tool for estimating temperature drift at a
particular power level with respect to the (nonideal) response at
ambient. The linearity and dynamic range tend to be improved
artificially with this type of plot because the ADL5501 does not
perfectly follow the ideal linear equation (especially outside of
its linear operating range). Achieving this level of accuracy in
an end application requires calibration at multiple points in the
operating range of the device.
3
2
In some applications, very high accuracy is required at just one
power level or over a reduced input range. For example, in a wire-
less transmitter, the accuracy of the high power amplifier (HPA)
is most critical at or close to full power. The ADL5501 offers a
tight error distribution in the high input power range, as shown
in Figure 52. The high accuracy range, centered around 9 dBm at
1900 MHz, offers 7 dB of 0.1 dB detection error over temperature.
Multiple point calibration at ambient temperature in the reduced
range offers precise power measurement with near 0 dB error
from −40°C to +85°C.
1
+85°C
+25°C
0
–40°C
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
The high accuracy range center varies over frequency. At
1900 MHz, the region is centered at approximately 9 dBm.
At higher frequencies, the high accuracy range is centered
at higher input powers (see Figure 13 through Figure 15 and
Figure 19 through Figure 21).
Figure 51. Error from Linear Reference vs. Input at −40°C, +25°C, and
+85°C vs. +25°C Linear Reference, Frequency = 1900 MHz, Supply = 5.0 V
Figure 51 also includes error plots for the output voltage at
−40°C and +85°C. These error plots are calculated using the
gain and intercept at +25°C. This is consistent with calibra-
tion in a mass-production environment where calibration at
temperature is not practical.
Rev. B | Page 22 of 28
ADL5501
DRIFT OVER A REDUCED TEMPERATURE RANGE
Due to the repeatability of the performance from part to part,
compensation can be applied to reduce the effects of temperature
drift and linearity error. To detect larger dynamic ranges at
lower frequencies, the transfer function at ambient can be
calibrated, thus eliminating the linearity error. This technique
is discussed in detail in the Calibration for Improved Accuracy
section. Figure 55 shows that the dynamic range within 0.5 dB
error improves to 30 dB by using this method.
Figure 53 shows the error over temperature for a 1.9 GHz input
signal. Error due to drift over temperature consistently remains
within 0.25 dB and begins to exceed this limit only when the
ambient temperature goes above +25°C and below −10°C. For
all frequencies using a reduced temperature range, higher
measurement accuracy is achievable.
1.00
+15°C
0°C
–10°C
–25°C
–40°C
+85°C
+70°C
+50°C
+35°C
+25°C
3
0.75
0.50
0.25
0
2
1
0
–0.25
–0.50
–0.75
–1.00
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm rms)
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
Figure 53. Typical Drift at 1.9 GHz for Various Temperatures
Figure 55. Output Delta from +25°C Output Voltage for
12 Devices at −40°C and +85°C, Frequency = 50 MHz, Supply = 5.0 V
OPERATION BELOW 100 MHz
The ADL5501 works at frequencies below 100 MHz but exhibits a
slightly higher linearity error. Figure 54 shows the error distribution
of 12 devices at 50 MHz over temperature. When compared to
an ideal linear transfer function at ambient, the error of the
ADL5501 over temperature remains within 0.5 dB for the
central 20 dB of the dynamic range. At the higher input power
levels, the error grows as the response becomes nonlinear. The
typical slope and intercept at 50 MHz are 4.5 V/V rms and
0.04 V, respectively.
EVALUATION BOARD
Figure 56 shows the schematic of the ADL5501 evaluation
board. The layout and silkscreen of the evaluation board layers
are shown in Figure 57 and Figure 58. The board is powered by
a single supply in the 2.7 V to 5.5 V range. The power supply is
decoupled by 100 pF and 0.1 μF capacitors. Table 5 details the
various configuration options of the evaluation board.
Problems caused by impedance mismatch can arise when the
evaluation board is used to examine ADL5501 performance.
One way to reduce these problems is to put a coaxial 3 dB atten-
uator on the RFIN SMA connector. Mismatches at the source,
cable, and cable interconnection, as well as those occurring on
the evaluation board, can cause these problems.
3
2
1
A simple (and common) example of such a problem is triple
travel due to mismatch at both the source and the evaluation
board. Here the signal from the source reaches the evaluation
board, and mismatch causes a reflection. When that reflection
reaches the source mismatch, it causes a new reflection, which
travels back to the evaluation board, adding to the original signal
incident at the board. The resulting voltage varies with both
cable length and frequency dependence on the relative phase of
the initial and reflected signals. Placing the 3 dB pad at the input of
the board improves the match at the board and, thus, reduces
the sensitivity to mismatches at the source. When such precau-
tions are taken, measurements are less sensitive to cable length and
other fixture issues. In an actual application when the distance
between the ADL5501 and the source is short and well defined,
this 3 dB attenuator is not needed.
0
–1
–2
–3
–25
–20
–15
–10
–5
0
5
10
15
INPUT (dBm)
Figure 54. Temperature Drift Distributions for 12 Devices at −40°C, +25°C,
and +85°C vs. +25°C Linear Reference, Frequency = 50 MHz, Supply = 5.0 V
Rev. B | Page 23 of 28
ADL5501
TO EDGE
CONNECTOR
C1
C2
R5
100pF
0.1µF
(OPEN)
R3
0Ω
ADL5501
1
2
3
6
5
4
VRMS
ENBL
VPOS
VRMS
VPOS
C3
(OPEN)
C4
R2
100nF
(OPEN)
FLTR
RFIN
ENBL
VPOS
SW1
RFIN
COMM
R1
(OPEN)
R4
49.9Ω
TO EDGE
CONNECTOR
Figure 56. Evaluation Board Schematic
Table 5. Evaluation Board Configuration Options
Component Description
Default Condition
GND, VPOS
C1, C2
Ground and supply vector pins.
Power supply decoupling. The nominal supply decoupling of 100 pF and 0.1 μF.
Not applicable
C1 = 100 pF (Size 0402)
C2 = 0.1 μF (Size 0402)
C3
Filter capacitor. The internal averaging capacitor can be augmented by placing additional
capacitance in C3.
C3 = open (Size 0402)
R2, R3, C4
Output filtering. The combination of the internal 100 Ω output resistance and C4 produces a low-
pass filter to reduce output ripple. The output can also be scaled down using the resistor divider
pads, R3 and R2. In addition, resistors and capacitors can be placed in C4 and R2 to load test VRMS.
R2 = open (Size 0402)
R3 = 0 Ω (Size 0402)
C4 = 100 nF (Size 0402)
R4, SW1
R1, R5
Device enable. When the switch is set toward the SW1 label, the ENBL pin is connected to VPOS,
and the ADL5501 is in operating mode. In the opposite switch position, the ENBL pin is grounded
(through the 49.9 Ω resistor), putting the device in power-down mode. While in this switch position,
the ENBL pin can be driven by a signal generator via the SMA labeled ENBL. In this case, R4 serves as
a termination resistor for generators requiring a 50 Ω match.
R4 = 49.9 Ω (Size 0402)
SW1 = toward SW1 label
Alternate interface. R1and R5 allow for VRMS and ENBL to be accessible from the edge
connector, which is used only for characterization.
R1 = open (Size 0402)
R5 = open (Size 0402)
Figure 57. Layout of Evaluation Board, Component Side
Figure 58. Layout of Evaluation Board, Circuit Side
Rev. B | Page 24 of 28
ADL5501
OUTLINE DIMENSIONS
2.20
2.00
1.80
2.40
2.10
1.80
6
1
5
2
4
3
1.35
1.25
1.15
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
0.40
0.10
1.10
0.80
0.46
0.36
0.26
0.30
0.15
0.22
0.08
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 59. 6-Lead Thin Shrink Small Outline Transistor Package [SC-70]
(KS-6)
Dimensions shown in millimeters
ORDERING GUIDE
Ordering
Model
Temperature Range
Package Description
Package Option
Branding Quantity
ADL5501AKSZ-R71 –40°C to +85°C
6-Lead SC-70, 7”Tape and Reel
6-Lead SC-70, 7”Tape and Reel
Evaluation Board
KS-6
KS-6
Q0Z
Q0Z
3,000
250
ADL5501AKSZ-R21
ADL5501-EVALZ1
–40°C to +85°C
1 Z =RoHS Compliant Part.
Rev. B | Page 25 of 28
ADL5501
NOTES
Rev. B | Page 26 of 28
ADL5501
NOTES
Rev. B | Page 27 of 28
ADL5501
NOTES
©2006–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06056-0-3/09(B)
Rev. B | Page 28 of 28
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