ADL5385ACPZ-R7 [ADI]
50 MHz to 2200 MHz Quadrature Modulator; 50 MHz至2200 MHz的正交调制器
| 型号： | ADL5385ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | 50 MHz to 2200 MHz Quadrature Modulator |
| 文件： | 总24页 (文件大小：1060K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50 MHz to 2200 MHz
Quadrature Modulator
ADL5385
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ENBL
Output frequency range: 50 MHz to 2200 MHz
1 dB output compression: 11 dBm @ 350 MHz
Noise floor: –159 dBm/Hz @ 350 MHz
Sideband suppression: −50 dBc @ 350 MHz
Carrier feedthrough: −46 dBm @ 350 MHz
Single supply: 4.75 V to 5.5 V
BIAS
TEMPERATURE
TEMP
SENSOR
IBBP
IBBN
24-lead, Pb-free LFCSP_VQ with exposed paddle
APPLICATIONS
LOIP
LOIN
DIVIDE-BY-2
Radio-link infrastructure
VOUT
QUADRATURE
PHASE
Cable modem termination systems
Wireless infrastructure systems
Wireless local loop
SPLITTER
WiMAX/broadband wireless access systems
QBBP
QBBN
Figure 1.
PRODUCT DESCRIPTION
The ADL5385 is a silicon, monolithic, quadrature modulator
designed for use from 50 MHz to 2200 MHz. Its excellent phase
accuracy and amplitude balance enable both high performance
intermediate frequency (IF) and direct radio frequency (RF)
modulation for communication systems.
The ADL5385 can be used as either an IF or a direct-to-RF
modulator in digital communication systems. The wide
baseband input bandwidth allows for either baseband drive or
drive from a complex IF. Typical applications are in radio-link
transmitters, cable modem termination systems, and broadband
wireless access systems.
The AD5385 takes the signals from two differential baseband
inputs and modulates them onto two carriers in quadrature
with each other. The two internal carriers are derived from
a single-ended, external local oscillator input signal at twice the
frequency as the desired carrier output. The two modulated
signals are summed together in a differential-to-single-ended
amplifier designed to drive 50 Ω loads.
The ADL5385 is fabricated using the Analog Devices, Inc.,
advanced silicon germanium bipolar process and is packaged in
a 24-lead, Pb-free LFCSP_VQ with exposed paddle.
Performance is specified over –40°C to +85°C. A Pb-free
evaluation board is also available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADL5385
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Description......................................................................... 1
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Functional Descriptions.......................... 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 12
Overview...................................................................................... 12
LO Interface................................................................................. 12
V-to-I Converter......................................................................... 12
Mixers .......................................................................................... 12
D-to-S Amplifier......................................................................... 12
Bias Circuit.................................................................................. 12
Basic Connections.......................................................................... 13
Optimization............................................................................... 13
Applications..................................................................................... 15
DAC Modulator Interfacing ..................................................... 15
155 Mbps (STM-1) 128 QAM Transmitter............................. 16
CMTS Transmitter Application................................................ 16
Spectral Products from Harmonic Mixing ............................. 17
RF Second-Order Products....................................................... 17
LO Generation Using PLLs....................................................... 18
Transmit DAC Options ............................................................. 18
Modulator/Demodulator Options ........................................... 18
Evaluation Board ............................................................................ 19
Characterization Setup .................................................................. 21
SSB Setup..................................................................................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5385
SPECIFICATIONS
Unless otherwise noted, VS = 5 V; TA = 25°C; LO = −7 dBm; I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc
bias; baseband frequency = 1 MHz; LO source and RF output load impedances are 50 Ω.
Table 1.
Parameter
Conditions
Min
50
100
Typ
Max
2200
4400
Unit
MHz
MHz
OUTPUT FREQUENCY RANGE
EXTERNAL LO FREQUENCY
RANGE
External LO frequency is twice output frequency
OUTPUT FREQUENCY = 50 MHz
Output Power
Output P1 dB
Single (lower) sideband output
4
5.6
8
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
degrees
dB
dBm/Hz
dBm/Hz
dB
11
−57
−67
−67
−57
−64
−68
−83
−58
69
Carrier Feedthrough
Unadjusted (nominal drive level)
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
Unadjusted (nominal drive level)
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
(FLO − (2 × FBB)), POUT = 5 dBm
(FLO + (3 × FBB)), POUT = 5 dBm
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
26
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
−0.17
−0.03
−155
−150
−19
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Output Return Loss
OUTPUT FREQUENCY = 140 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Single (lower) sideband output
5.7
11
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
degrees
dB
dBm/Hz
dB
Unadjusted (nominal drive level)
−52
−66
−67
−53
−63
−68
−83
−57
70
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
Unadjusted (nominal drive level)
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
(FLO − (2 × FBB)), POUT = 5 dBm
(FLO + (3 × FBB)), POUT = 5 dBm
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT =−3 dBm per tone
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
26
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
Output Return Loss
OUTPUT FREQUENCY = 350 MHz
Output Power
−0.33
−0.03
−160
−20
20 MHz offset from LO, all BB inputs at a bias of 500 mV
Single (lower) sideband output
3
5.6
11
7
dBm
dBm
dBm
dBm
dBm
dBc
Output P1 dB
Carrier Feedthrough
Unadjusted (nominal drive level)
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
Unadjusted (nominal drive level)
@ +85°C after optimization at +25°C
@ −40°C after optimization at+25°C
−46
−65
−66
−50
−63
−61
Sideband Suppression
dBc
dBc
Rev. 0 | Page 3 of 24
ADL5385
Parameter
Conditions
Min
Typ
−80
−53
71
Max
Unit
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
(FLO − (2 × FBB)), POUT = 5 dBm
(FLO + (3 × FBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
dBc
dBc
dBm
dBm
degrees
dB
dBm/Hz
dBm/Hz
dB
Output IP3
26
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
0.39
−0.03
−159
−157
−21
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Output Return Loss
OUTPUT FREQUENCY = 860 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Single (lower) sideband output
2.5
5.3
11
6.5
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
degrees
dB
dBm/Hz
dBm/Hz
dB
Unadjusted (nominal drive level)
−41
−63
−65
−41
−58
−59
−73
−50
70
−35
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
Unadjusted (nominal drive level)
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
(FLO − (2 × FBB)), POUT = 5 dBm
(FLO + (3 × FBB)), POUT = 5 dBm
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
Sideband Suppression
−35
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
−57
−45
Output IP3
25
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
0.67
−0.03
−159
−157
−19
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Output Return Loss
OUTPUT FREQUENCY =
1450 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Single (lower) sideband output
4.4
10
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
degrees
dB
dBm/Hz
dB
Unadjusted (nominal drive level)
−36
−50
−50
−44
−61
−51
−64
−52
63
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
Unadjusted (nominal drive level)
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
(FLO − (2 × FBB)), POUT = 4 dBm
(FLO + (3 × FBB)), POUT = 4 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
24
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
0.42
−0.02
−160
−33
20 MHz offset from LO, all BB inputs at a bias of 500 mV
Output Return Loss
OUTPUT FREQUENCY =
1900 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Single (lower) sideband output
3.4
9
−35
−51
−51
−33
dBm
dBm
dBm
dBm
dBm
dBc
Unadjusted (nominal drive level)
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
Unadjusted (nominal drive level)
Sideband Suppression
Rev. 0 | Page 4 of 24
ADL5385
Parameter
Conditions
Min
Typ
−43
−47
−58
−47
57
22
2.6
0.003
−160
−156
−20
Max
Unit
dBc
dBc
dBc
dBc
dBm
dBm
degrees
dB
dBm/Hz
dBm/Hz
dB
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
(FLO − (2 × FBB)), POUT = 3 dBm
(FLO + (3 × FBB)), POUT = 3 dBm
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Output Return Loss
OUTPUT FREQUENCY =
2150 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Single (lower) sideband output
2.6
8
−36
−47
−48
−37
dBm
dBm
dBm
dBm
dBm
dBc
Unadjusted (nominal drive level)
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
Unadjusted (nominal drive level)
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
(FLO − (2 × FBB)), POUT = 2.6 dBm
(FLO + (3 × FBB)), POUT = 2.6 dBm
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
−56
−45
54
dBc
dBc
dBm
dBm
Output IP3
21
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
1.5
degrees
dB
dBm/Hz
dBm/Hz
dB
< 0.05
−160
−156
−15
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Output Return Loss
LO INPUTS
Pin LOIP and Pin LOIN
LO Drive Level
Characterization performed at typical level
−10
–7
50
−20
+5
dBm
Ω
dB
Input Impedance
Input Return Loss
BASEBAND INPUTS
I and Q Input Bias Level
Input Bias Current
Bandwidth (0.1 dB)
Bandwidth (3 dB)
ENABLE INPUT
350 MHz, LOIN ac-coupled to ground
Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN
500
−70
80
mV
μA
MHz
MHz
RF = 500 MHz, output power = 0 dBm
RF = 500 MHz, output power = 0 dBm
ENBL
>500
Turn-On Settling Time
Turn-Off Settling Time
ENBL High Level (Logic 1)
ENBL Low Level (Logic 0)
TEMPERATURE OUTPUT
Output Voltage
ENBL = high (for output to within 0.5 dB of final value)
ENBL = low (at supply current falling below 20 mA)
1.0
1.4
μs
μs
V
1.5
0.4
V
TEMP
1.56
4.6
V
TA = 27.15°C, 300K, RL = 1 MΩ (after full warmup)
−40°C ≤ TA ≤ +85°C, RL = 1 MΩ
Temperature Slope
Output Impedance
POWER SUPPLIES
Voltage
mV/°C
kΩ
1.0
Pin VPS1 and Pin VPS2
4.75
5.5
V
Supply Current
ENBL = high
ENBL = low
215
80
240
mA
μA
Rev. 0 | Page 5 of 24
ADL5385
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage VPOS
5.5 V
IBBP, IBBN, QBBP, QBBN Range
LOIP and LOIN
0 V to 2.0 V
13 dBm
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
1.375 W
58°C/W
164°C
−40°C to +85°C
−65°C to +150°C
ESD CAUTION
Rev. 0 | Page 6 of 24
ADL5385
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
PIN 1
INDICATOR
NC
NC
NC
COM1
COM1
COM1
1
2
3
4
5
6
18 QBBP
17 QBBN
16 COM2
15 COM2
14 IBBN
13 IBBP
EXPOSED
PADDLE
ADL5385
4 × 4 LFCSP
NC = NO CONNECT
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 3
NC
No Connection. These pins can be left open or tied to ground.
4, 5, 6, 15,
16, 19, 20
COM1, COM2,
COM3
Power Supply Common Pins. COM1, COM2, and COM3 must all be connected to a ground plane via a
low impedance path.
7
VOUT
Device Output. Single-ended, 50 Ω internally biased RF/IF output; pin must be ac-coupled to the load.
8, 9, 11, 23,
24
VPS1, VPS2,
VPS3
Power Supply Pins. Decouple each pin with a 0.1 ꢀF capacitor; Pin 8 and Pin 9 can share a single
capacitor, as can Pin 23 and Pin 24. All pins must be connected to the same supply (Vs).
10
12
TEMP
ENBL
Temperature Sensor Output. Provides dc voltage proportional to die temperature. Slope is 4.6 mV/°C
Device Enable. Shuts device down when grounded and enables device when pulled to supply
voltage.
13, 14, 17,
18
IBBP, IBBN,
QBBN, QBBP
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be
externally dc-biased to 500 mV dc and driven from a low impedance source. Nominal characterized
ac signal swing is 700 mV p-p on each pin (150 mV to 850 mV). This results in a differential drive of
1.4 V p-p with a 500 mV dc bias.
21
22
LOIP
LOIN
Single-Ended Two-Times Local Oscillator Input. This input is internally biased and must be
ac-coupled to the LO source.
Common for LO Input. Must be ac-coupled to ground through a low impedance path.
Rev. 0 | Page 7 of 24
ADL5385
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, VS = 5 V; TA = 25°C; LO = −7 dBm; I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias;
baseband frequency = 1 MHz; LO source and RF output load impedances are 50 Ω.
8
7
14
13
12
11
10
9
V
V
V
= 5.5V
= 5.V
= 4.75V
V
V
V
= 5.5V
= 5.V
= 4.75V
S
S
S
S
S
S
6
5
4
3
2
1
8
0
7
–1
–2
–3
–4
6
5
4
50
550
1050
1550
2050
50
550
1050
1550
2050
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
Figure 3. Single Sideband (SSB) Output Power (POUT) vs. Output Frequency
and Power Supply
Figure 6. Output 1 dB Compression Point (OP1dB) vs. Output Frequency
and Power Supply
8
14
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
7
6
5
4
3
2
1
0
12
10
8
6
4
2
0
50
550
1050
1550
2050
50
550
1050
1550
2050
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
Figure 7. Output 1 dB Compression Point (OP1dB) vs. Output Frequency
and Temperature
Figure 4. Single Sideband (SSB) Output Power (POUT) vs. Output Frequency
and Temperature
–20
–30
–40
–50
–60
–70
–80
15
10
5
SSB OUTPUT POWER (dBm)
2.0
1.5
CARRIER FEEDTHROUGH (dBm)
SIDEBAND SUPPRESSION (dBc)
SECOND-ORDER DISTORTION (dBc)
THIRD-ORDER DISTORTION (dBc)
1.0
0.5
0
0
–5
–10
–15
–0.5
–1.0
–1.5
–2.0
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
3.4
BASEBAND AMPLITUDE (V p-p)
10M
100M
1G
BASEBAND FREQUENCY (Hz)
Figure 8. SSB Output Power, Second- and Third-Order Distortion,
Carrier Feedthrough and Sideband Suppression vs. Differential
Baseband Input Level; Output Frequency = 350 MHz
Figure 5. Baseband Frequency Response Normalized to Response for 1 MHz
BB Signal; Carrier Frequency = 500 MHz
Rev. 0 | Page 8 of 24
ADL5385
–20
–30
–40
–50
–60
–70
–80
15
10
5
0.7100
0.7075
0.7050
0.7025
0.7000
0.6975
0.6950
0.6925
0.6900
SSB OUTPUT POWER (dBm)
CARRIER FEEDTHROUGH (dBm)
SIDEBAND SUPPRESSION (dBc)
SECOND-ORDER DISTORTION (dBc)
THIRD-ORDER DISTORTION (dBc)
0
–5
–10
–15
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
3.4
50
250
450
650
850 1050 1250 1450 1650 1850
BASEBAND AMPLITUDE (V p-p)
OUTPUT FREQUENCY (MHz)
Figure 12. Distribution of Peak Q Amplitude to Null Undesired Sideband
(Peak I Amplitude Held Constant at 0.7 V)
Figure 9. SSB Output Power, Second- and Third-Order Distortion,
Carrier Feedthrough and Sideband Suppression vs. Baseband Single-
Ended Input Level; Output Frequency = 860 MHz
0
98
97
96
95
94
93
92
91
90
89
88
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
50
550
1050
1550
2050
50
250
450
650
850 1050 1250 1450 1650 1850
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
Figure 13. Distribution of IQ Phase to Null Undesired Sideband
Figure 10. Sideband Suppression vs. Output Frequency and
Temperature
–20
0
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–10
–20
–30
–40
–50
–60
–70
–80
–90
1M
10M
100M
50
250
450
650
850 1050 1250 1450 1650 1850
BASEBAND FREQUENCY (Hz)
OUTPUT FREQUENCY (MHz)
Figure 11. Sideband Suppression vs. Baseband Frequency;
Output Frequency = 350 MHz
Figure 14. Sideband Suppression Distribution at Temperature Extremes,
After Sideband Suppression Nulled to < −50 dBc at TA = +25°C
Rev. 0 | Page 9 of 24
ADL5385
–20
–30
–40
–50
–60
–70
–80
–90
0.010
0.008
0.006
0.004
0.002
0
50MHz
350MHz
Q OFFSET
I OFFSET
–0.002
–0.004
–0.006
–0.008
–0.010
–10
–8
–6
–4
–2
0
2
4
50
550
1050
1550
2050
LO AMPLITUDE (dBm)
OUTPUT FREQUENCY (MHz)
Figure 15. Distribution of Sideband Suppression vs. LO Input Power at
50 MHz and 350 MHz
Figure 18. Distribution of I and Q Offset Required to Null Carrier
Feedthrough
–20
–20
T
T
T
= –40°C
= +25°C
= +85°C
50MHz
350MHz
A
A
A
–30
–40
–50
–60
–70
–80
–90
–30
–40
–50
–60
–70
–80
50
550
1050
1550
2050
–10
–8
–6
–4
–2
0
2
4
OUTPUT FREQUENCY (MHz)
LO AMPLITUDE (dBm)
Figure 16. Distribution Carrier Feedthrough vs. Output Frequency and
Temperature
Figure 19. Distribution Carrier Feedthrough vs. LO Input Power at
50 MHz and 350 MHz
0
80
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
OIP2
–10
–20
–30
–40
–50
–60
–70
–80
–90
70
60
50
40
30
20
10
0
OIP3
50
550
1050
1550
2050
50
550
1050
1550
2050
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
Figure 17. Carrier Feedthrough Distribution at Temperature Extremes,
After Nulling to < −65 dBm at TA = +25°C
Figure 20. OIP3 and OIP2 vs. Output Frequency and Temperature
Rev. 0 | Page 10 of 24
ADL5385
20
18
16
14
12
10
8
90
60
120
S11 OF LOIP
4400MHz
150
30
S22 OF OUTPUT
2200MHz
50MHz
180
0
6
4
100MHz
2
210
330
0
–156.7 –156.6 –156.5 –156.4 –156.3 –156.2 –156.1 –156.0 –155.9
dBm/Hz AT 20MHz OFFSET FROM LO FREQUENCY
Figure 21. 20 MHz Offset Noise Floor Distribution,
Output Frequency = 350 MHz, POUT = −5 dBm, QPSK Carrier,
Symbol Rate = 3.84 MSPS
240
300
270
20
Figure 24. Output Impedance and LO Input Impedance vs. Frequency
18
16
14
12
10
8
0.300
V
V
V
= 5.5V
= 5V
= 4.75V
S
S
S
0.275
0.250
0.225
0.200
0.175
0.150
6
4
2
0
–155.2 –155.1 –155.0 –154.9 –154.8 –154.7 –154.6 –154.5 –154.4
dBm/Hz AT 12MHz OFFSET FROM LO FREQUENCY
–40
25
85
Figure 22. 12 MHz Offset Noise Floor Distribution,
TEMPERATURE (°C)
Output Frequency = 860 MHz, POUT = −5 dBm, 64 QAM Carrier,
Symbol Rate = 5 MSPS
Figure 25. Power Supply Current vs. Temperature and Supply Voltage
0
–5
–10
–15
–20
–25
100 530 960 1390 1820 2250 2680 3110 3540 3970 4400
LOIP FREQUENCY (MHz)
Figure 23. LO Port Input Return Loss vs. Frequency
Rev. 0 | Page 11 of 24
ADL5385
CIRCUIT DESCRIPTION
OVERVIEW
V-TO-I CONVERTER
The differential baseband input voltages that are applied to the
baseband input pins are fed to a pair of common-emitter,
voltage-to-current converters. The output currents then
modulate the two half-frequency LO carriers in the mixer stage.
The ADL5385 can be divided into five sections: the local
oscillator (LO) interface, the baseband voltage-to-current (V-to-I)
converter, the mixers, the differential-to-single-ended (D-to-S)
amplifier, and the bias circuit. A detailed block diagram of the
device is shown in Figure 26.
MIXERS
ENBL
The ADL5385 has two double-balanced mixers: one for the in-
phase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistor-inductor
(RL) loads in the D-to-S amplifier.
BIAS
TEMPERATURE
TEMP
SENSOR
IBBP
IBBN
D-TO-S AMPLIFIER
The output D-to-S amplifier consists of two emitter followers
driving a totem-pole output stage. Output impedance is
established by the emitter resistors in the output transistors.
The output of this stage connects to the output (VOUT) pin.
LOIP
LOIN
DIVIDE-BY-2
QUADRATURE
PHASE
VOUT
SPLITTER
BIAS CIRCUIT
A band gap reference circuit generates the proportional-to-
absolute-temperature (PTAT) as well as temperature-independ-
ent reference currents used by different sections. The band-gap
circuit is turned on by a logic HIGH at the ENBL pin, which in
turn powers up the whole device. A PTAT voltage output is
available at the TEMP pin, which can be used for temperature
monitoring as well as for temperature compensation purposes.
QBBP
QBBN
Figure 26. ADL5385 Block Diagram
The LO interface generates two LO signals at 90° of phase
difference to drive two mixers in quadrature. Baseband signals
are converted into currents by the V-to-I converters that feed
into the two mixers. The outputs of the mixers are combined in
the differential-to-single-ended amplifier, which provides a 50 Ω
output interface. Reference currents to each section are
generated by the bias circuit. A detailed description of each
section follows.
LO INTERFACE
The LO interface consists of a buffer amplifier followed by a
pair of frequency dividers that generate two carriers at half the
input frequency and in quadrature with each other. Each carrier
is then amplified and amplitude-limited to drive the double-
balanced mixers.
Rev. 0 | Page 12 of 24
ADL5385
RF Output
BASIC CONNECTIONS
The RF output is available at the VOUT pin (Pin 7). This pin
must also be ac-coupled. The VOUT pin has a nominal
broadband impedance of 50 Ω and does not need further
external matching.
Figure 27 shows the basic connections for the ADL5385.
QBBP
QBBN
IBBN
IBBP
RFPQ
0Ω
RFNQ
0Ω
RFNI
0Ω
RFPI
0Ω
CFPQ
OPEN
CFNQ
OPEN
CFNI
OPEN
CFPI
OPEN
RTQ
OPEN
RTI
OPEN
OPTIMIZATION
R21
The carrier feedthrough and sideband suppression performance
of the ADL5385 can be improved through the use of optimiza-
tion techniques.
49.9Ω
OFF
ON
SW21
ENB
ENBL
19 COM3
ENBL 12
R22
10kΩ
VPOS
R13
0Ω
20 COM3
21 LOIP
22 LOIN
VPS2 11
TEMP 10
CLOP
C16
0.1µF
C15
OPEN
LO
Carrier Feedthrough Nulling
0.1µF
ADL5385
RTEMP
200Ω
TEMP
VPS1
9
4 × 4 LFCSP
Carrier feedthrough results from minute dc offsets that occur
between each of the differential baseband inputs. In an ideal
R12
0Ω
CLON
0.1µF
VPOS
23 VPS3
24 VPS3
VPS1
VOUT
8
7
EXPOSED PADDLE
R11
0Ω
C14
0.1µF
C13
OPEN
modulator, the quantities (VIOPP − VIOPN) and (VQOPP − VQOPN
are equal to zero, and this results in no carrier feedthrough. In
a real modulator, those two quantities are nonzero and, when
)
C11
C12
0.1µF
VOUT
OPEN
COUT
0.1µF
VPOS
GND
mixed with the LO, result in a finite amount of carrier feedthrough.
The ADL5385 is designed to provide a minimal amount of carrier
feedthrough. If even lower carrier feedthrough levels are required,
Figure 27. Basic Connections for the ADL5385
Power Supply and Grounding
All the VPS pins must be connected to the same 5 V source. Adja-
cent pins of the same name can be tied together and decoupled with
a 0.1 μF capacitor. These capacitors are located as close as possible
to the device. The power supply can range from 4.75 V to 5.5 V.
minor adjustments can be made to the (VIOPP − VIOPN) and (VQOPP
QOPN) offsets. The I-channel offset is held constant while the
−
V
Q-channel offset is varied until a minimum carrier feedthrough
level is obtained. The Q-channel offset required to achieve this
minimum is held constant while the offset on the I-channel is
adjusted, until a better minimum is reached. Through two
iterations of this process, the carrier feedthrough can be
reduced to as low as the output noise. The ability to null is
sometimes limited by the resolution of the offset adjustment.
Figure 28 shows the relationship of carrier feedthrough vs. dc offset.
–58
The COM1 pin, COM2 pin, and COM3 pin are tied to the same
ground plane through low impedance paths. The exposed
paddle on the underside of the package is also soldered to a low
thermal and electrical impedance ground plane. If the ground
plane spans multiple layers on the circuit board, they should be
stitched together with nine vias under the exposed paddle. The
Analog Devices AN-772 application note discusses the thermal
and electrical grounding of the LFCSP in greater detail.
–62
–66
–70
–74
–78
–82
–86
–90
–94
Baseband Inputs
The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. The nominal drive level of
1.4 V p-p differential (700 mV p-p on each pin) is biased to
a common-mode level of 500 mV dc.
The dc common-mode bias level for the baseband inputs can
range from 400 mV to 600 mV. This results in a reduction in the
usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5385 input range and on the top end by the output
compliance range on most Analog Devices DACs.
VP-VN OFFEST (µV)
LO Input
Figure 28. Carrier Feedthrough vs. DC Offset Voltage at 450 MHz
A single-ended LO signal is applied to the LOIP pin through an
ac coupling capacitor. The recommended LO drive power is
−7 dBm. The LO return pin, LOIN, must be ac-coupled to
ground though a low impedance path.
Note that throughout the nulling process, the dc bias for the
baseband inputs remains at 500 mV. When no offset is applied,
V
V
IOPP = VIOPN = 500 mV, or
IOPP − VIOPN = VIOS = 0 V
The nominal LO drive of −7 dBm can be increased to up to
+5 dBm. The effect of LO power on sideband suppression and
carrier feedthrough is shown in Figure 15 and Figure 19.
Rev. 0 | Page 13 of 24
ADL5385
When an offset of +VIOS is applied to the I-channel inputs,
Sideband Suppression Optimization
Sideband suppression results from relative gain and relative
phase offsets between the I and Q channels and can be
suppressed through adjustments to those two parameters.
Figure 30 illustrates how sideband suppression is affected by the
gain and phase imbalances.
V
V
V
IOPP = 500 mV + VIOS/2, while
IOPN = 500 mV − VIOS/2, such that
IOPP − VIOPN = VIOS
The same applies to the Q channel.
It is often desirable to perform a one-time carrier null
calibration. This is usually performed at a single frequency.
Figure 29 shows how carrier feedthrough varies with LO
frequency over a range of 50 MHz on either side of a null at
350 MHz.
0
–10
2.5dB
–20
1.25dB
0.5dB
–30
–40
–50
–60
–70
–80
0.25dB
0.125dB
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
0.05dB
0.025dB
0.0125dB
0dB
–90
0.01
0.1
1
10
100
PHASE ERROR (Degrees)
Figure 30. Sideband Suppression vs. Quadrature Phase Error for Various
Quadrature Amplitude Offsets
Figure 30 underscores the fact that adjusting one parameter
improves the sideband suppression only to a point; the other
parameter must also be adjusted. For example, if the amplitude
offset is 0.25 dB, improving the phase imbalance better than 1°
does not yield any improvement in the sideband suppression.
For optimum sideband suppression, an iterative adjustment
between phase and amplitude is required.
–85
300 310 320 330 340 350 360 370 380 390 400
OUTPUT FREQUENCY (MHz)
Figure 29. Carrier Feedthrough vs. Frequency After Nulling at 350 MHz
The sideband suppression nulling can be performed either through
adjusting the gain for each channel or through the modification
of the phase and gain of the digital data coming from the digital
signal processor.
Rev. 0 | Page 14 of 24
ADL5385
APPLICATIONS
DAC MODULATOR INTERFACING
AD9777
ADL5385
73
72
13
14
The ADL5385 is designed to interface with minimal components
to members of the Analog Devices family of digital-to-analog
converters (DAC). These DACs feature an output current swing
from 0 to 20 mA, and the interface described in this section can
be used with any DAC that has a similar output.
I
IBBP
OUTA1
RBIP
50Ω
RSLI
100Ω
RBIN
50Ω
I
IBBN
QBBN
QBBP
OUTB1
Driving the ADL5385 with an Analog Devices TxDAC®
69
68
17
18
I
OUTB2
An example of the interface using the AD9777 TxDAC is shown
in Figure 31. The baseband inputs of the ADL5385 require a dc
bias of 500 mV. The average output current on each of the
outputs of the AD9777 is 10 mA. Therefore, a single 50 Ω
resistor to ground from each of the DAC outputs results in an
average current of 10 mA flowing through each of the resistors,
thus producing the desired 500 mV dc bias for the inputs to the
ADL5385.
RBQN
50Ω
RSLQ
100Ω
RBQP
50Ω
I
OUTA2
Figure 32. AC Voltage Swing Reduction Through Introduction of Shunt
Resistor Between Differential Pair
The value of this ac voltage swing-limiting resistor is chosen
based on the desired ac voltage swing. Figure 33 shows the
relationship between the swing-limiting resistor and the peak-
to-peak ac swing that it produces when 50 Ω bias-setting
resistors are used.
AD9777
ADL5385
73
72
13
14
I
IBBP
OUTA1
RBIP
50Ω
RBIN
50Ω
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
I
OUTB1
IBBN
QBBN
QBBP
69
68
17
18
I
OUTB2
RBQN
50Ω
RBQP
50Ω
I
OUTA2
Figure 31. Interface Between AD9777 and ADL5385 with 50 Ω Resistors to
Ground to Establish the 500 mV DC Bias for the ADL5385 Baseband Inputs
The AD9777 output currents have a swing that ranges from
0 to 20 mA. With the 50 Ω resistors in place, the ac voltage
swing going into the ADL5385 baseband inputs ranges from
0 V to 1 V. A full-scale sine wave out of the AD9777 can be
described as a 1 V p-p single-ended (or 2 V p-p differential)
sine wave with a 500 mV dc bias.
10
100
1000
10000
R
(Ω)
L
Figure 33. Relationship Between AC Swing-Limiting Resistor and
Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors
Filtering
Limiting the AC Swing
When driving a modulator from a DAC, it is necessary to
introduce a low-pass filter between the DAC and the modulator
to reduce the DAC images. The interface for setting up the
biasing and ac swing lends itself well to the introduction of such
a filter. The filter can be inserted in between the dc bias setting
resistors and the ac swing-limiting resistor, thus establishing the
input and output impedances for the filter.
There are situations in which it is desirable to reduce the
ac voltage swing for a given DAC output current. This can be
achieved through the addition of another resistor to the
interface. This resistor is placed in shunt between each side of
the differential pair, as illustrated in Figure 32. It has the effect
of reducing the ac swing without changing the dc bias already
established by the 50 Ω resistors.
Examples of filters are discussed in the 155 MBPS (STM-1) 128
QAM Transmitter and the CMTS Transmitter Application
sections.
Rev. 0 | Page 15 of 24
ADL5385
Using AD9777 Auxiliary DAC for Carrier Feedthrough
Nulling
79
77
75
73
71
69
67
65
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
SNR
The AD9777 features an auxiliary DAC that can be used to
inject small currents into the differential outputs for each
channel. The auxiliary DAC can produce the small offset
currents necessary to implement the nulling described in the
Carrier Feedthrough Nulling section.
EVM WITHOUT EQUALIZATION
EVM WITH EQUALIZATION
155 Mbps (STM-1) 128 QAM TRANSMITTER
Figure 34 shows how the ADL5385 can be interfaced to the
AD9777 DAC (or any Analog Devices dual DAC with an output
bias level of 0.5 V) to generate a 155 Mbps 128 QAM carrier at
355 MHz. Because the TxDAC output and the IQ modulator inputs
operate at the same bias levels of 0.5 V, a simple dc-coupled
connection can be implemented without any active or passive
level shifting. The bias level and modulator drive level is set by
the 50 Ω ground-referenced resistors and the 100 Ω shunt
resistors, respectively (see the DAC Modulator Interfacing
section). A baseband filter is placed between the bias and signal
swing resistors. This 5-pole Chebychev filter with in-band
ripple of 0.1 dB has a corner frequency of 39 MHz.
I
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
CARRIER POWER (dBm)
Figure 36. EVM and SNR vs. Output Power for 128 QAM Transmitter
Application
CMTS TRANSMITTER APPLICATION
Because of its broadband operating range from 50 MHz to
2200 MHz, the ADL5385 can be used in direct-launch cable
modem termination systems (CMTS) applications in the
50 MHz to 860 MHz cable band.
50Ω LINE
100Ω LINE
CHANNEL
0Ω
317.4nH
372.5nH
The same DAC and DAC-to-modulator interface and filtering
circuit shown in Figure 34 was used in this application. Figure 37
shows a plot of a 4-carrier 256 QAM spectrum at an output
frequency of 485 MHz. Figure 38 shows how adjacent channel
power (measured at 750 KHz, 5.25 MHz, and 12 MHz offset
from the last carrier) and modulation error ratio (MER) vary
with carrier power.
IBBP
50Ω
67.5pF
1/2
AD9777
156.9pF
372.5nH
124.7pF
100Ω LINE
200Ω
317.4nH
50Ω LINE
0Ω
IBBN
50Ω
67.5pF
156.9pF
124.7pF
ADL5385
QBBP
Q
50Ω LINE
100Ω LINE
CHANNEL
0Ω
0Ω
317.4nH
317.4nH
372.5nH
50Ω
67.5pF
1/2
AD9777
156.9pF
372.5nH
124.7pF
100Ω LINE
200Ω
50Ω LINE
QBBN
50Ω
67.5pF
156.9pF
124.7pF
–70
Figure 34. Recommended DAC-Modulator Interconnect for128 QAM
Transmitter
–80
–90
Figure 35 shows a spectral plot of the 128 QAM spectrum at
a carrier power of −6.3 dBm. Figure 36 shows how EVM
(measured with the analyzer’s internal equalizer both on and
off) and SNR, measured at 55 MHz carrier offset (2.5 times the
carrier bandwidth) varies with output power.
–70
–100
–110
–120
–130
–140
–150
–160
–80
–90
–170
–100
–110
–120
–130
–140
–150
430 440 450 460 470 480 490 500 510 520 530 540
FREQUENCY (MHz)
Figure 37. Spectrum of 4-Carrier 256 QAM CMTS Signal at 485 MHz
–160
290 300 310 320 330 340 350 360 370 380 390 400 410 420
FREQUENCY (MHz)
Figure 35. Spectral Plot of 128 QAM Transmitter at −6.3 dBm Output Power
Rev. 0 | Page 16 of 24
ADL5385
–50
–55
–60
–65
–70
–75
–80
–85
–90
48
47
46
45
44
43
42
41
40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
P
OUT
P
3LO + BB
ACPR2 (5.25MHz)
ACPR3 (6.00MHz)
P
7LO + BB
P
5LO – BB
ACPR1 (750kHz)
P
2LO – BB
MER
P
4LO + BB
P
6LO – BB
–24
–22
–20
–18
–16
–14
–12
–10
0
100 200 300 400 500 600 700 800 900 1000
OUTPUT FREQUENCY (MHz)
CARRIER POWER (dBm)
Figure 38. ACP1, ACP2, ACP3, and Modulation Error Ratio (MER) vs. Output
Power for 256 QAM Transmitter
Figure 39. Spectral Components for Output Frequencies
from 50 MHz to 1000 MHz
SPECTRAL PRODUCTS FROM HARMONIC MIXING
RF SECOND-ORDER PRODUCTS
For broadband applications such as cable TV head-end
modulators, special attention must be paid to harmonics of the
LO. Figure 39 shows the level of these harmonics (out to 3 GHz)
as a function of the output frequency from 50 MHz to 1000 MHz,
in a single-sideband (SSB) test configuration, with a baseband
signal of 1 MHz and a SSB level of approximately −5 dBm. To
read this plot correctly, first pick the output frequency of
interest on the trace called POUT. The associated harmonics can
be read off the harmonic traces at multiples of this frequency.
For example, at an output frequency of 500 MHz, the
fundamental power is −5 dBm. The power of the second
(P2fc − BB) and third (P3fc + BB) harmonics is −63 dBm (at 1000 MHz)
and −16 dBm (at 1500 MHz), respectively. Of particular
importance are the products from odd-harmonics of the LO,
generated from the switching operation in the mixers.
A two-tone RF output signal produces second-order spectral
components at sum and difference frequencies. In broadband
systems, these intermodulation products fall inside the carrier
or in the adjacent channels. Output second-order RF
intermodulation intercept is defined as
OIP2_RF = POUT + (POUT − PIM(RF)
)
where PIM(RF) is the level of the intermodulation product at
FOUT1 + FOUT2. OIP2_RF levels from a two-tone test are plotted
as a function of carrier frequency in Figure 40, where the
baseband tones are 3.5 MHz and 4.5 MHz at −5 dBm each.
70
60
50
40
30
20
10
0
For cable TV operation at frequencies above approximately
500 MHz, these harmonics fall out of the band and can be
filtered by a fixed filter. However, as the frequency drops below
500 MHz, these harmonics start to fall close to or inside the
cable band. This calls for either limitation of the frequency
range to above 500 MHz or the use of a switchable filter bank to
block in-band harmonics at low frequencies.
0
250
500
750 1000 1250 1500 1750 2000 2250
OUTPUT FREQUENCY (MHz)
Figure 40. Output Second-Order Intermodulation vs. Carrier Frequency
Rev. 0 | Page 17 of 24
ADL5385
LO GENERATION USING PLLs
TRANSMIT DAC OPTIONS
Analog Devices has a line of PLLs that can be used for
generating the LO signal. Table 4 lists the PLLs together with
their maximum frequency and phase noise performance.
The AD9777 recommended in the previous sections is by no
means the only DAC that can be used to drive the ADL5385.
There are other appropriate DACs depending on the level of
performance required. Table 6 lists the dual Tx-DACs that
Analog Devices offers.
Table 4. PLL Selection Table
@ 1 kHz Phase Noise
Table 6. Dual Tx—DAC Selection Table
Model
Frequency FIN (MHz)
dBc/Hz, 200 kHz PFD
−91 @ 540 MHz
−87@ 900 MHz
−90 @ 900 MHz
−91 @ 900 MHz
−89 @ 540 MHz
−87 @ 900 MHz
−90 @ 900 MHz
Update Rate
(MSPS Minimum)
ADF4110 550
ADF4111 1200
ADF4112 3000
ADF4113 4000
ADF4116 550
ADF4117 1200
ADF4118 3000
Part
Resolution (Bits)
AD9709
AD9761
AD9763
AD9765
AD9767
AD9773
AD9775
AD9777
AD9776
AD9778
AD9779
8
125
40
10
10
12
14
12
14
16
12
14
16
125
125
125
160
160
160
1000
1000
1000
The ADF4360 comes as a family of chips, with nine operating
frequency ranges. One can be chosen depending on the local
oscillator frequency required. While the use of the integrated
synthesizer might come at the expense of slightly degraded
noise performance from the ADL5385, it can be a cheaper
alternative to a separate PLL and VCO solution. Table 5 shows
the options available.
All DACs listed have nominal bias levels of 0.5 V and use the
same DAC-modulator interface shown in Figure 31.
Table 5. ADF4360 Family Operating Frequencies
MODULATOR/DEMODULATOR OPTIONS
Model
Output Frequency Range (MHz)
Table 7 lists other Analog Devices modulators and
demodulators.
ADF4360-0
ADF4360-1
ADF4360-2
ADF4360-3
ADF4360-4
ADF4360-5
ADF4360-6
ADF4360-7
ADF4360-8
2400/2725
2050/2450
1850/2150
1600/1950
1450/1750
1200/1400
1050/1250
350/1800
Table 7. Modulator/Demodulator Options
Frequency
Part
Mod/Demod Range (MHz) Comments
AD8345
AD8346
AD8349
ADL5390 Mod
ADL5370 Mod
ADL5371 Mod
ADL5372 Mod
ADL5373 Mod
ADL5374 Mod
AD8347
AD8348
AD8340
AD8341
Mod
Mod
Mod
140 to 1000
800 to 2500
700 to 2700
20 to 2400
300 to 1000
700 to 1300
1600 to 2400
2300 to 3000
3000 to 4000
800 to 2700
50 to 1000
65/400
External Quadrature
Demod
Demod
Vector Mod
Vector Mod
700 to 1000
1500 to 2400
Rev. 0 | Page 18 of 24
ADL5385
EVALUATION BOARD
A populated, RoHS-compliant ADL5385 evaluation board is available. The ADL5385 has an exposed paddle underneath the package,
which is soldered to the board. The evaluation board is designed without any components on the underside so that heat can be applied to
the underside for easy removal and replacement of the ADL5385.
QBBP
QBBN
IBBN
IBBP
RFPQ
0Ω
RFNQ
0Ω
RFNI
0Ω
RFPI
0Ω
CFPQ
OPEN
CFNQ
OPEN
CFNI
OPEN
CFPI
OPEN
RTQ
OPEN
RTI
OPEN
R21
49.9Ω
ON
OFF
SW21
ENB
ENBL
19 COM3
ENBL 12
R22
10kΩ
VPOS
C15
OPEN
R13
0Ω
VPS2 11
TEMP 10
20 COM3
21 LOIP
22 LOIN
CLOP
0.1µF
C16
0.1µF
LO
ADL5385
RTEMP
200Ω
TEMP
VPS1
9
4 × 4 LFCSP
R12
CLON
0.1µF
0Ω
VPOS
VPS1
VOUT
8
7
23 VPS3
24 VPS3
EXPOSED PADDLE
R11
0Ω
C14
0.1µF
C13
OPEN
C11
OPEN
C12
0.1µF
VOUT
COUT
0.1µF
VPOS
GND
Figure 41. Evaluation Board Schematic
Table 8. Evaluation Board Configuration Options
Component
Function
Default Condition
VPOS, GND
Power Supply and Ground Clip Leads.
Not applicable
SW21, R21,
R22, ENB Test
Point, ENBL
SMA
Device Enable. Set SW21 to the OFF position to power down the device; set SW21 to the ON
position to enable the device. Part can be driven from an external enable control source via the
test point or the SMA connector. R21 provides a 50 Ω termination for any 50 Ω driving source.
R21 = 50 Ω, R22 =
10k Ω, SW21 = ON
RFNQ, CFNQ,
RTQ, CFPQ,
RFPQ, RFNI,
CFNI, RTI, CFPI,
RFPI
Baseband Input Filters. These components can be used to implement a low-pass filter for the
baseband signals.
RFNQ, RFPQ, RFNI
RFPI = 0 Ω (0402)
RTQ, RTI = open
(0402)
CFNQ, CFPQ, CFNI,
CFPI = open (0402)
Rev. 0 | Page 19 of 24
ADL5385
Figure 42. Layout of Evaluation Board
Rev. 0 | Page 20 of 24
ADL5385
CHARACTERIZATION SETUP
SSB SETUP
Figure 43 is a diagram of the characterization test stand setup for the ADL5385, which is intended to test the product as a single-sideband
modulator. The Aeroflex IFR3416 signal generator provides the I and Q inputs as well as the LO input. Output signals are measured
directly using the spectrum analyzer, and currents and voltages are measured using the Agilent 34401A multimeter.
AEROFLEX IFR 3416 250kHz TO 6GHz
FREQ 100MHz TO 4GHz LEVEL 0dBm
SIGNAL GENERATOR
BIAS 0.5V
BIAS 0.5V
GAIN 0.7V
GAIN 0.7V
R&S SPECTRUM ANALYZER FSU 20Hz TO 8GHz
RF
OUT
LO
50MHz TO 2GHz
+6dBm
CONNECT TO BACK OF UNIT
RF
IN
Q
I
90 DEG
0 DEG
OUTPUT
RLM TEST RACK 1
GND
VPOS
ADL5385
AGILENT 34401A MULTIMETER
0.210 ADC
J1(OUT)
J3(QN)
J4(QP)
J7(LO)
J6(IP)
J5(IN)
VPOS +5V
5.0000 0.210A
AGILENT E3631A
POWER SUPPLY
±25V
COM
+
6V
–
–
+
DELL
Figure 43. ADL5385 Characterization Board SSB Test Setup
Rev. 0 | Page 21 of 24
ADL5385
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
0.50
BSC
PIN 1
INDICATOR
*
2.45
2.30 SQ
2.15
TOP
3.75
EXPOSED
VIEW
BSC SQ
PA D
(BOTTOMVIEW)
0.50
0.40
0.30
6
13
12
7
0.23 MIN
2.50 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 44. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5385ACPZ-WP1
ADL5385ACPZ-R21
ADL5385ACPZ-R71
ADL5385-EVALZ1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
CP-24-2
CP-24-2
Ordering Quantity
24-Lead LFCSP_VQ, Waffle Pack
24-Lead LFCSP_VQ, 7”Tape and Reel
24-Lead LFCSP_VQ, 7”Tape and Reel
Evaluation Board
64
250
1500
1
–40°C to +85°C
CP-24-2
1 Z = Pb-free part.
Rev. 0 | Page 22 of 24
ADL5385
NOTES
Rev. 0 | Page 23 of 24
ADL5385
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06118-0-10/06(0)
Rev. 0 | Page 24 of 24
相关型号：
ADL5386ACPZ-R2
SPECIALTY TELECOM CIRCUIT, QCC40, 6 X 6 MM, ROHS COMPLIANT, MO-220-VJJD-2, LFCSP-40
ADI
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