ADL5382 [ADI]
700 MHz to 2.7 GHz Quadrature Demodulator; 700 MHz至2.7 GHz的正交解调器
| 型号： | ADL5382 |
| 厂家： | 
ADI |
| 描述： | 700 MHz to 2.7 GHz Quadrature Demodulator |
| 文件： | 总28页 (文件大小：728K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
700 MHz to 2.7 GHz
Quadrature Demodulator
ADL5382
FEATURES
FUNCTIONAL BLOCK DIAGRAM
CMRF CMRF RFIP RFIN CMRF VPX
Operating RF and LO frequency: 700 MHz to 2.7 GHz
Input IP3
24
23
22
21
20
19
33.5 dBm @ 900 MHz
30.5 dBm @1900 MHz
Input IP2: >70 dBm @ 900 MHz
Input P1dB: 14.7 dBm @ 900 MHz
Noise figure (NF)
14.0 dB @ 900 MHz
15.6 dB @ 1900 MHz
Voltage conversion gain: ~4 dB
Quadrature demodulation accuracy
Phase accuracy: ~0.2°
VPA
COM
BIAS
VPL
1
2
3
4
5
6
18 VPB
17 VPB
16 QHI
15 QLO
14 IHI
ADL5382
BIAS
GEN
0°
90°
VPL
VPL
13 ILO
Amplitude balance: ~0.05 dB
Demodulation bandwidth: ~370 MHz
Baseband I/Q drive: 2 V p-p into 200 Ω
Single 5 V supply
7
8
9
10
11
12
CML LOIP LOIN CML CML COM
Figure 1.
APPLICATIONS
Cellular W-CDMA/CDMA/CDMA2000/GSM
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX
GENERAL DESCRIPTION
The ADL5382 is a broadband quadrature I-Q demodulator that
covers an RF input frequency range from 700 MHz to 2.7 GHz.
With a NF = 14 dB, IP1dB = 14.7 dBm, and IIP3 = 33.5 dBm at
900 MHz, the ADL5382 demodulator offers outstanding dynamic
range suitable for the demanding infrastructure direct-conversion
requirements. The differential RF inputs provide a well-behaved
broadband input impedance of 50 Ω and are best driven from a
1:1 balun for optimum performance.
The fully balanced design minimizes effects from second-order
distortion. The leakage from the LO port to the RF port is
<−65 dBc. Differential dc offsets at the I and Q outputs are typically
<10 mV. Both of these factors contribute to the excellent IIP2
specifications which is >60 dBm.
The ADL5382 operates off a single 4.75 V to 5.25 V supply. The
supply current is adjustable with an external resistor from the
BIAS pin to ground.
Excellent demodulation accuracy is achieved with amplitude and
phase balances ~0.05 dB and ~0.2°, respectively. The demodulated
in-phase (I) and quadrature (Q) differential outputs are fully
buffered and provide a voltage conversion gain of ~4 dB. The
buffered baseband outputs are capable of driving a 2 V p-p
differential signal into 200 Ω.
The ADL5382 is fabricated using the Analog Devices, Inc.,
advanced Silicon-Germanium bipolar process and is available
in a 24-lead exposed paddle LFCSP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADL5382
TABLE OF CONTENTS
Features .............................................................................................. 1
Emitter Follower Buffers ........................................................... 13
Bias Circuit.................................................................................. 13
Applications Information.............................................................. 14
Basic Connections...................................................................... 14
Power Supply............................................................................... 14
Local Oscillator (LO) Input ...................................................... 14
RF Input....................................................................................... 15
Baseband Outputs ...................................................................... 15
Error Vector Magnitude (EVM) Performance........................... 16
Low IF Image Rejection............................................................. 17
Example Baseband Interface..................................................... 17
Characterization Setups................................................................. 21
Evaluation Board ............................................................................ 23
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Distributions for fRF = 900 MHz............................................... 10
Distributions for fRF = 1900 MHz............................................. 11
Distributions for fRF = 2700 MHz............................................. 12
Circuit Description......................................................................... 13
LO Interface................................................................................. 13
V-to-I Converter......................................................................... 13
Mixers .......................................................................................... 13
REVISION HISTORY
3/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADL5382
SPECIFICATIONS
VS = 5 V, TA = 25°C, fLO = 900 MHz, fIF = 4.5 MHz, PLO = 0 dBm, BIAS pin open, ZO = 50 ꢀ, unless otherwise noted. Baseband outputs
differentially loaded with 450 ꢀ. Loss of the balun used to drive the RF port was de-embedded from these measurements.
Table 1.
Parameter
Condition
Min Typ
0.7
Max Unit
OPERATING CONDITIONS
LO and RF Frequency Range
LO INPUT
Input Return Loss
LO Input Level
2.7
+6
GHz
LOIP, LOIN
LO driven differentially through a balun at 900 MHz
−11
dB
dBm
−6
0
I/Q BASEBAND OUTPUTS
Voltage Conversion Gain
QHI, QLO, IHI, ILO
450 Ω differential load on I and Q outputs at 900 MHz
200 Ω differential load on I and Q outputs at 900 MHz
1 V p-p signal, 3 dB bandwidth
At 900 MHz
3.9
3.0
370
0.2
0.05
5
VPOS − 2.8
50
2
dB
dB
MHz
Degrees
dB
mV
V
MHz
V p-p
mA
Demodulation Bandwidth
Quadrature Phase Error
I/Q Amplitude Imbalance
Output DC Offset (Differential)
Output Common Mode
0.1 dB Gain Flatness
Output Swing
0 dBm LO input at 900 MHz
Differential 200 Ω load
Each pin
Peak Output Current
POWER SUPPLIES
12
VPA, VPL, VPB, VPX
Voltage
4.75
5.25
V
Current
BIAS pin open
RBIAS = 4 kΩ
220
196
mA
mA
DYNAMIC PERFORMANCE at RF = 900 MHz
Conversion Gain
3.9
dB
Input P1dB
14.7
73
dBm
dBm
dBm
dBm
dBc
Second-Order Input Intercept (IIP2)
Third-Order Input Intercept (IIP3)
LO to RF
RF to LO
IQ Magnitude Imbalance
IQ Phase Imbalance
LO to IQ
Noise Figure
Noise Figure under Blocking Conditions
DYNAMIC PERFORMANCE at RF = 1900 MHz
Conversion Gain
−5 dBm each input tone
−5 dBm each input tone
RFIN, RFIP terminated in 50 Ω
LOIN, LOIP terminated in 50 Ω
33.5
−92
−89
0.05
0.2
−43
14.0
19.9
dB
Degrees
dBm
dB
RFIN, RFIP terminated in 50 Ω
With a −5 dBm interferer 5 MHz away
dB
3.9
dB
Input P1dB
14.4
65
dBm
dBm
dBm
dBm
dBc
Second-Order Input Intercept (IIP2)
Third-Order Input Intercept (IIP3)
LO to RF
RF to LO
IQ Magnitude Imbalance
IQ Phase Imbalance
LO to IQ
Noise Figure
Noise Figure under Blocking Conditions
−5 dBm each input tone
−5 dBm each input tone
RFIN, RFIP terminated in 50 Ω
LOIN, LOIP terminated in 50 Ω
30.5
−71
−78
0.05
0.2
−41
15.6
20.5
dB
Degrees
dBm
dB
RFIN, RFIP terminated in 50 Ω
With a −5 dBm interferer 5 MHz away
dB
Rev. 0 | Page 3 of 28
ADL5382
Parameter
Condition
Min Typ
Max Unit
DYNAMIC PERFORMANCE at RF = 2700 MHz RFIP, RFIN
Conversion Gain
Input P1dB
Second-Order Input Intercept (IIP2)
Third-Order Input Intercept (IIP3)
LO to RF
3.3
14.5
52
28.3
−70
−55
0.16
0.1
dB
dBm
dBm
dBm
dBm
dBc
dB
Degrees
dBm
dB
−5 dBm each input tone
−5 dBm each input tone
RFIN, RFIP terminated in 50 Ω, 1xLO appearing at RF port
LOIN, LOIP terminated in 50 Ω
RF to LO
IQ Magnitude Imbalance
IQ Phase Imbalance
LO to IQ
RFIN, RFIP terminated in 50 Ω, 1xLO appearing at BB port
−42
17.6
Noise Figure
Rev. 0 | Page 4 of 28
ADL5382
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
Supply Voltage (VPA, VPL, VPB, VPX)
LO Input Power
5.5 V
13 dBm (re: 50 Ω)
15 dBm (re: 50 Ω)
1230 mW
RF Input Power
Internal Maximum Power Dissipation
θJA
54°C/W
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
150°C
−40°C to +85°C
−65°C to +125°C
ESD CAUTION
Rev. 0 | Page 5 of 28
ADL5382
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
CMRF CMRF RFIP RFIN CMRF VPX
VPB
23
22
21
20
19
1
2
3
4
5
6
18
VPA
COM
BIAS
VPL
VPL
VPL
VPB 17
QHI 16
QLO 15
IHI 14
ADL5382
TOP VIEW
(Not to Scale)
ILO 13
CML LOIP LOIN CML CML COM
10 11 12
7
8
9
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 4 to 6,
17 to 19
VPA, VPL, VPB, VPX Supply. Positive supply for LO, IF, biasing, and baseband sections. These pins should be decoupled
to the board ground using appropriate-sized capacitors.
2, 7, 10 to 12, COM, CML, CMRF
20, 23, 24
Ground. Connect to a low impedance ground plane.
3
BIAS
Bias Control. A resistor (RBIAS) can be connected between BIAS and COM to reduce the mixer core
current. The default setting for this pin is open.
8, 9
LOIP, LOIN
ILO, IHI, QLO, QHI
Local Oscillator Input. Pins must be ac-coupled. A differential drive through a balun (recommended
balun is the M/A-COM ETC1-1-13) is necessary to achieve optimal performance.
I Channel and Q Channel Mixer Baseband Outputs. These outputs have a 50 Ω differential output
impedance (25 Ω per pin). The bias level on these pins is equal to VPOS − 2.8 V. Each output pair can
swing 2 V p-p (differential) into a load of 200 Ω. Output 3 dB bandwidth is 370 MHz.
13 to 16
21, 22
RFIN, RFIP
EP
RF Input. A single-ended 50 Ω signal can be applied to the RF inputs through a 1:1 balun (recommended
balun is the M/A-COM ETC1-1-13). Ground-referenced inductors must also be connected to RFIP and
RFIN (recommended values = 33 nH).
Exposed Paddle. Connect to a low impedance thermal and electrical ground plane.
Rev. 0 | Page 6 of 28
ADL5382
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, LO drive level = 0 dBm, RBIAS = open, RF input balun loss is de-embedded, unless otherwise noted.
20
15
10
5
2
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
1
INPUT P1dB
0
–1
–2
–3
–4
–5
–6
–7
–8
GAIN
0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
10
100
1000
RF FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
Figure 3. Conversion Gain and Input IP1 dB Compression Point (IP1dB) vs.
RF Frequency
Figure 6. Normalized IQ Baseband Frequency Response
80
19
18
17
16
15
14
13
12
I CHANNEL
Q CHANNEL
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
70
INPUT IP2
60
50
INPUT IP3 (I AND Q CHANNELS)
40
30
20
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
10
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
Figure 4. Input Third-Order Intercept (IIP3) and
Figure 7. Noise Figure vs. RF Frequency
Input Second-Order Intercept Point (IIP2) vs. RF Frequency
4
3
2.0
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
1.5
1.0
2
1
0.5
0
0
–1
–2
–3
–4
–0.5
–1.0
–1.5
–2.0
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 8. IQ Quadrature Phase Error vs. RF Frequency
Figure 5. IQ Gain Mismatch vs. RF Frequency
Rev. 0 | Page 7 of 28
ADL5382
20
80
65
50
35
20
20
18
16
14
12
10
8
75
65
55
45
35
25
15
IIP2, Q CHANNEL
IIP2, Q CHANNEL
IIP2, I CHANNEL
NOISE FIGURE
IIP2, I CHANNEL
IP1dB
15
NOISE FIGURE
IP1dB
10
5
IIP3
6
IIP3
4
GAIN
GAIN
2
0
0
–6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
–6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
LO LEVEL (dBm)
LO LEVEL (dBm)
Figure 9. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs.
LO Level, fRF = 900 MHz
Figure 12. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs.
LO Level, fRF = 1900 MHz
34
32
250
240
230
220
210
200
190
180
170
160
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
INPUT IP3
30
26
22
18
14
10
28
24
20
16
12
8
SUPPLY CURRENT
INPUT IP3
NOISE FIGURE
NOISE FIGURE
1
10
(kΩ)
100
1
10
100
R
R
(kΩ)
BIAS
BIAS
Figure 10. IIP3, Noise Figure, and Supply Current vs. RBIAS, fRF = 900 MHz
Figure 13. IIP3 and Noise Figure vs. RBIAS, fRF = 1900 MHz
29
27
25
23
21
19
80
70
60
50
40
30
20
10
0
900MHz: GAIN
900MHz: IP1dB
900MHz: IIP2, I CHANNEL
900MHz: IIP2, Q CHANNEL
1900MHz: GAIN
1900MHz: IP1dB
1900MHz: IIP2, I CHANNEL
1900MHz: IIP2, Q CHANNEL
1900MHz
900MHz
17
15
13
–30
–25
–20
–15
–10
–5
0
5
1
10
(kΩ)
100
RF BLOCKER INPUT POWER (dBm)
R
BIAS
Figure 11. Noise Figure vs. Input Blocker Level, fRF = 900 MHz, 1900 MHz
(RF Blocker 5 MHz Offset)
Figure 14. Conversion Gain, IP1dB, IIP2_I, and IIP2_Q vs.
RBIAS, fRF = 900 MHz, 1900MHz
Rev. 0 | Page 8 of 28
ADL5382
40
35
30
25
20
15
10
5
85
80
75
70
65
60
–20
–30
–40
–50
–60
–70
–80
–90
–100
I CHANNEL
Q CHANNEL
IIP3
IIP2
IP1dB
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
0
0
10
20
30
40
50
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
BASEBAND FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 15. IP1dB, IIP3, and IIP2 vs. Baseband Frequency
Figure 18. LO-to-RF Leakage vs. LO Frequency
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 19. RF-to-LO Leakage vs. RF Frequency
Figure 16. LO-to-BB Leakage vs. LO Frequency
0
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–5
–10
–15
–20
–25
–30
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 17. RF Port Return Loss vs. RF Frequency Measured on a Characterization
Board through an ETC1-1-13 Balun with 33 nH Bias Inductors
Figure 20. LO Port Return Loss vs. LO Frequency Measured on
Characterization Board through an ETC1-1-13 Balun
Rev. 0 | Page 9 of 28
ADL5382
DISTRIBUTIONS FOR fRF = 900 MHz
100
100
80
60
40
20
0
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
80
60
40
20
0
I CHANNEL
Q CHANNEL
31
32
33
34
35
36
37
45
50
55
60
65
70
75
80
85
INPUT IP3 (dBm)
INPUT IP2 (dBm)
Figure 21. IIP3 Distributions, fRF = 900 MHz
Figure 24. IIP2 Distributions for I Channel and Q Channel, fRF = 900 MHz
100
80
60
40
20
0
100
T
T
T
= –40°C
= +25°C
= +85°C
T
= –40°C
= +25°C
= +85°C
A
A
A
A
T
A
A
T
80
60
40
20
0
12
13
14
15
16
17
12.5
13.0
13.5
14.0
14.5
15.0
15.5
INPUT P1dB (dBm)
NOISE FIGURE (dB)
Figure 22. IP1dB Distributions, fRF = 900 MHz
Figure 25. Noise Figure Distributions, fRF = 900 MHz
100
80
60
40
20
0
100
80
60
40
20
0
T
T
T
= –40°C
= +25°C
A
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
–0.2
–0.1
0
0.1
0.2
–1.00 –0.75 –0.50 –0.25
0
0.25
0.50
0.75
1.00
GAIN MISMATCH (dB)
QUADRATURE PHASE ERROR (Degrees)
Figure 23. IQ Gain Mismatch Distributions, fRF = 900 MHz
Figure 26. IQ Quadrature Phase Error Distributions, fRF = 900 MHz
Rev. 0 | Page 10 of 28
ADL5382
DISTRIBUTIONS FOR fRF = 1900 MHz
100
100
80
60
40
20
0
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
80
60
40
20
0
I CHANNEL
Q CHANNEL
28
29
30
31
32
33
45
50
55
60
65
70
75
80
85
INPUT IP3 (dBm)
INPUT IP2 (dBm)
Figure 27. IIP3 Distributions, fRF = 1900 MHz
Figure 30. IIP2 Distributions for I Channel and Q Channel, fRF = 1900 MHz
100
80
60
40
20
0
100
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
A
= +85°C
A
A
A
A
A
80
60
40
20
0
12
13
14
15
16
17
14.0
14.5
15.0
15.5
16.0
16.5
17.0
INPUT P1dB (dBm)
NOISE FIGURE (dB)
Figure 28. IP1dB Distributions, fRF = 1900 MHz
Figure 31. Noise Figure Distributions, fRF = 1900 MHz
100
80
60
40
20
0
100
80
60
40
20
0
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
–1.00 –0.75 –0.50 –0.25
0
0.25
0.50
0.75
1.00
–0.2
–0.1
0
0.1
0.2
QUADRATURE PHASE ERROR (Degrees)
GAIN MISMATCH (dB)
Figure 32. IQ Quadrature Phase Error Distributions, fRF = 1900 MHz
Figure 29. IQ Gain Mismatch Distributions, fRF = 1900 MHz
Rev. 0 | Page 11 of 28
ADL5382
DISTRIBUTIONS FOR fRF = 2700 MHz
100
100
80
60
40
20
0
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
80
60
40
20
0
I CHANNEL
Q CHANNEL
26
27
28
29
30
31
45
50
55
60
65
70
75
80
85
INPUT IP3 (dBm)
INPUT IP2 (dBm)
Figure 33. IIP3 Distributions, fRF = 2700 MHz
Figure 36. IIP2 Distributions for I Channel and Q Channel, fRF = 2700 MHz
100
80
60
40
20
0
100
T
T
T
= –40°C
= +25°C
= +85°C
T
= –40°C
= +25°C
A
A
A
A
T
A
T = +85°C
A
80
60
40
20
0
12
13
14
15
16
17
16.0
16.5
17.0
17.5
18.0
18.5
19.0
INPUT P1dB (dBm)
NOISE FIGURE (dB)
Figure 34. IP1dB Distributions, fRF = 2700 MHz
Figure 37. Noise Figure Distributions, fRF = 2700 MHz
100
80
60
40
20
0
100
80
60
40
20
0
T
T
T
= –40°C
= +25°C
= +85°C
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
A
A
A
–0.1
0
0.1
0.2
0.3
–1.00 –0.75 –0.50 –0.25
0
0.25
0.50
0.75
1.00
GAIN MISMATCH (dB)
QUADRATURE PHASE ERROR (Degrees)
Figure 35. IQ Gain Mismatch Distributions, fRF = 2700 MHz
Figure 38. IQ Quadrature Phase Error Distributions, fRF = 2700 MHz
Rev. 0 | Page 12 of 28
ADL5382
CIRCUIT DESCRIPTION
The ADL5382 can be divided into five sections: the local
oscillator (LO) interface, the RF voltage-to-current (V-to-I)
converter, the mixers, the differential emitter follower outputs,
and the bias circuit. A detailed block diagram of the device is
shown in Figure 39.
V-TO-I CONVERTER
The differential RF input signal is applied to a resistively
degenerated common base stage, which converts the differential
input voltage to output currents. The output currents then
modulate the two half frequency LO carriers in the mixer stage.
BIAS
MIXERS
The ADL5382 has two double-balanced mixers: one for the
in-phase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistive loads that
then feed into the subsequent emitter follower buffers.
IHI
ILO
LOIP
RFIP
POLYPHASE
EMITTER FOLLOWER BUFFERS
QUADRATURE
PHASE SPLITTER
RFIN
The output emitter followers drive the differential I and Q
signals off-chip. The output impedance is set by on-chip 25 ꢀ
series resistors that yield a 50 ꢀ differential output impedance
for each baseband port. The fixed output impedance forms a
voltage divider with the load impedance that reduces the effective
gain. For example, a 500 ꢀ differential load has 1 dB lower
effective gain than a high (10 kꢀ) differential load impedance.
LOIN
QHI
QLO
Figure 39. Block Diagram
BIAS CIRCUIT
The LO interface generates two LO signals at 90° of phase
difference to drive two mixers in quadrature. RF signals are
converted into currents by the V-to-I converters that feed into
the two mixers. The differential I and Q outputs of the mixers
are buffered via emitter followers. Reference currents to each
section are generated by the bias circuit. A detailed description
of each section follows.
A band gap reference circuit generates the proportional-to-
absolute temperature (PTAT) as well as temperature-independent
reference currents used by different sections. The mixer current
can be reduced via an external resistor between the BIAS pin
and ground. When the BIAS pin is open, the mixer runs at
maximum current and therefore the greatest dynamic range.
The mixer current can be reduced by placing a resistance to
ground; therefore, reducing overall power consumption, noise
figure, and IIP3. The effect on each of these parameters is
shown in Figure 10, Figure 13, and Figure 14.
LO INTERFACE
The LO interface consists of a polyphase quadrature splitter
followed by a limiting amplifier. The LO input impedance is set
by the polyphase, which splits the LO signal into two differential
signals in quadrature. Each quadrature LO signal then passes
through a limiting amplifier that provides the mixer with a
limited drive signal. For optimal performance, the LO inputs
must be driven differentially.
Rev. 0 | Page 13 of 28
ADL5382
APPLICATIONS INFORMATION
BASIC CONNECTIONS
LOCAL OSCILLATOR (LO) INPUT
Figure 41 shows the basic connections schematic for the ADL5382.
For optimum performance, the LO port should be driven
differentially through a balun. The recommended balun is
the M/A-COM ETC1-1-13. The LO inputs to the device should
be ac-coupled with 1000 pF capacitors. The LO port is designed
for a broadband 50 ꢀ match from 700 MHz to 2.7 GHz. The
LO return loss can be seen in Figure 20. Figure 40 shows the LO
input configuration.
POWER SUPPLY
The nominal voltage supply for the ADL5382 is 5 V and is
applied to the VPA, VPB, VPL, and VPX pins. Ground should
be connected to the COM, CML, and CMRF pins. The exposed
paddle on the underside of the package should also be soldered
to a low thermal and electrical impedance ground plane. If the
ground plane spans multiple layers on the circuit board, these
layers should be stitched together with nine vias under the
exposed paddle. The Application Note AN-772 discusses the
thermal and electrical grounding of the LFCSP in detail. Each
of the supply pins should be decoupled using two capacitors;
recommended capacitor values are 100 pF and 0.1 μF.
LO INPUT
8
LOIP
LOIN
1000pF
1000pF
ETC1-1-13
9
Figure 40. Differential LO Drive
The recommended LO drive level is between −6 dBm and +6 dBm.
The applied LO frequency range is between 700 MHz and 2.7 GHz.
ETC1-1-13
RFC
1000pF
33nH
1000pF
33nH
V
POS
24
23
22
21
20
19
V
1 VPA
VPB 18
POS
0.1µF
100pF
100pF
0.1µF
2 COM
3 BIAS
4 VPL
5 VPL
6 VPL
VPB 17
QHI 16
QLO15
IHI 14
QHI
QLO
ADL5382
V
POS
IHI
ILO
0.1µF
100pF
ILO13
7
8
9
10
11
12
1000pF
1000pF
ETC1-1-13
LO
Figure 41. Basic Connections Schematic
Rev. 0 | Page 14 of 28
ADL5382
The differential RF port return loss is characterized as shown in
Figure 43.
RF INPUT
The RF inputs have a differential input impedance of
–10
approximately 50 ꢀ. For optimum performance, the RF port
should be driven differentially through a balun. The recommended
balun is the M/A-COM ETC1-1-13. The RF inputs to the device
should be ac-coupled with 1000 pF capacitors. Ground-referenced
choke inductors must also be connected to RFIP and RFIN (the
recommended value is 33 nH, Coilcraft 0603CS-33NX) for
appropriate biasing. Several important aspects must be taken
into account when selecting an appropriate choke inductor for
this application. First, the inductor must be able to handle the
approximately 40 mA of standing dc current being delivered
from each of the RF input pins (RFIP, RFIN). The suggested
0603 inductor has a 600 mA current rating. The purpose of the
choke inductors is to provide a very low resistance dc path to
ground and high ac impedance at the RF frequency so as not to
affect the RF input impedance. A choke inductor that has a self-
resonant frequency greater than the RF input frequency ensures
that the choke is still looking inductive and therefore has a more
predictable ac impedance (jωL) at the RF frequency. Figure 42
shows the RF input configuration.
–12
–14
–16
–18
–20
–22
–24
0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
FREQUENCY (GHz)
Figure 43. Differential RF Port Return Loss
BASEBAND OUTPUTS
The baseband outputs QHI, QLO, IHI, and ILO are fixed
impedance ports. Each baseband pair has a 50 ꢀ differential
output impedance. The outputs can be presented with differential
loads as low as 200 ꢀ (with some degradation in gain) or high
impedance differential loads (500 ꢀ or greater impedance yields
the same excellent linearity) that is typical of an ADC. The
TCM9-1 9:1 balun converts the differential IF output to single-
ended. When loaded with 50 ꢀ, this balun presents a 450 ꢀ
load to the device. The typical maximum linear voltage swing
for these outputs is 2 V p-p differential. The bias level on these
pins is equal to VPOS − 2.8 V. The output 3 dB bandwidth is
370 MHz. Figure 44 shows the baseband output configuration.
33nH
21
22
RFIN
RFIP
1000pF
1000pF
ETC1-1-13
RF INPUT
33nH
16
QHI
QLO
IHI
QHI
QLO
IHI
Figure 42. RF Input
15
14
13
ILO
ILO
Figure 44. Baseband Output Configuration
Rev. 0 | Page 15 of 28
ADL5382
0
–5
ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE
EVM is a measure used to quantify the performance of a digital
radio transmitter or receiver. A signal received by a receiver
would have all constellation points at the ideal locations; however,
various imperfections in the implementation (such as magnitude
imbalance, noise floor, and phase imbalance) cause the actual
constellation points to deviate from the ideal locations.
–10
–15
–20
–25
–30
–35
–40
–45
–50
The ADL5382 shows excellent EVM performance for various
modulation schemes. Figure 45 shows the EVM performance of
the ADL5382 with a 16 QAM, 200 kHz low IF.
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
5
10
RF INPUT POWER (dBm)
Figure 46. EVM, RF = 2.6 GHz, IF = 0 Hz vs. RF Input Power for a 16 QAM
10 MHz Bandwidth Mobile WiMAX Signal (AC-Coupled Baseband Outputs)
Figure 47 exhibits multiple W-CDMA low-IF EVM
performance curves over a wide RF input power range into the
ADL5382. In the case of zero-IF, the noise contribution by the
vector signal analyzer becomes predominant at lower power
levels, making it difficult to measure SNR accurately.
0
–5
–10
–15
–20
–25
–30
–85
–75
–65
–55
–45
–35
–25
–15
–5
RF INPUT POWER (dBm)
Figure 45. EVM, RF = 900 MHz, IF = 200 kHz vs.
RF Input Power for a 16 QAM 160 ksym/s Signal
Figure 46 shows the zero-IF EVM performance of a 10 MHz
IEEE 802.16e WiMAX signal through the ADL5382. The
differential dc offsets on the ADL5382 are in the order of a few
millivolts. However, ac coupling the baseband outputs with
10 μF capacitors eliminates dc offsets and enhances EVM
performance. With a 10 MHz BW signal, 10 μF ac coupling
capacitors with the 500 ꢀ differential load results in a high-pass
corner frequency of ~64 Hz, which absorbs an insignificant
amount of modulated signal energy from the baseband signal.
By using ac-coupling capacitors at the baseband outputs, the dc
offset effects, which can limit dynamic range at low input power
levels, can be eliminated.
–35
–40
–45
–50
0Hz
5MHz
2.5MHz
7.5MHz
–75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
RF INPUT POWER (dBm)
Figure 47. EVM, RF = 1900 MHz, IF = 0 Hz, 2.5 MHz, 5 MHz, and 7.5 MHz vs. RF
Input Power for a W-CDMA Signal (AC-Coupled Baseband Outputs)
Rev. 0 | Page 16 of 28
ADL5382
COSωLO
t
0°
ωIF
ωIF
0
0
+
ωIF
–
ωIF
0
+ωIF
–90°
+90°
ωLSB ωLO ωUSB
0°
+ωIF
–
ωIF
0
+ωIF
SINωLO
t
Figure 48. Illustration of the Image Problem
EXAMPLE BASEBAND INTERFACE
LOW IF IMAGE REJECTION
In most direct conversion receiver designs, it is desirable to
select a wanted carrier within a specified band. The desired
channel can be demodulated by tuning the LO to the appropriate
carrier frequency. If the desired RF band contains multiple
carriers of interest, the adjacent carriers would also be down
converted to a lower IF frequency. These adjacent carriers can
be problematic if they are large relative to the wanted carrier as
they can overdrive the baseband signal detection circuitry. As a
result, it is often necessary to insert a filter to provide sufficient
rejection of the adjacent carriers.
The image rejection ratio is the ratio of the intermediate frequency
(IF) signal level produced by the desired input frequency to that
produced by the image frequency. The image rejection ratio is
expressed in decibels. Appropriate image rejection is critical
because the image power can be much higher than that of the
desired signal, thereby plaguing the down conversion process.
Figure 48 illustrates the image problem. If the upper sideband
(lower sideband) is the desired band, a 90° shift to the Q channel
(I channel) cancels the image at the lower sideband (upper
sideband). Phase and gain balance between I and Q channels
are critical for high levels of image rejection.
It is necessary to consider the overall source and load impedance
presented by the ADL5382 and ADC input to design the filter
network. The differential baseband output impedance of the
ADL5382 is 50 ꢀ. The ADL5382 is designed to drive a high
impedance ADC input. It may be desirable to terminate the
ADC input down to lower impedance by using a terminating
resistor, such as 500 ꢀ. The terminating resistor helps to better
define the input impedance at the ADC input at the cost of a
slightly reduced gain (see the Circuit Description section for
details on the emitter-follower output loading effects). The order
and type of filter network depends on the desired high frequency
rejection required, pass-band ripple, and group delay. Filter
design tables provide outlines for various filter types and orders,
illustrating the normalized inductor and capacitor values for a
1 Hz cutoff frequency and 1 ꢀ load. After scaling the normalized
prototype element values by the actual desired cut-off frequency
and load impedance, the series reactance elements are halved to
realize the final balanced filter network component values.
Figure 49 shows the excellent image rejection capabilities of
the ADL5382 for low IF applications, such as W-CDMA. The
ADL5382 exhibits image rejection greater than 45 dB over a
broad frequency range.
70
5MHz LOW IF
2.5MHz LOW IF
60
50
40
30
20
10
0
7.5MHz LOW IF
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
Figure 49. Image Rejection vs. RF Frequency for a W-CDMA Signal,
IF = 2.5 MHz, 5 MHz, and 7.5 MHz
Rev. 0 | Page 17 of 28
ADL5382
As an example, a second-order Butterworth, low-pass filter
design is shown in Figure 50 where the differential load impedance
is 500 ꢀ and the source impedance of the ADL5382 is 50 ꢀ. The
normalized series inductor value for the 10-to-1, load-to-source
impedance ratio is 0.074 H, and the normalized shunt capacitor
is 14.814 F. For a 10.9 MHz cutoff frequency, the single-ended
equivalent circuit consists of a 0.54 μH series inductor followed
by a 433 pF shunt capacitor.
Figure 51 and Figure 52 show the measured frequency response
and group delay of the filter.
10
5
0
–5
The balanced configuration is realized as the 0.54 μH inductor
is split in half to realize the network shown in Figure 50.
–10
–15
–20
R
= 50Ω
L
= 0.074H
S
N
NORMALIZED
SINGLE-ENDED
CONFIGURATION
V
C
14.814F
R = 500Ω
S
N
L
R
R
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
S
L
fC = 1Hz
= 0.1
FREQUENCY (MHz)
0.54µH
R
= 50Ω
S
Figure 51. Sixth-Order Baseband Filter Response
DENORMALIZED
SINGLE-ENDED
EQUIVALENT
900
V
V
433pF
433pF
R = 500Ω
S
L
800
700
600
500
400
300
200
100
fC = 10.9MHz
R
2
S
= 25Ω
= 25Ω
0.27µH
R
L
2
= 250Ω
BALANCED
CONFIGURATION
S
R
2
L
= 250Ω
R
0.27µH
S
2
Figure 50. Second-Order Butterworth, Low-Pass Filter Design Example
A complete design example is shown in Figure 53. A sixth-order
Butterworth differential filter having a 1.9 MHz corner frequency
interfaces the output of the ADL5382 to that of an ADC input.
The 500 ꢀ load resistor defines the input impedance of the
ADC. The filter adheres to typical direct conversion W-CDMA
applications, where 1.92 MHz away from the carrier IF frequency,
1 dB of rejection is desired and 2.7 MHz away 10 dB of rejection
is desired.
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
FREQUENCY (MHz)
Figure 52. Sixth-Order Baseband Filter Group Delay
Rev. 0 | Page 18 of 28
ADL5382
ETC1-1-13
RFC
1000pF
33nH
1000pF
33nH
C
AC
27µH
27µH
10µH
10µF
V
POS
24
23
22
21
20
19
C
AC
10µF
V
1 VPA
VPB 18
POS
0.1µF
100pF
100pF
0.1µF
27µH
27µH
10µH
2 COM
3 BIAS
4 VPL
5 VPL
6 VPL
VPB 17
QHI 16
QLO15
IHI 14
ADL5382
V
POS
0.1µF
100pF
ILO13
C
AC
27µH
27µH
10µH
10µF
7
8
9
10
11
12
C
AC
10µF
1000pF
1000pF
27µH
27µH
10µH
ETC1-1-13
LO
Figure 53. Sixth-Order Low-Pass Butterworth, Baseband Filter Schematic
Rev. 0 | Page 19 of 28
ADL5382
5
0
As the load impedance of the filter increases, the filter design
becomes more challenging in terms of meeting the required
rejection and pass band specifications. In the previous W-
CDMA example, the 500 ꢀ load impedance resulted in the
design of a sixth-order filter that has relatively large inductor
values and small capacitor values. If the load impedance is 200 ꢀ,
the filter design becomes much more manageable. As shown in
Figure 54, the resultant inductor and capacitor values become
much more practical.
–5
–10
–15
–20
10µH
8µH
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
3.4
3.8
FREQUENCY (MHz)
Figure 55. Fourth-Order Low-Pass W-CDMA Filter Magnitude Response
10µH
8µH
900
Figure 54. Fourth-Order Low-Pass W-CDMA Filter Schematic
800
700
600
500
400
300
200
100
Figure 55 and Figure 56 illustrate the magnitude response and
group delay response of the fourth-order filter, respectively.
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (MHz)
Figure 56. Fourth-Order Low-Pass W-CDMA Filter Group Delay Response
Rev. 0 | Page 20 of 28
ADL5382
CHARACTERIZATION SETUPS
Figure 57 to Figure 59 show the general characterization bench
setups used extensively for the ADL5382. The setup shown in
Figure 59 was used to do the bulk of the testing and used sinusoidal
signals on both the LO and RF inputs. An automated Agilent
VEE program was used to control the equipment over the IEEE
bus. This setup was used to measure gain, IP1dB, IIP2, IIP3, I/Q
gain match, and quadrature error. The ADL5382 characterization
board had a 9-to-1 impedance transformer on each of the
differential baseband ports to do the differential-to-single-
ended conversion, which presented a 450 ꢀ differential load to
each baseband port, when interfaced with 50 ꢀ test equipment.
For all measurements of the ADL5382, the loss of the RF input
balun (the M/A-COM ETC1-1-13 was used on RF input during
characterization) was de-embedded.
The two setups shown in Figure 57 and Figure 58 were used for
making NF measurements. Figure 57 shows the setup for
measuring NF with no blocker signal applied while Figure 58
was used to measure NF in the presence of a blocker. For both
setups, the noise was measured at a baseband frequency of
10 MHz. For the case where a blocker was applied, the output
blocker was at a 15 MHz baseband frequency. Note that great
care must be taken when measuring NF in the presence of a
blocker. The RF blocker generator must be filtered to prevent its
noise (which increases with increasing generator output power)
from swamping the noise contribution of the ADL5382. At least
30 dB of attention at the RF and image frequencies is desired.
For example, assume a 915 MHz signal applied to the LO inputs of
the ADL5382. To obtain a 15 MHz output blocker signal, the RF
blocker generator is set to 930 MHz and the filters tuned such
that there is at least 30 dB of attenuation from the generator at
both the desired RF frequency (925 MHz) and the image RF
frequency (905 MHz). Finally, the blocker must be removed
from the output (by the 10 MHz low-pass filter) to prevent the
blocker from swamping the analyzer.
SNS
CONTROL
AGILENT N8974A
NOISE FIGURE ANALYZER
OUTPUT
R1
50Ω
RF
Q
GND
ADL5382
CHAR BOARD
V
POS
I
LO
HP 6235A
POWER SUPPLY
INPUT
LOW-PASS
FILTER
AGILENT 8665B
SIGNAL GENERATOR
IEEE
PC CONTROLLER
Figure 57. General Noise Figure Measurement Setup
Rev. 0 | Page 21 of 28
ADL5382
BAND-PASS
TUNABLE FILTER
BAND-REJECT
TUNABLE FILTER
R&S SMT03
SIGNAL GENERATOR
R&S FSEA30
SPECTRUM ANALYZER
R1
50Ω
RF
Q
I
GND
ADL5382
LOW-PASS
FILTER
6dB PAD
CHAR BOARD
V
POS
LO
HP 6235A
POWER SUPPLY
BAND-PASS
CAVITY FILTER
HP87405
LOW NOISE
PREAMP
AGILENT 8665B
SIGNAL GENERATOR
Figure 58. Measurement Setup for Noise Figure in the Presence of a Blocker
3dB PAD
RF
AMPLIFIER
IN
OUT
3dB PAD
3dB PAD
RF
VP GND
AGILENT
11636A
3dB PAD
R&S SMT06
RF
R&S SMT06
RF
Q
I
6dB PAD
GND
SWITCH
MATRIX
ADL5382
CHAR BOARD
V
POS
6dB PAD
LO
AGILENT E3631
PWER SUPPLY
RF
INPUT
AGILENT E8257D
SIGNAL GENERATOR
IEEE
IEEE
R&S FSEA30
SPECTRUM ANALYZER
HP 8508A
VECTOR VOLTMETER
PC CONTROLLER
Figure 59. General Characterization Setup
Rev. 0 | Page 22 of 28
ADL5382
EVALUATION BOARD
The ADL5382 evaluation board is available. The board can be
used for single-ended or differential baseband analysis. The default
configuration of the board is for single-ended baseband analysis.
T1
RFC
C11
C10
L2
24
L1
19
R8
R7
VPOS
R1
23
22
21
20
R6
V
1 VPA
VPB 18
POS
C1
C2
C8
C9
2 COM
3 BIAS
4 VPL
5 VPL
6 VPL
VPB 17
QHI 16
QLO15
IHI 14
R2
R9
Q OUTPUT OR QHI
R14
R15
T2
ADL5382
C12
R3
VPOS
R16
C3
C4
QLO
ILO13
R10
R11
7
8
9
10
11
12
I OUTPUT OR IHI
R4
R5
T3
C13
R13
ILO
C6
C7
T4
R12
LO
Figure 60. Evaluation Board Schematic
Rev. 0 | Page 23 of 28
ADL5382
Table 4. Evaluation Board Configuration Options
Component Function
Default Condition
Not applicable
VPOS, GND
R1, R3, R6
Power Supply and Ground Vector Pins.
Power Supply Decoupling. Shorts or power supply decoupling resistors.
These capacitors provide the required decoupling up to 2.7 GHz.
R1, R3, R6 = 0 Ω (0603)
C1, C2, C3,
C4, C8, C9
C2, C4, C8 = 100 pF (0402)
C1, C3, C9 = 0.1 μF (0603)
C6, C7,
C10, C11
AC Coupling Capacitors. These capacitors provide the required ac coupling from
700 MHz to 2.7 GHz.
C6, C10, C11 = 1000 pF (0402)
C7 = open
R4, R5,
R9 to R16
Single-Ended Baseband Output Path. This is the default configuration of the evaluation
board. R14 to R16 and R4, R5, and R13 are populated for appropriate balun interface.
R9, R10 and R11, R12 are not populated. Baseband outputs are taken from QHI and IHI.
R4, R5, R13 to R16 = 0 Ω (0402)
R9 to R12 = open
The user can reconfigure the board to use full differential baseband outputs. R9 to R12
provide a means to bypass the 9:1 TCM9-1 transformer to allow for differential baseband
outputs. Access the differential baseband signals by populating R9 to R12 with 0 Ω and
not populating R4, R5, R13 to R16. This way the transformer does not need to be
removed. The baseband outputs are taken from the SMAs of Q_HI, Q_LO, I_HI, and I_LO.
L1, L2,
R7, R8
Input Biasing. Inductance and resistance sets the input biasing of the common
base input stage. The default value is 33 nH.
L1, L2 = 33 nH (0603CS-33NX,
Coilcraft)
R7, R8 = 0 Ω (0402)
T2, T3
IF Output Interface. TCM9-1 converts a differential high impedance IF output to a single-
ended output. When loaded with 50 Ω, this balun presents a 450 Ω load to the device.
The center tap can be decoupled through a capacitor to ground.
T2, T3 = TCM9-1, 9:1
(Mini-Circuits)
C12, C13
Decoupling Capacitors. C12 and C13 are the decoupling capacitors used to reject noise
on the center tap of the TCM9-1.
C12, C13 = 0.1 μF (0402)
T4 = ETC1-1-13, 1:1 (M/A-COM)
T1 = ETC1-1-13, 1:1 (M/A-COM)
R2 = open
T4
T1
R2
LO Input Interface. The LO is driven differentially. ETC1-1-13 is a 1:1 RF balun that
converts the single-ended RF input to differential signal.
RF Input Interface. ETC1-1-13 is a 1:1 RF balun that converts the single-ended RF input
to differential signal.
RBIAS. Optional bias setting resistor. See the Bias Circuit section to see how to use this feature.
Rev. 0 | Page 24 of 28
ADL5382
Figure 62. Evaluation Board Top Layer Silkscreen
Figure 61. Evaluation Board Top Layer
Rev. 0 | Page 25 of 28
ADL5382
Figure 63. Evaluation Board Bottom Layer
Figure 64. Evaluation Board Bottom Layer Silkscreen
Rev. 0 | Page 26 of 28
ADL5382
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
0.50
BSC
PIN 1
INDICATOR
*
2.45
2.30 SQ
2.15
TOP
3.75
EXPOSED
VIEW
BSC SQ
PA D
(BOTTOMVIEW)
0.50
0.40
0.30
6
13
7
12
0.23 MIN
2.50 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 65. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5382ACPZ-R71
ADL5382ACPZ-WP1
ADL5382-EVALZ1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
CP-24-2
CP-24-2
Ordering Quantity
24-Lead LFCSP_VQ, 7”Tape and Reel
24-Lead LFCSP_VQ, Waffle Pack
Evaluation Board
1,500
64
1 Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
ADL5382
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07208-0-3/08(0)
Rev. 0 | Page 28 of 28
相关型号：
ADL5386ACPZ-R2
SPECIALTY TELECOM CIRCUIT, QCC40, 6 X 6 MM, ROHS COMPLIANT, MO-220-VJJD-2, LFCSP-40
ADI
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