ADIS16475-1 [ADI]
Precision, Miniature MEMs IMU;型号: | ADIS16475-1 |
厂家: | ADI |
描述: | Precision, Miniature MEMs IMU |
文件: | 总37页 (文件大小:1266K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Precision, Miniature MEMs IMU
Data Sheet
ADIS16475
FEATURES
GENERAL DESCRIPTION
Triaxial, digital gyroscope
The ADIS16475 is a precision, miniature MEMS inertial measure-
ment unit (IMU) that includes a triaxial gyroscope and a triaxial
accelerometer. Each inertial sensor in the ADIS16475 combines
with signal conditioning that optimizes dynamic performance.
The factory calibration characterizes each sensor for sensitivity,
bias, alignment, linear acceleration (gyroscope bias), and point
of percussion (accelerometer location). As a result, each sensor
has dynamic compensation formulas that provide accurate
sensor measurements over a broad set of conditions.
125°/sec, 500°/sec, 2000°/sec range models
2°/hr in-run bias stability (ADIS16475-1)
0.15°/√hr angle random walk (ADIS16475-1 and
ADIS16475-2)
0.1° axis to axis misalignment error
Triaxial, digital accelerometer, 8 g
3.6 μg in-run bias stability
Triaxial, delta angle and delta velocity outputs
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −40°C to +85°C
SPI compatible data communications
Programmable operation and control
Automatic and manual bias correction controls
Data ready indicator for synchronous data acquisition
External sync modes: direct, pulse, scaled, and output
On demand self test of inertial sensors
On demand self test of flash memory
The ADIS16475 provides a simple, cost effective method for
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at the
factory, greatly reducing system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation
systems. The serial peripheral interface (SPI) and register
structure provide a simple interface for data collection and
configuration control.
Single-supply operation (VDD): 3.0 V to 3.6 V
2000 g mechanical shock survivability
Operating temperature range: −40°C to +105°C
The ADIS16475 is available in a 44-ball, ball grid array (BGA)
package that is approximately 11 mm × 15 mm × 11 mm.
APPLICATIONS
Navigation, stabilization, and instrumentation
Unmanned and autonomous vehicles
Smart agriculture and construction machinery
Factory/industrial automation, robotics
Virtual/augmented reality
Internet of Moving Things
FUNCTIONAL BLOCK DIAGRAM
DR
RST
VDD
POWER
MANAGEMENT
GND
SELF TEST
I/O
OUTPUT
DATA
CS
TRIAXIAL
GYROSCOPE
REGISTERS
SCLK
DIN
CALIBRATION
TRIAXIAL
ACCELEROMETER
SPI
CONTROLLER
AND
FILTERS
USER
CONTROL
REGISTERS
TEMPERATURE
SENSOR
DOUT
CLOCK
ADIS16475
SYNC
Figure 1.
Rev. D
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Tel: 781.329.4700 ©2017–2020 Analog Devices, Inc. All rights reserved.
Technical Support
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ADIS16475
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Device Configuration ................................................................ 16
User Register Memory Map.......................................................... 17
User Register Defintions ............................................................... 19
Gyroscope Data .......................................................................... 19
Delta Angles................................................................................ 22
Delta Velocity ............................................................................. 24
Calibration .................................................................................. 25
Applications Information ............................................................. 32
Assembly and Handling Tips ................................................... 32
Power Supply Considerations .................................................. 33
Serial Port Operation................................................................. 33
Digital Resolution of Gyroscopes and Accelerometers ........ 33
Evaluation Tools......................................................................... 34
Tray Drawing.............................................................................. 36
Packaging and Ordering Information......................................... 37
Outline Dimensions................................................................... 37
Ordering Guide .......................................................................... 37
Applications ...................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings....................................................... 7
Thermal Resistance...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions ............................ 8
Typical Performance Characteristics........................................... 10
Theory of Operation ...................................................................... 12
Introduction................................................................................ 12
Inertial Sensor Signal Chain ..................................................... 12
Register Structure....................................................................... 13
Serial Peripheral Interface (SPI)............................................... 14
Data Ready (DR) ........................................................................ 14
Reading Sensor Data.................................................................. 15
REVISION HISTORY
4/2020—Rev. C to Rev. D
Change to Logic Inputs Parameter, Table 1 ................................. 4
Changes to Endnote 1, Table 3....................................................... 7
Changes to Figure 5 ..........................................................................6
Changes to Figure 11 ..................................................................... 10
Added Figure 12 and Figure 13; Renumbered Sequentially..... 10
Added Figure 14, Figure 15, Figure 16, and Figure 17.............. 11
Changes to Figure 18, Figure 19, and Figure 20 ........................ 12
Changes to Figure 22 and Figure 23............................................ 13
Added Gyroscope Data Width (Digital Resolution) Section... 19
Changes to Gyroscope Measurement Range/Scale Factor Section,
Table 11, Table 12, Table 13, Table 17, Table 21, and Table 25 20
Added Accelerometer Data Width (Digital Resolution)
Section.............................................................................................. 21
Change to Calibration, Accelerometer Bias (XA_BIAS_LOW
and XA_BIAS_HIGH) Section..................................................... 26
Change to Filter Control Register (FILT_CTRL) Section........ 27
Changes to Direct Sync Mode Section and to Pulse Sync Mode
Section.............................................................................................. 28
Changes to Sensor Self Test Section ............................................ 30
4/2019—Rev. B to Rev. C
Changes to Serial Peripheral Interface (SPI) Section ................ 14
Changes to Figure 32 ..................................................................... 15
Changes to Table 10 and Gyroscope Data Section.................... 19
Changes to Acceleration Data Section ........................................ 20
Added Accelerometer Data Formatting Section........................ 21
Deleted Accelerometer Resolution Section ................................ 21
Added Serial Port Operation Section, Maximum Throughput
Section, Serial Port SCLK Underrun/Overrun Conditions Section,
and Digital Resolution of Gyroscopes and Accelerometers Section
.....................................................................................................................33
Moved Gyroscope Data Width (Digital Resolution) Section... 33
Moved Accelerometer Data Width (Digital Resolution) Section. 33
Moved Figure 52 and Figure 53.................................................... 35
Added Tray Drawing Section ....................................................... 36
Added Figure 54 ............................................................................. 36
11/2017—Rev. 0 to Rev. A
Changes to Table 1............................................................................3
Deleted Endnote 1, Table 1; Renumbered Sequentially...............4
Added Endnote 2, Table 1; Renumbered Sequentially ................4
1/2019—Rev. A to Rev. B
Changes to Table 1 ........................................................................... 3
Changes to Table 2 ........................................................................... 5
10/2017—Revision 0: Initial Version
Rev. D | Page 2 of 37
Data Sheet
ADIS16475
SPECIFICATIONS
Case temperature (TC) = 25°C, VDD = 3.3 V, angular rate = 0°/sec, dynamic range = ±2000°/sec ± 1 g, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
125
Typ
Max
Unit
GYROSCOPES
Dynamic Range
ADIS16475-1
°/sec
ADIS16475-2
500
°/sec
ADIS16475-3
2000
°/sec
Sensitivity
ADIS16475-1, 16-bit
ADIS16475-2, 16-bit
ADIS16475-3, 16-bit
ADIS16475-1, 32-bit
ADIS16475-2, 32-bit
ADIS16475-3, 32-bit
−40°C ≤ TC ≤ +85°C, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
Axis to axis, −40°C ≤ TC ≤ +85°C, 1 σ
ADIS16475-1, full scale (FS) = 125°/sec
ADIS16475-2, FS = 500°/sec
ADIS16475-3, FS = 2000°/sec
160
40
10
10,485,760
2,621,440
655,360
0.3
0.3
0.1
LSB/°/sec
LSB/°/sec
LSB/°/sec
LSB/°/sec
LSB/°/sec
LSB/°/sec
%
Error over Temperature
Repeatability1
Misalignment Error
Nonlinearity2
%
Degrees
% FS
% FS
0.2
0.2
0.25
% FS
Bias
Repeatability1
In-Run Bias Stability
−40°C ≤ TC ≤ +85°C, 1 σ
ADIS16475-1, 1 σ
0.7
2
°/sec
°/hr
ADIS16475-2, 1 σ
2.5
°/hr
ADIS16475-3, 1 σ
7
°/hr
Angular Random Walk
ADIS16475-1, 1 σ
ADIS16475-2, 1 σ
ADIS16475-3, 1 σ
0.15
0.15
0.3
°/√hr
°/√hr
°/√hr
Error over Temperature
Linear Acceleration Effect
Vibration Rectified Error (VRE)
Output Noise
−40°C ≤ TC ≤ +85°C, 1 σ
Any direction, 1 σ
0.2
°/sec
0.01
0.0005
0.07
0.08
0.17
0.003
0.003
0.007
550
66
°/sec/g
°/sec/g2
°/sec rms
°/sec rms
°/sec rms
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
Hz
Random vibration, 2 grms, 50 Hz to 2 kHz
ADIS16475-1, 1 σ, no filtering
ADIS16475-2, 1 σ, no filtering
ADIS16475-3, 1 σ, no filtering
ADIS16475-1, f = 10 Hz to 40 Hz
ADIS16475-2, f = 10 Hz to 40 Hz
ADIS16475-3, f = 10 Hz to 40 Hz
Rate Noise Density
3 dB Bandwidth
Sensor Resonant Frequency
ACCELEROMETERS3
Dynamic Range
kHz
Each axis
8
g
Sensitivity
Error over temperature
Repeatability1
32-bit data format
−40°C ≤ TC ≤ +85°C, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
262,144,000
0.1
0.1
LSB/g
%
%
Misalignment Error
Nonlinearity
Axis to axis, −40°C ≤ TC ≤ +85°C, 1 σ
Best fit straight line, 2 g
Best fit straight line, 8 g, x-axis
Best fit straight line, 8 g, y-axis and z-axis
0.05
0.25
0.5
Degrees
% FS
% FS
% FS
1.5
Bias
Repeatability1
−40°C ≤ TC ≤ +85°C, 1 σ
1 σ
1 σ
1.4
3.6
0.012
1
mg
μg
m/sec/√hr
mg
In-Run Bias Stability
Velocity Random Walk
Error over Temperature
−40°C ≤ TC ≤ +85°C, 1 σ
Rev. D | Page 3 of 37
ADIS16475
Data Sheet
Parameter
Test Conditions/Comments
No filtering
f = 10 Hz to 40 Hz, no filtering
Min
Typ
0.6
23
600
2.4
2.2
Max
Unit
Output Noise
Noise Density
3 dB Bandwidth
Sensor Resonant Frequency
mg rms
μg/√Hz rms
Hz
kHz
kHz
Y-axis and z-axis
X-axis
TEMPERATURE SENSOR
Scale Factor
Output = 0x0000 at 0°C ( 5°C)
0.1
°C/LSB
LOGIC INPUTS4
Input Voltage
High, VIH
Low, VIL
RST Pulse Width
Input Current
2.0
1
V
V
µs
0.8
Logic 1, IIH
Logic 0, IIL
All Pins Except RST
RST Pin
VIH = 3.3 V
VIL = 0 V
10
10
µA
µA
mA
pF
0.33
10
Input Capacitance, CIN
DIGITAL OUTPUTS
Output Voltage
High, VOH
ISOURCE = 0.5 mA
ISINK = 2.0 mA
2.4
V
V
Low, VOL
0.4
FLASH MEMORY
Data Retention6
FUNCTIONAL TIMES7
Power-On Start-Up Time
Reset Recovery Time8
Factory Calibration Restore
Flash Memory Backup
Flash Memory Test Time
Self Test Time9
Endurance5
TJ = 85°C
10000
20
Cycles
Years
Time until data is available
252
193
142
72
32
14
ms
ms
ms
ms
ms
ms
SPS
%
GLOB_CMD, Bit 7 = 1 (see Table 113)
GLOB_CMD, Bit 1 = 1 (see Table 113)
GLOB_CMD, Bit 3 = 1 (see Table 113)
GLOB_CMD, Bit 4 = 1 (see Table 113)
GLOB_CMD, Bit 2 = 1 (see Table 113)
CONVERSION RATE
Initial Clock Accuracy
Sync Input Clock
POWER SUPPLY, VDD
Power Supply Current10
2000
3
1.9
3.0
2.1
3.6
55
kHz
V
mA
Operating voltage range
Normal mode, VDD = 3.3 V
44
1 Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of high temperature operating life (HTOL) at 105°C.
2 This measurement is based on the deviation from a best fit linear model.
3 All specifications associated with the accelerometers relate to the full-scale range of 8 g, unless otherwise noted.
4 The digital input/output signals use a 3.3 V system.
5 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C.
6 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ.
7 These times do not include thermal settling and internal filter response times, which may affect overall accuracy.
8
RST
The
line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery.
9 The self test time can extend when using external clock rates lower than 2000 Hz.
10 Power supply current transients can reach 100 mA during initial startup or reset recovery.
Rev. D | Page 4 of 37
Data Sheet
ADIS16475
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Normal Mode
Burst Read Mode
Parameter
fSCLK
tSTALL
tREADRATE
tCS
Description
Min
0.1
16
24
200
Typ
Max
Min1
Typ
Max
Unit
MHz
µs
µs
ns
Serial clock
Stall period between data
Read rate
2
0.1
N/A
1
Chip select to SCLK edge
200
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDR, tDF
tSFS
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise/fall times
DOUT rise/fall times
CS high after SCLK edge
25
25
ns
ns
ns
ns
ns
ns
µs
25
50
25
50
5
5
12.5
12.5
5
5
12.5
12.5
0
5
0
5
t1
Input sync positive pulse width; pulse sync mode, MSC_CTRL =
101 (binary, see Table 105)
tSTDR
Input sync to data ready valid transition
Direct sync mode, MSC_CTRL = 001 (binary, see Table 105)
Pulse sync mode, MSC_CTRL = 101 (binary, see Table 105)
Data invalid time
256
256
20
256
256
20
µs
µs
µs
µs
tNV
t2
Input sync period2
477
477
1 N/A means not applicable.
2 This specification is rounded up from the cycle time that comes from the maximum input clock frequency (2100 Hz).
Timing Diagrams
CS
tSCLKR
tSCLKF
tCS
tSFS
1
2
3
4
5
6
15
16
SCLK
DOUT
tDAV
tDR
MSB
R/W
DB14
tDSU
DB13
A5
DB12
DB11
A3
DB10
tDF
DB2
DB1
LSB
LSB
tDHD
DIN
A6
A4
A2
D2
D1
Figure 2. SPI Timing and Sequence Diagram
tREADRATE
tSTALL
CS
SCLK
Figure 3. Stall Time and Data Rate Timing Diagram
Rev. D | Page 5 of 37
ADIS16475
Data Sheet
t2
tSTDR
t1
SYNC
DR
tNV
Figure 4. Input Clock Timing Diagram, Pulse Sync Mode, Register MSC_CTRL, Bits[4:2] = 101 (Binary)
t2
t1
SYNC
DR
tNV
tSTDR
Figure 5. Input Clock Timing Diagram, Direct Sync Mode, Register MSC_CTRL, Bits[4:2] = 001 (Binary)
Rev. D | Page 6 of 37
Data Sheet
ADIS16475
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Mechanical Shock Survivability
Any Axis, Unpowered
2000 g
Any Axis, Powered
VDD to GND
2000 g
The ADIS16475 is a multichip module that includes many
active components. The values in Table 4 identify the thermal
response of the hottest component inside of the ADIS16475,
with respect to the overall power dissipation of the module.
This approach enables a simple method for predicting the
temperature of the hottest junction, based on either ambient or
case temperature.
−0.3 V to +3.6 V
−0.3 V to VDD + 0.2 V
−0.3 V to VDD + 0.2 V
−40°C to +85°C
−40°C to +105°C
−65°C to +150°C
2 bar
Digital Input Voltage to GND
Digital Output Voltage to GND
Calibration Temperature Range
Operating Temperature Range
Storage Temperature Range1
Barometric Pressure
For example, when the ambient temperature is 70°C, the
hottest junction temperature (TJ) inside of the ADIS16475 is
76.7°C.
1 Extended exposure to temperatures that are lower than −40°C or higher
than +105°C may adversely affect the accuracy of the factory calibration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
TJ = θJA × VDD × IDD + 70°C
TJ = 158.2°C/W × 3.3 V × 0.044 A + 70°C
TJ = 93°C
Table 4. Package Characteristics
1
2
Package Type θJA
ML-44-13
158.2°C/W
θJC
Device Weight
106.1°C/W
1.3 g
1 θJA is the natural convection junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure.
2 θJC is the junction to case thermal resistance.
3 Thermal impedance values come from direct observation of the hottest
temperature inside of the ADIS16475 when it is attached to an FR4-08 PCB
that has two metal layers and has a thickness of 0.063 inches.
ESD CAUTION
Rev. D | Page 7 of 37
ADIS16475
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIS16475
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
7
8
PIN A1
PIN A8
PIN K8
BOTTOM VIEW OF PACKAGE
Figure 7. Pin Assignments, Package Level View
Figure 6. Pin Assignments, Bottom View
Table 5. Pin Function Descriptions
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
B3
B4
B5
B6
C2
C3
C6
C7
D3
D6
E2
Mnemonic
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
GND
VDD
GND
VDD
GND
VDD
GND
GND
GND
RST
Type
Description
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Not applicable
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Input
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Power Ground
Do Not Connect
Power Ground
Power Supply
Power Ground
Power Supply
Power Ground
Power Supply
Power Ground
Power Ground
Power Ground
Reset
E3
E6
E7
F1
F3
F6
F8
GND
GND
GND
CS
Supply
Supply
Supply
Input
Power Ground
Power Ground
Power Ground
SPI, Chip Select
SPI, Data Input
Power Supply
Power Supply
SPI, Data Output
SPI, Serial Clock
Power Ground
G2
G3
G6
G7
H1
H3
H6
H8
DIN
Input
GND
VDD
DOUT
SCLK
GND
Supply
Supply
Output
Input
Supply
Rev. D | Page 8 of 37
Data Sheet
ADIS16475
Pin No.
J2
J3
J4
J5
J6
J7
K1
K3
K6
K8
Mnemonic
GND
SYNC
VDD
VDD
DR
GND
GND
GND
VDD
Type
Description
Supply
Input
Power Ground
Sync (External Clock)
Power Supply
Power Supply
Data Ready
Power Ground
Power Ground
Power Ground
Power Supply
Power Ground
Supply
Supply
Output
Supply
Supply
Supply
Supply
Supply
GND
Rev. D | Page 9 of 37
ADIS16475
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1000
X-AXIS
X-AXIS
Y-AXIS
Z-AXIS
Y-AXIS
Z-AXIS
100
10
1
0.1
0.001
0.01
0.1
1
10
100
1000 10000 100000
0.001
0.01
0.1
1
10
100
1000 10000 100000
INTEGRATION PERIOD (Seconds)
INTEGRATION PERIOD (Seconds)
Figure 8. Gyroscope Allan Deviation, TC = 25°C, ADIS16475-1
Figure 11. Accelerometer Allan Deviation, TC = 25°C
1000
0.5
0.4
X-AXIS
Y-AXIS
Z-AXIS
0.3
100
10
1
0.2
0.1
µ + 1σ
0
–0.1
–0.2
–0.3
–0.4
–0.5
µ
µ – 1σ
0.1
0.001 0.01
0.1
1
10
100
1000 10000 100000
–60
–40
–20
0
20
40
60
80
100
INTEGRATION PERIOD (Seconds)
AMBIENT TEMPERATURE (°C)
Figure 12. ADIS16475-1 Gyroscope Sensitivity Error vs. Ambient Temperature
Figure 9. Gyroscope Allan Deviation vs. TC = 25°C, ADIS16475-2
0.5
0.4
0.3
0.2
1000
X-AXIS
Y-AXIS
Z-AXIS
100
10
1
µ + 1σ
µ – 1σ
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
µ
0.1
0.001
–60
–40
–20
0
20
40
60
80
100
0.01
0.1
1
10
100
1000 10000 100000
AMBIENT TEMPERATURE (°C)
INTEGRATION PERIOD (Seconds)
Figure 13. ADIS16475-2 Gyroscope Sensitivity Error vs. Ambient Temperature
Figure 10. Gyroscope Allan Deviation, TC = 25°C, ADIS16475-3
Rev. D | Page 10 of 37
Data Sheet
ADIS16475
0.5
0.5
0.4
0.4
0.3
0.3
µ + 1σ
0.2
0.2
0.1
0.1
0
0
µ + 1σ
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
µ
µ – 1σ
µ
µ – 1σ
–60
–40
–20
0
20
40
60
80
100
–60
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 14. ADIS16475-3 Gyroscope Sensitivity Error vs. Ambient Temperature
Figure 16. ADIS16475-2 Gyroscope Bias Error vs. Ambient Temperature
0.5
0.4
0.3
0.2
0.5
0.4
0.3
0.2
µ + 1σ
µ + 1σ
0.1
0.1
0
0
µ
µ
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
µ – 1σ
µ – 1σ
–0.2
–0.3
–0.4
–0.5
–60
–40
–20
0
20
40
60
80
100
–60
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 15. ADIS16475-1 Gyroscope Bias Error vs. Ambient Temperature
Figure 17. ADIS16475-3 Gyroscope Bias Error vs. Ambient Temperature
Rev. D | Page 11 of 37
ADIS16475
Data Sheet
THEORY OF OPERATION
External Clock Options
INTRODUCTION
The ADIS16475 provides three different modes of operation
that support the device using an external clock to control the
internal processing rate (fSM in Figure 19 and Figure 20) through
the SYNC pin. The MSC_CTRL register (see Table 105) provides
the configuration options for these external clock modes in
Bits[4:2].
When using the factory default configuration for all user
configurable control registers, the ADIS16475 initializes itself
and automatically starts a continuous process of sampling,
processing, and loading calibrated sensor data into its output
registers at a rate of 2000 SPS.
INERTIAL SENSOR SIGNAL CHAIN
Inertial Sensor Calibration
Figure 18 provides the basic signal chain for the inertial sensors
in the ADIS16475. This signal chain produces an update rate
of 2000 SPS in the output data registers when it operates in
internal clock mode (default, see Register MSC_CTRL, Bits[4:2]
in Table 105).
The inertial sensor calibration function for the gyroscopes and the
accelerometers has two components: factory calibration and
user calibration (see Figure 21).
FROM
TO
BARTLETT
WINDOW
FIR FILTER
FACTORY
CALIBRATION
USER
CALIBRATION
AVERAGING
DECIMATING
FILTER
BARTLETT
AVERAGING
DECIMATING
FILTER
OUTPUT
DATA
REGISTERS
MEMS
SENSORS
WINDOW
FIR
CALIBRATION
FILTER
Figure 21. Inertial Sensor Calibration Processing
The factory calibration of the gyroscope applies the following
correction formulas to the data of each gyroscope:
Figure 18. Signal Processing Diagram, Inertial Sensors
Gyroscope Data Sampling
bX
ω
m11 m12
m
ω
The three gyroscopes produce angular rate measurements around
three orthogonal axes (x, y, and z). Figure 19 shows the data
sampling plan for each gyroscope when the ADIS16475 operates
in internal clock mode (default, see Register MSC_CTRL,
Bits[4:2] in Table 105). Each gyroscope has an analog-to-digital
converter (ADC) and sample clock (fSG) that drives data sampling
at a rate of 4100 Hz (±5%). The internal processor reads and
processes this data from each gyroscope at a rate of 2000 Hz (fSM).
XC
13
X
ωYC = m21 m22 m23
×
ωY + bY
+
ωZC
m31 m32 m33
ωZ
bZ
l
l12
l
a
11
13
XC
l21 l22 l23 × aYC
l31 l32 l33
aZC
where:
TO
INTERNAL
BARTLETT
WINDOW
MEMS
GYROSCOPE
ωXC, ωYC, and ωZC are the gyroscope outputs (post calibration).
m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and
alignment correction.
DATA
ADC
REGISTER
FIR FILTER
fSG = 4100Hz
fSM = 2000Hz
ωX, ωY, and ωZ are the gyroscope outputs (precalibration).
bX, bY, and bZ provide bias correction.
l11, l12, l13, l21, l22, l23, l31, l32, and l33 provide linear g correction
aXC, aYC, and aZC are the accelerometer outputs (post calibration).
Figure 19. Gyroscope Data Sampling
Accelerometer Data Sampling
The three accelerometers produce linear acceleration measurements
along the same orthogonal axes (x, y, and z) as the gyroscopes.
Figure 20 shows the data sampling plan for each accelerometer
when the ADIS16475 operates in internal clock mode (default,
see Register MSC_CTRL, Bits[4:2] in Table 105).
All of the correction factors in this relationship come from
direct observation of the response of each gyroscope at multiple
temperatures over the calibration temperature range (−40°C ≤
TC ≤ +85°C). These correction factors are stored in the flash
memory bank, but they are not available for observation or
configuration. Register MSC_CTRL, Bit 7 (see Table 105)
provides the only user configuration option for the factory
calibration of the gyroscopes: an on/off control for the linear g
compensation. See Figure 44 for more details on the user
calibration options available for the gyroscopes.
TO
2
1
2
MEMS
BARTLETT
WINDOW
a(n)
ADC
ACCELEROMETER
n = 1
÷2
FIR FILTER
2 × fSM = 4000Hz
Figure 20. Accelerometer Data Sampling
Rev. D | Page 12 of 37
Data Sheet
ADIS16475
The factory calibration of the accelerometer applies the following
correction formulas to the data of each accelerometer:
Bartlett Window FIR Filter
The Bartlett window finite impulse response (FIR) filter
(see Figure 22) contains two averaging filter stages in a cascade
configuration. The FILT_CTRL register (see Table 101) provides
the configuration controls for this filter.
aXC
aYC
aZC
m11 m12 m13
m21 m22 m23
m31 m32 m33
aX
aY
aZ
bX
bY
bZ
=
×
+
+
FROM
MEMS
SENSOR
N
N
TO
1
N
1
N
2
ω(n)
ω(n)
FACTORY
CALIBRATION
ω
0
p21
p31 p32
p12 p13
0
n = 1
n = 1
XC
p23 × ω2
YC
Figure 22. Bartlett Window FIR Filter Signal Path
ω2ZC
0
Averaging/Decimating Filter
where:
The second digital filter averages multiple samples together to
produce each register update. In this type of filter structure, the
number of samples in the average is equal to the reduction in
the update rate for the output data registers. The DEC_RATE
register (see Table 109) provides the configuration controls for
this filter.
aXC, aYC, and aZC are the accelerometer outputs (post calibration).
m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and
alignment correction.
aX, aY, and aZ are the accelerometer outputs (precalibration).
bX, bY, and bZ provide bias correction.
p12, p13, p21, p23, p31, and p32 provide a point of percussion
alignment correction (see Figure 47).
FROM
USER
CALIBRATION
N
1
N
TO OUTPUT
REGISTERS
ω(n)
Σ
ω2XC, ω2YC, and ω2ZC are the square of the gyroscope outputs
(post calibration).
÷N
n = 1
Figure 23. Averaging/Decimating Filter Diagram
All of the correction factors in this relationship come from
direct observation of the response of each accelerometer at
multiple temperatures over the calibration temperature range
(−40°C ≤ TC ≤ +85°C). These correction factors are stored
in the flash memory bank, but they are not available for
observation or configuration. MSC_CTRL, Bit 6 (see Table 105)
provides the only user configuration option for the factory
calibration of the accelerometers: an on/off control for the point of
percussion, alignment function. See Figure 45 for more details
on the user calibration options available for the accelerometers.
REGISTER STRUCTURE
All communication between the ADIS16475 and an external
processor involves either reading the contents of an output
register or writing configuration/command information to a
control register. The output data registers include the latest
sensor data, error flags, and identification information. The
control registers include sample rate, filtering, calibration, and
diagnostic options. Each user accessible register has two bytes
(upper and lower), each of which has its own unique address.
See Table 8 for a detailed list of all user registers, along with
their addresses.
TRIAXIAL
SENSOR
OUTPUT
REGISTERS
GYROSCOPE
SIGNAL
PROCESSING
TRIAXIAL
ACCELLEROMETER
CONTROL
REGISTERS
TEMPERATURE
SENSOR
CONTROLLER
Figure 24. Basic Operation of the ADIS16475
Rev. D | Page 13 of 37
ADIS16475
Data Sheet
SERIAL PERIPHERAL INTERFACE (SPI)
DATA READY (DR)
The SPI provides access to the user registers (see Table 8).
Figure 25 shows the most common connections between the
ADIS16475 and a SPI master device, which is often an embedded
processor that has a SPI-compatible interface. In this example,
the SPI master uses an interrupt service routine to collect data
every time the data ready (DR) signal pulses.
The factory default configuration provides users with a DR
signal on the DR pin (see Table 5), which pulses when the output
data registers are updating. Connect the DR pin to a pin on the
embedded processor, which triggers data collection, on the
second edge of this pulse. The MSC_CTRL register, Bit 0 (see
Table 105), controls the polarity of this signal. In Figure 26,
Register MSC_CTRL, Bit 0 = 1, which means that data
collection must start on the rising edges of the DR pulses.
Additional information on the ADIS16475 SPI can be found in
the Serial Port Operation section of this data sheet.
I/O LINES ARE COMPATIBLE WITH
3.3V LOGIC LEVELS
DR
INACTIVE
ACTIVE
+3.3V
VDD
Figure 26. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default)
SYSTEM
ADIS16475
During the start-up and reset recovery processes, the DR signal
may exhibit some transient behavior before data production
begins. Figure 27 shows an example of the DR behavior during
startup, and Figure 28 and Figure 29 provide examples of the
DR behavior during recovery from reset commands.
PROCESSOR
SS
SCLK
MOSI
MISO
IRQ
CS
SPI MASTER
SCLK
DIN
DOUT
DR
TIME THAT VDD > 3V
VDD
Figure 25. Electrical Connection Diagram
PULSING INDICATES
DATA PRODUCTION
Table 6. Generic SPI Master Pin Names and Functions
Mnemonic
Function
DR
SS
Slave select
SCLK
MOSI
MISO
IRQ
Serial clock
START-UP TIME
Master output, slave input
Master input, slave output
Interrupt request
Figure 27. Data Ready Response During Startup
SOFTWARE RESET COMMAND
GLOB_CMD[7] = 1
Embedded processors typically use control registers to configure
their serial ports for communicating with SPI slave devices such
as the ADIS16475. Table 7 provides a list of settings that describe
the SPI protocol of the ADIS16475. The initialization routine
of the master processor typically establishes these settings using
firmware commands to write them into the control registers.
DR PULSING
RESUMES
DR
RESET RECOVERY TIME
Figure 28. Data Ready Response During Reset
(Register GLOB_CMD, Bit 7 = 1) Recovery
Table 7. Generic Master Processor SPI Settings
Processor Setting Description
RST PIN
RELEASED
Master
ADIS16475 operates as slave
SCLK ≤ 2 MHz1
SPI Mode 3
MSB First Mode
16-Bit Mode
Maximum serial clock rate
RST
DR PULSING
RESUMES
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence, see Figure 30 for coding
Shift register and data length
DR
1 A burst mode read requires this value to be ≤1 MHz (see Table 2 for more
information).
RESET RECOVERY TIME
RST
Figure 29. Data Ready Response During Reset (
= 0) Recovery
Rev. D | Page 14 of 37
Data Sheet
ADIS16475
CS
SCLK
DIN
R/W A6
A5
R/W A6
A5
A4
A3
A2
A1
A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
D15 D14 D13 D12 D11 D10 D9
D15 D14 D13
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS INA THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
Figure 30. SPI Communication Bit Sequence
1
2
3
11
CS
SCLK
0x6800
DIN
DIAG_STAT
XGYRO_OUT
CHECKSUM
DOUT
Figure 31. Burst Read Sequence
CS
SCLK
DIN
DIN = 0x7200 = 0111 0010 0000 0000
HIGH-Z
HIGH-Z
DOUT
DOUT = 0100 0000 0101 1011 = 0x405B = 16475 (PROD_ID)
Figure 32. SPI Signal Pattern Showing a Read of the PROD_ID Register
Burst Read Function
READING SENSOR DATA
The burst read function provides a way to read a batch of
Reading a single register requires two 16-bit cycles on the SPI:
one to request the contents of a register and another to receive
those contents. The 16-bit command code (see Figure 30) for a
output data registers, using a continuous stream of bits, at a
rate of up to 1 MHz (SCLK). This method does not require a
stall time between each 16-bit segment (see Figure 3). As shown
in Figure 31, start this mode by setting DIN = 0x6800, and then
read each of the registers in the sequence out of DOUT while
R
read request on the SPI has three parts: the read bit ( /W = 0),
either address of the register, [A6:A0], and eight don’t care bits,
[DC7:DC0]. Figure 33 shows an example that includes two register
reads in succession. This example starts with DIN = 0x0C00 to
request the contents of the Z_GYRO_LOW register, and
follows with 0x0E00 to request the contents of the Z_GYRO_OUT
register. The sequence in Figure 33 also shows full duplex mode
of operation, which means that the ADIS16475 can receive
requests on DIN while also transmitting data out on DOUT
within the same 16-bit SPI cycle.
CS
keeping
low for the entire 176-bit sequence.
The sequence of registers (and checksum value) in the burst read
response depends on which sample clock mode that the ADIS16475
is operating in (Register MSC_CTRL, Bits[4:2], see Table 105). In
all clock modes, except when operating in scaled sync mode
(Register MSC_CTRL, Bits[4:2] = 010), the burst read response
includes the following registers and value: DIAG_STAT,
X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT, X_ACCL_
OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT, DATA_
CNTR, and the checksum value. In these cases, use the following
formula to verify the checksum value, treating each byte in the
formula as an independent, unsigned, 8-bit number:
NEXT
DIN
0x0C00
0x0E00
ADDRESS
DOUT
Z_GYRO_LOW
Z_GYRO_OUT
Figure 33. SPI Read Example
Figure 32 provides an example of the four SPI signals when
reading the PROD_ID register (see Table 121) in a repeating
pattern. This pattern can be helpful when troubleshooting the
SPI interface setup and communications because the signals are
the same for each 16-bit sequence, except during the first cycle.
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +
Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +
Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +
X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +
Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +
Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0]
Rev. D | Page 15 of 37
ADIS16475
Data Sheet
When operating in scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010), the burst read response includes the following
registers and value: DIAG_STAT, X_GYRO_OUT,
Memory Structure
Figure 35 provides a functional diagram for the memory
structure of the ADIS16475. The flash memory bank contains
the operational code, unit specific calibration coefficients, and
user configuration settings. During initialization (power
application or reset recover), this information loads from the
flash memory into the static random access memory (SRAM),
which supports all normal operation, including register access
through the SPI port. Writing to a configuration register using
the SPI updates the SRAM location of the register, but does not
automatically update its settings in the flash memory bank. The
manual flash memory update command (Register GLOB_CMD,
Bit 3, see Table 113) provides a convenient method for saving
all of these settings to the flash memory bank at one time. A yes
in the flash backup column of Table 8 identifies the registers
that have storage support in the flash memory bank.
Y_GYRO_OUT, Z_GYRO_OUT, X_ACCL_OUT,
Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT, TIME_STAMP,
and the checksum value. In this case, use the following formula
to verify the checksum value, treating each byte in the formula
as an independent, unsigned, 8-bit number.
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +
Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +
Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +
X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +
Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +
Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
TIME_STAMP, Bits[15:8] + TIME_STAMP, Bits[7:0]
MANUAL
FLASH
BACKUP
DEVICE CONFIGURATION
Each configuration register contains 16 bits (two bytes). Bits[7:0]
contain the low byte, and Bits[15:8] contain the high byte of
each register. Each byte has its own unique address in the user
register map (see Table 8). Updating the contents of a register
requires writing to both of its bytes in the following sequence:
low byte first, high byte second. There are three parts to coding
a SPI command (see Figure 30) that write a new byte of data to
NONVOLATILE
FLASH MEMORY
VOLATILE
SRAM
SPI ACCESS
(NO SPI ACCESS)
START-UP
RESET
Figure 35. SRAM and Flash Memory Diagram
R
a register: the write bit ( /W = 1), the address of the byte, [A6:A0],
and the new data for that location, [DC7:DC0]. Figure 34 shows a
coding example for writing 0x0004 to the FILT_CTRL register
(see Table 101). In Figure 34, the 0xDC04 command writes 0x04 to
Address 0x5C (lower byte) and the 0xDD00 command writes
0x00 to Address 0x5D (upper byte).
CS
SCLK
DIN
0xDC04
0xDD00
Figure 34. SPI Sequence for Writing 0x0004 to FILT_CTRL
Rev. D | Page 16 of 37
Data Sheet
ADIS16475
USER REGISTER MEMORY MAP
Table 8. User Register Memory Map (N/A Means Not Applicable)
Name
R/W
N/A
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
R
R
R
R
R
R
R
R
R
R
R
R
Flash Backup
N/A
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
N/A
No
No
No
No
No
No
No
No
No
No
No
No
Address
Default
Register Description
Reserved
DIAG_STAT
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
0x0E, 0x0F
0x10, 0x11
0x12, 0x13
0x14, 0x15
0x16, 0x17
0x18, 0x19
0x1A, 0x1B
0x1C, 0x1D
0x1E, 0x1F
0x20, 0x21
0x22, 0x23
0x24, 0x25
0x26, 0x27
0x28, 0x29
0x2A, 0x2B
0x2C, 0x2D
0x2E, 0x2F
0x30, 0x31
0x32, 0x33
0x34, 0x35
0x36, 0x37
0x38, 0x39
0x3A, 0x3B
0x3C to 0x3F
0x40, 0x41
0x42, 0x43
0x44, 0x45
0x46, 0x47
0x48, 0x49
0x4A, 0x4B
0x4C, 0x4D
0x4E, 0x4F
0x50, 0x51
0x52, 0x53
0x54, 0x55
0x56, 0x57
0x58 to 0x5B
0x5C, 0x5D
0x5E, 0x5F
0x60, 0x61
0x62, 0x63
N/A
0x0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
N/A
Reserved
Output, system error flags
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
TEMP_OUT
Output, x-axis gyroscope, low word
Output, x-axis gyroscope, high word
Output, y-axis gyroscope, low word
Output, y-axis gyroscope, high word
Output, z-axis gyroscope, low word
Output, z-axis gyroscope, high word
Output, x-axis accelerometer, low word
Output, x-axis accelerometer, high word
Output, y-axis accelerometer, low word
Output, y-axis accelerometer, high word
Output, z-axis accelerometer, low word
Output, z-axis accelerometer, high word
Output, temperature
TIME_STAMP
Reserved
DATA_CNTR
Output, time stamp
Reserved
New data counter
X_DELTANG_LOW
X_DELTANG_OUT
Y_DELTANG_LOW
Y_DELTANG_OUT
Z_DELTANG_LOW
Z_DELTANG_OUT
X_DELTVEL_LOW
X_DELTVEL_OUT
Y_DELTVEL_LOW
Y_DELTVEL_OUT
Z_DELTVEL_LOW
Z_DELTVEL_OUT
Reserved
XG_BIAS_LOW
XG_BIAS_HIGH
YG_BIAS_LOW
YG_BIAS_HIGH
ZG_BIAS_LOW
ZG_BIAS_HIGH
XA_BIAS_LOW
XA_BIAS_HIGH
YA_BIAS_LOW
YA_BIAS_HIGH
ZA_BIAS_LOW
ZA_BIAS_HIGH
Reserved
Output, x-axis delta angle, low word
Output, x-axis delta angle, high word
Output, y-axis delta angle, low word
Output, y-axis delta angle, high word
Output, z-axis delta angle, low word
Output, z-axis delta angle, high word
Output, x-axis delta velocity, low word
Output, x-axis delta velocity, high word
Output, y-axis delta velocity, low word
Output, y-axis delta velocity, high word
Output, z-axis delta velocity, low word
Output, z-axis delta velocity, high word
Reserved
Calibration, offset, gyroscope, x-axis, low word
Calibration, offset, gyroscope, x-axis, high word
Calibration, offset, gyroscope, y-axis, low word
Calibration, offset, gyroscope, y-axis, high word
Calibration, offset, gyroscope, z-axis, low word
Calibration, offset, gyroscope, z-axis, high word
Calibration, offset, accelerometer, x-axis, low word
Calibration, offset, accelerometer, x-axis, high word
Calibration, offset, accelerometer, y-axis, low word
Calibration, offset, accelerometer, y-axis, high word
Calibration, offset, accelerometer, z-axis, low word
Calibration, offset, accelerometer, z-axis, high word
Reserved
R
No
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
R/W
R
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
N/A
Yes
No
FILT_CTRL
RANG_MDL
MSC_CTRL
UP_SCALE
0x0000
N/A1
0x00C1
0x07D0
Control, Bartlett window FIR filter
Measurement range (model specific) identifier
Control, input/output and other miscellaneous options
Control, scale factor for input clock, pulse per second (PPS)
mode
R/W
R/W
Yes
Yes
DEC_RATE
R/W
Yes
0x64, 0x65
0x0000
Control, decimation filter (output data rate)
Rev. D | Page 17 of 37
ADIS16475
Data Sheet
Name
R/W
R/W
W
N/A
R
R
R
R
R
R/W
R/W
R/W
R
Flash Backup
Address
Default
0x070A
N/A
N/A
N/A
N/A
N/A
0x405B
N/A
N/A
Register Description
NULL_CNFG
GLOB_CMD
Reserved
FIRM_REV
FIRM_DM
Yes
No
N/A
No
No
No
No
No
Yes
Yes
Yes
No
No
0x66, 0x67
0x68, 0x69
0x6A to 0x6B
0x6C, 0x6D
0x6E, 0x6F
0x70, 0x71
0x72, 0x73
0x74, 0x75
0x76, 0x77
0x78, 0x79
0x7A, 0x7B
0x7C, 0x7D
0x7E, 0x7E
Control, bias estimation period
Control, global commands
Reserved
Identification, firmware revision
Identification, date code, day and month
Identification, date code, year
Identification, device number
Identification, serial number
User Scratch Register 1
User Scratch Register 2
User Scratch Register 3
Output, flash memory write cycle counter, lower word
Output, flash memory write cycle counter, upper word
FIRM_Y
PROD_ID
SERIAL_NUM
USER_SCR_1
USER_SCR_2
USER_SCR_3
FLSHCNT_LOW
FLSHCNT_HIGH
N/A
N/A
N/A
N/A
R
1 See Table 102 for the default value in this register, which is model specific.
Rev. D | Page 18 of 37
Data Sheet
ADIS16475
USER REGISTER DEFINTIONS
Status/Error Flag Indicators (DIAG_STAT)
GYROSCOPE DATA
The gyroscopes in the ADIS16475 measure the angular rate of
rotation around three orthogonal axes (x, y, and z). Figure 36
shows the orientation of each gyroscope axis, along with the
direction of rotation that produces a positive response in each
of their measurements.
Table 9. DIAG_STAT Register Definition
Addresses
Default
Access
Flash Backup
0x02, 0x03
0x0000
R
No
Table 10. DIAG_STAT Bit Assignments
Bits Description
[15:8] Reserved.
Z
ω
Z
7
6
Clock error. A 1 indicates that the internal data sampling
clock (fSM, see Figure 19 and Figure 20) does not
synchronize with the external clock, which only applies
when using scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010, see Table 105). When this error occurs,
adjust the frequency of the clock signal on the SYNC pin
to operate within the appropriate range.
X
Y
ω
ω
X
Y
PIN K1
PIN A8
Memory failure. A 1 indicates a failure in the flash memory
test (Register GLOB_CMD, Bit 4, see Table 113), which
involves a comparison between a cyclic redundancy
check (CRC) calculation of the present flash memory and
a CRC calculation from the same memory locations at
the time of initial programming (during the production
process). If this error occurs, repeat the same test. If this
error persists, replace the ADIS16475 device.
Figure 36. Gyroscope Axis and Polarity Assignments
Each gyroscope has two output data registers. Figure 37 shows
how these two registers combine to support a 32-bit, twos
complement data format for the x-axis gyroscope measurements.
This format also applies to the y- and z-axes.
Additional information on the precision and resolution of the
accelerometers can be found in the Digital Resolution of
Gyroscopes and Accelerometers section of this data sheet.
5
Sensor failure. A 1 indicates failure of at least one sensor,
at the conclusion of the self test (Register GLOB_CMD,
Bit 2, see Table 113). If this error occurs, repeat the same
test. If this error persists, replace the ADIS16475. Motion
during the execution of this test can cause a false failure.
X_GYRO_OUT
X_GYRO_LOW
BIT 15
BIT 0 BIT 15
X-AXIS GYROSCOPE DATA
BIT 0
4
3
Standby mode. A 1 indicates that the voltage across
VDD and GND is <2.8 V, which causes data processing to
stop. When VDD ≥ 2.8 V for 250 ms, the ADIS16475
reinitializes itself and starts producing data again.
Figure 37. Gyroscope Output Data Structure
Gyroscope Measurement Range/Scale Factor
SPI communication error. A 1 indicates that the total
number of SCLK cycles is not equal to an integer
multiple of 16. When this error occurs, repeat the
previous communication sequence. Persistence in this
error may indicate a weakness in the SPI service that the
ADIS16475 is receiving from the system it is supporting.
Table 11 provides the measurement range (±±MAX) and scale
factor (KG) for the gyroscope in each ADIS16475 model.
Table 11. Gyroscope Measurement Range and Scale Factors
Range, ωMAX
(°/sec)
Scale Factor, KG
(LSB/°/sec)
Model
2
1
Flash memory update failure. A 1 indicates that the most
recent flash memory update (Register GLOB_CMD, Bit 3,
see Table 113) failed. If this error occurs, ensure that VDD ≥
3 V and repeat the update attempt. If this error persists,
replace the ADIS16475.
ADIS16475-1
ADIS16475-2
ADIS16475-3
125
500
2000
160
40
10
Gyroscope Data Formatting
Data path overrun. A 1 indicates that one of the data
paths experienced an overrun condition. If this error
occurs, initiate a reset using the RST pin (see Table 5,
Pin F3) or Register GLOB_CMD, Bit 7 (see Table 113). See
the Serial Port Operation section for more details on
conditions that may cause this bit to be set to 1.
Table 12 and Table 13 offer various numerical examples that
demonstrate the format of the rotation rate data in both 16-bit
and 32-bit formats.
Table 12. 16-Bit Gyroscope Data Format Examples
0
Reserved.
Rotation Rate
Decimal Hex
Binary
The DIAG_STAT register (see Table 9 and Table 10) provides
error flags for monitoring the integrity and operation of the
ADIS16475. Reading this register causes all of its bits to return
to 0. The error flags in DIAG_STAT are sticky, meaning that,
when they raise to a 1, they remain there until a read request
clears them. If an error condition persists, the flag (bit)
automatically returns to an alarm value of 1.
+ωMAX
+2/KG
+1/KG
0°/sec
−1/KG
−2/KG
−ωMAX
+20,000
+2
+1
0
−1
−2
−20,000
0x4E20
0100 1110 0010 0000
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1011 0001 1110 0000
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0xB1E0
Rev. D | Page 19 of 37
ADIS16475
Data Sheet
Table 13. 32-Bit Gyroscope Data Format Examples
Z-Axis Gyroscope (Z_GYRO_LOW and Z_GYRO_OUT)
Rotation Rate (°/sec)
Decimal
Hex
Table 22. Z_GYRO_LOW Register Definition
+ωMAX
+1,310,720,000 0x4E200000
Addresses
Default
Access
Flash Backup
+2/(KG × 216)
+1/(KG × 216)
0
+2
+1
0
−1
−2
0x00000002
0x00000001
0x0000000
0xFFFFFFFF
0xFFFFFFFE
0x0C, 0x0D
Not applicable
R
No
Table 23. Z_GYRO_LOW Bit Definitions
−1/(KG × 216)
−2/(KG × 216)
−ωMAX
Bits
Description
[15:0]
Z-axis gyroscope data; additional resolution bits
−1,310,720,000 0xB1E00000
Table 24. Z_GYRO_OUT Register Definition
X-Axis Gyroscope (X_GYRO_LOW and X_GYRO_OUT)
Addresses
Default
Access
Flash Backup
0x0E, 0x0F
Not applicable
R
No
Table 14. X_GYRO_LOW Register Definition
Addresses
Default
Access
Flash Backup
Table 25. Z_GYRO_OUT Bit Definitions
0x04, 0x05
Not applicable
R
No
Bits
Description
[15:0]
Z-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG)
Table 15. X_GYRO_LOW Bit Definitions
Bits
Description
The Z_GYRO_LOW (see Table 22 and Table 23) and Z_GYRO_
OUT (see Table 24 and Table 25) registers contain the gyroscope
data for the z-axis.
[15:0]
X-axis gyroscope data; additional resolution bits
Table 16. X_GYRO_OUT Register Definition
Addresses
Default
Access
Flash Backup
Acceleration Data
0x06, 0x07
Not applicable
R
No
The accelerometers in the ADIS16475 measure both dynamic
and static (response to gravity) acceleration along the same three
orthogonal axes that define the axes of rotation for the gyroscopes
(x, y, and z). Figure 38 shows the orientation of each accelerometer
axis, along with the direction of acceleration that produces a
positive response in each of their measurements.
Table 17. X_GYRO_OUT Bit Definitions
Bits
Description
[15:0]
X-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 1/KG (See Table 11 for KG)
The X_GYRO_LOW (see Table 14 and Table 15) and X_GYRO_
OUT (see Table 16 and Table 17) registers contain the gyroscope
data for the x-axis.
Z
a
z
Y-Axis Gyroscope (Y_GYRO_LOW and Y_GYRO_OUT)
Table 18. Y_GYRO_LOW Register Definition
Addresses
Default
Access
Flash Backup
PIN K1
PIN A8
0x08, 0x09
Not applicable
R
No
Table 19. Y_GYRO_LOW Bit Definitions
X
a
x
a
y
Y
Bits
Description
Figure 38. Accelerometer Axis and Polarity Assignments
[15:0]
Y-axis gyroscope data; additional resolution bits
Each accelerometer has two output data registers. Figure 39
shows how these two registers combine to support a 32-bit,
twos complement data format for the x-axis accelerometer
measurements. This format also applies to the y- and z-axes.
Table 20. Y_GYRO_OUT Register Definition
Addresses
Default
Access
Flash Backup
0x0A, 0x0B
Not applicable
R
No
Table 21. Y_GYRO_OUT Bit Definitions
Additional information on the precision and resolution of the
accelerometers can be found in the Digital Resolution of
Gyroscopes and Accelerometers section of this data sheet.
Bits
Description
[15:0]
Y-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG)
X_ACCL_OUT
X_ACCL_LOW
The Y_GYRO_LOW (see Table 18 and Table 19) and Y_GYRO_
OUT (see Table 20 and Table 21) registers contain the gyroscope
data for the y-axis.
BIT 15
BIT 0 BIT 15
X-AXIS ACCELEROMETER DATA
BIT 0
Figure 39. Accelerometer Output Data Structure
Rev. D | Page 20 of 37
Data Sheet
ADIS16475
Accelerometer Data Formatting
Y-Axis Accelerometer (Y_ACCL_LOW and Y_ACCL_OUT)
Table 26 and Table 27 offer various numerical examples that
demonstrate the format of the linear acceleration data in both
16-bit and 32-bit formats.
Table 32. Y_ACCL_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x14, 0x15
Not applicable
R
No
Table 26. 16-Bit Accelerometer Data Format Examples
Table 33. Y_ACCL_LOW Bit Definitions
Bits Description
Acceleration
Decimal
+32,000
+2
+1
0
−1
−2
−32,000
Hex
Binary
+8 g
0x7D00 0111 1101 0000 0000
[15:0] Y-axis accelerometer data; additional resolution bits
+0.5 mg
+0.25 mg
0 mg
−0.25 mg
−0.5 mg
−8 g
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0x8300
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1000 0011 0000 0000
Table 34. Y_ACCL_OUT Register Definition
Addresses Default
Access
Flash Backup
0x16, 0x17 Not applicable
R
No
Table 35. Y_ACCL_OUT Bit Definitions
Bits Description
Table 27. 32-Bit Accelerometer Data Format Examples
[15:0] Y-axis accelerometer data, high word; twos
Acceleration
Decimal
Hex
complement, 8 g range; 0 g = 0x0000, 1 LSB = 0.25 mg
+8 g
+2,097,152,000
+2
+1
0
−1
−2
0x7D000000
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0x83000000
The Y_ACCL_LOW (see Table 32 and Table 33) and
Y_ACCL_ OUT (see Table 34 and Table 35) registers contain
the accelerometer data for the y-axis.
+0.25/215 mg
+0.25/216 mg
0
−0.25/216 mg
−0.25/215 mg
−8 g
Z-Axis Accelerometer (Z_ACCL_LOW and Z_ACCL_OUT)
Table 36. Z_ACCL_LOW Register Definition
−2,097,152,000
Addresses
Default
Access
Flash Backup
X-Axis Accelerometer (X_ACCL_LOW and X_ACCL_OUT)
0x18, 0x19
Not applicable
R
No
Table 28. X_ACCL_LOW Register Definition
Table 37. Z_ACCL_LOW Bit Definitions
Bits Description
Addresses
Default
Access
Flash Backup
0x10, 0x11
Not applicable
R
No
[15:0] Z-axis accelerometer data; additional resolution bits
Table 29. X_ACCL_LOW Bit Definitions
Bits Description
Table 38. Z_ACCL_OUT Register Definition
Addresses
Default
Access
Flash Backup
[15:0] X-axis accelerometer data; additional resolution bits
0x1A, 0x1B
Not applicable
R
No
Table 30. X_ACCL_OUT Register Definition
Table 39. Z_ACCL_OUT Bit Definitions
Bits Description
[15:0] Z-axis accelerometer data, high word; twos
Addresses
Default
Access
Flash Backup
0x12, 0x13
Not applicable
R
No
complement, 8 g range; 0 g = 0x0000, 1 LSB = 0.25 mg
Table 31. X_ACCL_OUT Bit Definitions
Bits Description
The Z_ACCL_LOW (see Table 36 and Table 37) and Z_ACCL_
OUT (see Table 38 and Table 39) registers contain the
accelerometer data for the z-axis.
[15:0] X-axis accelerometer data, high word; twos
complement, 8 g range; 0 g = 0x0000, 1 LSB = 0.25 mg
The X_ACCL_LOW (see Table 28 and Table 29) and X_ACCL_
OUT (see Table 30 and Table 31) registers contain the
accelerometer data for the x-axis.
Rev. D | Page 21 of 37
ADIS16475
Data Sheet
Internal Temperature (TEMP_OUT)
Data Update Counter (DATA_CNTR)
Table 40. TEMP_OUT Register Definition
Table 45. DATA_CNTR Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x1C, 0x1D
Not applicable
R
No
0x22, 0x23
Not applicable
R
No
Table 41. TEMP_OUT Bit Definitions
Table 46. DATA_CNTR Bit Definitions
Bits
Description
Bits
Description
[15:0]
Temperature data; twos complement, 1 LSB = 0.1°C, 0°C
= 0x0000
[15:0]
Data update counter, offset binary format
When the ADIS16475 goes through its power-on sequence or
when it recovers from a reset command, DATA_CNTR (see
Table 45 and Table 46) starts with a value of 0x0000 and
increments every time new data loads into the output registers.
When the DATA_CNTR value reaches 0xFFFF, the next data
update causes it to wrap back around to 0x0000, where it
continues to increment every time new data loads into the
output registers.
The TEMP_OUT register (see Table 40 and Table 41) provides
a coarse measurement of the temperature inside of the ADIS16475.
This data is most useful for monitoring relative changes in the
thermal environment.
Table 42. TEMP_OUT Data Format Examples
Temperature (°C)
Decimal Hex
Binary
+105
+25
+0.2
+0.1
+0
+0.1
+0.2
−40
+1050
+250
+2
+1
0
−1
−2
−400
0x041A 0000 0100 0001 1010
0x00FA 0000 0000 1111 1010
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0xFE70 1111 1110 0111 0000
DELTA ANGLES
In addition to the angular rate of rotation (gyroscope)
measurements around each axis (x, y, and z), the ADIS16475 also
provides delta angle measurements that represent a calculation
of angular displacement between each sample update.
Z
Δθ
Z
Time Stamp (TIME_STAMP)
Table 43. TIME_STAMP Register Definition
X
Addresses
Default
Access
Flash Backup
Y
0x1E, 0x1F
Not applicable
R
No
Δθ
Δθ
X
Y
PIN K1
PIN A8
Table 44. TIME_STAMP Bit Definitions
Figure 40. Delta Angle Axis and Polarity Assignments
Bits
Description
[15:0]
Time from the last pulse on the SYNC pin; offset binary
format, 1 LSB = 49.02 µs
The delta angle outputs represent an integration of the gyroscope
measurements and use the following formula for all three axes (x-
axis displayed):
The TIME_STAMP register (see Table 43 and Table 44) works
in conjunction with scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010, see Table 105). The 16-bit number in TIME_
STAMP contains the time associated with the last sample in
each data update relative to the most recent edge of the clock
signal in the SYNC pin. For example, when the value in the
UP_SCALE register (see Table 107) represents a scale factor of
20, DEC_RATE = 0, and the external SYNC rate = 100 Hz, the
following time stamp sequence results: 0 LSB, 10 LSB, 21 LSB,
31 LSB, 41 LSB, 51 LSB, 61 LSB, 72 LSB, …, 194 LSB for the 20th
sample, which translates to 0 µs, 490 µs, …, 9510 µs, the time
from the first SYNC edge.
D − 1
1
∆θx, nD
=
×
(
ωx, nD+d + ωx, nD+d −1
)
∑
2× fS
d =0
where:
D is the decimation rate (DEC_RATE + 1, see Table 109).
fS is the sample rate.
d is the incremental variable in the summation formula.
ωX is the x-axis rate of rotation (gyroscope).
n is the sample time, prior to the decimation filter.
When using the internal sample clock, fS is equal to a nominal
rate of 2000 SPS. For better precision in this measurement,
measure the internal sample rate (fS) using the data ready signal
on the DR pin (DEC_RATE = 0x0000, see Table 108), divide
each delta angle result (from the delta angle output registers) by
the data ready frequency, and multiply it by 2000. Each axis of
the delta angle measurements has two output data registers.
Figure 41 shows how these two registers combine to support a
Rev. D | Page 22 of 37
Data Sheet
ADIS16475
32-bit, twos complement data format for the x-axis delta angle
measurements. This format also applies to the y- and z-axes.
Table 55. Y_DELTANG_OUT Bit Definitions
Bits Description
[15:0] Y-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 47 for ΔθMAX
X_DELTANG_OUT
X_DELTANG_LOW
BIT 0 BIT 15
X-AXIS DELTA ANGLE DATA
)
BIT 15
BIT 0
The Y_DELTANG_LOW (see Table 52 and Table 53) and
Y_DELTANG_OUT (see Table 54 and Table 55) registers
contain the delta angle data for the y-axis.
Figure 41. Delta Angle Output Data Structure
Delta Angle Measurement Range
Z-Axis Delta Angle (Z_DELTANG_LOW and
Z_DELTANG_OUT)
Table 47 shows the measurement range and scale factor for
each ADIS16475 model.
Table 56. Z_DELTANG_LOW Register Definitions
Addresses
Default
Access
Flash Backup
Table 47. Delta Angle Measurement Range and Scale Factor
0x2C, 0x2D
Not applicable
R
No
Model
Measurement Range, ΔΘMAX (°)
ADIS16475-1BMLZ
ADIS16475-2BMLZ
ADIS16475-3BMLZ
360
720
2160
Table 57. Z_DELTANG_LOW Bit Definitions
Bits
Description
[15:0]
Z-axis delta angle data; low word
X-Axis Delta Angle (X_DELTANG_LOW and
X_DELTANG_OUT)
Table 58. Z_DELTANG_OUT Register Definitions
Addresses
Default
Access
Flash Backup
Table 48. X_DELTANG_LOW Register Definitions
0x2E, 0x2F
Not applicable
R
No
Addresses
Default
Access
Flash Backup
Table 59. Z_DELTANG_OUT Bit Definitions
Bits Description
[15:0] Z-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 47 for ΔθMAX
0x24, 0x25
Not applicable
R
No
Table 49. X_DELTANG_LOW Bit Definitions
Bits
Description
)
[15:0]
X-axis delta angle data; low word
The Z_DELTANG_LOW (see Table 56 and Table 57) and
Z_DELTANG_OUT (see Table 58 and Table 59) registers
contain the delta angle data for the z-axis.
Table 50. X_DELTANG_OUT Register Definitions
Addresses
Default
Access
Flash Backup
0x26, 0x27
Not applicable
R
No
Delta Angle Resolution
Table 60 and Table 61 show various numerical examples that
demonstrate the format of the delta angle data in both 16-bit
and 32-bit formats.
Table 51. X_DELTANG_OUT Bit Definitions
Bits Description
[15:0] X-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 47 for ΔθMAX
)
Table 60. 16-Bit Delta Angle Data Format Examples
The X_DELTANG_LOW (see Table 48 and Table 49) and
X_DELTANG_OUT (see Table 50 and Table 51) registers
contain the delta angle data for the x-axis.
Delta Angle (°)
ΔθMAX × (215−1)/215 +32,767
Decimal Hex
Binary
0x7FFF 0111 1111 1110 1111
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0x8000 1000 0000 0000 0000
+ΔθMAX/214
+ΔθMAX/215
0
−ΔθMAX/215
−ΔθMAX/214
−ΔθMAX
+2
+1
0
−1
−2
−32,768
Y-Axis Delta Angle (Y_DELTANG_LOW and
Y_DELTANG_OUT)
Table 52. Y_DELTANG_LOW Register Definitions
Addresses
Default
Access
Flash Backup
0x28, 0x29
Not applicable
R
No
Table 61. 32-Bit Delta Angle Data Format Examples
Table 53. Y_DELTANG_LOW Bit Definitions
Delta Angle (°)
+ΔθMAX × (231 − 1)/231
+ΔθMAX/230
+ΔθMAX/231
0
−ΔθMAX/231
−ΔθMAX/230
−ΔθMAX
Decimal
Hex
Bits
Description
+2,147,483,647 0x7FFFFFFF
[15:0]
Y-axis delta angle data; low word
+2
+1
0
−1
−2
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
Table 54. Y_DELTANG_OUT Register Definitions
Addresses
Default
Access
Flash Backup
0x2A, 0x2B
Not applicable
R
No
−2,147,483,648 0x80000000
Rev. D | Page 23 of 37
ADIS16475
Data Sheet
Table 63. X_DELTVEL_LOW Bit Definitions
DELTA VELOCITY
Bits
Description
In addition to the linear acceleration measurements along each
axis (x, y, and z), the ADIS16475 also provides delta velocity
measurements that represent a calculation of linear velocity
change between each sample update.
[15:0]
X-axis delta velocity data; additional resolution bits
Table 64. X_DELTVEL_OUT Register Definition
Addresses
Default
Access
Flash Backup
Z
0x32, 0x33
Not applicable
R
No
ΔV
Z
Table 65. X_DELTVEL_OUT Bit Definitions
Bits
Description
[15:0]
X-axis delta velocity data; twos complement,
100 m/sec range, 0 m/sec = 0x0000;
1 LSB = 100 m/sec ÷ 215 = ~0.003052 m/sec
PIN K1
PIN A8
The X_DELTVEL_LOW (see Table 62 and Table 63) and
X_DELTVEL_OUT (see Table 64 and Table 65) registers
contain the delta velocity data for the x-axis.
ΔV
ΔV
Y
X
X
Y
Figure 42. Delta Velocity Axis and Polarity Assignments
Y-Axis Delta Velocity (Y_DELTVEL_LOW and
Y_DELTVEL_OUT)
The delta velocity outputs represent an integration of the
acceleration measurements and use the following formula for
all three axes (x-axis displayed):
Table 66. Y_DELTVEL_LOW Register Definition
Addresses
Default
Access
Flash Backup
D−1
1
0x34, 0x35
Not applicable
R
No
∆Vx, nD
=
×
(
a
x, nD+d +ax, nD+d −1
)
∑
2× fS
d =0
Table 67. Y_DELTVEL_LOW Bit Definitions
where:
x is the x-axis.
Bits
Description
[15:0]
Y-axis delta velocity data; additional resolution bits
n is the sample time, prior to the decimation filter.
D is the decimation rate (DEC_RATE + 1, see Table 109).
fS is the sample rate.
d is the incremental variable in the summation formula.
aX is the x-axis acceleration.
Table 68. Y_DELTVEL_OUT Register Definition
Addresses
Default
Access
Flash Backup
0x36, 0x37
Not applicable
R
No
Table 69. Y_DELTVEL_OUT Bit Definitions
Bits Description
When using the internal sample clock, fS is equal to a nominal
rate of 2000 SPS. For better precision in this measurement,
measure the internal sample rate (fS) using the data ready signal
on the DR pin (DEC_RATE = 0x0000, see Table 108), divide
each delta angle result (from the delta angle output registers) by
the data ready frequency, and multiply it by 2000. Each axis of
the delta velocity measurements has two output data registers.
Figure 43 shows how these two registers combine to support
32-bit, twos complement data format for the delta velocity
measurements along the x-axis. This format also applies to the
y- and z-axes.
[15:0] Y-axis delta velocity data; twos complement,
100 m/sec range, 0 m/sec = 0x0000;
1 LSB = 100 m/sec ÷ 215 = ~0.003052 m/sec
The Y_DELTVEL_LOW (see Table 66 and Table 67) and
Y_DELTVEL_OUT (see Table 68 and Table 69) registers
contain the delta velocity data for the y-axis.
Z-Axis Delta Velocity (Z_DELTVEL_LOW and
Z_DELTVEL_OUT)
Table 70. Z_DELTVEL_LOW Register Definition
X_ DELTVEL_OUT
BIT 0 BIT 15
X-AXIS DELTA VELOCITY DATA
X_ DELTVEL_LOW
Addresses
Default
Access
Flash Backup
BIT 15
BIT 0
0x38, 0x39
Not applicable
R
No
Table 71. Z_DELTVEL_LOW Bit Definitions
Figure 43. Delta Angle Output Data Structure
Bits
Description
X-Axis Delta Velocity (X_DELTVEL_LOW and
X_DELTVEL_OUT)
[15:0]
Z-axis delta velocity data; additional resolution bits
Table 72. Z_DELTVEL_OUT Register Definition
Table 62. X_DELTVEL_LOW Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x3A, 0x3B
Not applicable
R
No
0x30, 0x31
Not applicable
R
No
Rev. D | Page 24 of 37
Data Sheet
ADIS16475
Table 73. Z_DELTVEL_OUT Bit Definitions
Table 77. XG_BIAS_LOW Bit Definitions
Bits
Description
Bits
Description
[15:0] Z-axis delta velocity data; twos complement,
100 m/sec range, 0 m/sec = 0x0000;
[15:0]
X-axis gyroscope offset correction; lower word
1 LSB = 100 m/sec ÷ 215 = ~0.003052 m/sec
Table 78. XG_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
The Z_DELTVEL_LOW (see Table 70 and Table 71) and
Z_DELTVEL_OUT (see Table 72 and Table 73) registers
contain the delta velocity data for the z-axis.
0x42, 0x43
0x0000
R/W
Yes
Table 79. XG_BIAS_HIGH Bit Definitions
Bits Description
Delta Velocity Resolution
[15:0] X-axis gyroscope offset correction factor, upper word
Table 74 and Table 75 offer various numerical examples that
demonstrate the format of the delta velocity data in both 16-bit
and 32-bit formats.
The XG_BIAS_LOW (see Table 76 and Table 77) and XG_BIAS_
HIGH (see Table 78 and Table 79) registers combine to allow
users to adjust the bias of the x-axis gyroscopes. The data format
examples in Table 12 also apply to the XG_BIAS_HIGH register,
and the data format examples in Table 13 apply to the 32-bit
combination of the XG_BIAS_LOW and XG_BIAS_HIGH
registers. See Figure 44 for an illustration of how these two
registers combine and influence the x-axis gyroscope
measurements.
Table 74. 16-Bit Delta Velocity Data Format Examples
Velocity (m/sec)
Decimal Hex
Binary
+100 × (215 − 1)/215 +32,767
0x7FFF 0111 1111 1111 1111
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0x8000 1000 0000 0000 0000
+100/214
+100/215
0
+2
+1
0
−100/215
−100/214
−100
−1
−2
−32,768
FACTORY
X-AXIS
GYRO
CALIBRATION
AND
X_GYRO_OUT X_GYRO_LOW
FILTERING
Table 75. 32-Bit Delta Velocity Data Format Examples
XG_BIAS_HIGH XG_BIAS_LOW
Velocity (m/sec)
+100 × (231 − 1)/231
+100/230
+100/231
0
−100/231
−100/230
−100
Decimal
Hex
Figure 44. User Calibration Signal Path, Gyroscopes
+2,147,483,647
+2
+1
0
−1
−2
0x7FFFFFFF
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0x80000000
Calibration, Gyroscope Bias (YG_BIAS_LOW and
YG_BIAS_HIGH)
Table 80. YG_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x44, 0x45
0x0000
R/W
Yes
+2,147,483,648
Table 81. YG_BIAS_LOW Bit Definitions
Bits Description
CALIBRATION
[15:0] Y-axis gyroscope offset correction; lower word
The signal chain of each inertial sensor (accelerometers and
gyroscopes) includes the application of unique correction
formulas, which are derived from extensive characterization of
bias, sensitivity, alignment, response to linear acceleration
(gyroscopes), and point of percussion (accelerometer location)
over a temperature range of −40°C to +85°C, for each ADIS16475.
These correction formulas are not accessible, but users do have
the opportunity to adjust the bias for each sensor individually
through user accessible registers. These correction factors
follow immediately after the factory derived correction formulas
in the signal chain, which processes at a rate of 2000 Hz when
using the internal sample clock.
Table 82. YG_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
0x46, 0x47
0x0000
R/W
Yes
Table 83. YG_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis gyroscope offset correction factor, upper word
The YG_BIAS_LOW (see Table 80 and Table 81) and YG_BIAS_
HIGH (see Table 82 and Table 83) registers combine to allow
users to adjust the bias of the y-axis gyroscopes. The data format
examples in Table 12 also apply to the YG_BIAS_HIGH register,
and the data format examples in Table 13 apply to the 32-bit
combination of the YG_BIAS_LOW and YG_BIAS_HIGH
registers. These registers influence the y-axis gyroscope
measurements in the same manner that the XG_BIAS_LOW
and XG_BIAS_HIGH registers influence the x-axis gyroscope
measurements (see Figure 44).
Calibration, Gyroscope Bias (XG_BIAS_LOW and
XG_BIAS_HIGH)
Table 76. XG_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x40, 0x41
0x0000
R/W
Yes
Rev. D | Page 25 of 37
ADIS16475
Data Sheet
Calibration, Gyroscope Bias (ZG_BIAS_LOW and
ZG_BIAS_HIGH)
FACTORY
CALIBRATION
AND
X-AXIS
ACCL
X_ACCL_OUT X_ACCL_LOW
FILTERING
Table 84. ZG_BIAS_LOW Register Definition
XA_BIAS_HIGH XA_BIAS_LOW
Addresses
Default
Access
Flash Backup
0x48, 0x49
0x0000
R/W
Yes
Figure 45. User Calibration Signal Path, Accelerometers
Table 85. ZG_BIAS_LOW Bit Definitions
Bits Description
Calibration, Accelerometer Bias (YA_BIAS_LOW and
YA_BIAS_HIGH)
[15:0] Z-axis gyroscope offset correction; lower word
Table 92. YA_BIAS_LOW Register Definition
Table 86. ZG_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x50, 0x51
0x0000
R/W
Yes
0x4A, 0x4B
0x0000
R/W
Yes
Table 93. YA_BIAS_LOW Bit Definitions
Table 87. ZG_BIAS_HIGH Bit Definitions
Bits Description
Bits
Description
[15:0]
Y-axis accelerometer offset correction; lower word
[15:0] Z-axis gyroscope offset correction factor, upper word
Table 94. YA_BIAS_HIGH Register Definition
The ZG_BIAS_LOW (see Table 84 and Table 85) and ZG_BIAS_
HIGH (see Table 86 and Table 87) registers combine to allow
users to adjust the bias of the z-axis gyroscopes. The data
format examples in Table 12 also apply to the ZG_BIAS_HIGH
register, and the data format examples in Table 13 apply to the
32-bit combination of the ZG_BIAS_LOW and ZG_BIAS_HIGH
registers. These registers influence the z-axis gyroscope
measurements in the same manner that the XG_BIAS_LOW
and XG_BIAS_HIGH registers influence the x-axis gyroscope
measurements (see Figure 44).
Addresses
Default
Access
Flash Backup
0x52, 0x53
0x0000
R/W
Yes
Table 95. YA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis accelerometer offset correction, upper word
The YA_BIAS_LOW (see Table 92 and Table 93) and
YA_BIAS_HIGH (see Table 94 and Table 95) registers combine to
allow users to adjust the bias of the y-axis accelerometers. The data
format examples in Table 26 also apply to the YA_BIAS_HIGH
register, and the data format examples in Table 27 apply to the 32-
bit combination of the YA_BIAS_LOW and YA_BIAS_HIGH
registers. These registers influence the y-axis accelerometer
measurements in the same manner that the XA_BIAS_LOW and
XA_BIAS_HIGH registers influence the x-axis accelerometer
measurements (see Figure 45).
Calibration, Accelerometer Bias (XA_BIAS_LOW and
XA_BIAS_HIGH)
Table 88. XA_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x4C, 0x4D
0x0000
R/W
Yes
Table 89. XA_BIAS_LOW Bit Definitions
Calibration, Accelerometer Bias (ZA_BIAS_LOW and
ZA_BIAS_HIGH)
Bits
Description
[15:0]
X-axis accelerometer offset correction; lower word
Table 96. ZA_BIAS_LOW Register Definition
Table 90. XA_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x54, 0x55
0x0000
R/W
Yes
0x4E, 0x4F
0x0000
R/W
Yes
Table 97. ZA_BIAS_LOW Bit Definitions
Bits Description
Table 91. XA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Z-axis accelerometer offset correction; lower word
[15:0] X-axis accelerometer offset correction, upper word
Table 98. ZA_BIAS_HIGH Register Definition
The XA_BIAS_LOW (see Table 88 and Table 89) and XA_BIAS_
HIGH (see Table 90 and Table 91) registers combine to allow
users to adjust the bias of the x-axis accelerometers. The data
format examples in Table 26 also apply to the XA_BIAS_HIGH
register and the data format examples in Table 27 apply to the
32-bit combination of the XA_BIAS_LOW and XA_BIAS_HIGH
registers. See Figure 45 for an illustration of how these two registers
combine and influence the x-axis accelerometer measurements.
Addresses
Default
Access
Flash Backup
0x56, 0x57
0x0000
R/W
Yes
Table 99. ZA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Z-axis accelerometer offset correction, upper word
The ZA_BIAS_LOW (see Table 96 and Table 97) and ZA_BIAS_
HIGH (see Table 98 and Table 99) registers combine to allow
users to adjust the bias of the z-axis accelerometers. The data
format examples in Table 26 also apply to the ZA_BIAS_HIGH
Rev. D | Page 26 of 37
Data Sheet
ADIS16475
register and the data format examples in Table 27 apply to the
32-bit combination of the ZA_BIAS_LOW and ZA_BIAS_HIGH
registers. These registers influence the z-axis accelerometer
measurements in the same manner that the XA_BIAS_LOW
and XA_BIAS_HIGH registers influence the x-axis accelerometer
measurements (see Figure 45).
Miscellaneous Control Register (MSC_CTRL)
Table 104. MSC_CTRL Register Definition
Addresses
Default
Access
Flash Backup
0x60, 0x61
0x00C1
R/W
Yes
Table 105. MSC_CTRL Bit Definitions
Bits Description
[15:8] Not used
Filter Control Register (FILT_CTRL)
Table 100. FILT_CTRL Register Definition
7
Linear g compensation for gyroscopes (1 = enabled)
Point of percussion alignment (1 = enabled)
Not used, always set to zero
SYNC function setting
Addresses
Default
Access
Flash Backup
6
0x5C, 0x5D
0x0000
R/W
Yes
5
Table 101. FILT_CTRL Bit Definitions
Bits Description
[15:3] Not used
[2:0]
Filter Size Variable B; number of taps in each stage; N = 2B
[4:2]
111 = reserved (do not use)
110 = reserved (do not use)
101 = pulse sync mode
100 = reserved (do not use)
011 = output sync mode
The FILT_CTRL register (see Table 100 and Table 101)
provides user controls for the Bartlett window FIR filter (see
Figure 22), which contains two cascaded averaging filters. For
example, use the following sequence to set Register
FILT_CTRL, Bits[2:0] = 100, which sets each stage to have 16
taps: 0xCC04 and 0xCD00. Figure 46 provides the frequency
response for several settings in the FILT_CTRL register.
0
010 = scaled sync mode
001 = direct sync mode
000 = internal clock mode (default)
SYNC polarity (input or output)
1 = rising edge triggers sampling
0 = falling edge triggers sampling
DR polarity
1
0
–20
–40
–60
–80
1 = active high when data is valid
0 = active low when data is valid
Point of Percussion
Register MSC_CTRL, Bit 6 (see Table 105) offers an on/off control
for the point of percussion alignment function, which maps the
accelerometer sensors to the corner of the package that is closest to
Pin A1 (see Figure 47). The factory default setting in the MSC_
CTRL register activates this function. To turn this function off
while retaining the rest of the factory default settings in the
MSC_CTRL register, set Register MSC_CTRL, Bit 6 = 0, using
the following command sequence on the DIN pin: 0xE081, then
0xE100.
–100
N = 2
–120
N = 4
N = 16
N = 64
–140
0.001
0.01
FREQUENCY (f/fS
0.1
1
Figure 46. Bartlett Window, FIR Filter Frequency Response
(Phase Delay = N Samples)
Range Identifier (RANG_MDL)
Table 102. RANG_MDL Register Definition
Addresses
Default
Access
Flash Backup
PIN A8
0x5E, 0x5F
Not applicable
R
No
PIN A1
POINT OF
PERCUSSION
Table 103. RANG_MDL Bit Definitions
Figure 47. Point of Percussion Reference Point
Bits
Description
Linear Acceleration Effect on Gyroscope Bias
[15:3]
[3:2]
Not used
Register MSC_CTRL, Bit 7 (see Table 105) provides an on/off
control for the linear g compensation in the signal calibration
routines of the gyroscope. The factory default contents in the
MSC_CTRL register enable this compensation. To turn the
compensation off, set Register MSC_CTRL, Bit 7 = 0, using
the following sequence on the DIN pin: 0xE041, 0xEF00.
Gyroscope measurement range
00 = 125°/sec (ADIS16475-1BMLZ)
01 = 500°/sec (ADIS16475-2BMLZ)
10 = reserved
11 = 2000°/sec (ADIS16475-3BMLZ)
Reserved, binary value = 11
[1:0]
Rev. D | Page 27 of 37
ADIS16475
Data Sheet
when the clock frequency (SYNC pin) is less than 1000 Hz, but
with risk of performance degradation, especially when tracking
dynamic inertial conditions (including vibration).
Internal Clock Mode
Register MSC_CTRL, Bits[4:2] (see Table 105), provide five
different configuration options for controlling the clock (fSM
;
see Figure 19 and Figure 20), which controls data acquisition
and processing for the inertial sensors. The default setting for
Register MSC_CTRL, Bits[4:2] is 000 (binary), which places the
ADIS16475 in the internal clock mode. In this mode, an internal
clock controls inertial sensor data acquisition and processing at a
nominal rate of 2000 Hz. In this mode, each accelerometer data
update comes from an average of two data samples (sample rate =
4000 Hz).
Scaled Sync Mode
When Register MSC_CTRL, Bits[4:2] = 010, the ADIS16475
operates in scaled sync mode that supports a frequency range of
1 Hz to 128 Hz for the clock signal on the SYNC pin. This
mode of operation is particularly useful when synchronizing
the data processing with a PPS signal from a global positioning
system (GPS) receiver or with a synchronization signal from a
video processing system. When operating in scaled sync mode,
the frequency of the sample clock is equal to the product of the
external clock scale factor, KECSF (from the UP_SCALE register,
see Table 106 and Table 107), and the frequency of the clock
signal on the SYNC pin.
Output Sync Mode
When Register MSC_CTRL, Bits[4:2] = 011, the ADIS16475
operates in output sync mode, which is the same as internal
clock mode with one exception, the SYNC pin pulses when
the internal processor collects data from the inertial sensors.
Figure 48 provides an example of this signal.
For example, when using a 1 Hz input signal, set UP_SCALE =
0x07D0 (KECSF = 2000 (decimal)) to establish a sample rate of
2000 SPS for the inertial sensors and their signal processing.
Use the following sequence on the DIN pin to configure
UP_SCALE for this scenario: 0xE2D0, then 0xE307.
GYROSCOPE AND
ACCELEROMETER
DATA ACQUISITION
ACCELEROMETER
DATA ACQUISITION
SYNC
Table 106. UP_SCALE Register Definition
250µs
Addresses
Default
Access
Flash Backup
500µs
0x62, 0x63
0x07D0
R/W
Yes
Figure 48. Sync Output Signal, Register MSC_CTRL, Bits[4:2] = 011
Table 107. UP_SCALE Bit Definitions
Direct Sync Mode
Bits
Description
[15:0]
KECSF; binary format
When Register MSC_CTRL, Bits[4:2] = 001, the ADIS16475
operates in direct sync mode. The signal on the SYNC pin
directly controls the sample clock. In this mode, the internal
processor collects gyroscope data samples on the rising edge of
the clock signal (SYNC pin) and it collects accelerometer data
samples on both rising and falling edges of the clock signal. The
internal processor averages both accelerometer samples (from
rising and falling edges of the clock signal) together to produce
a single data sample. When using this mode, the input clock
signal requires a 50% duty cycle. Therefore, when operating the
ADIS16475 in this mode, the clock signal (SYNC pin) must
have a duty cycle of 50% and a frequency that is within the
range of 1900 Hz to 2100 Hz. The ADIS16475 is capable of
operating when the clock frequency (SYNC pin) is less than
1900 Hz, but with risk of performance degradation, especially
when tracking dynamic inertial conditions (including vibration).
Decimation Filter (DEC_RATE)
Table 108. DEC_RATE Register Definition
Addresses
Default
Access
Flash Backup
0x64, 0x65
0x0000
R/W
Yes
Table 109. DEC_RATE Bit Definitions
Bits
Description
[15:11]
[10:0]
Don’t care
Decimation rate, binary format, maximum = 1999
The DEC_RATE register (see Table 108 and Table 109)
provides user control for the averaging decimating filter, which
averages and decimates the gyroscope and accelerometer data; it
also extends the time that the delta angle and the delta velocity
track between each update. When the ADIS16475 operates in
internal clock mode (see Register MSC_CTRL, Bits [4:2], in
Table 105), the nominal output data rate is equal to 2000/
(DEC_RATE + 1). For example, set DEC_RATE = 0x0013 to
reduce the output sample rate to 100 SPS (2000 ÷ 20), using the
following DIN pin sequence: 0xE413, then 0xE500.
Pulse Sync Mode
When operating in pulse sync mode (Register MSC_CTRL,
Bits[4:2] = 101), the internal processor only collects accelerometer
samples on the leading edge of the clock signal, which enables
the use of a narrow pulse width (see Table 2) in the clock signal on
the SYNC pin. Using pulse sync mode also lowers the bandwidth
on the inertial sensors to 370 Hz. When operating in pulse sync
mode, the ADIS16475 provides the best performance when the
frequency of the clock signal (SYNC pin) is within the range of
1000 Hz to 2100 Hz. The ADIS16475 is capable of operating
Rev. D | Page 28 of 37
Data Sheet
ADIS16475
The GLOB_CMD register (see Table 112 and Table 113)
Data Update Rate in External Sync Modes
provides trigger bits for several operations. Write a 1 to the
appropriate bit in GLOB_CMD to start a particular function.
During the execution of these commands, data production
stops, pulsing stops on the DR pin, and the SPI interface does
not respond to requests. Table 1 provides the execution time
for each GLOB_CMD command.
When using the input sync option, in scaled sync mode
(Register MSC_CTRL, Bits[4:2] = 010, see Table 105), the
output data rate is equal to
(fSYNC × KECSF)/(DEC_RATE + 1)
where:
f
SYNC is the frequency of the clock signal on the SYNC pin.
Software Reset
KESCF is the value from the UP_SCALE register (see Table 107).
Use the following DIN sequence to set Register GLOB_CMD,
Bit 7 = 1, which triggers a reset: 0xE880, then 0xE900. This reset
clears all data, and then restarts data sampling and processing.
This function provides a firmware alternative to toggling the
When using direct sync mode and pulse sync mode, KESCF = 1.
Continuous Bias Estimation (NULL_CNFG)
Table 110. NULL_CNFG Register Definition
RST
pin (see Table 5, Pin F3).
Addresses
Default
Access
Flash Backup
Flash Memory Test
0x66, 0x67
0x070A
R/W
Yes
Use the following DIN sequence to set Register GLOB_CMD,
Bit 4 = 1, which tests the flash memory: 0xE810, then 0xE900.
The command performs a CRC computation on the flash memory
(excluding user register locations) and compares it to the original
CRC value, which comes from the factory configuration process.
If the current CRC value does not match the original CRC
value, Register DIAG_STAT, Bit 6 (see Table 10), rises to 1,
indicating a failing result.
Table 111. NULL_CNFG Bit Definitions
Bits Description
[15:14] Not used
13
12
11
10
9
Z-axis accelerometer bias correction enable (1 = enabled)
Y-axis accelerometer bias correction enable (1 = enabled)
X-axis accelerometer bias correction enable (1 = enabled)
Z-axis gyroscope bias correction enable (1 = enabled)
Y-axis gyroscope bias correction enable (1 = enabled)
X-axis gyroscope bias correction enable (1 = enabled)
Not used
Flash Memory Update
8
Use the following DIN sequence to set Register GLOB_CMD,
Bit 3 = 1, which triggers a backup of all user configurable registers
in the flash memory: 0xE808, then 0xE900. Register DIAG_
STAT, Bit 2 (see Table 10), identifies success (0) or failure (1) in
completing this process.
[7:4]
[3:0]
Time base control (TBC), range: 0 to 12 (default = 10);
tB = 2TBC/2000, time base; tA = 64 × tB, average time
The NULL_CNFG register (see Table 110 and Table 111) provides
the configuration controls for the continuous bias estimator (CBE),
which associates with the bias correction update command in
Register GLOB_CMD, Bit 0 (see Table 113). Register NULL_
CNFG, Bits[3:0], establishes the total average time (tA) for the bias
estimates and Register NULL_CNFG, Bits[13:8], provide the
on/off controls for each sensor. The factory default configuration
for the NULL_CNFG register enables the bias null command for
the gyroscopes, disables the bias null command for the
Sensor Self Test
Use the following DIN sequence to set Register GLOB_CMD,
Bit 2 = 1, which triggers the self test routine for the inertial sensors:
0xE804 and 0xE900. The self test routine uses the following steps
to validate the integrity of each inertial sensor:
1. Measure the output on each sensor.
2. Activate an internal stimulus on the mechanical elements of
each sensor to move them in a predictable manner and
create an observable response in the sensors.
accelerometers, and sets the average time to ~32 sec.
Global Commands (GLOB_CMD)
3. Measure the output response on each sensor.
4. Deactivate the internal stimulus on each sensor.
5. Calculate the difference between the sensor measurements
from Step 1 (stimulus is off) and from Step 3 (stimulus is on).
6. Compare the difference with internal pass and fail criteria.
7. Report the pass and fail result to Register DIAG_STAT, Bit 5
(see Table 10).
Table 112. GLOB_CMD Register Definition
Addresses
Default
Access
Flash Backup
0x68, 0x69
Not applicable
W
No
Table 113. GLOB_CMD Bit Definitions
Bits
Description
[15:8]
Not used
Motion during the execution of this test can indicate a false
failure.
7
Software reset
[6:5]
4
3
Not used
Factory Calibration Restore
Flash memory test
Flash memory update
Sensor self test
Use the following DIN sequence to set Register GLOB_CMD,
Bit 1 = 1, to restore the factory default settings for the MSC_
CTRL, DEC_RATE, and FILT_CTRL registers and to clear all
user configurable bias correction settings: 0xE802, then 0xE900.
2
1
0
Factory calibration restore
Bias correction update
Rev. D | Page 29 of 37
ADIS16475
Data Sheet
Executing this command results in writing 0x0000 to the
following registers: XG_BIAS_LOW, XG_BIAS_HIGH,
YG_BIAS_LOW, YG_BIAS_HIGH, ZG_BIAS_LOW,
ZG_BIAS_ HIGH, XA_BIAS_LOW, XA_BIAS_HIGH,
YA_BIAS_LOW, YA_BIAS_HIGH, ZA_BIAS_LOW, and
ZA_BIAS_HIGH.
The FIRM_Y register (see Table 118 and Table 119) contains
the year of the factory configuration date. For example, the
year, 2017, is represented by FIRM_Y = 0x2017.
Product Identification (PROD_ID)
Table 120. PROD_ID Register Definition
Addresses
Default
Access
Flash Backup
Bias Correction Update
0x72, 0x73
0x405B
R
No
Use the following DIN pin sequence to set Register GLOB_CMD,
Bit 0 = 1, to trigger a bias correction, using the correction
factors from the CBE (see Table 111): 0xE801, then 0xE900.
Table 121. PROD_ID Bit Definitions
Bits
Description
Firmware Revision (FIRM_REV)
[15:0]
Product identification = 0x405B
Table 114. FIRM_REV Register Definition
The PROD_ID register (see Table 120 and Table 121) contains
the numerical portion of the device number (16,475). See Figure 32
for an example of how to use a looping read of this register to
validate the integrity of the communication.
Addresses
Default
Access
Flash Backup
0x6C, 0x6D
Not applicable
R
No
Table 115. FIRM_REV Bit Definitions
Serial Number (SERIAL_NUM)
Bits
Description
[15:0]
Firmware revision, binary coded decimal (BCD) format
Table 122. SERIAL_NUM Register Definition
The FIRM_REV register (see Table 114 and Table 115)
provides the firmware revision for the internal firmware. This
register uses a BCD format, where each nibble represents a
digit. For example, if FIRM_REV = 0x0104, the firmware revision
is 1.04.
Addresses
Default
Access
Flash Backup
0x74, 0x75
Not applicable
R
No
Table 123. SERIAL_NUM Bit Definitions
Bits Description
[15:0] Lot specific serial number
Firmware Revision Day and Month (FIRM_DM)
Scratch Registers (USER_SCR_1 to USER_SCR_3)
Table 116. FIRM_DM Register Definition
Addresses
Default
Access
Flash Backup
Table 124. USER_SCR_1 Register Definition
0x6E, 0x6F
Not applicable
R
No
Addresses
Default
Access
Flash Backup
0x76, 0x77
Not applicable
R/W
Yes
Table 117. FIRM_DM Bit Definitions
Bits
Description
Table 125. USER_SCR_1 Bit Definitions
Bits Description
[15:8]
[7:0]
Factory configuration month, BCD format
Factory configuration day, BCD format
[15:0] User defined
The FIRM_DM register (see Table 116 and Table 117)
contains the month and day of the factory configuration date.
Register FIRM_DM, Bits[15:8], contain digits that represent the
month of the factory configuration. For example, November is
the 11th month in a year and is represented by Register
FIRM_DM, Bits[15:8] = 0x11. Register FIRM_DM, Bits[7:0],
contain the day of factory configuration. For example, the 27th
day of the month is represented by Register FIRM_DM,
Bits[7:0] = 0x27.
Table 126. USER_SCR_2 Register Definition
Addresses
Default
Access
Flash Backup
0x78, 0x79
Not applicable
R/W
Yes
Table 127. USER_SCR_2 Bit Definitions
Bits Description
[15:0] User defined
Table 128. USER_SCR_3 Register Definition
Addresses
Default
Access
Flash Backup
Firmware Revision Year (FIRM_Y)
0x7A, 0x7B
Not applicable
R/W
Yes
Table 118. FIRM_Y Register Definition
Table 129. USER_SCR_3 Bit Definitions
Bits Description
[15:0] User defined
Addresses
Default
Access
Flash Backup
0x70, 0x71
Not applicable
R
No
Table 119. FIRM_Y Bit Definitions
Bits
Description
[15:0]
Factory configuration year, BCD format
Rev. D | Page 30 of 37
Data Sheet
ADIS16475
The USER_SCR_1 (see Table 124 and Table 125), USER_SCR_2
(see Table 126 and Table 127), and USER_SCR_3 (see Table 128
and Table 129) registers provide three locations for the user to
store information. For nonvolatile storage, use the manual flash
memory update command (Register GLOB_CMD, Bit 3, see
Table 113), after writing information to these registers.
The FLSHCNT_LOW (see Table 130 and Table 131) and
FLSHCNT_HIGH (see Table 132 and Table 133) registers
combine to provide a 32-bit, binary counter that tracks the
number of flash memory write cycles. In addition to the
number of write cycles, the flash memory has a finite service
lifetime, which depends on the junction temperature. Figure 49
provides guidance for estimating the retention life for the flash
memory at specific junction temperatures. The junction
temperature is approximately 7°C above the case temperature.
Flash Memory Endurance Counter (FLSHCNT_LOW and
FLSHCNT_HIGH)
Table 130. FLSHCNT_LOW Register Definition
Addresses
Default
Access
Flash Backup
600
450
300
0x7C, 0x7D
Not applicable
R
No
Table 131. FLSHCNT_LOW Bit Definitions
Bits Description
[15:0] Flash memory write counter, low word
Table 132. FLSHCNT_HIGH Register Definition
Addresses
Default
Access
Flash Backup
150
0
0x7E, 0x7F
Not applicable
R
No
Table 133. FLSHCNT_HIGH Bit Definitions
Bits Description
[15:0] Flash memory write counter, high word
30
40
55
70
85
100
125
135
150
JUNCTION TEMPERATURE (°C)
Figure 49. Flash Memory Retention
Rev. D | Page 31 of 37
ADIS16475
Data Sheet
APPLICATIONS INFORMATION
ASSEMBLY AND HANDLING TIPS
Package Attributes
PCB Layout Suggestions
Figure 51 shows an example of the pad design and layout for
the ADIS16475 on a PCB. This example uses a solder mask
opening, with a diameter of 0.73 mm, around a metal pad that
has a diameter of 0.56 mm. When using a material for the system
PCB, which has similar thermal expansion properties as the
substrate material of the ADIS16475, the system PCB can also
use the solder mask to define the pads that support attachment
to the balls of the ADIS16475. The coefficient of thermal
expansion (CTE) in the substrate of the ADIS16475 is
approximately 14 ppm/°C.
The ADIS16475 is a multichip module package that has a
44-ball BGA interface. This package has three basic attributes
that influence its handling and assembly to the PCB of the
system: the lid, the substrate, and the BGA pattern. The
material of the lid is a liquid crystal polymer (LCP), and
its nominal thickness is 0.5 mm. The substrate is a laminate
composition that has a nominal thickness of 1.57 mm. The
solder ball material is SAC305, and each ball has a nominal
diameter of 0.75 mm (±0.15 mm). The BGA pattern follows an
8 × 10 array, with 36 unpopulated positions, which simplifies
the escape pattern for the power, ground, and signal traces on
the system PCB.
0.73
(MASK OPENING)
0.56
(COPPER PAD)
Assembly Tips
When developing a process to attach the ADIS16475 to a PCB,
consider the following guidelines and insights:
•
The ADIS16475 is capable of supporting solder reflow
attachment processes, which are in accordance with
J-STD-020E.
1.27
1.27
•
•
Limit device exposure to one pass through the solder
reflow process (no rework).
The hole in the top of the lid (see Figure 50) provides
venting and pressure relief during the assembly process of
the ADIS16475. Keep this hole clear of obstruction while
attaching the ADIS16475 to a PCB.
ALL DIMENSIONS IN MILLIMETERS
Figure 51. Recommend PCB Pattern, Solder Mask Defined Pads
Underfill
Underfill can be a useful technique in managing certain threats
to the integrity of the solder joints of the ADIS16475, including
peeling stress and extended exposure to vibration. When selecting
underfill material and developing an application and curing
process, ensure that the material fills the gap between each surface
(the ADIS16475 substrate and system PCB) and adheres
to both surfaces. The ADIS16475 does not require the use of
underfill materials in applications that do not anticipate exposure
to these types of mechanical stresses and when the CTE of the
system PCB is close to the same value as the CTE of the
substrate of the ADIS16475 (~14 ppm/°C).
OPENING IN
PACKAGE LID
Figure 50. Pressure Relief Hole
•
Use no clean flux to avoid exposing the device to cleaning
solvents, which can penetrate the inside of the ADIS16475
through the hole in the lid and be difficult to remove.
When the assembly process requires the use of liquids that
can reach the hole in the lid, use a temporary seal to
prevent entrapment of those liquids inside the cavity.
Manage moisture exposure prior to the solder reflow
processing, in accordance with J-STD-033, Moisture
Sensitivity Level 5.
Avoid exposing the ADIS16475 to mechanical shock
survivability that exceeds the maximum rating of 2000 g
(see Table 3). In standard PCB processing, high speed
handling equipment and panel separation processes often
present the most risk of introducing harmful levels of
mechanical shock survivability.
Process Validation and Control
These guidelines provide a starting point for developing a process
for attaching the ADIS16475 to a system PCB. Because each
system and situation may present unique requirements for this
attachment process, ensure that the process supports optimal
solder joint integrity, verify that the final system meets all
environmental test requirements, and establish observation and
control strategies for all key process attributes (for example, peak
temperatures, dwell times, and ramp rates).
•
•
Rev. D | Page 32 of 37
Data Sheet
ADIS16475
section and the Accelerometer Data Width (Digital Resolution)
section for more information.
POWER SUPPLY CONSIDERATIONS
The ADIS16475 contains 6 µF of decoupling capacitance across
the VDD and GND pins. When the VDD voltage rises from 0 V
to 3.3 V, the charging current for this capacitor bank imposes
the following current profile (in amperes):
Serial Port SCLK Underrun/Overrun Conditions
The serial port operates in 16-bit segments, and it is critical that
the number of SCLK cycles be equal to an integer multiple of 16
CS
when the
pin is low. Failure to meet this condition causes
dVDD
dt
dVDD
dt
t
( )
IDD
(
t
)
= C
= 6×10−6
×
the serial port controller inside of the ADIS16465 to be unable
to correctly receive and respond to new requests.
where:
DD(t) is the current demand on the VDD pin during the initial
power supply ramp, with respect to time.
C is the internal capacitance across the VDD and GND pins (6 µF).
VDD(t) is the voltage on the VDD pin, with respect to time.
CS
pin is
I
If too many SCLK cycles are received before the
deasserted, the user can recover serial port operation by
CS
asserting , providing 17 rising edges on the SCLK line,
CS
deasserting , and then attempting to correctly read the
PROD_ID (or other read-only) register on the ADIS16475. The
user should repeat these steps up to a maximum of 15 times
until the correct data is read.
For example, if VDD follows a linear ramp from 0 V to 3.3 V,
in 66 µs, the charging current is 300 mA for that timeframe.
The ADIS16475 also contains embedded processing functions
that present transient current demands during initialization or
reset recovery operations. During these processes, the peak
current demand reaches 250 mA and occurs at a time that is
approximately 40 ms after VDD reaches 3.0 V (or ~40 ms
after initiating a reset sequence).
CS
If
user must either power cycle or issue a hard reset (using the
RST
is deasserted before enough SCLK cycles are received, the
pin) to regain SPI port access.
DIGITAL RESOLUTION OF GYROSCOPES AND
ACCELEROMETERS
SERIAL PORT OPERATION
Maximum Throughput
Gyroscope Data Width (Digital Resolution)
The decimation filter (DEC_RATE register, see Table 109) and
Bartlett window filter (FILT_CTRL register, see Table 101)
have direct influence over the total number of bits in the output
data registers, which contain relevant information. When using
the factory default settings (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) for these filters, the gyroscope data width is 16 bits, which
means that application processors can acquire all relevant
information through the X_GYRO_OUT, Y_GYRO_OUT, and
Z_GYRO_OUT registers.
When operating with the maximum output data (DEC_RATE =
0x0000, as described in Table 109), the maximum SCLK rate
(defined in Table 2), and minimum stall time, the SPI port can
support up to 12, 16-bit register reads in between each pulse of
the data ready signal. Attempting to read more than 12 registers
can result in a datapath overrun error in the DIAG_STAT
register (see Table 10). The serial port stall time (tSTALL) to meet
these requirements must be no more than 10% greater than the
minimum specification for tSTALL in Table 2.
The X_GYRO_LOW, Y_GYRO_LOW, and Z_GYRO_LOW
registers capture the bit growth that comes from each
The number of allowable registers reads between each pulse on
the data ready line increases proportionally with the decimation
rate (set by the DEC_RATE register, see Table 109). For example,
when the decimation rate equals 3 (DEC_RATE = 0x0002), the
SPI is able to support up to 36 register reads, assuming
maximum SCLK rate and minimum stall times in the protocol.
Decreasing the SCLK rate and increasing the stall time lowers
the total number of register reads supported by the ADIS16465
before a datapath overrun error occurs.
accumulation operation in the decimation and Bartlett window
filters. When using these filters (DEC_RATE ≠ 0x0000 and/or
FILT_CTRL ≠ 0x0000), the data width increases by one bit
every time the number of summations (in a filter stage) increases
by a factor of two. For example, when DEC_RATE = 0x0007, the
decimation filter adds eight (7 + 1 = 8, see Table 109) successive
samples together, which causes the data width to increase by 3
bits (log28 = 3). When FILT_CTRL = 0x0002, both stages in the
Bartlett window filter use four (22 = 4, see Table 101) summation
operations, which increases the data width by two bits (log24 =
2). When using both DEC_RATE = 0x0007 and FILT_CTRL =
0x0002, the total bit growth is 7 bits, which increases the overall
data width to 23 bits.
This limitation of reading 12, 16-bit registers does not impact
the ability of the user to access the full precision of the
gyroscopes and accelerometers if the factory default settings of
DEC_RATE = 0x0000 and FILT_CTRL = 0x0000 are used. In
this case, the data width for the gyroscope and accelerometer
data is 16 bits, and application processors can acquire all
relevant information through the X_GYRO_OUT,
Accelerometer Data Width (Digital Resolution)
Y_GYRO_OUT, Z_GYRO_OUT, X_ACCEL_OUT,
The decimation filter (DEC_RATE register, see Table 109) and
Bartlett window filter (FILT_CTRL register, see Table 101)
have direct influence over the total number of bits in the output
data registers, which contain relevant information. When using
the factory default settings (DEC_RATE = 0x0000, FILT_CTRL
Y_ACCEL_OUT, and Z_ACCEL_OUT registers. Thirty-two
bit reads of the sensor data do not provide additional precision
in this case. See the Gyroscope Data Width (Digital Resolution)
Rev. D | Page 33 of 37
ADIS16475
Data Sheet
= 0x0000) for these filters, the accelerometer data width is 20 bits.
The X_ACCL_OUT, Y_ACCL_OUT, and Z_ACCL_OUT
registers contain the most significant 16 bits of this data, while
the remaining (least significant) bits are in the upper 4 bits of
the X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW
registers. Since the total noise (0.6 mg rms, see Table 1) in the
accelerometer data (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) is greater than the 16-bit quantization noise (0.25 mg ÷
120.5 = 0.072 mg), application processors can acquire all relevant
information through the X_ACCL_OUT, Y_ACCL_OUT, and
Z_ACCL_OUT registers. This enables applications to preserve
optimal performance, while using the burst read (see Figure 31),
which only provides 16-bit data for the accelerometers.
EVALUATION TOOLS
Breakout Boards
The ADIS16475 has three difference breakout boards, which
provide a simple way to connect an ADIS16475 model and an
existing embedded processor platform. Table 134 provides a list
of the model numbers for each breakout board, along with the
ADIS16475 model that is on each breakout board.
Table 134. Breakout Board Models
Breakout Board Model
ADIS16475-1/PCBZ
ADIS16475-2/PCBZ
ADIS16475-3/PCBZ
ADIS16475 Model
ADIS16475-1BMLZ
ADIS16475-2BMLZ
ADIS16475-3BMLZ
The X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW
registers also capture the bit growth that comes from each
accumulation operation in the decimation and Bartlett window
filters. When using these filters (DEC_RATE ≠ 0x0000 and/or
FILT_CTRL ≠ 0x0000), the data width increases by one bit
every time the number of summations (in a filter stage) increases
by a factor of two. For example, when DEC_RATE = 0x0001, the
decimation filter adds two (1 + 1 = 2, see Table 109) successive
samples together, which causes the data width to increase by 1 bit
(log22 = 1). When FILT_CTRL = 0x0001, both stages in the
Bartlett window filter add two (21 = 2, see Table 101) successive
samples together, which increases the data width by 1 bit (log22
= 1) as well. When using both DEC_RATE = 0x0001 and
FILT_CTRL = 0x0001, the total bit growth is 3 bits, which
increases the overall data width to 23 bits.
The electrical interface (J1) on each breakout board comes from
a dual row, 2 mm pitch, 16-pin interface, which supports standard
ribbon cabling (1 mm pitch). Table 135 provides the J1 pin assign-
ments, which support direct connection with an embedded
processor board using standard ribbon cables. Although each
case may present its own set of sensitivities (such as electromag-
netic interference (EMI)), these boards can typically support
reliable communication over ribbon cables up to 20 cm in length.
Table 135. J1 Pin Assignments, Breakout Board
J1 Pin Number
Signal
Function
1
RST
Reset
2
3
SCLK
CS
SPI
SPI
4
5
6
DOUT
NC
DIN
SPI
No connect
SPI
7
8
9
10
11
12
13
14
15
16
GND
GND
GND
VDD
VDD
VDD
DR
SYNC
NC
NC
Ground
Ground
Ground
Power, 3.3 V
Power, 3.3 V
Power, 3.3 V
Data ready
Input clock
No connect
No connect
Figure 52 provides a top level view of the breakout board,
including dimensional locations for all the key mechanical features,
such as the mounting holes and the 16-pin header. Figure 53
provides an electrical schematic for this breakout board. For
additional information, refer to the ADIS1647x/PCB Wiki
Guide.
Rev. D | Page 34 of 37
Data Sheet
ADIS16475
30.07mm
ADIS1647X/PCB
BREAKOUT BOARD
08-045113rA
5.125mm
J1
16.99mm
*
33.25mm
16.26mm
5.125mm
6.03mm
3.625mm
Figure 52. Top Level View of the Breakout Board
VDD
DUT1
C7
K6
VDD
J5
VDD
D6
VDD
H1
VDD
J4
VDD
VDD
D3
C3
GND
GND
CS
GND
NC
F3
E3
RST
DIN
RST
VDD
VDD
VDD
F6
H6
H3
GND
SCLK
SCLK
DR
J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RST
CS
G6
DIN
DOUT
DOUT
SYNC
SCLK
DOUT
G3
CS
J6
J3
DR
SYNC
DIN
ADIS16475AMLZ
K8
K3
K1
J7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
A1
GND
GND
A2
GND
A3
J2
GND
A4
H8
G7
G2
F8
F1
E7
E6
E2
C6
C2
GND
A5
DR
NC
GND
A6
SYNC
GND
A7
GND
A8
GND
B8
HIROSE
A3-16-PA-2SV(71)
GND
B3
GND
GND
B4
GND
B5
GND
B6
GND
GND
Figure 53. Breakout Board Schematic
Rev. D | Page 35 of 37
ADIS16475
Data Sheet
EVAL-ADIS2 provides a simple, functional test platform that
allows users to configure and collect data from the ADIS16475
models.
PC-Based Evaluation, EVAL-ADIS2
In addition to supporting quick prototype connections between
the ADIS16475 and an embedded processing system, J1 on the
breakout boards also connects directly to J1 on the EVAL-ADIS2
evaluation system. When used in conjunction with the IMU
Evaluation Software for the EVAL-ADISX Platforms, the
TRAY DRAWING
The ADIS16475 parts are shipped in the tray shown in Figure 54.
322.60 REF
315.00
112.25
112.00
111.75
92.10
135.90
16.00
BSC
TOP VIEW
12.70
DETAIL A
11.95 BSC
22.00 BSC
14.50 BSC
DETAIL C
272.05
271.80
271.55
0.76
R 4.75
DETAIL C
21.40
DETAIL B
SIDE VIEW
3.80
1.30
2.54
2.50
17.90
34.30
25.40
2.00
255.30
30°
±
1°
3.50
B
A
DETAIL B
15.43
15.35
15.27
11.43
11.35
11.27
A
11.10
NOTES:
1. MATERIAL IS MPPO.
2. TOLERANCES ARE x.x = ± 0.25
7.90
x.xx = ± 0.13
UNLESS OTHERWISE SPECITIED.
3. ESD
–
SURFACE RESISTIVITY
SECTION A-A
SECTION B-B
105 TO 1011 Ω/SQ.
C 3.00 × 0.45°
DETAIL A
B
Figure 54. Drawing of Shipping Tray
Rev. D | Page 36 of 37
Data Sheet
ADIS16475
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
11.25
11.00
10.75
1.055
BSC
1.270
BSC
A1 BALL
CORNER INDICATOR
1.785
BSC
1.270
BSC
15.25
15.00
14.75
0.900
Ø 0.750
0.600
TOP VIEW
END VIEW
BOTTOM VIEW
11.350
11.000
*10.475
0.90
MAX
*Including Lable
Thickness
SEATING
PLANE
Figure 55. 44-Ball Ball Grid Array Module [BGA]
(ML-44-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADIS16475-1BMLZ
ADIS16475-2BMLZ
ADIS16475-3BMLZ
ADIS16475-1/PCBZ
ADIS16475-2/PCBZ
ADIS16475-3/PCBZ
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
44-Ball Ball Grid Array Module [BGA]
44-Ball Ball Grid Array Module [BGA]
44-Ball Ball Grid Array Module [BGA]
ADIS16475-1 Breakout Board
ADIS16475-2 Breakout Board
ADIS16475-3 Breakout Board
ML-44-1
ML-44-1
ML-44-1
1 Z = RoHS Compliant Part.
©2017–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15436-4/20(D)
www.analog.com/ADIS16475
Rev. D | Page 37 of 37
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