ADIS16000_技术文档

Digital MEMS Vibration Sensor

w/ Embedded RF Transceiver

Preliminary Technical Data

ADIS16000/ADIS16229

FEATURES

GENERAL DESCRIPTION

Wireless vibration system, 862MHz – 928MHz

Clear Channel Assessment/Packet collision avoidance

Error Detection and Correction in RF protocol

Programmable RF Output power

Gateway node (ADIS16000)

SPI to RF function

The ADIS16000 and ADIS16229 enable creation of a simple

wireless vibration-sensing network for a wide variety of

industrial-equipment applications. . The ADIS16000 provides

the gateway function, which manages the network, while the

ADIS16229 provides the remote sensing function.

The ADIS16229 iSesnor is a complete wireless vibration sensor

node that combines dual-axis acceleration sensing with advanced

time domain and frequency domain signal processing. Time

domain signal processing includes a programmable decimation

filter and selectable windowing function. Frequency domain

processing includes a 512-point, real-valued FFT, FFT

magnitude averaging, and programmable spectral alarms. The

FFT record storage system offers users the ability to track

changes over time and capture FFTs with multiple decimation

filter settings.

Manage up to 6 sensor nodes

Sensor Node (ADIS16229)

Dual-axis, 18g MEMS accelerometer

5.5kHz Resonant frequency

Digital range settings: 0 g to 1 g/5 g/10 g/20 g

Sample rate up to 20kSPS

Programmable wake-up capture, update cycle times

FFT, 512-point, real valued

Rectangular, Hanning, flat top window options

Programmable decimation filter, 11 rate settings

Multi-record capture for selected filter settings

Manual capture mode for time domain data collection

Programmable FFT averaging: up to 255 averages

Record Storage: 14 FFT records on all three axes (x, y)

Programmable alarms, 6 spectral bands, 2 levels

Adjustable response delay to reduce false alarms

Internal self-test with status flags

Digital temperature and power supply measurements

Identification registers: serial number, device ID, user ID

47mm x 38mm PCB package with SMA antenna interface

Single-supply operation: 3.0 V to 3.6 V

Operating temperature range: −40°C to +85°C

The ADIS16229’s dynamic range, bandwidth, sample rate and

noise performance are well suited for a wide variety of machine

health and production equipment monitoring systems. This

devices also provides a number of wireless configuration

parameters enable a wide level of flexibility in managing the

trade-off between battery life and communication frequency.

The ADIS16000 SPI interface provides simple connectivity with

most embedded processor platforms and the SMA connector

interface enables the use of many different antennas. This

module supports up to six ADIS16229 devices at one time,

using a proprietary wireless protocol.

Both ADIS16000 and ADIS16229 modules are in in

APPLICATIONS

47.0x37.6x22.6mm PCB structures, have an SMA connector for

simple antenna connection, have two mounting holes for simple

installation and support operation over a temperature range of -

40°C to +85°C. The ADIS16000 also includes a standard 1mm,

14-pin connector for connecting to an embedded processor

system. The ADIS16229 provides a lead structure that enables

simple connection with standard batteries.

Vibration analysis

Condition monitoring

Machine health

Instrumentation, diagnostics

Safety shutoff sensing

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Rev. PrA

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADIS16000/ADIS16229

Preliminary Technical Data

TABLE OF CONTENTS

Features .............................................................................................. 1

Alarm Definition........................................................................ 23

Alarm Indicator Signals............................................................. 24

Alarm Flags and Conditions..................................................... 24

Alarm Status................................................................................ 25

Worst-Case Condition Monitoring.......................................... 25

Reading Output Data..................................................................... 26

Reading Data from the Data Buffer......................................... 26

Accessing FFT Record Data...................................................... 26

Data Format ................................................................................ 27

Real-Time Data Collection ....................................................... 27

Power Supply/Temperature....................................................... 27

FFT Event Header ...................................................................... 29

System Tools.................................................................................... 30

Global Commands ..................................................................... 30

Status/Error Flags............................................................................

Power-Down ....................................................................................

Operation Managment ...................................................................

Input/Output Functions .................................................................

Self-Test ....................................................................................... 31

Flash Memory Management..................................................... 31

Device Identification.......................................................................

Applications Information.............................................................. 32

Interface Board ........................................................................... 32

Mating Connector...................................................................... 32

Outline Dimensions....................................................................... 33

Ordering Guide .......................................................................... 36

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Theory of Operation ........................................................................ 8

Sensing Element ........................................................................... 8

Signal Processing.......................................................................... 8

Basic Operation............................................................................... 10

SPI Write Commands ................................................................ 10

SPI Read Commands ................................................................. 10

Data Recording and Signal Processing........................................ 13

Recording Mode .............................................................................

Spectral Record Production...................................................... 17

Sample Rate/Filtering................................................................. 17

Dynamic Range/Sensitivity....................................................... 19

Pre-FFT Windowing.................................................................. 20

FFT ............................................................................................... 21

Recording Times......................................................................... 21

Data Records ............................................................................... 21

FFT Record Flash Endurance ................................................... 21

Spectral Alarms............................................................................... 23

Rev. PrA | Page 2 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

SPECIFICATIONS

T_A= −40°C to +125°C, VDD = 3.3 V, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ACCELEROMETERS (ADIS16229)

Measurement Range¹

Sensitivity, FFT

Sensitivity, Time Domain

Sensitivity Error

T_A= 25°C

T_A= 25°C, 0 g to 20 g range setting

T_A= 25°C

1ꢀ

g

0.3052

0.6104

0.3

mg/LSB

%

T_A= 25°C

6

Nonlinearity

With respect to full scale

0.2

1.25

%

Cross-Axis Sensitivity

Alignment Error

Offset Error

Offset Temperature Coefficient

Output Noise

Output Noise Density

Bandwidth

Sensor Resonant Frequency

LOGIC INPUTS³(ADIS16000)

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Leakage Current

All Except RST

4

2.3

0.01

2

11

0.24ꢀ

ꢀ40

5.5

%

With respect to package mounting holes

T_A= 25°C

Degrees

g

mg/°C

mg rms

mg/√Hz

Hz

1

T_A= 25°C, 20.4ꢀ kHz sample rate, time domain

T_A= 25°C, 10 Hz to 1 kHz

5% flatness,², see Figure 19

kHz

0.7 x VDD

V

0.2xVDD

TBD

−1

μA

mA

pF

RST

Input Capacitance, C_IN

DIGITAL OUTPUTS³

Output High Voltage, V_OH

Output Low Voltage, V_OL

FLASH MEMORY

Endurance⁴

Data Retention⁵

10

I_SOURCE= 1 mA

I_SINK= 1 mA

VDD-0.4

V

0.36

20,000

20

Cycles

Years

T_J= ꢀ5°C, see Figure 23

START-UP TIME⁶

Initial Startup

ADIS16000

ADIS16229

ADIS16000

ADIS16229

200

100

200

50

2.3

20

ms

kSPS

%

Reset Recovery⁷

Sleep Mode Recovery

CONVERSION RATE

Clock Accuracy

ADIS16229

REC_CTRL1[11:ꢀ] = 0x1 (SR0 sample rate selection)

3

POWER SUPPLY

Power Supply Current, ADIS16229

Operating voltage range, VDD

Transmission mode, 10dBm, +25C

Transmission mode, 10dBm, -40C to +ꢀ5C

Transmission mode, -1dBm, +25C

Transmission mode, -1dBm, -40C to +ꢀ5C

Receive mode, +25C

3.0

3.3

39

TBD

1ꢀ

TBD

20

3.6

41

V

mA

TBD

mA

Receive mode, +40C to +ꢀ5C

Data capture mode, no transceiver activity, +25C

Sleep mode, T_A= 25°C

Transmission mode, 10dBm, +25C

Transmission mode, -1dBm, +25C

Receive mode, +25C

TBD

7.2

2.5

37

1ꢀ

20

ꢁA

Power Supply Current, ADIS16000

mA

Rev. PrA | Page 3 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

¹The maximum range depends on the frequency of vibration.

²Assumes that frequency flatness calibration is enabled.

³The digital I/O signals are 5 V tolerant.

⁴Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +ꢀ5°C, and +125°C.

⁵Retention lifetime equivalent at junction temperature (T_J) = ꢀ5°C as per JEDEC Standard 22, Method A117. Retention lifetime depends on junction temperature.

⁶The start-up times presented reflect the time it takes for data collection to begin.

7

RST

pin must be held low for at least 10 ꢁs.

Applies to the reset line (

= 0) and the software reset command (GLOB_CMD[7] = 1). The

Rev. PrA | Page 4 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

TIMING SPECIFICATIONS

T_A= 25°C, VDD = 3.3 V, unless otherwise noted.

Table 2.

Parameter

Description

Min¹

0.01

25

Typ

Max

Unit

MHz

μs

f_SCLK

t_STALL

t_CS

t_DAV

t_DSU

SCLK frequency

2.5

Stall period between data, between 16^thand 17^thSCLK

Chip select to SCLK edge

DOUT valid after SCLK edge

DIN setup time before SCLK rising edge

DIN hold time after SCLK rising edge

SCLK rise time

4ꢀ.ꢀ

ns

100

ns

24.4

4ꢀ.ꢀ

ns

t_DHD

t_SR

12.5

ns

t_SF

t_DF, t_DR

t_SFS

SCLK fall time

DOUT rise/fall times

CS high after SCLK edge

5

¹Guaranteed by design, not tested.

Timing Diagrams

t_SR

CS

t_SF

t_CS

t_SFS

1

2

3

4

5

6

15

16

SCLK

t_DAV

DOUT

DIN

MSB

DB14

t_DSU

DB13

A5

DB12

DB11

A3

DB10

DB2

DB1

LSB

t_DHD

R/W

A6

A4

A2

D2

D1

Figure 2. SPI Timing and Sequence

t_STALL

CS

SCLK

Figure 3. DIN Bit Sequence

Rev. PrA | Page 5 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 3.

Table 4. Package Characteristics

Parameter

Rating

Package Type

θ_JA

θ_JC

Device Weight

Acceleration

15-Lead Module

31°C/W

11°C/W

6.5 grams

Any Axis, Unpowered

Any Axis, Powered

VDD to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

Temperature

2000 g

−0.3 V to +3.96 V

ESD CAUTION

Operating Temperature Range

Storage Temperature Range

−40°C to +ꢀ5°C

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. PrA | Page 6 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. ADIS16000 Pin Assignments

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Type¹

S

Description

1, 2

3, 4

VDD

GND

Power Supply, 3.3 V.

Ground.

S

5

DO2

DNC

DOUT

I/O

O

Digital Input/Output Line 2.

Do not connect

SPI, Data Output. DOUT is an output when CS is low. When CS is high, DOUT is in a three-

6, ꢀ, 9 , 10

7

state, high impedance mode.

SPI, Serial Clock.

SPI, Chip Select.

9

SCLK

CS

I

11

12

13

14

DIN/RXD

DO1

RST

I

SPI, Data Input.

Digital Input/Output Line 1.

Reset, Active Low.

I/O

I

¹S is supply, O is output, I is input, and I/O is input/output.

Rev. PrA | Page 7 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

THEORY OF OPERATION

The ADIS16000 is the “Gateway Node” and the ADIS16229 serves

as the remote “Sensor Node” in a wireless vibration monitoring

system. Using a proprietary wireless protocol, one ADIS16000 can

support up to six ADIS16229 nodes at one time in local star

network configuration (see Figure 8). As the gateway node, the

ADIS16000’s SPI interface provides access to an addressable

register map that manages configuration parameters (gateway and

sensor node), remote alarm flags and remote vibration data. The

ADIS16000’s SPI interface enables simple connection to most

embedded processors and its standard SMA connector supports

direct connection to a wide variety of antennas. The ADIS16229

only requires an antenna and battery to start-up, connect with the

ADIS16000 and begin operation.

averaging, and record storage. See Figure 16 for more details

on the signal processing operation.

SENSOR COMMUNICATION

The ADIS16000 provides access to the ADIS16229 through

dedicated pages in the register structure. When the ADIS16000

communicates with a remote ADIS16229, it copies all

configuration information in these registers to their respective

locations in the ADIS16229 and acquires all of the data in the

ADIS16229’s output registers/data records.

GATEWAY COMMUNICATION

SPI Interface

The data collection and configuration command uses the SPI,

SENSING ELEMENT

CS

which consists of four wires. The chip select ( ) signal

activates the SPI interface, and the serial clock (SCLK)

synchronizes the serial data lines. Input commands clock into

the DIN pin, one bit at a time, on the SCLK rising edge. Output

data clocks out of the DOUT pin on the SCLK falling edge.

Since the ADIS16000 serves only as a SPI slave, the DOUT

contents reflect the information requested using a DIN

command.

Digital vibration sensing in the ADIS16229 starts with a MEMS

accelerometer core on two different axes. Accelerometers

translate linear changes in velocity into a representative

electrical signal, using a micromechanical system like the one

shown in Figure 6. The mechanical part of this system includes

two different frames (one fixed, one moving) that have a series

of plates to form a variable, differential capacitive network.

When experiencing the force associated with gravity or

acceleration, the moving frame changes its physical position

with respect to the fixed frame, which results in a change in

capacitance. Tiny springs tether the moving frame to the fixed

frame and govern the relationship between acceleration and

physical displacement. A modulation signal on the moving plate

feeds through each capacitive path into the fixed frame plates and

into a demodulation circuit, which produces the electrical signal

that is proportional to the acceleration acting on the device.

Register organization

The ADIS16000’s memory map contains 7 pages of user

accessible registers, which enable simple organization of both

local (gateway) and remote (sensor) functions. Each page has a

page control register (PAGE_ID) address 0x00. Before

accessing a register within a particular page, write that page’s

identification number to this register. For example, write “2” to

the PAGE_ID register to access sensor node #2. Once a

particular page has been “accessed,” there is no need to write the

same value to PAGE_ID, in order to access the rest of the

registers within that page

ANCHOR

MOVABLE

FRAME

PLATE

CAPACITORS

Each 16-bit register has its own unique bit assignment and two

addresses: one for its upper byte and one for its lower byte.

Table 9 and Table 10 provide more details on these memory

maps, which list each register, along with its function and lower

byte address.

FIXED

PLATES

UNIT SENSING

CELL

UNIT

FORCING

CELL

Table 6. ADIS16000 Register Map Page Organization

MOVING

PLATE

PAGE_ID

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

Function

Reference

Gateway configuration

Sensor Node #1

Sensor Node #2

Sensor Node #3

Sensor Node #4

Sensor Node #5

Sensor Node #6

Table 9

Table 10

ANCHOR

Figure 6. MEMS Sensor Diagram

SIGNAL PROCESSING

Figure 9 offers a simplified block diagram for the ADIS16229.

The signal processing stage includes time-domain data capture,

digital decimation/filtering, windowing, FFT analysis, FFT

Dual-Memory Structure

The user registers provide addressing for all input/output

operations in the SPI interface. The control registers use a dual-

Rev. PrA | Page ꢀ of 37

Preliminary Technical Data

ADIS16000/ADIS16229

memory structure. The controller uses SRAM registers for

normal operation, including user-configuration commands.

The flash memory provides nonvolatile storage for control

registers that have flash backup (see Table 9 and Table 10).

When the device powers on or resets, the flash memory

contents load into the SRAM, and the device starts producing

data according to the configuration in the control registers.

Storing configuration data in the flash memory requires a

manual flash update command. For the ADIS16000, set DIN =

0x8000 (access page 0), then set DIN = 0x9240 (set

MANUAL

FLASH

BACKUP

NONVOLATILE

FLASH MEMORY

(NO SPI ACCESS)

VOLATILE

SRAM

SPI ACCESS

START-UP

RESET

Figure 7. SRAM and Flash Memory Diagram

GLOB_CMD[6] = 1). For a remote ADIS16229, using the

following steps to update its flash: (1) turn to its page (DIN =

0x8001, to access note, for example), (2) set DIN = 0xB640

(GLOB_CMD[6] = 1), (3) set DIN = 0x8000 (turn to page 0)

and (4) set DIN = 0x9202 (GLOB_CMD[8] = 1).

Figure 8. Star Wireless Network Example

Figure 9. ADIS16229 Simplified Block Diagram

Rev. PrA | Page 9 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

ADIS16000 BASIC OPERATION

Once it has appropriate power on the VDD pin, the ADIS16000

will automatically begin a self-initialization process. Once this

process is complete, the SPI interface activates and provides

access to its register structure. The SPI interface supports

connectivity with most embedded processor platforms, using

the connection diagram in Figure 10. The factory default

configuration for DO1 provides a busy indicator signal that

indicates when to avoid SPI communication requests.

Table 9 and Table 10 provide lists of user registers with their

lower byte addresses. Each register consists of two bytes that

each has its own unique 7-bit address. Figure 11 relates the bits

of each register to their upper and lower addresses.

15 14 13 12 11 10

UPPER BYTE

9

8

7

6

5

4

3

2

1

0

LOWER BYTE

Figure 11. Generic Register Bit Definitions

SPI WRITE COMMANDS

User control registers govern many internal operations. The

DIN bit sequence in Figure 14 provides the ability to write to

these registers, one byte at a time. Some configuration changes

and functions require only one write cycle. For example, set

PAGE_ID[7:0] = 1 (DIN = 0x8001) to select Page 1 of the

register map.

Figure 10. Electrical Hook-Up Diagram

Figure 12. SPI Sequence for Selecting Page 1 for Access (DIN = 0x8001)

Table 7. Generic Master Processor Pin Names and Functions

SPI READ COMMANDS

Pin Name

Function

A single register read requires two 16-bit SPI cycles that also

use the bit assignments that are shown in Figure 14. The first

SS

Slave select

SCLK

MOSI

MISO

IRQ1, IRQ2

Serial clock

R

sequence sets /W = 0 and communicates the target address

Master output, slave input

Master input, slave output

Interrupt request inputs (optional)

(Bits[A6:A0]). Bits[D7:D0] are don’t care bits for a read DIN

sequence. DOUT clocks out the requested register contents

during the second sequence. The second sequence can also use

DIN to set up the next read. Figure 13 provides a signal diagram

for all four SPI signals while reading the PROD_ID. In this

diagram, DIN = 0x1600 and DOUT reflects the decimal

equivalent of 16,000.

The ADIS16000 SPI interface supports full duplex serial

communication (simultaneous transmit and receive) and uses

the bit sequence shown in Figure 14. Table 8 provides a list of

the most common settings that require attention to initialize

a processor serial port for the ADIS16000 SPI interface.

Table 8. Generic Master Processor SPI Settings

Processor Setting

Description

Master

SCLK Rate ≤ 2.5 MHz

SPI Mode 3

The ADIS16000 operates as a slave.

Bit rate setting.

Clock polarity/phase

(CPOL = 1, CPHA = 1).

Bit sequence.

MSB First

16-Bit

Figure 13. Example SPI Read, PROD_ID (Page 0), Second Sequence

Shift register/data length.

CS

SCLK

DIN

R/W A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

R/W A6

DB14 DB13

DB15

A5

DOUT

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

NOTES

1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).

Figure 14. Example SPI Read Sequence

Rev. PrA | Page 10 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

Table 9. User Register Memory Map, PAGE_ID = 0x0000

Register

Name

Flash

Backup

Access

Address

0x00

0x02

Default Function

Reference

PAGE_ID

NETWORK_ID

FLASH_CNT

Read/write N/A

Read/write Yes

0x0000

1234

N/A

Page Identifier

Network Identifier, unique to a network

Flash update counter

Read

Yes

No

0x04

NW_ERROR_STAT

TX_PWR_CTRL_G

RSSI_G

TEMP_OUT_G

SUPPLY_OUT_G

BEACON_SETUP

GLOB_CMD

CMD_DATA

PROD_ID

Reserved

LOT_ID1

LOT_ID2

Reserved

GPO_CTRL

0x06

0x0ꢀ

0x0A

0x0C

0x0E

0x10

0x12

0x14

0x16

0x1ꢀ

0x1A

0x1C

0x1E

0x20

0x22

0x24

0x26

0x2ꢀ

0x2A

0x0000

0xꢀ000

0x0000

0x3Eꢀ0

N/A

Network error indicators

Transmission power control, Gateway

Received signal strength

Output, temperature

Output, supply voltage

Beacon frequency

System commands

Data to sensor nodes

Product identifier, 16000

Reserved

Read/write Yes

Read

No

Read/write Yes

Read/write No

Read only

N/A

Read only

N/A

Yes

No

N/A

Reserved

N/A

Reserved

N/A

Reserved

N/A

Reserved

N/A

Reserved

N/A

Lot identifier 1

N/A

Lot identifier 2

N/A

Reserved

Read/write Yes

N/A

General-purpose output control

Rev. PrA | Page 11 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

Table 10. User Register Memory Map, PAGE_ID ≥ 0x0001

Register

Name

Flash

Backup

Access

Address

0x00

0x02

0x04

0x06

0x0ꢀ

0x0A

0x0C

0x0E

0x10

0x12

0x14

0x16

0x1ꢀ

0x1A

0x1C

0x1E

0x20

0x22

0x24

0x26

0x2ꢀ

0x2A

0x2C

0x2E

0x30

0x32

0x34

0x36

0x3ꢀ

0x3A

0x3C

0x3E

0x40

0x42

0x44

0x46

0x4ꢀ

0x4A

0x4C

0x4E

0x50

0x52

0x54

0x56

0x5ꢀ

0x5A

0x5C

0x5E

0x60

0x62

0x64

Default¹

N/A

0xꢀ000

0x010ꢀ

0x0101

0x0000

Function

Reference

PAGE_ID

SENS_ID

FLASH_CNT

X_BUF

Y_BUF

TEMP_OUT

SUPPLY_OUT

FFT_AVG1

FFT_AVG2

BUF_PNTR

REC_PNTR

X_SENS

Y_SENS

REC_CTRL1

REC_CTRL2

Read/write

Read only

Read/write

N/A

Yes

No

Yes

No

Yes

Page Identifier

Sensor Identifier

Status, flash memory write count

Output, buffer for x-axis acceleration data

Output, buffer for y-axis acceleration data

Output, temperature during capture

Output, power supply during capture

Control, FFT average size of 1, SR0 and SR1

Control, FFT average size of 2, SR2 and SR3

Control, buffer address pointer

Table 59

Table 60

Table 34

Table 35

Table 57

Table 5ꢀ

Table 32

Table 33

Table 27

Table 30

Control, record address pointer

Control, x-axis acceleration scale adjustment

Control, y-axis acceleration scale adjustment

Record Control Register

0x0002

0x000F

Record Control Register

ALM_F_LOW

ALM_F_HIGH

ALM_X_MAG1

ALM_Y_MAG1

ALM_X_MAG2

ALM_Y_MAG2

ALM_PNTR

ALM_S_MAG

ALM_CTRL

AVG_CNT

Read/write

Read only

Write only

Read only

Read/write

Read only

Read/write

Read only

Yes

No

Yes

No

Yes

No

Yes

No

Yes

0x0000

0x9630

0x0000

Spectral Alarm Band, Low Frequency

Spectral Alarm Band, High Frequency

Spectral Alarm Band, X-axis, Alarm 1 Magnitude

Spectral Alarm Band, Y-axis, Alarm 1 Magnitude

Spectral Alarm Band, X-axis, Alarm 2 Magnitude

Spectral Alarm Band, Y-axis, Alarm 2 Magnitude

Spectral Alarm Band Pointer

Alarm, system alarm threshold

Alarm, control register

Sample rate control (average count)

System status register

Global command register

Alarm, X-axis status register

Alarm, Y-axis status register

Alarm, X-axis peak level

Alarm, Y-axis peak level

Time stamp, low integer

Time stamp, high integer

Table 43

Table 44

Table 45

Table 46

Table 47

Table 4ꢀ

Table 42

Table 49

Table 41

Table 2ꢀ

DIAG_STAT

GLOB_CMD

ALM_X_STAT

ALM_Y_STAT

ALM_X_PEAK

ALM_Y_PEAK

TIME_STAMP_L

TIME_STAMP_H

ALM_X_FREQ

ALM_Y_FREQ

PROD_ID

Table 74

Table 50

Table 51

Table 52

Table 53

Table 72

Table 73

Table 54

Table 55

Alarm, x-axis, frequency of ALM_X_PEAK

Alarm, y-axis, frequency of ALM_Y_PEAK

Product identification register

REC_FLSH_CNT

REC_INFO1

REC_INFO2

Table 39

Table 70

Table 71

Table 37

Record settings 1

Record settings 2

Record counter

Received packet time stamp, low integer

Received packet time stamp, high integer

Missed packets/Error indicator

Transmission power control

Received signal strength indicator

Wireless communication configuration

Update interval

REC_CNTR

PKT_TIME_L

PKT_TIME_H

PKT_ERR_STAT

TX_PWR_CTRL_S

RSSI_S

RF_MODE

UPDAT_INT

INT_SCL

0x0000

Update interval scale

Beacon interval

User scratch register

BEACON_INT

USER_SCR

Rev. PrA | Page 12 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

Reserved

LOT_ID1

LOT_ID2

Reserved

X_ANULL

Y_ANULL

UPDT_FLAG

N/A

Yes

N/A

Yes

0x66

0x6ꢀ

0x6A

0x6C

0x6E

0x70

0x72

0x74

N/A

0x0000

Reserved

Read only

N/A

Lot identification 1

Lot identification 2

Reserved

Automatic null value, x-axis

Automatic null value, y-axis

N/A

Read only

Read/write

Register update tracking register

¹All registers in pages 1, 2, 3, 4, 5 and 6 will read 0x0000, prior to connecting with the ADIS16229

NETWORK MANAGEMENT

Once they have an appropriate supply voltage across their VDD

and GND pins, both ADIS16000 and ADIS16229 will self-initialize

and prepare themselves for connecting. After completing this

process, the ADIS16229 will start sending “connection requests” to

any available ADIS16000 devices that are within range. The system

microcontroller manages the ADIS16000’s response to these

requests, using the CMD_DATA (See Table 11) and GLOB_CMD

registers (See Table 12), which are both in Page 0 of the

4

3

Clear DIAG_STAT register

Restore factory register settings,

including capture buffer and

alarm registers

2

1

Self-test, result in DIAG_STAT[5]

Update sensor node in

CMD_DATA register, in one of the

manual modes

Add sensor node in CMD_DATA to

the network

0

ADIS16000. Adding an ADIS16229 network requires two steps:

(1) write the node number (between 0 and 6) to the CMD_DATA

register and then (2) set GLOB_CMD[0] = 1 (DIN = 0x9201, in

page 0). After this second step, the connection process can take up

to 3 minutes after writing this code. Removing a sensor from the

network uses a similar two-step process: (1) write the sensor node

number to the CMD_DATA register and then (2) Set

After connecting with an ADIS16229, the ADIS16000 will

automatically copy the contents from its own NETWORK_ID[7:0]

location (see Table 13) to the SENS_ID[7:0] location in the

ADIS16229’s page. (see Table 14).

GLOB_CMD[8] = 1 (DIN = 0x9301, page 0).

Set GLOB_CMD[1] = 1 (DIN = 0x9202) to initial an update of all

of the registers, except those associated with the spectral alarms. Set

GLOB_CMD[12] = 1 (DIN = 0x9310) to update all of the alarm

registers, after configuring them. Separating this function will help

manage the flash memory endurance.

Table 13. NETWORK_ID

Page 0, Low-Byte Address = 0x02, Read/Write

Bits

Description (Default = 0x1234)

[15:0]

Network identification number

Table 11. CMD_DATA,

Page 0, Low-Byte Address = 0x14, Read/Write

The SENS_ID register will contain the value 0x0000 when not

connected to a network. When connected to the network, as node

1, it will contain 0xAD34.

Bits

Description (Default = 0x0000)

[15:4]

[3:0]

Not used

Table 14. SENS_ID

Page 1-6, Low-Byte Address = 0x02, Read Only

Sensor node for GLOB_CMD[1] and GLOB_CMD[0]

commands. Range = 000 (0) to 110 (6)

Bits

Description (Default = 0xAAAA)

[15:0]

Sensor identification

Table 12. GLOB_CMD

Page 0, Low-Byte Address = 0x12, Write Only

Receiver Signal Strength

Bits

[15:ꢀ]

ꢀ

Description

Execution Time

The RSSI_G (see Table 15) and RSSI_S (see Table 16) provide

tools for tuning the transmission power control at each location.

In order to maintain effective communication, keep the

transmission power high enough to maintain at least -94dBm in

these registers.

Not used

Remove sensor node in

CMD_DATA from the network

7

6

5

Software reset

Save registers to flash memory

Flash test, compare sum of flash

memory with factory value

Rev. PrA | Page 13 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

Table 15. RSSI_G

Page 0, Low Byte Address = 0x0A, Read Only

Table 19. RF_MODE

Page 0, Low Byte Address = 0x58, Read/Write

Bits

Description (Default = 0x)

Bits

[15:9]

[ꢀ]

Description (Default = 0x)

[15:0]

Received signal strength

Twos complement format, 1 LSB = 1dBm

0x0000 = 0dBm

Not used (do not care)

Complete register dump during update cycle

(0 = enable, 1 = disable)

Periodic wake-up/beacon synchronization

(0 = disable, 1 = enable)

Frequency hoping

(0 = disable, 1 = enable)

Complete synchronization after missing 2 beacons

(0 = disable, 1 = enable)

Not used (do not care)

Update gateway on Alarm only

(0 = disable, 1 = enable)

0xFFA2 = -94dBm

[7]

[6]

[5]

Table 16. RSSI_S

Page 1-6, Low Byte Address = 0x5A, Read Only

Bits

Description (Default = 0x1100)

[15:0]

Received signal strength

Twos complement format, 1 LSB = 1dBm

0x0000 = 0dBm

[4:2]

[1]

0xFFA2 = -94dBm

[0]

Update gateway on beacon synchronization

(0 = disable, 1 = enable)

Transmission Power Control

The UPDAT_INT (See Table 20) and INT_SCL (See Table 21)

registers establish the time between wake-up events, where the

remote ADIS16229 captures data, analyzes it and communicates

the information.

Both ADIS16000 and ADIS16229 units provide controls for

transmission power in a registers called, TX_PWR_CTRL_G (see

Table 17) and TX_PWR_CTRL_S. The registers provide users

with the ability to optimize the transmission power for battery

optimization and to manage interference influence on other

networks. Note that compliance with FCC Part 15.249 involves

limiting the transmission power to -1dBm.

Table 20. UPDAT_INT

Page 1-6, Low Byte Address = 0x5E, Read/Write

Table 17. TX_PWR_CTRL_G

Page 0, Low Byte Address = 0x08, Read/Write

Bits

Description (Default = 0x)

[15:0]

Offset binary number, scale factor set by INT_SCL

register

Bits

Description (Default = 0x)

[15:5]

[40]

Not used (do not care)

Transmission power, offset binary format

1LSB = 1.6dBm (25.5/15)

Table 21. INT_SCL

Page 1-6, Low Byte Address = 0x60, Read/Write

0 = -15.5dBm (minimum)

F = +10dBm (maximum)

Bits

Description (Default = 0x)

[15:2]

[1:0]

Not used (do not care)

Scale factor

00 = 30.52ꢁsec/LSB, maximum = 2 seconds

01 = 0.4ꢀꢀmsc/LSB, maximum = 31.9ꢀ seconds

10 = 1/12ꢀ sec/LSB, maximum = 512 seconds

11 = 1 sec/LSB, maximum = 1ꢀ.2 hours

Table 18. TX_PWR_CTRL_S

Page 1-6, Low Byte Address = 0x58, Read/Write

Bits

Description (Default = 0x)

[15:5]

[40]

Not used (do not care)

Transmission power, offset binary format

1LSB = 1.6dBm (25.5/15)

0 = -15.5dBm (minimum)

F = +10dBm (maximum)

The beacon synchronization function uses periodic monitoring

for drift in sensor node clocks and limits their sleep time to 30

minutes (or less) in order to maintain consistent

synchronization. The BEACON_SETUP (See Table 22) register

provides a user control for this function. When operating in

real-time mode (REC_CTRL1 register, See Table 27) this mode

is not necessary and automatically turns off.

Wireless Configuration

The RF_MODE (see Table 19) register provides a number of

important wireless configuration parameters. Note that when the

transmission power exceeds -1dBm, FCC Part 15.247 requires the

use of “frequency-hopping.”

Table 22. BEACON_SETUP

Page 0, Low Byte Address = 0x10, Read/Write

Bits

[15:1]

0

Description (Default = 0x)

Not used

1 = Beacon synchronization enable

Rev. PrA | Page 14 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

0 = Beacon synchronization disable

The NW_ERROR_STAT (see Table 26) register provides all of the

error flags associated with the wireless communication.

The BEACON_INT (See Table 23) register sets the interval time

between re-synchronizing events with the ADIS16000 (gateway).

Table 26. NW_ERROR_STAT

Page 0, Low Byte Address = 0x06), Read/Write

Table 23. BEACON_INT

Page 1-6, Low Byte Address = 0x62, Read/Write

Bits

Description (Default = 0x1100)

[15:12] Sensor node associated present error flags in this

register

[11:10] Not used

Bits

Description (Default = 0x)

[15:0]

Offset binary number, scale factor set by INT_SCL

register

9

ꢀ

Received packet from an unknown device.

Packet synchronization failure, from the most recent

received packet

7

No response from one or more sensor nodes during

beacon synchronization

Communication Tools

The PKT_TIME_H (upper word) and PKT_TIME_L (lower word)

registers provide a 32-bit timer for tracking the relative times

associated with packet transmission times. This maximum value

for this number is 49.71 days. At this point, the registers start over

at 0x0000.

6

5

4

3

2

Failed to receive a packet from the sensor node

Packet length mismatch

Missing packet

Packets received out of SYNC

Failure to receive acknowledgement from a sensor

node

Low signal strength from a sensor node, read RSSI_S

register for power level of this signal. See Table 16

CRC mismatch error associated with the most recent

packet from the Sensor Node Packet

Table 24. PKT_TIME_H

Page 1-6, Low Byte Address = 0x54, Read/Write

1

0

Bits

Description (Default = N/A))

[15:0]

Offset binary number, upper word

Table 25. PKT_TIME_L

Page 1-6, Low Byte Address = 0x52, Read/Write

Bits

Description (Default = N/A)

[15:0]

Offset binary number, lower word, 1 LSB = 1msec

Rev. PrA | Page 15 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

SENSOR NODE RECORDING MODE/SIGNAL PROCESSING

The ADIS16229 provides a complete sensing system for recording

Manual FFT Mode

and monitoring vibration data. Figure 15 provides a simplified

block diagram for the signal processing associated with spectral

record acquisition on both axes (x and y). User registers provide

controls for data type (time or frequency), trigger mode (manual

or automatic), collection mode (real time or capture), sample

rates/filtering, windowing, FFT averaging, spectral alarms, and I/O

management.

Set REC_CTRL1[1:0] = 00 to place the device in manual FFT

mode, which will result in triggering a single FFT cycle. When

the spectral record is complete, the device will transmit the data

to the ADIS16000 and wait for another start command.

Automatic FFT Mode

Set REC_CTRL1[1:0] = 01 to place the device in automatic FFT

mode. Use the UPDAT_INT and INT_SCL registers to establish

the period between “wake-up times,” which triggers data

capture, FFT computation and analysis.

RECORDING MODE

The recording mode selection establishes the data type (time or

frequency domain), trigger type (manual or automatic), and

data collection (captured or real time). The REC_CTRL1[1:0]

bits (see Table 27) provide four operating modes: manual FFT,

automatic FFT, manual time capture, and real time. After setting

REC_CTRL1, the manual FFT, automatic FFT, and manual time

capture modes require a start command to start acquiring a

spectral or time domain record. All of these modes automatically

trigger when the sensor receives the configuration packet from

the gateway. Set GLOB_CMD[11] = 1 to halt the operation and

wait for further instructions from the ADIS16000..

Manual Time Capture Mode

Set REC_CTRL1[1:0] = 10 to place the device into manual time

capture mode, which will result in triggering a single time

domain data capture. When the device is operating in this

mode, 512 samples of time domain data are loaded into the

buffer for each axis. This data goes through all time domain

signal processing, except the pre-FFT windowing, prior to

loading into the data buffer for user access. When the data

record is complete, the device will transmit the data to the

ADIS16000 and wait for another start command.

Table 27. REC_CTRL1

Page 1-6, Low Byte Address = 0x1A, Read/Write

Bits

Description (Default = 0x1100)

[15:14] Not used (don’t care).

[13:12] Window setting.

00 = rectangular, 01 = Hanning, 10 = flat top, 11 = N/A.

11

10

9

SR3, 1 = enabled for FFT, 0 = disable.

Sample rate = 20,000 ÷ 2^{AVG_CNT[15:12]}(see Table 2ꢀ).

SR2, 1 = enabled for FFT, 0 = disable.

Sample rate = 20,000 ÷ 2^{AVG_CNT[11:ꢀ]}(see Table 2ꢀ).

SR1, 1 = enabled for FFT, 0 = disable.

Sample rate = 20,000 ÷ 2^AVG_CNT[7:4](see Table 2ꢀ).

SR0, 1 = enabled for FFT, 0 = disable.

Sample rate = 20,000 ÷ 2^AVG_CNT[3:0](see Table 2ꢀ).

Power-down between each recording. 1 = enabled.

Not used (don’t care).

ꢀ

7

[6:4]

[3:2]

Storage method.

00 = none, 01 = alarm trigger, 10 = all, 11 = N/A.

[1:0]

Recording mode.

00 = manual FFT, 01 = automatic FFT,

10 = manual time capture, 11 = real-time sampling/data

access.

DATA

BUFFER

SPI AND

REGISTERS

MEMS

ADC

PROCESSING

RECORDS

Figure 15. Simplified Block Diagram

Rev. PrA | Page 16 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

Real-Time Mode

more than one sample rate option is enabled while the device is in

the automatic FFT mode, the device produces a spectral record

for one SRx option, and then waits for the next automatic trigger,

which occurs based on the UPDAT_INT and INT_SCL registers.

See Figure 17 for more details on how multiple SRx options

influence data collection and spectral record production. When

in real-time mode, the output data rate reflects the SR0 setting.

Set REC_CTRL1[1:0] = 11 to place the device into real-time mode.

In this mode, the device samples only one axis, at a rate of

5 kSPS, and provides data on its output register at the SR0

sample rate setting in AVG_CNT[3:0] (see Table 28). Select the

axis of measurement in this mode by reading its assigned register.

For example, select the x-axis by reading X_BUF, using DIN =

0x1400. See Table 59 or Table 60 for more information on the

x_BUF registers. No other ADIS16229 nodes will be able to

communicate with the ADIS16000 when one of them is in real-

time mode.

Table 29 provides a list of SRx settings available in the AVG_CNT

register (see Table 28), along with the resulting sample rates, FFT

bin widths, bandwidth, and estimated total noise. Note that each

SRx setting also has associated range settings in the REC_CTRL2

register (see Table 30) and the FFT averaging settings that are

shown in the FFT_AVG1 and FFT_AVG2 registers (see Table 34

and Table 35, respectively).

SPECTRAL RECORD PRODUCTION

The ADIS16229 produces a spectral record by taking a time

record of data on both axes, then scaling, windowing, and

performing an FFT process on each time record. This process

repeats for a programmable number of FFT averages, with the FFT

result of each cycle accumulating in the data buffer. After com-

pleting the selected number of cycles, the FFT averaging process

completes by scaling the data buffer contents. Then the data

buffer contents are available to the SPI and output data registers.

Table 28. AVG_CNT

Page 1-6, Low Byte Address = 0x32, Read/Write

Bits

Description (Default = 0x9630)

[15:12]

Sample Rate Option 3, binary (0 to 10),

SR3 option sample rate = 20,000 ÷ 2^{AVG_CNT[15:12]}

[11:ꢀ]

[7:4]

[3:0]

Sample Rate Option 2, binary (0 to 10),

SR2 option sample rate = 20,000 ÷ 2^{AVG_CNT[11:ꢀ]}

Sample Rate Option 1, binary (0 to 10),

SR1 option sample rate = 20,000 ÷ 2^AVG_CNT[7:4]

Sample Rate Option 0, binary (0 to 10),

SR0 option sample rate = 20,000 ÷ 2^AVG_CNT[3:0]

SAMPLE RATE/FILTERING

The sample rate for each axis is 20 kSPS. The internal ADC

samples both axes in a time-interleaving pattern (x1, y1, x2,

y2…) that provides even distribution of data across the data

record. The averaging/decimating filter provides a control for

the final sample rate in the time record. By averaging and

decimating the time domain data, this filter provides the ability

to focus the spectral record on lower bandwidths, which produces

finer frequency resolution in each FFT frequency bin. AVG_CNT

(see Table 28) provides the setting for the four different sample

rate options in REC_CTRL1[11:8] (SRx, see Table 27). All four

options are available when using the manual FFT, automatic

FFT, and manual time capture modes. When more than one

sample rate option is enabled while the device is in one of the

manual modes, the device produces a spectral record for one

SRx at a time, starting with the lowest number. After completing

the spectral record for one SRx option, the device waits for

another start command before producing a spectral record for

the next SRx option that is enabled in REC_CTRL1[11:8]. When

Table 29. Sample Rate Settings and Filter Performance

Sample

Rate, f_S

(SPS)

Bin

Width

(Hz)

Peak Noise

per Bin

(mg)

SRx

Option

Bandwidth

(Hz)

0

1

2

3

4

5

6

7

ꢀ

9

10

20,000

10,000

5,000

2,500

1,250

625

313

156

7ꢀ

39

39.1

19.5

9.ꢀ

4.9

2.4

1.2

0.6

0.3

0.2

0.1

0.0

10,000

5,000

2,500

1,250

625

313

156

7ꢀ

5.1ꢀ

3.66

2.59

1.ꢀ3

1.29

0.91

0.65

0.46

0.32

0.23

0.16

39

20

10

20

Figure 16. Signal Flow Diagram, REC_CTRL1[1:0] = 00 or 01, FFT Analysis Modes

Rev. PrA | Page 17 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

Figure 17. Spectral Record Production, with All SRx Settings Enabled

Rev. PrA | Page 1ꢀ of 37

Preliminary Technical Data

ADIS16000/ADIS16229

Dynamic Range Settings

DYNAMIC RANGE/SENSITIVITY

REC_CTRL2 (see Table 30) provides four range settings that

are associated with each sample rate option, SRx. The range options

that are referenced in REC_CTRL2 reflect the maximum dynamic

range, which occurs at the lower part of the frequency range and

does not account for the decrease in range (see Figure 18). For

example, set REC_CTRL2[5:4] = 10 (DIN = 0x9C20) to set the

peak acceleration (A_MAX) to 10 g on the SR2 sample rate option.

These settings help optimize FFT precision and sensitivity when

monitoring lower magnitude vibrations. For each range setting

in Table 30, this stage scales the time domain data so that the

maximum value equates to 2¹⁵LSBs for time domain data and

2¹⁶LSBs for frequency domain data.

The range of the ADIS16229 accelerometers depends on the

frequency of the vibration. The accelerometers have a self-

resonant frequency of 5.5 kHz, and the signal conditioning

circuit applies a single-pole, low-pass filter (2.5 kHz) to the

response. The self-resonant behavior of the accelerometer

influences the relationship between vibration frequency and

dynamic range, as shown in Figure 18, which displays the

response to peak input amplitudes, assuming a sinusoidal

vibration signature at each frequency. The accelerometer

resonance and low-pass filter also influence the magnitude

response, as shown in Figure 19.

20

18g PEAK RESPONSE

Note that the maximum range for each setting is 1 LSB smaller

than the listed maximum. For example, the maximum number

of codes in the frequency domain analysis is 2¹⁶− 1, or 65,535.

For example, when using a range setting of 1 g in one of the FFT

modes, the maximum measurement is equal to 1 g times 2¹⁶− 1,

divided by 2¹⁶. See Table 31 for the resolution associated with

each setting and Figure 16 for the location of this operation in

the signal flow diagram. The real-time mode automatically uses

the 20 g range setting.

18

16g PEAK RESPONSE

16

14g PEAK RESPONSE

14

12

10

8

6

4

Table 30. REC_CTRL2

Page 1-6, Low Byte Address = 0x1C, Read/Write

2g PEAK RESPONSE

2

Bits

Description (Default = 0x00FF)

0

1000

2000

4000

5000

6000

[15:ꢀ]

[7:6]

Not used (don’t care)

Measurement range, SR3

00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g

Measurement range, SR2

00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g

Measurement range, SR1

00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g

Measurement range, SR0

00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g

FREQUENCY (Hz)

Figure 18. Peak Magnitude vs. Frequency

[5:4]

[3:2]

[1:0]

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

Table 31. Range Settings and LSB Weights

Range Setting (g)

(REC_CTRL2[5:4])

0 to 1

0 to 5

0 to 10

Time Mode

(mg/LSB)

0.0305

0.1526

0.3052

FFT Mode

(mg/LSB)

0.0153

0.0763

0.1526

+3σ

MEAN

0 to 20

0.6104

0.3052

–3σ

100

1000

FREQUENCY (Hz)

5000

Figure 19. Magnitude/Frequency Response (CAL_ENABLE[4] = 0)

Rev. PrA | Page 19 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

Scale Adjustment

The x_SENS registers (see Table 32 and Table 33) provide a

fine-scale adjustment function for each axis. The following

equation describes how to use measured and ideal values to

calculate the scale factor for each register in LSBs:

18

a







× 2

SCFx =

XI

 1

a_XM







where:

is the ideal x-axis value.

a_XI

is the actual x-axis measurement.

a_XM

These registers contain correction factors, which come from the

factory calibration process. The calibration process records

accelerometer output in four different orientations and

computes the correction factors for each register.

These registers also provide write access for in-system adjust-

ment. Gravity provides a common stimulus for this type of

correction process. Use both +1 g and −1 g orientations to reduce

the effect of offset on this measurement. In this case, the ideal

measurement is 2 g, and the measured value is the difference of

the accelerometer measurements at +1 g and −1 g orientations.

The factory-programmed values are stored in flash memory and

are restored by setting GLOB_CMD[3] = 1 (DIN = 0xB604)

(see Table 74).

Table 32. X_SENS

Pages 1-6, Low Byte Address = 0x16, Read/Write

Bits

Description (Default = N/A)

[15:0] X-axis scale correction factor (SCFx), twos complement

Table 33. Y_SENS

Pages 1-6, Low Byte Address = 0x18, Read/Write

Bits

Description (Default = N/A)

[15:0] Y-axis scale correction factor (SCFy), twos complement

PRE-FFT WINDOWING

REC_CTRL1[13:12] provide three options for pre-FFT windowing

of time data. For example, set REC_CTRL1[13:12] = 01 to use

the Hanning window, which offers the best amplitude resolution

of the peaks between frequency bins and minimal broadening

of peak amplitudes. The rectangular and flat top windows are

also available because they are common windowing options for

vibration monitoring. The flat top window provides accurate

amplitude resolution with a trade-off of broadening the peak

amplitudes.

Rev. PrA | Page 20 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

FFT

The storage time (t_ST) applies only when a storage method is

selected in REC_CTRL1[3:2] (see Table 27 for more details

The FFT process converts each 512-sample time record into

a 256-point spectral record that provides magnitude vs.

frequency data.

about the record storage settings). The alarm scan time (t_AST

)

applies only when the alarms are enabled in ALM_CTRL[4:0]

(see Table 41 for more information). Understanding the

recording time helps predict when data is available, for systems

that cannot use DO1 to monitor the status of these operations.

Note that when using automatic FFT mode, the automatic

recording period (REC_PRD) must be greater than the total

recording time.

FFT Averaging

The FFT averaging function combines multiple FFT records to

reduce the variation of the FFT noise floor, which enables detection

of lower vibration levels. Each SRx option in the REC_CTRL1

register has its own FFT average control, which establishes the

number of FFT records to average into the final FFT record.

To enable this function, write the number of averages for each

SRx option that is enabled in the REC_CTRL1 register to the

FFT_AVGx registers. For example, set FFT_AVG2[8:0] = 0x4A

(DIN = 0x904A) to set the number of FFT averages to 16 for the

SR2 sample rate option and 1024 for the SR3 sample rate option.

DATA RECORDS

After the ADIS16229 finishes processing FFT data, it stores the

data into the data buffer, where it is available for external access

using the SPI and x_BUF registers (see Table 59 and Table 60).

REC_CTRL1[3:2] (see Table 27) provides programmable

conditions for writing buffer data into the FFT records, which

are in nonvolatile flash memory locations. Set

Table 34. FFT_AVG1

Page 0, Low Byte Address = 0x0E, Read/Write

REC_CTRL1[3:2] = 01 to store data buffer data into the flash

memory records only when an alarm condition is met. Set

REC_CTRL1[3:2] = 10 to store every set of FFT data into the

flash memory locations. The flash memory record provides space

for a total of 14 records. Each record stored in flash memory

contains a header and frequency domain (FFT) data from all

axes (x, and y). When all 14 records are full, new records do not

load into the flash memory. The REC_CNTR register (see Table

37) provides a running count for the number of records that are

stored. Set GLOB_CMD[8] = 1 (DIN = 0xBF01) to clear all of the

records in flash memory.

Bits

Description (Default = 0x0108)

[15:ꢀ] FFT averages for a single record, SR1 sample rate,

N_Fin Figure 16; range = 1 to 255, binary

[7:0]

FFT averages for a single record, SR0 sample rate,

N_Fin Figure 16; range = 1 to 255, binary

Table 35. FFT_AVG2

Page 0, Low Byte Address = 0x10, Read/Write

Bits

[15:ꢀ] FFT averages for a single record, SR3 sample rate,

N_Fin Figure 16; range = 1 to 255, binary

[7:0]

Description (Default = 0x0101)

FFT averages for a single record, SR2 sample rate,

N_Fin Figure 16; range = 1 to 255, binary

Table 37. REC_CNTR

Page 0, Low Byte Address = 0x50), Read Only

RECORDING TIMES

Bits

Description (Default = 0x0000)

When using automatic FFT mode, the automatic recording period

(REC_PRD) must be greater than the total recording time. Use

the following equations to calculate the recording time:

[15:5]

[4:0]

Not used

Total number of records taken; range = 0 to 14, binary

When used in conjunction with automatic trigger mode and record

storage, FFT analysis for each sample rate option requires no addi-

tional inputs. Depending on the number of FFT averages, the time

between each sample rate selection may be quite large. Note that

selecting multiple sample rates reduces the number of records

available for each sample rate setting, as shown in Table 38.

Manual time mode

t_R= t_S+ t_PT+ t_ST+ t_AST

FFT modes

t_R= N_F× (t_S+ t_PT+ t_FFT) + t_ST+ t_AST

Table 36 provides a list of the processing times and settings that

are used in these equations.

Table 38. Available Records per Sample Rate Selected

Number of Sample Rates Selected

Available Records

1

2

3

4

14

7

4

Table 36. Typical Processing Times

Function

Time (ms)

Sample Time, t_S

1 ÷ f_S, per AVG_CNT

3

Processing Time, t_PT

FFT Time, t_FFT

1ꢀ.7

32.7

FFT RECORD FLASH ENDURANCE

Number of FFT Averages, N_F

Storage Time, t_ST

Alarm Scan Time, t_AST

Per FFT_AVG1, FFT_AVG2

120.0

2.21

The REC_FLSH_CNT register (see Table 39) increments when

all 14 records contain FFT data.

Rev. PrA | Page 21 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

Table 39. REC_FLSH_CNT

Page 1-6, Low Byte Address = 0x4A, Read Only

Bits

Description

[15:0]

Flash write cycle count; record data only, binary

Rev. PrA | Page 22 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

SENSOR NODE SPECTRAL ALARMS

The alarm function offers six spectral bands for alarm detection.

Each spectral band has high and low frequency definitions,

along with two different trigger thresholds (Alarm 1 and Alarm 2)

for each accelerometer axis. Table 40 provides a summary of

each register used to configure the alarm function.

(SRx). It also has two independent trigger level settings, which

are useful for systems that value warning and fault condition

indicators.

ALM_F_HIGH

ALM_F_LOW

Table 40. Alarm Function Register Summary

ALM_x_MAG2

ALM_x_MAG1

Register

Address Description

ALM_F_LOW

ALM_F_HIGH

ALM_X_MAG1 0x24

ALM_Y_MAG1 0x26

ALM_X_MAG2 0x2A

ALM_Y_MAG2 0x2C

ALM_PNTR

ALM_S_MAG

ALM_CTRL

0x20

0x22

Alarm frequency band, lower limit

Alarm frequency band, upper limit

X-Axis AlarmTrigger Level 1 (warning)

Y-Axis AlarmTrigger Level 1 (warning)

X-Axis Alarm Trigger Level 2 (fault)

Y-Axis Alarm Trigger Level 2 (fault)

Alarm pointer

System alarm trigger level

Alarm configuration

Alarm status

X-axis alarm status

Y-axis alarm status

X-axis alarm peak

Y-axis alarm peak

0x2C

0x2E

0x30

0x34

0x3ꢀ

0x3A

0x3C

0x3E

0x44

0x46

1

2

3

4

5

6

DIAG_STAT

FREQUENCY

ALM_X_STAT

ALM_Y_STAT

ALM_X_PEAK

ALM_Y_PEAK

ALM_X_FREQ

ALM_Y_FREQ

Figure 20. Spectral Band Alarm Setting Example, ALM_PNTR = 0x03

Select the spectral band for configuration by writing its number

(1 to 6) to ALM_PNTR[2:0] (see Table 42). Then select the sample

rate option using ALM_PNTR[9:8]. This number represents a

binary number, which corresponds to the x in the SRx sample

rates option associated with REC_CTRL1[11:8] (see ). For

example, set ALM_PNTR[7:0] = 0x05 (DIN = 0xAC05) to select

Alarm Spectral Band 5, and set ALM_PNTR[15:8] = 0x02 (DIN

= 0xB102) to select the SR2 sample rate option.

X-axis alarm frequency of peak alarm

Y-axis alarm frequency of peak alarm

The ALM_CTRL register (see Table 41) provides control bits

that enable the spectral alarms of each axis, configures the system

alarm, sets the record delay for the spectral alarms, and configures

the clearing function for the DIAG_STAT error flags (see Table 84).

Table 42. ALM_PNTR

Page 1-6, Low Byte Address = 0x2C, Read/Write

Table 41. ALM_CTRL

Page 1-6, Low Byte Address = 0x30, Read/Write

Bits

Description (Default = 0x0000)

[15:10] Not used

Bits

Description (Default = 0x0000)

[9:ꢀ]

[7:3]

[2:0]

Sample rate option; range = 0 to 3 for SR0 to SR3

Not used

Spectral band number; range = 1 to 6

[15:12] Not used.

[11:ꢀ]

7

Response delay; range = 0 to 15. Represents the number

of spectral records for each spectral alarm before a

spectral alarm flag is set high.

Latch DIAG_STAT error flags. Requires a clear status

command (GLOB_CMD[4]) to reset the flags to 0.

1 = enabled, 0 = disabled.

Alarm Band Frequency Definitions

After the spectral band and sample rate settings are set, program

the lower and upper frequency boundaries by writing their bin

numbers to the ALM_F_LOW register (see Table 43) and

ALM_F_HIGH register (see Table 44). Use the bin width

definitions listed in Table 29 to convert a frequency into a bin

number for this definition. Calculate the bin number by dividing

the frequency by the bin width that is associated with the sample

rate setting. For example, if the sample rate is 5000 Hz and the

lower band frequency is 400 Hz, divide that number by the bin

width of 10 Hz to arrive at the 40^thbin as the lower band setting.

Then set ALM_F_LOW[7:0] = 0x28 (DIN = 0xA028) to establish

400 Hz as the lower frequency for the 5000 SPS sample rate setting.

6

5

Enable DO1 as an Alarm 1 output indicator and enable

DO2 as an Alarm 2 output indicator. 1 = enabled.

System alarm comparison polarity.

1 = trigger when less than ALM_S_MAG[11:0].

0 = trigger when greater than ALM_S_MAG[11:0].

System alarm. 1 = temperature, 0 = power supply.

Alarm S enable (ALM_S_MAG). 1 = enabled, 0 = disabled.

Not used

4

3

2

1

0

Alarm Y enable (ALM_Y_MAG). 1 = enabled, 0 = disabled.

Alarm X enable (ALM_X_MAG). 1 = enabled, 0 = disabled.

ALARM DEFINITION

Table 43. ALM_F_LOW

Page 1-6, Low Byte Address = 0x20, Read/Write

Bits

The alarm function provides six programmable spectral bands,

as shown in Figure 20. Each spectral alarm band has lower and

upper frequency definitions for all of the sample rate options

Description (Default = 0x0000)

Rev. PrA | Page 23 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

Table 47. ALM_X_MAG2

Page 1-6, Low Byte Address = 0x2A, Read/Write

Bits Description (Default = 0x0000)

[15:0] X-axis Alarm Trigger Level 2, 16-bit unsigned (see Table 30

and Table 31 for the scale factor)

[15:ꢀ] Not used

[7:0]

Lower frequency, bin number; range = 0 to 255

Table 44. ALM_F_HIGH

Page 1-6, Low Byte Address = 0x22, Read/Write

Bits

Description (Default = 0x0000)

Table 48. ALM_Y_MAG2

[15:ꢀ] Not used

Page 1-6, Low Byte Address = 0x2C, Read/Write

[7:0]

Upper frequency, bin number; range = 0 to 255

Bits

Description (Default = 0x0000)

Alarm Trigger Settings

[15:0] Y-axis Alarm Trigger Level 2, 16-bit unsigned (see Table 30

and Table 31 for the scale factor)

The ALM_x_MAG1 and ALM_x_MAG2 registers (see Table 45

to Table 48) provide two independent trigger settings for both

axes of acceleration data. They use the data format established

by the range settings in the REC_CTRL2 register (see Table 30)

and recording mode in REC_CTRL1[1:0] (see Table 27). For

example, when using the 0 g to 1 g mode for FFT analysis,

32,768 LSB is the closest setting to 500 mg. Therefore, set

ALM_Y_MAG2 = 0x8000 (DIN = 0xAB80, 0xAA00) to set the

critical alarm to 500 mg, when using the 0 g to 1 g range option

in REC_CTRL2 for FFT records. See Table 30 and Table 31 for

more information about formatting each trigger level. Note that

trigger settings that are associated with Alarm 2 should be

greater than the trigger settings for Alarm 1. In other words, the

alarm magnitude settings should meet the following criteria:

Table 49. ALM_S_MAG

Page 1-6, Low Byte Address = 0x2E, Read/Write

Bits

Description (Default = 0x0000)

[15:0] System alarm trigger level, data format matches target

from ALM_CTRL[4]

Enable Alarm Settings

Before configuring the spectral alarm registers, clear their

current contents by setting GLOB_CMD[9] = 1 (DIN = 0xB702).

After completing the spectral alarm band definitions, save

the settings by setting GLOB_CMD[12] = 1 (DIN = 0xB710).

The device ignores the save command if any of these locations

has already been written to.

ALM_X_MAG2 > ALM_X_MAG1

ALM_Y_MAG2 > ALM_Y_MAG1

ALARM INDICATOR SIGNALS

GPO_CTRL[5:0] (see Table 83) and ALM_CTRL[6] (see Table

41) provide controls for establishing DO1 and DO2 as dedicated

alarm output indicator signals. Use GPO_CTRL[5:0] to select the

alarm function for DO1 and/or DO2; then set ALM_CTRL[6] = 1

to enable DO1 to serve as an Alarm 1 indi-cator and DO2 as an

Alarm 2 indicator. This setting establishes DO1 to indicate

Alarm 1 (warning) conditions and DO2 to indicate Alarm 2

(critical) conditions.

Table 45. ALM_X_MAG1

Page 1-6, Low Byte Address = 0x24, Read/Write

Bits

Description (Default = 0x0000)

[15:0] X-axis Alarm Trigger Level 1, 16-bit unsigned (see Table 30

and Table 31 for the scale factor)

Table 46. ALM_Y_MAG1

Page 1-6, Low Byte Address = 0x26, Read/Write

Bits

Description (Default = 0x0000)

ALARM FLAGS AND CONDITIONS

[15:0] Y-axis Alarm Trigger Level 1, 16-bit unsigned (see Table 30

and Table 31 for the scale factor)

The FFT header (see Table 69) contains both generic alarm flags

(DIAG_STAT[13:8]; seeTable 84) and spectral band-specific

alarm flags (ALM_x_STAT; see Table 50, Table 51). The FFT

header also contains magnitude (ALM_x_PEAK; see Table 52,

Table 53) and frequency information (ALM_x_FREQ; see Table

54, Table 55) associated with the highest magnitude of vibration

content in the record.

Rev. PrA | Page 24 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

ALARM STATUS

WORST-CASE CONDITION MONITORING

The ALM_x_STAT registers (see Table 50, Table 51) provide

alarm bits for each spectral band on the current sample rate

option.

The ALM_x_PEAK registers (see Table 52, Table 53) contain the

peak magnitude for the worst-case alarm condition in each axis.

The ALM_x_FREQ registers (see Table 54, Table 55) contain the

frequency bin number for the worst-case alarm condition.

Table 50. ALM_X_STAT

Low Byte Address = 0x38, Read Only

Table 52. ALM_X_PEAK

Page 1-6, Low Byte Address = 0x3C, Read Only

Bits

15

14

13

12

11

10

9

ꢀ

7

6

5

Description (Default = 0x0000)

Alarm 2 on Band 6; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 6; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 5; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 5; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 4; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 4; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 3; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 3; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 2; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 2; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 1; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 1; 1 = alarm set, 0 = no alarm

Not used

Bits

Description (Default = 0x0000)

[15:0]

Alarm peak, x-axis, accelerometer data format

Table 53. ALM_Y_PEAK

Page 1-6, Low Byte Address = 0x3E, Read Only

Bits

Description (Default = 0x0000)

[15:0]

Alarm peak, y-axis, accelerometer data format

Table 54. ALM_X_FREQ

Page 1-6, Low Byte Address = 0x44, Read Only

Bits

Description (Default = 0x0000)

[15:ꢀ]

[7:0]

Not used

4

3

Alarm frequency for x-axis peak alarm level,

FFT bin number; range = 0 to 255

[2:0]

Most critical alarm condition, spectral band; range = 1 to 6

Table 55. ALM_Y_FREQ

Page 1-6, Low Byte Address = 0x46, Read Only

Table 51. ALM_Y_STAT

Low Byte Address = 0x3C, Read Only

Bits

Description (Default = 0x0000)

Bits

15

14

13

12

11

10

9

ꢀ

7

6

5

Description (Default = 0x0000)

[15:ꢀ]

[7:0]

Not used

Alarm 2 on Band 6; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 6; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 5; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 5; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 4; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 4; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 3; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 3; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 2; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 2; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 1; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 1; 1 = alarm set, 0 = no alarm

Not used

Alarm frequency for y-axis peak alarm level,

FFT bin number; range = 0 to 255

4

3

[2:0]

Most critical alarm condition, spectral band; range = 1 to 6

Rev. PrA | Page 25 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

READING OUTPUT DATA

After the ADIS16229 updates the ADIS16000 with its data, it is

available in the data buffer and FFT records (if selected). In

manual time capture mode, the record for each axis contains 512

samples. In manual and automatic FFT mode, each record

contains the 256-point FFT result for each accelerometer axis.

Table 56 provides a summary of registers that provide access to

processed sensor data.

Table 57. BUF_PNTR

Page 1-6, Low Byte Address =10, Read/Write

Bits

Description (Default = 0x0000)

[15:9]

[ꢀ:0]

Not used

Data bits; range = 0 to 255 (FFT), 0 to 511 (time)

ACCESSING FFT RECORD DATA

The FFT records can be stored in flash memory. The REC_PNTR

register (see Table 58) and GLOB_CMD[13] (see Table 74)

provide access to the FFT records, as shown in Figure 22. For

example, set REC_PNTR[7:0] = 0x0A (DIN = 0x940A) and

GLOB_CMD[13] = 1 (DIN = 0xB720) to load FFT Record 10 in

the FFT buffer for SPI/register access.

Table 56. Output Data Registers

Register

Address Description

TEMP_OUT

SUPPLY_OUT

BUF_PNTR

REC_PNTR

X_BUF

Y_BUF

GLOB_CMD

TIME_STAMP_L 0x40

TIME_STAMP_H 0x42

0x0A

0x0C

0x12

0x14

0x06

0x0ꢀ

0x36

Internal temperature

Internal power supply

Data buffer index pointer

FFT record index pointer

X-axis accelerometer buffer

Y- axis accelerometer buffer

FFT record retrieve command

Time stamp, lower word

Table 58. REC_PNTR

Page 1-6, Low Byte Address = 0x14, Read/Write

Bits

Description (Default = 0x0000)

[15:4]

[3:0]

Not used

Data bits

Time stamp, upper word

REC_INFO1

REC_INFO2

0x4C

0x4E

FFT record header information

READING DATA FROM THE DATA BUFFER

After completing a spectral record and updating each data

buffer, the ADIS16000 loads the first data sample from each

data buffer into the x_BUF registers (see Table 59 and Table 60)

and sets the buffer index pointer in the BUF_PNTR register

(see Table 57) to 0x0000. The index pointer determines which

data samples load into the x_BUF registers. For example, writing

0x009F to the BUF_PNTR register (DIN = 0x9300, DIN =

0x929F) causes the 160th sample in each data buffer location to

load into the x_BUF registers. The index pointer increments

with every x_BUF read command, which causes the next set of

capture data to load into each capture buffer register

Figure 22. FFT Record Access

automatically. This enables an efficient method for reading all

256 samples in a record, using sequential read commands,

without having to manipulate the BUF_PNTR register.

Figure 21. Data Buffer Structure and Operation

Rev. PrA | Page 26 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

DATA FORMAT

REAL-TIME DATA COLLECTION

Table 59 and Table 60 list the bit assignments for the x_BUF

registers. The acceleration data format depends on the range

scale setting in REC_CTRL2 (see Table 30) and the recording

mode settings in REC_CTRL1 (see Table 27). Table 61 provides

some data formatting examples for the FFT mode, and Table 62

offers some data formatting examples for the16-bit, twos

complement format used in manual time mode.

When using real-time mode, select the output channel by

reading the associated x_BUF register. For example, set DIN =

0x1600 to select the y-axis sensor for sampling. After selecting

the channel, use the data-ready signal to trigger subsequent data

reading of the Y_BUF register. In this mode, use the time domain

data formatting for a range setting of 20 g, as shown in Table 31.

POWER SUPPLY/TEMPERATURE

Table 59. X_BUF

Low Byte Address = 0x06, Read Only

At the end of each spectral record, the ADIS16229 also

measures power supply and internal temperature. It

accumulates a 5.12 ms record of power supply measurements at

a sample rate of 50 kHz and takes 64 samples of internal

temperature data over a period of 1.7 ms. The average of the

power supply and internal tempera-ture loads into the

SUPPLY_OUT register (see

Bits

Description (Default = 0x8000)

[15:0]

X-acceleration data buffer register.

See Table 31 for scale sensitivity.

Format = twos complement (time), binary (FFT).

Table 60. Y_BUF

Low Byte Address = 0x08, Read Only

Table 64 and Table 65) and the TEMP_OUT registers (See

Table 66 and Table 67), respectively. When using real-time

mode, these registers update only when this mode starts.

Bits

Description (Default = 0x8000)

[15:0]

Y-acceleration data buffer register.

See Table 31 for scale sensitivity.

Table 63. SUPPLY_OUT

Page 0, Low Byte Address = 0x0C, Read Only

Format = twos complement (time), binary (FFT).

Bits

Description (Default = 0x8000)

Table 61. FFT Mode, 5 g Range, Data Format Examples

[15:12] Not used

[11:0]

Acceleration (mg) LSB

Hex

Binary

Power supply, binary, 3.3 V = 0xAꢀF, 1.22 mV/LSB

4,999.9237

100 × 5 ÷ 65,536

2 × 5 ÷ 65,536

1 × 5 ÷ 65,536

0

65,535

100

2

1

0

0xFFFF

1111 1111 1111 1111

0x0064 0000 0000 0110 0100

0x0002 0000 0000 0000 0010

0x0001 0000 0000 0000 0001

0x0000 0000 0000 0000 0000

Table 64. SUPPLY_OUT

Page 1- 6, Low Byte Address = 0x0A, Read Only

Bits

Description (Default = 0x8000)

[15:12] Not used

Table 62. Manual Time Mode, 5 g Range, Data Format

Examples

[11:0]

Power supply, binary, 3.3 V = 0xAꢀF, 1.22 mV/LSB

Acceleration (mg) LSB

Hex

Binary

Table 65. Power Supply Data Format Examples

+4999.ꢀ47

~1000

+2 × 5 ÷ 32,76ꢀ

+1 × 5 ÷ 32,76ꢀ

0

+32,767 0x7FFF

+6,554

+2

+1

0

1111 1111 1111 1111

Supply Level (V) LSB

Hex

Binary

0x199A 0001 0001 10011010

0x0002 0000 0000 0000 0010

0x0001 0000 0000 0000 0001

0x0000 0000 0000 0000 0000

0xFFFF

0xFFFE

3.6

2949

2704

2703

2702

25ꢀ0

0xBꢀ5

0xA90

0xAꢀF

0xAꢀE

0xA14

1011 1000 0101

1010 1001 0000

1010 1000 1111

1010 1000 1110

1010 0001 0100

3.3 + 0.0012207

3.3

3.3 − 0.0012207

3.15

−1 × 5 ÷ 32,76ꢀ

−2 × 5 ÷ 32,76ꢀ

~−1000

−1

−2

−6554

1111 1111 1111 1111

1111 1111 1111 1110

0xE666 1110 0110 0110 0110

−5000

−32,76ꢀ 0xꢀ000 1000 0000 0000 0000

Table 66. TEMP_OUT

Page 0, Low Byte Address = 0x0E, Read Only

Bits Description (Default = 0x8000)

[15:12] Not used

[11:0]

Temperature data, offset binary, 127ꢀ LSB = +25°C,

−0.47°C/LSB

Table 67. TEMP_OUT

Page 1-6, Low Byte Address = 0x0C8, Read Only

Bits

[15:12] Not used

[11:0]

Temperature data, offset binary, 127ꢀ LSB = +25°C,

Description (Default = 0x8000)

Rev. PrA | Page 27 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

−0.47°C/LSB

Table 68. Internal Temperature Data Format Examples

Temperature (°C) LSB

Hex

Binary

125

25 + 0.47

25

25 − 0.47

0

−40

1065

1277

127ꢀ

1279

1331

1416

0x429

0x4FD

0x4FE

0x4FF

0x533

0x5ꢀꢀ

0100 0010 1001

0100 1111 1101

0100 1111 1110

0100 1111 1111

0101 0011 0011

0101 1000 1000

Rev. PrA | Page 2ꢀ of 37

Preliminary Technical Data

ADIS16000/ADIS16229

Table 71. REC_INFO2

Page 1-6, Low Byte Address = 0x4E, Read Only

FFT EVENT HEADER

Each FFT record has an FFT header that contains information

that fills all of the registers listed in Table 69. The information

in these registers contains recording time, record configuration

settings, status/error flags, and several alarm outputs. The registers

listed in Table 69 update with every record event and also update

with record-specific information when using GLOB_CMD[13]

(see Table 74) to retrieve a data set from the FFT record in flash

memory.

Bits

Description

[15:4]

[3:0]

Not used (don’t care)

AVG_CNT setting

The TIME_STMP_x registers (see Table 72 and Table 73)

provide a relative time stamp that identifies the time for the

current FFT record.

Table 72. TIME_STMP_L

Page 1-6, Low Byte Address = 0x40, Read Only

Table 69. FFT Header Register Information

Bits

Description (Default = 0x0000)

Register

Address

Description

[15:0]

Record time stamp, low integer, binary, seconds

DIAG_STAT

0x34

Alarm status

ALM_X_STAT

ALM_Y_STAT

ALM_X_PEAK

ALM_Y_PEAK

TIME_STMP_L

0x3ꢀ

X-axis alarm status

Y-axis alarm status

X-axis alarm peak

Y-axis alarm peak

Time stamp, lower word

Time stamp, upper word

X-axis alarm frequency of peak alarm

Y-axis alarm frequency of peak alarm

FFT record header information

Table 73. TIME_STMP_H

Page 1-6, Low Byte Address = 0x42, Read Only

0x3A

0x3C

0x3E

Bits

Description (Default = 0x0000)

[15:0]

Record time stamp, high integer, binary, seconds

0x40

TIME_STMP_H 0x42

ALM_X_FREQ

ALM_Y_FREQ

REC_INFO1

0x44

0x46

0x4C

0x4E

REC_INFO2

The REC_INFO1 register (see Table 70) and the REC_INFO2

register (see Table 71) capture the settings associated with the

current FFT record.

Table 70. REC_INFO1

Page 1-6, Low Byte Address = 0x4E), Read Only

Bits

[15:14] Sample rate option

00 = SR0, 01 = SR1, 10 = SR2, 11 = SR3

[13:12] Window setting

00 = rectangular, 01 = Hanning, 10 = flat top, 11 = N/A

[11:10] Signal range

00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g

Description

[9:ꢀ]

[7:0]

Not used (don’t care)

FFT averages; range = 1 to 255

Rev. PrA | Page 29 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

SYSTEM TOOLS

GLOBAL COMMANDS

Table 77. LOT_ID2

Page 0, Low Byte Address = 0x1C, Read Only

The GLOB_CMD register (see Table 74) provides an array of

single-write commands for convenience. Setting the assigned bit

to 1 activates each function. When the function completes, the

bit restores itself to 0. For example, clear the capture buffers by

setting GLOB_CMD[8] = 1 (DIN = 0xB701). All of the commands

in the GLOB_CMD register require that the power supply be

within normal limits for the execution times listed in Table 74.

Bits

Description

[15:0]

Lot identification code

Table 78. LOT_ID2

Page 1-6, Low Byte Address = 0x6A, Read Only

Bits

Description

Table 74. GLOB_CMD

Page 1-6, Low Byte Address = 0x36, Write Only

[15:0]

Lot identification code

Bits

Description

Execution Time

15

Clear autonull correction

35 μs

14

Retrieve spectral alarm band infor-

mation from the ALM_PNTR setting

40 μs

Table 79. PROD_ID

Page 0, Low Byte Address = 0x16), Read Only

13

12

Retrieve record data from flash

memory

1.9 ms

Bits

Description (Default = 0x3E80

Save spectral alarm band registers 461 μs

to SRAM

[15:0]

0x3Eꢀ0 = 16,000

11

10

9

Record start/stop

Set BUF_PNTR = 0x0000

Clear spectral alarm band

registers from flash memory

Clear records

Software reset

Save registers to flash memory

Flash test, compare sum of flash

memory with factory value

Clear DIAG_STAT register

Restore factory register settings

and clear the capture buffers

Self-test, result in DIAG_STAT[5]

Power-down

Autonull

N/A

36 μs

25.ꢀ ms

Table 80. PROD_ID

Page 0, Low Byte Address = 0x48), Read Only

Bits

Description (Default = 0x3E80

ꢀ

7

6

5

25.9 ms

52 ms

29.3 ms

5 ms

[15:0]

0x3F65 = 16,229

Table 81. SERIAL_NUM (Base Address = 0x58), Read Only

Bits

Description

4

3

36 μs

ꢀ4 ms

[15:0]

Serial number, lot specific

Table 82 shows a blank register that is available for writing user-

specific identification.

2

1

0

32.9 ms

N/A

ꢀ22 ms

Table 82. USER_ID (Base Address = 0x5C), Read/Write

Bits

Description (Default = 0x000)

[15:0]

User-written identification

Table 83. GPO_CTRL

Page 0, Low Byte Address = 0x2A, Read/Write

DEVICE IDENTIFICATION

Table 75. LOT_ID1

Page = 0, Low Byte Address = 0x1A, Read Only

Bits

Description (Default = 0x)

[15:6]

[5:4]

Not used

Bits

Description

DO2 Function selection

00 = General purpose

01 = Alarm indicator

[15:0]

Lot identification code

10 = Busy indicator/data-ready (real-time mode)

11 = Not used

DO1 Function selection

00 = General purpose

01 = Alarm indicator

Table 76. LOT_ID1

Page = 1-6, Low Byte Address = 0x68, Read Only

[3:2]

Bits

Description

[15:0]

Lot identification code

10 = Busy indicator/data-ready (real-time mode)

11 = Not used

1

DO2 Polarity

1 = active high

Rev. PrA | Page 30 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

0 = active low

0

DO1 Polarity

1 = active high

0 = active low

SELF-TEST

Set GLOB_CMD[2] = 1 (DIN = 0xBE02) (see Table 74) to run

an automatic self-test routine, which reports a pass/fail result to

DIAG_STAT[5] (see Table 84).

FLASH MEMORY MANAGEMENT

STATUS/ERROR FLAGS

Set GLOB_CMD[5] = 1 (DIN = 0xB620) to run an internal

checksum test on the flash memory, which reports a pass/fail

result to DIAG_STAT[6]. The FLASH_CNT register (see Table 85)

provides a running count of flash memory write cycles. This is a

tool for managing the endurance of the flash memory. Figure 23

quantifies the relationship between data retention and junction

temperature.

Critical system error flags are in the DIAG_STAT register for

each ADIS16229. These flags indicate various error or alarm

conditions that may influence system performance. Multiple

flags in these registers can be high at one time and the flags will

persist (go high again, after clearing) when the error conditions

continue to exist. The flags in bits 0 through 6 will remain in a

latch condition, until clearing the problem or clearing (using

Use GLOB_CMD[4]). The Alarm flags (upper byte) will latch if

ALM_CTRL[7] = 1 (See Table 41)

Table 85. FLASH_CNT

Page 1-6, Low Byte Address = 0x04, Read Only

Bits

Description

Table 84. DIAG_STAT

Page 1-6, Low Byte Address = 0x34, Read/Write

[15:0]

Binary counter for writing to flash memory

Bits

15

14

13

12

11

10

9

ꢀ

7

6

[5:4]

3

Description (Default = 0x)

Not used

600

System alarm (1 = error condition exists, 0 = no error)

Not used

Sensor Node 6 (1 = alarm condition, 0 = no alarm)

Sensor Node 5 (1 = alarm condition, 0 = no alarm)

Sensor Node 4 (1 = alarm condition, 0 = no alarm)

Sensor Node 3 (1 = alarm condition, 0 = no alarm)

Sensor Node 2 (1 = alarm condition, 0 = no alarm)

Sensor Node 1 (1 = alarm condition, 0 = no alarm)

Flash memory failure, from GLOB_CMD[5] test

Not used

450

300

150

0

SPI communication failure (SCLKs ≠ even multiple of

16)

30

40

55

70

85

100

125

135

150

JUNCTION TEMPERATURE (°C)

2

1

0

Flash update failure

Power supply > 3.625 V

Power supply < 3.125 V

Figure 23. Flash®/EE Memory Data Retention

Rev. PrA | Page 31 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

APPLICATIONS INFORMATION

INTERFACE BOARD

The ADIS16COM1/PCBZ accessory provides a direct attachment

method for connecting the ADIS16000CMLZ directly to the

EVAL-ADIS evaluation system.

MATING CONNECTOR

TBD

Figure 25. Mating Connector Detail

Figure 24. PCB Assembly View and Dimensions

Figure 26. Electrical Schematic

Rev. PrA | Page 32 of 37

Preliminary Technical Data

OUTLINE DIMENSIONS

ADIS16000/ADIS16229

Rev. PrA | Page 33 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

Figure 27. 14-Lead Module with Connector Interface

(ML-14-2))

Dimensions shown in millimeters

Rev. PrA | Page 34 of 37

Preliminary Technical Data

ADIS16000/ADIS16229

Rev. PrA | Page 35 of 37

ADIS16000/ADIS16229

Preliminary Technical Data

Figure 28. Remote Sensor with SMA Antenna Interface

(ML-1-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

ADIS16000AMLZ

−40°C to +ꢀ5°C

14-Lead Module with Connector Interface and

ML-14-2

SMA Antenna Interface

ADIS16COM1/PCBZ

ADIS16229AMLZ

Evaluation Board

Sensor Module with SMA Antenna Interface

−40°C to +ꢀ5°C

ML-1-1

¹Z = RoHS Compliant Part.

Rev. PrA | Page 36 of 37

Data Sheet

NOTES

ADIS16000/ADIS16229

registered trademarks are the property of their respective owners.

PR11483-0-5/13(PrA)

Rev. PrA | Page 37 of 37


型号：	ADIS16000
厂家：	ADI
描述：	Digital MEMS Vibration Sensor w/ Embedded RF Transceiver 数字MEMS振动传感器瓦特/嵌入式射频收发器传感器射频
文件：	总37页 (文件大小：567K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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