ADG3246BRUZ [ADI]
10-BIT DRIVER, TRUE OUTPUT, PDSO24, MS-153AD, TSSOP-24;
| 型号： | ADG3246BRUZ |
| 厂家： | 
ADI |
| 描述： | 10-BIT DRIVER, TRUE OUTPUT, PDSO24, MS-153AD, TSSOP-24 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总13页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V/3.3 V, 10-Bit, 2-Port
Level Translating, Bus Switch
ADG3246
FEATURES
FUNCTIONAL BLOCK DIAGRAM
225 ps Propagation Delay through the Switch
4.5 ꢀ Switch Connection between Ports
Data Rate 1.244 Gbps
A0
B0
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Small Signal Bandwidth 610 MHz
Level Translation
3.3 V to 2.5 V
B9
A9
3.3 V to 1.8 V
2.5 V to 1.8 V
24-Lead LFCSP Package
APPLICATIONS
BE
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Signal Switching
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3246 is a 2.5 V or 3.3 V, 10-bit, 2-port digital switch.
It is designed on Analog Devices’ low voltage CMOS process,
which provides low power dissipation yet gives high switching
speed and very low on resistance, allowing inputs to be connected
to outputs without additional propagation delay or generating
additional ground bounce noise.
1. 3.3 V or 2.5 V supply operation
2. Extremely low propagation delay through switch
3. 4.5 W switches connect inputs to outputs
4. Level/voltage translation
5.
24-lead 4 mm ¥ 4 mm LFCSP package
The switches are enabled by means of the bus enable (BE)
input signal. These digital switches allow bidirectional signals to
be switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs occurs. Similarly, if the device is oper-
ated from a 2.5 V supply and 2.5 V inputs are applied, the device
will translate the outputs to 1.8 V. In addition to this, the ADG3246
has a level translating select pin (SEL). When SEL is low, VCC is
reduced internally, allowing for level translation between 3.3 V
inputs and 1.8 V outputs. This makes the device suited to appli-
cations requiring level translation between different supplies,
such as converter to DSP/microcontroller interfacing.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003-2016 Analog Devices, Inc. All rights reserved.
ADG3246* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
• ADG3246 Material Declaration
• PCN-PDN Information
EVALUATION KITS
• Evaluation Board for 24-Lead TSSOP Devices in the
Switches and Multiplexers Portfolio
• Quality And Reliability
• Symbols and Footprints
DISCUSSIONS
View all ADG3246 EngineerZone Discussions.
DOCUMENTATION
Data Sheet
• ADG3246: 2.5 V/3.3 V, 10 Bit, 2 Port Level Translator, Bus
Switch Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
User Guides
• UG-1036: Evaluation Board for 24-Lead TSSOP Devices in
the Switches and Multiplexers Portfolio
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
REFERENCE MATERIALS
Product Selection Guide
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
• Switches and Multiplexers Product Selection Guide
Technical Articles
• CMOS Switches Offer High Performance in Low Power,
Wideband Applications
• Data-acquisition system uses fault protection
• Enhanced Multiplexing for MEMS Optical Cross Connects
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
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(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless
ADG3246–SPECIFICATIONS1 otherwise noted.)
B Version
Typ2
Parameter
Symbol
Conditions
Min
Max
Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
VINH
VINL
VINL
II
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
V
V
V
V
mA
mA
mA
V
V
V
Input Low Voltage
0.8
0.7
±1
±1
±1
2.9
2.1
2.1
Input Leakage Current
±0.01
±0.01
±0.01
2.5
1.8
1.8
OFF State Leakage Current
ON State Leakage Current
Maximum Pass Voltage
IOZ
0 £ A, B £ VCC
0 £ A, B £ VCC
VA/VB = VCC = SEL = 3.3 V, IO = –5 mA
VA/VB = VCC = SEL = 2.5 V, IO = –5 mA
VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 mA
VP
2.0
1.5
1.5
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
CA OFF
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
5
5
10
6
pF
pF
pF
pF
C
B OFF
CA, CB ON
CIN
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, tPD
4
tPHL, tPLH
CL = 50 pF, VCC = SEL = 3 V
0.225 ns
Propagation Delay Matching5
Bus Enable Time BE to A or B6
Bus Disable Time BE to A or B6
Bus Enable Time BE to A or B6
Bus Disable Time BE to A or B6
Bus Enable Time BE to A or B6
Bus Disable Time BE to A or B6
Maximum Data Rate
22.5
4.8
4.8
3.3
2.9
3
ps
ns
ns
ns
ns
ns
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 3.0 V tp 3.6 V; SEL = 0 V
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = 2.3 V to 2.7 V; SEL = VCC
1
1
0.5
0.5
0.5
0.5
3.2
3.2
2.2
1.7
2.2
1.75
1.244
50
2.6
ns
V
CC = SEL = 3.3 V; VA/VB = 2 V
Gbps
ps p-p
MHz
Channel Jitter
Operating Frequency—Bus Enable
VCC = SEL = 3.3 V; VA/VB = 2 V
fBE
10
DIGITAL SWITCH
On Resistance
RON
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
4.5
15
5
11
5
14
0.45
0.65
8
28
9
18
8
W
W
W
W
W
W
W
W
V
V
CC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA
CC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
V
V
CC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA
CC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA
On Resistance Matching
⌬RON
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
2.3
3.6
1
1.2
130
V
ICC
ICC
⌬ICC
Digital Inputs = 0 V or VCC; SEL = VCC
Digital Inputs = 0 V or VCC; SEL = 0 V
VCC = 3.6 V, BE = 3.0 V; SEL = VCC
0.001
0.65
mA
mA
mA
Increase in ICC per Input7
NOTES
1Temperature range is as follows: B Version: –40∞C to +85∞C.
2Typical values are at 25∞C, unless otherwise stated.
3Guaranteed by design, not subject to production test.
4The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6See Timing Measurement Information section.
7This current applies to the control pin (BE) only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
–2–
REV. A
ADG3246
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
LFCSP Package
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 35°C/W
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . . 25 mA per channel
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ORDERING GUIDE
Temperature
Range
Model1
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Package Option
CP-24-10
CP-24-10
ADG3246BCPZ
ADG3246BCPZ-REEL7
1 Z = RoHS Compliant Part.
−40°C to +85°C
−40°C to +85°C
Table I. Pin Description
Table II. Truth Table
BE SEL* Function
Mnemonic
Description
Bus Enable (Active Low)
Level Translation Select
Port A, Inputs or Outputs
Port B, Inputs or Outputs
Exposed Pad. It is
recommended that the
exposed pad be thermally
connected to a copper plane
for enhanced thermal
performance. The pad
should be grounded as well.
BE
SEL
Ax
Bx
EPAD
L
L
H
L
H
X
A = B, 3.3 V to 1.8 V Level Shifting
A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
Disconnect
*SEL = 0 only when VDD = 3.3 V 10%
PIN CONFIGURATION
24-Lead LFCSP
1
2
3
18
17
16
15
14
13
SEL
A5
BE
B0
B1
B2
B3
B4
A6
ADG3246
TOP VIEW
(Not to Scale)
A7 4
5
6
A8
A9
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED
TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
THE PAD SHOULD BE GROUNDED AS WELL.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3246 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–3–
REV. A
ADG3246
TERMINOLOGY
VCC
GND
VINH
VINL
II
Positive Power Supply Voltage.
Ground (0 V) Reference.
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
IOZ
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
IOL
VP
Maximum Pass Voltage. The maximum pass voltage relates to the clipped output voltage of an NMOS device
when the switch input voltage is equal to the supply voltage.
RON
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
⌬RON
CX OFF
CX ON
CIN
On Resistance Match between Any Two Channels, i.e., RON Max – RON Min.
OFF Switch Capacitance.
ON Switch Capacitance.
Control Input Capacitance. This consists of BE and SEL.
ICC
Quiescent Power Supply Current. It is measured when all control inputs are at a logic HIGH or LOW level and
the switches are OFF.
⌬ICC
Extra power supply current component for the BE control input when the input is not criven at the supplies.
tPLH, tPHL
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
RON ¥ CL, where CL is the load capacitance.
tPZH, tPZL
tPHZ, tPLZ
Bus Enable Times. These are times taken to cross the VT voltage at the switch output when the switch turns on in
response to the control signal, BE.
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control
signal. It is measured as the time taken for the output voltage to change by V⌬ from the original quiescent level,
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.
Channel Jitter
fBE
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
Operating Frequency of Bus Enable. This is the maximum frequency at which bus enable (BE) can be toggled.
–4–
REV. A
Typical Performance Characteristics–ADG3246
40
35
30
25
40
35
30
25
20
15
10
5
40
V
= 3V
V
= 3V
V
= 2.3V
CC
CC
T
= 25ꢁC
CC
T
= 25ꢁC
A
T
= 25ꢁC
35
30
25
20
15
10
5
A
A
SEL = 0V
SEL = V
SEL = V
CC
CC
V
= 3.3V
= 3.6V
V
= 3.3V
V
= 2.5V
= 2.7V
CC
CC
CC
20
15
10
5
V
CC
V
CC
V
= 3.6V
CC
0
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0 3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
V
/V – V
V
/V – V
A
B
V
/V – V
A
B
A
B
TPC 3. On Resistance vs.
Input Voltage
TPC 1. On Resistance vs.
Input Voltage
TPC 2. On Resistance vs.
Input Voltage
3.0
2.5
20
15
10
5
15
10
5
V
= 3.6V
T
= 25ꢁC
CC
A
V
= 3.3V
V
= 2.5V
CC
CC
SEL = V
CC
= –5ꢄA
SEL = V
SEL = V
CC
I
CC
O
2.0
1.5
V
= 3.3V
CC
ꢂ85ꢁC
V
= 3V
CC
ꢂ85ꢁC
1.0
0.5
0
ꢃ40ꢁC
ꢂ25ꢁC
ꢂ25ꢁC
ꢃ40ꢁC
0
0
0
0.5
1.0
1.5
V
2.0 2.5
– V
3.0 3.5
1.0
/V – V
2.0
0
0.5
1.5
0
0.5
V
1.0
1.2
CC
V
A
B
/V – V
A B
TPC 5. On Resistance vs. Input
Voltage for Different Temperatures
TPC 6. Pass Voltage vs. VCC
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
1800
1600
1400
1200
1000
800
2.5
2.5
T
= 25ꢁC
A
T
= 25ꢁC
T
= 25ꢁC
A
V
= 2.7V
= 2.5V
A
V
= 3.6V
CC
CC
SEL = V
SEL = 0V
I = –5ꢄA
O
CC
= –5ꢄA
2.0
1.5
1.0
0.5
I
2.0
1.5
1.0
0.5
O
V
= 3.3V, SEL = 0V
CC
V
CC
V
= 3.3V
CC
V
= 2.3V
V
= 3V
CC
CC
600
V
= SEL = 3.3V
CC
400
200
V
= SEL = 2.5V
CC
0
0
0
0
0.5
1.0
1.5
– V
2.0
2.5
3.0
0
2
4
6
8
10 12 14 16 18 20
0
0.5
1.0
1.5
V
2.0
– V
2.5
3.0 3.5
V
ENABLE FREQUENCY – MHz
CC
CC
TPC 9. ICC vs. Enable Frequency
TPC 7. Pass Voltage vs. VCC
TPC 8. Pass Voltage vs. VCC
–5–
REV. A
ADG3246
3.0
3.0
2.5
2.0
1.5
0
T
= 25ꢁC
A
T
= 25ꢁC
T
V
= 25ꢁC
A
A
–0.2
SEL = V
V
= 0V
= V
CC
A
A CC
2.5
2.0
1.5
1.0
ON OFF
= InF
–0.4
–0.6
–0.8
–1.0
–1.2
BE = 0
BE = 0
C
L
V
= SEL = 3.3V
CC
V
= 3.3V; SEL = 0V
CC
V
= 2.5V
CC
V
= SEL = 3.3V
CC
1.0
V
= SEL = 2.5V
CC
–1.4
–1.6
V
= 3.3V
1.5
CC
0.5
0
0.5
0
–1.8
–2.0
V
= 3.3V; SEL = 0V
CC
V
= SEL = 2.5V
CC
0
0.02
0.04
0.06
– A
0.08
0.10
0
0.5
1.0
2.0
/V – V
2.5
3.0
–0.10 –0.08
–0.06
–0.04
I – A
O
–0.02
0
V
I
A
B
O
TPC 10. Output Low Characteristic
TPC 11. Output High Characteristic
TPC 12. Charge Injection vs.
Source Voltage
–20
–30
0
–20
T
V
= 25ꢁC
T
= 25ꢁC
A
A
= 3.3V/2.5V
V = 3.3V/2.5V
SEL =V
–30
–40
–50
–60
–70
–80
T
V
= 25ꢁC
CC
CC
–2
–4
A
SEL =V
= 3.3V/2.5V
CC
ADJACENT CHANNELS
= 0dBm
CC
= 0dBm
CC
–40
–50
–60
–70
–80
–90
–100
V
SEL =V
V
N/W ANALYZER:
R
IN
N/W ANALYZER:
= R = 50ꢀ
CC
V
= 0dBm
IN
N/W ANALYZER:
= R = 50ꢀ
IN
R
L
S
R
–6
–8
L
= R = 50ꢀ
S
L
S
–10
–12
–14
–90
–100
0.03 0.1
1
10
100
1000
0.03 0.1
1
10
100
1000
0.03 0.1
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
TPC 13. Bandwidth vs. Frequency
TPC 15. Off Isolation vs.
Frequency
TPC 14. Crosstalk vs. Frequency
100
90
80
70
60
50
40
30
20
10
0
3.5
2.5
V
= SEL = 3.3V
= 2V p-p
CC
ENABLE
3.0
V
IN
ENABLE
2.0
V
= SEL = 3.3V
CC
20dB ATTENUATION
DISABLE
ENABLE
V
= SEL = 2.5V
2.5
2.0
1.5
1.0
CC
DISABLE
1.5
1.0
V
= 3.3V, SEL = 0V
CC
DISABLE
0.5
0
0.5
0
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
DATA RATE – Gbps
–40 –20
0
20
40
60
80 100
–40 –20
0
20
40
60
80
100
TEMPERATURE – ꢁC
TEMPERATURE – ꢁC
TPC 16. Enable/Disable Time
vs. Temperature
TPC 17. Enable/Disable Time
vs. Temperature
TPC 18. Jitter vs. Data Rate;
PRBS 31
–6–
REV. A
ADG3246
100
95
90
85
80
75
V
= SEL = 3.3V
= 2V p-p
CC
V
IN
20dB ATTENUATION
70
65
60
55
50
V
= 2.5V
20dB
ATTENUATION
CC
V
= 3.3V
37mV/DIV
200ps/DIV
20dB
ATTENUATION
CC
SEL = 2.5V
= 2V p-p
35mV/DIV
100ps/DIV
SEL = 3.3V
V
T
= 25ꢁC
IN
A
V
= 2V p-p
T
= 25ꢁC
IN
A
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) ꢂ 100%
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
DATA RATE – Gbps
TPC 19. Eye Width vs. Data
Rate; PRBS 31
TPC 20. Eye Pattern; 1.244
Gbps, VCC = 3.3 V, PRBS 31
TPC 21. Eye Pattern; 1 Gbps,
VCC = 2.5 V, PRBS 31
20dB
ATTENUATION
= 3.3V
50.1mV/DIV
50ps/DIV
V
CC
T
= 25ꢁC
SEL = 3.3V
= 2V p-p
A
V
IN
TPC 22. Jitter @ 1.244 Gbps,
PRBS 31
–7–
REV. A
ADG3246
TIMING MEASUREMENT INFORMATION
For the following load circuit and waveforms, the notation that is used is VIN and VOUT where
VIN = VA and VOUT = VB or VIN = VB and VOUT = VA
V
IH
V
CC
CONTROL
INPUT BE
2 ꢂ V
CC
V
T
SW1
0V
tPLH
tPHL
GND
V
H
R
L
V
V
V
T
V
OUT
IN
OUT
PULSE
GENERATOR
V
L
D.U.T.
R
R
C
L
Figure 2. Propagation Delay
L
T
NOTES
PULSE GENERATOR FOR ALL PULSES: tR Յ 2.5ns, tF Յ 2.5ns,
FREQUENCY Յ 10MHz.
C
R
INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO Z
L
T
OUT
OF THE PULSE GENERATOR.
Figure 1. Load Circuit
Test Conditions
Symbol
VCC = 3.3 V ± 0.3 V (SEL = VCC
)
VCC = 2.5 V ± 0.2 V (SEL = VCC
)
VCC = 3.3 V ± 0.3 V (SEL = 0 V) Unit
RL
VD
CL
VT
500
300
50
500
150
30
500
150
30
W
mV
pF
V
1.5
0.9
0.9
DISABLE
ENABLE
V
INH
V
CONTROL INPUT BE
T
0V
tPZL
tPLZ
V
Table III. Switch Position
CC
V
CC
V
OUT
V
V
= 0V
= V
T
IN
V
V
+V
ꢃ
L
L
SW1 @ 2V
CC
TEST
PLZ, tPZL
tPHZ, tPZH
S1
tPZH
tPHZ
t
2 ¥ VCC
GND
V
V
H
H
V
OUT
V
–V
V
IN
CC
ꢃ
T
SW1 @ GND
0V
0V
Figure 3. Enable and Disable Times
–8–
REV. A
ADG3246
BUS SWITCH APPLICATIONS
2.5 V to 1.8 V Translation
Mixed Voltage Operation, Level Translation
Bus switches can be used to provide an ideal solution for interfac-
ing between mixed voltage systems. The ADG3246 is suitable
for applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or from 3.3 V
directly to 2.5 V.
When VCC is 2.5 V (SEL = VCC) and the input signal range is 0 V
to VCC, the maximum output signal will, as before, be clamped
to within a voltage threshold below the VCC supply.
2.5V
Figure 4 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V micro-
processor. The microprocessor may not have 3.3 V tolerant inputs,
therefore placing the ADG3246 between the two devices allows
the devices to communicate easily. The bus switch directly
connects the two blocks, thus introducing minimal propagation
delay, timing skew, or noise.
ADG3246
2.5V
1.8V
Figure 7. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
In this case, the output will be limited to approximately 1.8 V,
as shown in Figure 7.
3.3V
3.3V
2.5V
V
OUT
2.5V SUPPLY
SEL = 2.5V
2.5V
3.3V ADC
MICROPROCESSOR
1.8V
Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
V
IN
3.3 V to 2.5 V Translation
0V
SWITCH
INPUT
2.5V
When VCC is 3.3 V (SEL = VCC) and the input signal range is 0 V
to VCC, the maximum output signal will be clamped to within a
voltage threshold below the VCC supply.
Figure 8. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
3.3 V to 1.8 V Translation
3.3V
The ADG3246 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
SEL pin.
3.3V
2.5V
2.5V
2.5V
SEL pin: An active low control pin. SEL activates internal cir-
cuitry in the ADG3246 that allows voltage translation between
3.3 V devices and 1.8 V devices.
ADG3246
3.3V
Figure 5. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
In this case, the output will be limited to 2.5 V, as shown in
Figure 6.
3.3V
ADG3246
1.8V
V
OUT
3.3V SUPPLY
SEL = 3.3V
2.5V
Figure 9. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
V
IN
0V
SWITCH
INPUT
3.3V
SEL is unused, it should be tied directly to VCC
.
Figure 6. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
This device can be used for translation from 2.5 V to 3.3 V
devices and also between two 3.3 V devices.
–9–
REV. A
ADG3246
V
OUT
3.3V SUPPLY
SEL = 0V
PLUG-IN
CARD (1)
1.8V
CARD I/O
CARD I/O
CPU
RAM
PLUG-IN
CARD (2)
V
IN
0V
SWITCH
INPUT
3.3V
Figure 10. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
Bus Isolation
Figure 12. ADG3246 in a Hot Plug Application
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3246 is designed specifically for
applications that do not need drive yet require simple logic func-
tions, it solves this requirement. The device isolates access to the
bus, thus minimizing capacitance loading.
There are many systems that require the ability to handle hot
swapping, such as docking stations, PCI boards for servers, and
line cards for telecommunications switches. If the bus can be
isolated prior to insertion or removal, then there is more control
over the hot swap event. This isolation can be achieved using a
bus switch. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the back plane before any other signal or power pins.
LOAD A
LOAD C
BUS/
BACKPLANE
Analog Switching
Bus switches can be used in many analog switching applications;
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself consisting solely of an NMOS
switch limits the operating voltage (see TPC 1 for a typical plot),
but in many cases, this does not present an issue.
LOAD B
LOAD D
BUS SWITCH
LOCATION
Figure 11. Location of Bus Switched in a Bus
Isolation Application
Hot Plug and Hot Swap Isolation
The ADG3246 is suitable for hot swap and hot plug applications.
The output signal of the ADG3246 is limited to a voltage that is
below the VCC supply, as shown in Figures 6, 8, and 10. There-
fore the switch acts like a buffer to take the impact from hot
insertion, protecting vital and expensive chipsets from damage.
High Impedance During Power-Up/Power-Down
To ensure the high impedance state during power-up or power-
down, BE should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
In hot-plug applications, the system cannot be shutdown when
new hardware is being added. To overcome this, a bus switch
can be positioned on the backplane between the bus devices and
the hot plug connectors. The bus switch is turned off during hot
plug. Figure 12 shows a typical example of this type of application.
PACKAGE AND PINOUT
The ADG3246 is packaged in a tiny 24-lead LFCSP package.
The area of the LFCSP option is 16 mm2. This makes the
LFCSP option an excellent choice for space-constrained
applications.
–10–
REV. A
ADG3246
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
24
19
0.50
18
1
6
BSC
EXPOSED
PAD
2.20
2.10 SQ
2.00
13
12
7
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
Figure 13. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 x 4 mm Body and 0.75 mm Package Height
(CP-24-10)
Dimensions shown in millimeters
–11–
REV. A
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