ADG3247 [ADI]
2.5 V/3.3 V, 16-Bit, 2-Port Level Translating, Bus Switch; 2.5 V / 3.3 V ， 16位， 2端口电平转换，总线开关
| 型号： | ADG3247 |
| 厂家： | 
ADI |
| 描述： | 2.5 V/3.3 V, 16-Bit, 2-Port Level Translating, Bus Switch |
| 文件： | 总12页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
2.5 V/3.3 V, 16-Bit, 2-Port
Level Translating, Bus Switch
Preliminary Technical Data
ADG3247
FEATURES
FUNCTIONAL BLOCK DIAGRAM
225 ps Propagation Delay through the Switch
4.5 ꢀ Switch Connection between Ports
Data Rate 1.244 Gbps
A0
B0
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Small Signal Bandwidth 610 MHz
Level Translation
A7
B7
BE1
3.3 V to 2.5 V
A8
B8
3.3 V to 1.8 V
2.5 V to 1.8 V
40-Lead 6 mm ꢁ 6 mm LFCSP and 38-Lead TSSOP
Packages
A15
B15
BE2
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Plug
Hot Swap
Analog Switching Applications
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3247 is a 2.5 V or 3.3 V 16-bit, 2-port digital switch.
It is designed on Analog Devices’ low voltage CMOS process,
which provides low power dissipation yet gives high switching
speed and very low on resistance, allowing inputs to be connected
to outputs without additional propagation delay or generating
additional ground bounce noise.
1. 3.3 V or 2.5 V supply operation
2. Extremely low propagation delay through switch
3. 4.5 Ω switches connect inputs to outputs
4. Level/voltage translation
5. 40-lead 6 mm ϫ 6 mm LFCSP and 38-lead TSSOP packages
The ADG3247 is organized as dual 8-bit bus switches with
separate Bus Enable (BEx) inputs. This allows the device to be
used as two 8-bit digital switches or one 16-bit bus switch. These
bus switches allow bidirectional signals to be switched when ON.
In the OFF condition, signal levels up to the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs occurs. Similarly, if the device is operated
from a 2.5 V supply and 2.5 V inputs are applied, the device will
translate the outputs to 1.8 V. In addition to this, the ADG3247
has a level translating select pin (SEL). When SEL is low, VCC is
reduced internally, allowing for level translation between 3.3 V
inputs and 1.8 V outputs. This makes the device suited to appli-
cations requiring level translation between different supplies, such
as converter to DSP/microcontroller interfacing.
REV. PrD
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
PRELIMINARY TECHNICAL DATA
(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise
ADG3247–SPECIFICATIONS1 noted.)
B Version
Typ2
Parameter
Symbol
Conditions
Min
Max
Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
VINH
VINL
VINL
II
IOZ
IOL
VP
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
V
V
V
V
µA
µA
µA
V
V
V
Input Low Voltage
0.8
0.7
1
1
1
2.9
2.1
2.1
Input Leakage Current
OFF State Leakage Current
ON State Leakage Current
Max Pass Voltage
0.01
0.01
0.01
2.5
1.8
1.8
0 Յ A, B Յ VCC
0 Յ A, B Յ VCC
VA/VB = VCC = SEL = 3.3 V, IO = –5 µA
VA/VB = VCC = SEL = 2.5 V, IO = –5 µA
VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 µA
2.0
1.5
1.5
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
CA OFF f = 1 MHz
CB OFF f = 1 MHz
CA, CB ON f = 1 MHz
5
5
10
6
pF
pF
pF
pF
CIN
f = 1 MHz
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, tPD
4
tPHL, tPLH CL = 50 pF, VCC
=
SEL = 3 V
0.225 ns
Propagation Delay Matching5
Bus Enable Time BEx to A or B6
Bus Disable Time BEx to A or B6
Bus Enable Time BEx to A or B6
Bus Disable Time BEx to A or B6
Bus Enable Time BEx to A or B6
Bus Disable Time BEx to A or B6
Max Data Rate
22.5
4.8
4.8
3.3
2.9
3
ps
ns
ns
ns
ns
ns
tPZH, tPZL VCC = 3.0 V to 3.6 V; SEL = VCC
tPHZ, tPLZ VCC = 3.0 V to 3.6 V; SEL = VCC
tPZH, tPZL VCC = 3.0 V to 3.6 V; SEL = 0 V
tPHZ, tPLZ VCC = 3.0 V to 3.6 V; SEL = 0 V
tPZH, tPZL VCC = 2.3 V to 2.7 V;SEL = VCC
tPHZ, tPLZ VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = SEL = 3.3 V; VA/VB = 2 V
1
1
0.5
0.5
0.5
0.5
3.2
3.2
2.2
1.7
2.2
1.75
1.244
50
2.6
ns
Gbps
ps p-p
MHz
Channel Jitter
Operating Frequency—Bus Enable
VCC = SEL = 3.3 V; VA/VB = 2 V
fBEx
10
DIGITAL SWITCH
On Resistance
RON
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
4.5
15
5
11
5
14
0.45
0.65
8
28
9
18
8
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
On Resistance Matching
∆RON
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
2.3
3.6
1
1.2
V
µA
mA
ICC
ICC
∆ICC
Digital Inputs = 0 V or VCC; SEL = VCC
Digital Inputs = 0 V or VCC; SEL = 0 V
VCC = 3.6 V, BE1 = 3.0 V;
0.001
0.65
Increase in ICC per Input7
BE2 = VCC or GND; SEL = VCC
85
µA
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Typical values are at 25°C, unless otherwise stated.
3Guaranteed by design, not subject to production test.
4The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6See Timing Measurement Information.
7This current applies to the control pins (BEx) only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
–2–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG3247
LFCSP Package
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 32°C/W
TSSOP Package
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 98°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG3247BCP
ADG3247BRU
–40°C to +85°C
–40°C to +85°C
Leaded Chip Scale Package (LFCSP)
Thin Shrink Small Outline Package (TSSOP)
CP-40
RU-38
Table I. Pin Description
Mnemonic Description
Table II. Truth Table
BEx SEL* Function
L
L
H
L
H
X
A = B, 3.3 V to 1.8 V Level Shifting
A = B, 3.3 V to 2.5 V/2.5V to 1.8 V Level Shifting
Disconnect
BEx
SEL
Ax
Bus Enable (Active Low)
Level Translation Select
Port A, Inputs or Outputs
Port B, Inputs or Outputs
Bx
*SEL = 0 only when VDD = 3.3 V 10%
PIN CONFIGURATION
40-Lead LFCSP and 38-Lead TSSOP
1
2
3
4
5
6
7
38
37
36
35
34
33
32
SEL
A0
V
CC
BE2
BE1
A1
ADG3247
B0
B1
B2
B3
A2
TOP VIEW
A3
A6
A7
A8
1
2
3
4
5
6
7
8
9
(Not to Scale)
30 B0
29 B1
28 B2
27 B3
26 B4
25 B5
24 B6
23 B7
22 B8
21 B9
PIN 1
INDICATOR
A4
A5
A6
A9
A10
A11
A12
A13
A14
ADG3247
8
31
30
29
28
27
26
B4
B5
B6
B7
B8
B9
B10
9
A7
A8
TOP VIEW
10
11
12
13
14
A15 10
A9
A10
A11
A12
A13
25
NC = NO CONNECT
15
16
17
18
19
24
23
22
21
20
B11
B12
B13
B14
B15
A14
A15
GND
NC
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3247 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. PrD
–3–
PRELIMINARY TECHNICAL DATA
ADG3247
TERMINOLOGY
VCC
GND
VINH
VINL
II
Positive Power Supply Voltage
Ground (0 V) Reference
Minimum Input Voltage for Logic 1
Maximum Input Voltage for Logic 0
Input Leakage Current at the Control Inputs
IOZ
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
IOL
VP
Max Pass Voltage. The max pass voltage relates to the clamped output voltage of an NMOS device when the switch
input voltage is equal to the supply voltage.
RON
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
⌬RON
On Resistance Match between Any Two Channels, i.e., RON Max – RON Min
OFF Switch Capacitance
C
C
X OFF
X ON
ON Switch Capacitance
CIN
ICC
Control Input Capacitance. This consists of BEx and SEL.
Quiescent Power Supply Current. It is measured when all control inputs are at a logic HIGH or LOW level and
the switches are OFF.
⌬ICC
Extra Power Supply Current Component per each BEx Control Input when the Input is not Driven at the Supplies.
t
t
t
PLH, tPHL
PZH, tPZL
PHZ, tPLZ
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
R
ON ϫ CL, where CL is the load capacitance.
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BEx.
Bus Disable Times. These are the times taken to place the switch in the high impedance OFF state in response to the
control signal. They are measured as the time taken for the output voltage to change by V⌬ from the original quiescent
level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch
Channel Jitter
fBE
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel
Operating Frequency of Bus Enable. This is the maximum frequency at which Bus Enable (BE) can be toggled.
–4–
REV. PrD
PRELIMINARY TECHNICAL DATA
Typical Performance Characteristics–ADG3247
40
35
30
25
40
35
30
25
20
15
10
5
40
V
= 3V
V
= 3V
V
= 2.3V
CC
CC
T
= 25ꢂC
CC
T
= 25ꢂC
A
T
= 25ꢂC
35
A
A
SEL = 0V
SEL = V
SEL = V
CC
CC
30
25
20
15
10
5
V
= 3.3V
= 3.6V
V
= 3.3V
V
= 2.5V
= 2.7V
CC
CC
CC
20
15
10
5
V
CC
V
CC
V
= 3.6V
CC
0
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0 3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
V
/V – V
V
/V – V
A
B
V
/V – V
A
B
A
B
TPC 3. On Resistance vs.
Input Voltage
TPC 1. On Resistance vs.
Input Voltage
TPC 2. On Resistance vs.
Input Voltage
3.0
2.5
20
15
10
5
15
10
5
V
= 3.6V
T
= 25ꢂC
CC
A
V
= 3.3V
V
= 2.5V
CC
CC
SEL = V
CC
= –5ꢅA
SEL = V
SEL = V
CC
I
CC
O
2.0
1.5
V
= 3.3V
CC
ꢃ85ꢂC
V
= 3V
CC
ꢃ85ꢂC
1.0
0.5
0
ꢄ40ꢂC
ꢃ25ꢂC
ꢃ25ꢂC
ꢄ40ꢂC
0
0
0
0.5
1.0
1.5
V
2.0 2.5
– V
3.0 3.5
1.0
V /V – V
2.0
0
0.5
1.5
0
0.5
V /V – V
1.0
1.2
CC
A
B
A
B
TPC 5. On Resistance vs. Input
Voltage for Different Temperatures
TPC 6. Pass Voltage vs. VCC
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
1800
1600
1400
1200
1000
800
2.5
2.5
T
= 25ꢂC
A
T
= 25ꢂC
T
= 25ꢂC
A
V
= 2.7V
= 2.5V
A
V
= 3.6V
CC
CC
SEL = V
SEL = 0V
= –5ꢅA
CC
= –5ꢅA
2.0
1.5
1.0
0.5
2.0
1.5
1.0
0.5
I
I
O
O
V
= 3.3V, SEL = 0V
CC
V
CC
V
= 3.3V
CC
V
= 2.3V
V
= 3V
CC
CC
600
V
= SEL = 3.3V
CC
400
200
V
= SEL = 2.5V
CC
0
0
0
0
0.5
1.0
1.5
– V
2.0
2.5
3.0
0
0.5
1.0
1.5
V
2.0
– V
2.5
3.0 3.5
0
2
4
6
8
10 12 14 16 18 20
V
ENABLE FREQUENCY – MHz
CC
CC
TPC 9. ICC vs. Enable Frequency
TPC 8. Pass Voltage vs. VCC
TPC 7. Pass Voltage vs. VCC
REV. PrD
–5–
PRELIMINARY TECHNICAL DATA
ADG3247
3.0
3.0
2.5
2.0
1.5
0
T
= 25ꢂC
A
T
= 25ꢂC
T
V
= 25ꢂC
= V
CC
A
A
–0.2
SEL = V
CC
ON OFF
= InF
V
= 0V
A
A
2.5
2.0
1.5
1.0
–0.4
–0.6
–0.8
–1.0
–1.2
BE = 0
BE = 0
C
L
V
= SEL = 3.3V
CC
V
= 3.3V; SEL = 0V
CC
V
= 2.5V
CC
V
= SEL = 3.3V
CC
1.0
V
= SEL = 2.5V
CC
–1.4
–1.6
V
= 3.3V
1.5
CC
0.5
0
0.5
0
–1.8
–2.0
V
= 3.3V; SEL = 0V
CC
V
= SEL = 2.5V
CC
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
– A
0
0.5
1.0
2.0
/V – V
2.5
3.0
0
–0.10
–0.09
–0.08
–
0.07
–
0.06
–0.05
–0.04–0.03 –0.02–0.01 0
V
I
I
– A
A
B
O
O
TPC 10. Output Low Characteristic
TPC 11. Output High Characteristic
TPC 12. Charge Injection vs.
Source Voltage
–20
–30
0
–20
T
V
= 25ꢂC
T
= 25ꢂC
A
A
= 3.3V/2.5V
V = 3.3V/2.5V
SEL =V
–30
–40
–50
–60
–70
–80
T
V
= 25ꢂC
CC
CC
–2
–4
A
SEL =V
= 3.3V/2.5V
CC
ADJACENT CHANNELS
= 0dBm
CC
= 0dBm
CC
–40
–50
–60
–70
–80
–90
–100
V
SEL =V
V
N/W ANALYZER:
R
IN
N/W ANALYZER:
= R = 50ꢀ
CC
V
= 0dBm
IN
N/W ANALYZER:
= R = 50ꢀ
IN
R
L
S
R
–6
–8
L
= R = 50ꢀ
S
L
S
–10
–12
–14
–90
–100
0.03 0.1
1
10
100
1000
0.03 0.1
1
10
100
1000
0.03 0.1
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
TPC 13. Bandwidth vs. Frequency
TPC 15. Off Isolation vs.
Frequency
TPC 14. Crosstalk vs. Frequency
100
90
80
70
60
50
40
30
20
10
0
3.5
2.5
V
= SEL = 3.3V
= 2V p-p
CC
ENABLE
3.0
V
IN
ENABLE
2.0
V
= SEL = 3.3V
CC
20dB ATTENUATION
DISABLE
ENABLE
V
= SEL = 2.5V
2.5
2.0
1.5
1.0
CC
DISABLE
1.5
1.0
V
= 3.3V, SEL = 0V
CC
DISABLE
0.5
0
0.5
0
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
DATA RATE – GBPS
–40 –20
0
20
40
60
80 100
–40 –20
0
20
40
60
80
100
TEMPERATURE – ꢂC
TEMPERATURE – ꢂC
TPC 16. Enable/Disable Time
vs. Temperature
TPC 17. Enable/Disable Time
vs. Temperature
TPC 18. Jitter vs. Data Rate;
PRBS 31
–6–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG3247
100
95
90
85
80
75
V
= SEL = 3.3V
= 2V p-p
CC
V
IN
20dB ATTENUATION
70
65
60
55
50
V
= 2.5V
20dB
ATTENUATION
CC
SEL = 2.5V
= 2V p-p
V
= 3.3V
37mV/DIV
200ps/DIV
20dB
ATTENUATION
CC
SEL = 3.3V
= 2V p-p
35mV/DIV
100ps/DIV
T
= 28ꢂC
V
A
IN
V
T
= 25ꢂC
IN
A
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) ꢁ 100%
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
DATA RATE – GBPS
TPC 20. Eye Pattern; 1.244
GBPS, VCC = 3.3 V, PRBS 31
TPC 21. Eye Pattern; 1 GBPS,
VCC = 2.5 V, PRBS 31
TPC 19. Eye Width vs. Data
Rate; PRBS 31
20dB
ATTENUATION
= 3.3V
50.1mV/DIV
50ps/DIV
V
CC
SEL = 3.3V
= 2V p-p
T
= 25ꢂC
A
V
IN
TPC 22. Jitter @ 1.244 GBPS,
PRBS 31
REV. PrD
–7–
PRELIMINARY TECHNICAL DATA
ADG3247
TIMING MEASUREMENT INFORMATION
For the following load circuit and waveforms, the notation that is
used is VIN and VOUT where:
VIN =VA andVOUT =VB
or
VIN =VB andVOUT =VA
V
CC
2 ꢁ V
CC
SW1
OPEN
V
IH
SWITCH INPUT
tPLH
V
GND
T
R
L
V
V
0V
OUT
IN
tPHL
PULSE
GENERATOR
V
H
D.U.T.
V
T
OUTPUT
R
R
C
L
L
T
V
L
Figure 2. Propagation Delay
NOTES
PULSE GENERATOR FOR ALL PULSES: tR 2.5ns, tF 2.5ns,
FREQUENCY 10MHz.
C
R
INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO Z
L
T
OUT
OF THE PULSE GENERATOR.
Figure 1. Load Circuit
Test Conditions
Symbol
VCC = 3.3 V 0.3 V (SEL = VCC
)
VCC = 2.5 V 0.2 V (SEL = VCC
)
VCC = 3.3
V
0.3 V (SEL = 0 V) Unit
RL
V∆
CL
VT
500
300
50
500
150
30
500
150
30
Ω
mV
pF
V
1.5
0.9
0.9
DISABLE
ENABLE
V
INH
V
CONTROL INPUT BEx
T
Table III. Switch Position
0V
tPZL
tPLZ
TEST
PLZ, tPZL
tPHZ, tPZH
S1
V
CC
V
CC
V
OUT
SW1 @ 2V
t
2 ϫ VCC
GND
V
V
= 0V
= V
T
IN
V
V
+V
ꢆ
L
L
CC
tPZH
tPHZ
V
V
H
V
OUT
SW1 @ GND
V
–V
V
IN
CC
H
ꢆ
T
0V
0V
Figure 3. Enable and Disable Times
–8–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG3247
BUS SWITCH APPLICATIONS
2.5 V to 1.8 V Translation
Mixed Voltage Operation, Level Translation
When VCC is 2.5 V (SEL = VCC) and the input signal range is 0 V
to VCC, the maximum output signal will, as before, be clamped
to within a voltage threshold below the VCC supply.
Bus switches can be used to provide an ideal solution for inter-
facing between mixed voltage systems. The ADG3247 is suitable
for applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally from
3.3 V directly to 2.5 V.
2.5V
Figure 4 shows a block diagram of a typical application in which a
user needs to interface between a 3.3 V ADC and a 2.5 V micro-
processor. The microprocessor may not have 3.3 V tolerant inputs;
therefore placing the ADG3247 between the two devices allows the
devices to communicate easily. The bus switch directly connects
the two blocks, thus introducing minimal propagation delay,
timing skew, or noise.
2.5V
ADG3247
1.8V
Figure 7. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
In this case, the output will be limited to approximately 1.8 V,
as shown in Figure 7.
3.3V
3.3V
2.5V
V
OUT
2.5V SUPPLY
SEL = 2.5V
2.5V
3.3V ADC
MICROPROCESSOR
1.8V
Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
V
IN
3.3 V to 2.5 V Translation
0V
SWITCH
INPUT
2.5V
When VCC is 3.3 V (SEL = VCC) and the input signal range is 0 V
to VCC, the maximum output signal will be clamped to within
a voltage threshold below the VCC supply.
Figure 8. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
3.3Vto1.8VTranslation
3.3V
The ADG3247 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
SEL pin.
3.3V
2.5V
2.5V
2.5V
SEL pin: An active low control pin. SEL activates internal
circuitry in the ADG3247 that allows voltage translation between
3.3 V devices and 1.8 V devices.
ADG3247
3.3V
Figure 5. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
In this case, the output will be limited to 2.5 V, as shown in
Figure 6.
3.3V
ADG3247
1.8V
V
OUT
3.3V SUPPLY
SEL = 3.3V
2.5V
Figure 9. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
V
IN
0V
SWITCH
INPUT
3.3V
SEL is unused, it should be tied directly to VCC
.
Figure 6. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
This device can be used for translation from 2.5 V to 3.3 V
devices, and also between two 3.3 V devices.
REV. PrD
–9–
PRELIMINARY TECHNICAL DATA
ADG3247
V
OUT
3.3V SUPPLY
SEL = 0V
PLUG-IN
CARD (1)
CARD I/O
CARD I/O
1.8V
CPU
RAM
PLUG-IN
CARD (2)
V
IN
0V
SWITCH
INPUT
3.3V
Figure 10. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
Bus Isolation
Figure 12. ADG3247 in a Hot Plug Application
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3247 is designed specifically for
applications that do not need drive yet require simple logic func-
tions, it solves this requirement. The device isolates access to the
bus, thus minimizing capacitance loading.
There are many systems that require the ability to handle hot
swapping, such as docking stations, PCI boards for servers, and
line cards for telecommunications switches. If the bus can be
isolated prior to insertion or removal, then there is more control
over the hot swap event. This isolation can be achieved using a
bus switch. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the back plane before any other signal or power pins.
Load A
Load C
Analog Switching
Bus/
Backplane
Bus switches can be used in many analog switching applications;
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself consisting solely of an NMOS
switch limits the operating voltage (see TPC 1 for a typical plot),
but in many cases this does not present an issue.
Load B
Load D
Bus Switch
Location
Figure 11. Location of Bus Switched in a Bus
Isolation Application
Hot Plug and Hot Swap Isolation
The ADG3247 is suitable for hot swap and hot plug applications.
The output signal of the ADG3247 is limited to a voltage that is
below the VCC supply, as shown in Figures 6, 8, and 10. There-
fore the switch acts like a buffer to take the impact from hot
insertion, protecting vital and expensive chipsets from damage.
High Impedance during Power-Up/Power-Down
To ensure the high impedance state during power-up or power-
down, BEx should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
In hot-plug applications, the system cannot be shutdown when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 12 shows a typical example of this type of application.
PACKAGE AND PINOUT
The ADG3247 is packaged in both a small 38-lead TSSOP or a
tiny 40-lead LFCSP package. The area of the TSSOP option is
62.7 mm2, while the area of the LFCSP option is 36 mm2. This
leads to a 43% savings in board space when using the LFCSP
package compared with the TSSOP package. This makes the LFCSP
option an excellent choice for space-constrained applications.
The ADG3247 in the TSSOP package offers a flowthrough
pinout. The term flowthrough signifies that all the inputs are on
opposite sides from the outputs. A flowthrough pinout simplifies
the PCB layout.
–10–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG3247
OUTLINE DIMENSIONS
40-Lead Frame Chip Scale Package [LFCSP]
(CP-40)
Dimensions shown in millimeters
6.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
31
30
40
1
PIN 1
INDICATOR
0.50
BSC
4.25
TOP
VIEW
5.75
BSC SQ
BOTTOM
VIEW
3.70 SQ
1.75
0.50
0.40
0.30
21
20
10
11
4.50
REF
12ꢂ MAX
1.00 MAX
0.65 NOM
0.05 MAX
0.02 NOM
1.00
0.90
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
38-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-38)
Dimensions shown in millimeters
9.80
9.70
9.60
38
20
19
4.50
4.40
4.30
6.40 BSC
1
PIN 1
1.20
MAX
0.15
0.05
8ꢂ
0ꢂ
0.27
0.17
0.50
BSC
0.70
0.60
0.45
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153BD-1
REV. PrD
–11–
–12–
相关型号：
ADG3247BCP-REEL
IC DUAL 8-BIT DRIVER, TRUE OUTPUT, QCC40, 6 X 6 MM, MO-220-VJJD-2, CSP-40, Bus Driver/Transceiver
ADI
ADG3247BCPZ
ADG3247 SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, QCC40, 6 X 6 MM, MO-220-VJJD-2, CSP-40
ROCHESTER
ADG3247BRU-REEL7
ADG3247 SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO38, MS-153BD-1, TSSOP-38
ROCHESTER
©2020 ICPDF网 联系我们和版权申明