ADE7753_技术文档

PRELIMINARY TECHNICAL DATA

ActiveandApparentEnergyMeteringIC

a

PreliminaryTechnicalData

withdi/dtsensorinterface

ADE7753*

precise phase matching between the current and voltage

channels. T he integrator can be switched on and off based on

the current sensor selected.

T he AD E7753 contains an Active Energy register. It is

capable of holding more than 200 seconds of accumulated

power at full load. Data is read from the ADE7753 via the

serial interface. T he ADE7753 also provides a pulse output

(CF) with output frequency is proportional to the active

power.

In addition to rms calculation and active and apparent power

information, the AD E7753 also accumulates the signed

reactive energy. T he ADE7753 also provides various system

calibration features, i.e., channel offset correction, phase

calibration and power calibration. T he part also incorporates

a detection circuit for short duration low or high voltage

variations.

T he ADE7753 has a positive only accumulation mode which

gives the option to accumulate energy only when positive

power is detected. An internal no-load threshold ensures that

the part does not exhibit any creep when there is no load.

A zero crossing output (ZX) produces an output which is

synchronized to the zero crossing point of the line voltage.

T his information is used in the ADE7753 to measure the

line's period. T he signal is also used internally to the chip in

the line cycle Active and Apparent energy accumulation

mode. T his enables a faster and more precise energy accumu-

lation and is useful during calibration. T his signal is also

useful for synchronization of relay switching with a voltage

zero crossing.

FEATURES

High Accuracy, supports IEC 61036 and IEC61268

On-Chip Digital Integrator enables direct interface w ith

current sensors w ith di/ dt output

The ADE7753 supplies Active, Reactive and Apparent

Energy, Sam pled Waveform , Current and Voltage RMS

Less than 0.1% error over a dynam ic range of 1000 to 1

Positive only energy accum ulation m ode available

An On-Chip user Program m able threshold for line

voltage surge and SAG, and PSU supervisory

Digital Pow er, Phase & Input Offset Calibration

An On-Chip tem perature sensor (±3°C typical)

A SPI com patible Serial Interface

A pulse output w ith program m able frequency

An Interrupt Request pin (IRQ) and Status register

Proprietary ADCs and DSP provide high accuracy data over

large variations in environm ental conditions and tim e

Reference 2.4V±8% (20 ppm / °C typical)

w ith external overdrive capability

Single 5V Supply, Low pow er (25m W typical)

GENERAL DESCRIP TION

T he AD E7753 is an accurate active and apparent energy

measurements IC with a serial interface and a pulse output.

T he ADE7753 incorporates two second order sigma delta

AD Cs, a digital integrator (on CH 1), reference circuitry,

temperature sensor, and all the signal processing required to

perform RMS calculation on the voltage and current, active,

reactive, and apparent energy measurement.

T he interrupt request output is an open drain, active low logic

output. T he Interrupt Status Register indicates the nature of

the interrupt, and the Interrupt Enable Register controls

which event produces an output on the IRQ pin.

An on-chip digital integrator provides direct interface to di/

dt current sensors such as Rogowski coils. T he digital

integrator eliminates the need for external analog integrator,

and this solution provides excellent long-term stability and

T he ADE7753 is available in 20-lead SSOP package.

FUNCTIO NAL BLO CK D IAGRAM

DVDD

DGND

AVDD

RESET

ADE7753

WGAIN[11:0]

PGA

INTEGRATOR

MULTIPLIER

LPF2

V1P

V1N

+

-

ADC

Ύdt

Σ

HPF

CFNUM[11:0]

TEMP

SENSOR

APOS[15:0]

PHCAL[5:0]

DFC

CF

Φ

CFDEN[11:0]

IRMSOS[11:0]

VAGAIN[11:0]

2

X

Σ

ZX

PGA

VRMSOS[11:0]

V2P

V2N

SAG

+

-

ADC

2

X

Σ

VADIV[7:0]

WDIV[7:0]

LPF1

4kΩ

2.4V

REFERENCE

ADE7753 REGISTERS &

SERIAL INTERFACE

REF

DIN DOUT SCLK CS IRQ

AGND

IN/OUT

CLKIN CLKOUT

*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others Pending.

REV. PrF 10/02

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

w w w . a n a l o g . c o m

PRELIMINARY TECHNICAL DATA

1,3

(AV = DV = 5V ± 5%, AGND = DGND = 0V, On-Chip Reference,

CLKIN = 3.579545MHz XTAL, TMIN to TMAX = -40°C to +85°C)

DD

ADE7753–SPECIFICATIONS

Parameter

Spec

Units

Test Conditions/Comments

ENERGYMEASUREMENT ACCURACY

M easurem ent Bandwidth

1 4

k H z

C LKIN = 3.579545 M H z

Channel 2 = 300mV rms/60Hz, Gain = 2

Measurement Error¹on Channel1

Channel 1 Range = 0.5V full-scale

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Channel 1 Range = 0.25V full-scale

Gain = 1

Gain = 2

Gain = 4

0.1

0.2

% typ

Over a dynamic range 1000 to 1

0.1

0.2

% typ

Over a dynamic range 1000 to 1

Gain = 8

Gain = 16

Channel 1 Range = 0.125V full-scale

Gain = 1

Gain = 2

Gain = 4

Gain = 8

0.1

0.2

0.4

±0.05

% typ

°max

Over a dynamic range 1000 to 1

Gain = 16

Over a dynamic range 1000 to 1

Phase Error¹Between Channels

AC Power Supply Rejection¹

Output Frequency Variation (CF)

Line Frequency = 45Hz to 65Hz, HPF on

AV_DD= DV_DD= 5V+175mV rms/ 120Hz

Channel 1 = 20mV rms, Gain = 16, Range = 0.5V

Channel 2 = 300mV rms/60Hz, Gain = 1

AV_DD= DV_DD= 5V ± 250mV dc

0.2

% typ

DC Power Supply Rejection¹

Output Frequency Variation (CF)

±0.3

Channel 1 = 20mV rms/60Hz, Gain = 16, Range = 0.5V

Channel 2 = 300mV rms/60Hz, Gain = 1

ANALOG INPUT S

Maximum SignalLevels

Input Impedance (dc)

Bandwidth

See Analog Inputs Section

V1P, V1N, V2N and V2P to AGND

±0.5

390

14

V max

kΩ min

kHz

CLKIN/256, CLKIN = 3.579545MHz

External 2.5V reference, Gain = 1 on Channel 1 & 2

Gain Error^1,4

Channel1

Range = 0.5Vfull-scale

Range = 0.25Vfull-scale

Range = 0.125V full-scale

Channel2

±4

% typ

V1 = 0.5V dc

V1 = 0.25V dc

V1 = 0.125V dc

V2 = 0.5V dc

Gain Error Match¹

Channel1

External2.5Vreference

Range = 0.5Vfull-scale

Range = 0.25Vfull-scale

Range = 0.125V full-scale

Channel2

±0.3

% typ

Gain = 1, 2, 4, 8, 16

Offset Error¹

Channel1

Channel2

±10

mVmax

Channel 1 Range = 0.5V

Channel 2 Range = 0.5V

WAVEFORM SAMPLING

Channel1

SamplingCLKIN/128, 3.579545MHz/128 = 27.9kSPS

See Channel 1 Sampling

Signal-to-Noise plus distortion

Bandwidth (-3dB)

62

14

dB typ

kHz

150mV rms/60Hz, Range = 0.5V, Gain = 2

CLKIN = 3.579545MHz

Channel2

See Channel 2 Sampling

Signal-to-Noise plus distortion

Bandwidth (-3dB)

52

140

dB typ

Hz

150mV rms/60Hz, Gain = 2

CLKIN = 3.579545MHz

REV. PrF 10/02

-2-

PRELIMINARY TECHNICAL DATA

ADE7753

Parameter

Spec

Units

Test Conditions/Comments

REFERENCE INPUT

REF_IN/OUTInput Voltage Range

2.6

2.2

10

Vmax

V min

pF max

2.4 V +8%

2.4V -8%

Input Capacitance

ON-CHIP REFERENCE

Reference Error

Current source

Nominal 2.4V at REF_IN/OUTpin

±200

10

mV max

µA max

Output Impedance

Temperature Coefficient

4

20

kΩ min

ppm/°C typ

CLKIN

Note all specifications CLKIN of 3.579545MHz

Input Clock Frequency

4

1

MHz max

MHz min

LOGIC INPUTS

RESET, D IN , SC LK, C LKIN and CS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.4

0.8

±3

10

V min

DV_DD= 5 V ± 10%

T ypically 10nA, V_IN= 0V to DV_DD

Vmax

µA max

pF max

Input Capacitance, C_IN

LOGIC OUTPUTS³

SAG & IRQ

Output High Voltage, V_OH

Output Low Voltage, V_OL

ZX & DOUT

Open D rain outputs, 10kΩ pull up resistor

I_SOURCE= 5mA

I_SINK= 0.8mA

4

0.4

V min

Vmax

Output High Voltage, V_OH

Output Low Voltage, V_OL

CF

4

0.4

V min

Vmax

I_SOURCE= 5mA

I_SINK= 0.8mA

Output High Voltage, V_OH

Output Low Voltage, V_OL

4

1

V min

Vmax

I_SOURCE= 5mA

I_SINK= 7mA

POWER SUPPLY

AV_{D D}

For specified Performance

5V - 5%

5V +5%

5V - 5%

5V + 5%

4.75

5.25

4.75

5.25

3

V min

V max

V min

V max

mAmax

D V_DD

AI_DD

D I_DD

T ypically 2.0 mA

T ypically 3.0 mA

4

NOT ES:

¹See T erminologySection for explanation ofSpecifications

²See Plots in T ypical Performance Graphs

³Specifications subject to change without notice

⁴See Analog Inputs Section

ORDERING GUIDE

M O D E L

Package Option*

I

OL

200 µA

AD E7753ARS

RS-20

AD E7753ARSRL

EVAL-AD E7753EB

RS-20

TO

OUTPUT

+2.1V

AD E7753 evaluation board

C

50pF

* RS = Shrink Small Outline Package in tubes; RSRL = Shrink Small Outline

Package in reel.

L

I

OH

1.6 mA

Load Circuit for Tim ing Specifications

–3 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

(AV = DV = 5V ± 5%, AGND = DGND = 0V, On-Chip Reference,

CLKIN = 3.579545MHz XTAL, TMIN to TMAX = -40°C to +85°C)

TestConditions/Comments

ADE7753 TIMING CHARACTERISTICS^1,2

DD

Parameter

A,BVersions

Units

Write timing

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

20

ns (min)

CS falling edge to first SCLK falling edge

SCLK logic high pulse width

SCLK logic low pulse width

Valid Data Set up time before falling edge of SCLK

Data Hold time after SCLK falling edge

Minimum time between the end of data byte transfers.

Minimum time between byte transfers during a serial write.

CS H old time after SCLK falling edge.

150

10

5

T BD

100

Readtiming

t₉

3.1

us (min)

Minimum time between read command (i.e. a write to Communication

Reigster) and data read.

t₁₀

t₁₁

T BD

30

ns (min)

Minimum time between data byte transfers during a multibyte read.

Data access time after SCLK rising edge following a write to the

C ommunications Register

3

4

t₁₂

100

10

100

10

ns (max) Bus relinquish time after falling edge of SCLK.

ns (min)

ns (max) Bus relinquish time after rising edge of CS.

ns (min)

4

t₁₃

NOTES

¹Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%)

and timed from a voltage level of 1.6V.

²See timing diagram below and Serial Interface section of this data sheet.

³Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V.

⁴Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. T he measured number is then extrapolated back to

remove the effects of charging or discharging the 50pF capacitor. T his means that the time quoted in the timing characteristics is the true bus relinquish time of the part

and is independent of the bus loading.

Ser ial Wr ite T im in g

t

8

CS

t

6

1

2

3

t

7

SCLK

DIN

t

4

t

5

0

DB7

DB0

DB7

1

A4 A3 A2 A1 A0

DB0

Most Significant Byte

Least Significant Byte

Command Byte

Ser ial Read T im ing

CS

t

1

t

13

t

10

9

SCLK

DIN

0

A1

A4 A3 A2 A0

t

12

t

11

DB0

DB7

DB0

DB7

DOUT

Most Significant Byte

Least Significant Byte

Command Byte

–4 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

ABSO LUTE MAXIMUM RATINGS*

(T _A= +25°C unless otherwise noted)

Storage T emperature Range . . . . . . . . –65°C to +150°C

Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . +150°C

20 Pin SSOP, Power Dissipation . . . . . . . . . . . . 450 mW

θ_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . 112°C/W

Lead T emperature, Soldering

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDtoAV_DD. . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C

V

, V

,

V

and V

. . . . . . . . . . . . . . . . . . -6V to +6V

1P

1N

2P

2N

Reference Input Voltage to AGND . . . . –0.3 V to AV_DD

0.3 V

Digital Input Voltage to DGND –0.3 V to DV_DD+ 0.3 V

Digital Output Voltage to DGND –0.3 V to DV_DD+ 0.3 V

Operating T emperature Range

+

^*Stressesabove those listed under “Absolute Maximum Ratings” maycause permanent

damage to the device. Thisisa stressratingonlyand functionaloperation ofthe device

at these or any other conditions above those listed in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods mayaffect device reliability.

Industrial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu-

late on the human body and test equipment and can discharge without detection. Although the ADE7753

features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to

high energy electrostatic discharges. T herefore, proper ESD precautions are recommended to avoid

performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

Terminology

M E ASU RE M E NT E RRO R

T he error associated with the energy measurement made by

the ADE7753 is defined by the following formula:

input signal levels when the supplies are varied ±5%. Any

error introduced is again expressed as a percentage of

reading.

Percentage Error =

ADC OFFSET ERROR









Energy registered by ADE 7753 − True Energy

×100%

T his refers to the DC offset associated with the analog inputs

to the ADCs. It means that with the analog inputs connected

to AGND the ADCs still see a dc analog input signal. T he

magnitude of the offset depends on the gain and input range

selection - see characteristic curves. However, when HPF1 is

switched on the offset is removed from Channel 1 (current)

and the power calculation is not affected by this offset. T he

offsets may be removed by performing an offset calibration -

see Analog Inputs.

True Energy





P H ASE E RRO R B E T WE E N C H ANNE LS

T he digital integrator and the H PF (H igh Pass Filter) in

C hannel 1 have non-ideal phase response. T o offset this

phase response and equalize the phase response between

channels, two phase correction network is placed in Channel

1: one for the digital integrator and the other for the HPF.

Each phase correction network corrects the phase response of

the corresponding component and ensures a phase match

between Channel 1 (current) and Channel 2 (voltage) to

within ±0.1° over a range of 45Hz to 65Hz and ±0.2° over

a range 40Hz to 1kHz.

G AIN E RRO R

T he gain error in the AD E7753 AD Cs is defined as the

difference between the measured ADC output code (minus

the offset) and the ideal output code - see Channel 1 ADC &

Channel 2 ADC. It is measured for each of the input ranges

on Channel 1 (0.5V, 0.25V and 0.125V). T he difference is

expressed as a percentage of the ideal code.

P O WE R SU P P LY RE JE C T IO N

T his quantifies the ADE7753 measurement error as a per-

centage of reading when the power supplies are varied.

For the AC PSR measurement a reading at nominal supplies

(5V) is taken. A second reading is obtained with the same

input signal levels when an ac (175mV rms/120Hz) signal is

introduced onto the supplies. Any error introduced by this

AC signal is expressed as a percentage of reading—see

M easurement Error definition above.

G AIN E RRO R M AT C H

T he Gain Error Match is defined as the gain error (minus the

offset) obtained when switching between a gain of 1 (for each

of the input ranges) and a gain of 2, 4, 8, or 16. It is expressed

as a percentage of the output ADC code obtained under a gain

of 1. T his gives the gain error observed when the gain

selection is changed from 1 to 2, 4, 8 or 16.

For the DC PSR measurement a reading at nominal supplies

(5V) is taken. A second reading is obtained with the same

–5 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

P IN F UNC TIO N D E SC RIP TIO N

D E S C R IP T IO N

P in No.

M N E M O N I C

1

RESET

Reset pin for the ADE7753. A logic low on this pin will hold the ADCs and digital

circuitry (including the Serial Interface) in a reset condition.

2

3

DV_DD

Digital power supply. T his pin provides the supply voltage for the digital circuitry in

the ADE7753. T he supply voltage should be maintained at 5V ± 5% for specified op-

eration. T his pin should be decoupled to DGND with a 10µF capacitor in parallel with

a ceramic 100nF capacitor.

AV_DD

Analog power supply. T his pin provides the supply voltage for the analog circuitry in

the ADE7753. T he supply should be maintained at 5V ± 5% for specified operation.

Every effort should be made to minimize power supply ripple and noise at this pin by

the use of proper decoupling. T he typical performance graphs in this data sheet show

the power supply rejection performance. T his pin should be decoupled to AGND with a

10µF capacitor in parallel with a ceramic 100nF capacitor.

4,5

V1P, V1N

Analog inputs for Channel 1. T his channel is intended for use with the di/dt current

transducer such as Rogowski coil or other current sensor such as shunt or current trans-

former (CT ). T hese inputs are fully differential voltage inputs with maximum

differential input signal levels of ±0.5V, ±0.25V and ±0.125V, depending on the full

scale selection - See Analog Inputs. Channel 1 also has a PGA with gain selections of 1,

2, 4, 8 or 16. T he maximum signal level at these pins with respect to AGND is ±0.5V.

Both inputs have internal ESD protection circuitry and in addition an overvoltage of

±6V can be sustained on these inputs without risk of permanent damage.

6,7

V2N , V2P

Analog inputs for Channel 2. T his channel is intended for use with the voltage trans-

ducer. T hese inputs are fully differential voltage inputs with a maximum differential

signal level of ±0.5V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8 or

16. T he maximum signal level at these pins with respect to AGND is ±0.5V. Both

inputs have internal ESD protection circuitry, and an overvoltage of ±6V can be sus-

tained on these inputs without risk of permanent damage.

8

AG N D

T his pin provides the ground reference for the analog circuitry in the ADE7753, i.e.

ADCs and reference. T his pin should be tied to the analog ground plane or the quietest

ground reference in the system. T his quiet ground reference should be used for all ana-

log circuitry, e.g. anti-aliasing filters, current and voltage transducers etc. In order to

keep ground noise around the ADE7753 to a minimum, the quiet ground plane should

only connected to the digital ground plane at one point. It is acceptable to place the

entire device on the analog ground plane - see Applications Information.

9

REF_IN/OUT

T his pin provides access to the on-chip voltage reference. T he on-chip reference has a

nominal value of 2.4V ± 8% and a typical temperature coefficient of 20ppm/°C. An

external reference source may also be connected at this pin. In either case this pin

should be decoupled to AGND with a 1µF ceramic capacitor.

10

D G N D

T his provides the ground reference for the digital circuitry in the ADE7753, i.e. multi-

plier, filters and digital-to-frequency converter. Because the digital return currents in

the ADE7753 are small, it is acceptable to connect this pin to the analog ground plane

of the system - see Applications Information. However, high bus capacitance on the DOUT

pin may result in noisy digital current which could affect performance.

11

C F

Calibration Frequency logic output. T he CF logic output gives Active Power informa-

tion. T his output is intended to be used for operational and calibration purposes. T he

full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM

Register—see Energy To Frequency Conversion.

12

13

Z X

Voltage waveform (Channel 2) zero crossing output. T his output toggles logic high and

low at the zero crossing of the differential signal on Channel 2—see Zero Crossing Detection.

S A G

T his open drain logic output goes active low when either no zero crossings are detected

or a low voltage threshold (Channel 2) is crossed for a specified duration. See Line Volt-

ageSagDetection.

14

IRQ

Interrupt Request Output. T his is an active low open drain logic output. Maskable

interrupts include: Active Energy Register roll-over, Active Energy Register at half

level, and arrivals of new waveform samples. See ADE7753 Interrupts.

–6 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

P in No.

MNE MO NIC

D ESCRIP TIO N

15

C LK IN

Master clock for ADCs and digital signal processing. An external clock can be pro-

vided at this logic input. Alternatively, a parallel resonant AT crystal can be connected

across CLKIN and CLKOUT to provide a clock source for the ADE7753. T he clock

frequency for specified operation is 3.579545MH z. Ceramic load capacitors of between

22pF and 33pF should be used with the gate oscillator circuit. Refer to crystal manu-

facturers data sheet for load capacitance requirements.

16

17

18

C L K O U T

CS

A crystal can be connected across this pin and CLKIN as described above to provide a

clock source for the ADE7753. T he CLKOUT pin can drive one CMOS load when

either an external clock is supplied at CLKIN or a crystal is being used.

Chip Select. Part of the four wire SPI Serial Interface. T his active low logic input al-

lows the ADE7753 to share the serial bus with several other devices. See ADE7753 Serial

Interface.

SC L K

Serial Clock Input for the synchronous serial interface. All Serial data transfers are

synchronized to this clock—see ADE7753 Serial Interface. T he SCLK has a schmitt-trigger

input for use with a clock source which has a slow edge transition time, e.g., opto-

isolator outputs.

19

20

D O U T

D I N

Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of

SCLK. T his logic output is normally in a high impedance state unless it is driving data

onto the serial data bus—see ADE7753 Serial Interface..

Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of

SCLK—see ADE7753 Serial Interface..

P IN CONFIGURATION

SSOP Packages

RESET

DVDD

AVDD

20

19

DIN

1

2

DOUT

3

18 SCLK

17 CS

16

ADE7753

TOP VIEW

4

V1P

V1N

5

CLKOUT

(Not to Scale)

6

15 CLKIN

14 IRQ

V2N

V2P

7

AGND

8

13

12

11

SAG

ZX

REF

9

IN/OUT

DGND

10

CF

–7 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

TypicalPerformanceCharacteristics-ADE7753

TBD

TPC 4— Error as a % of Reading (Full-Scale input for Chan-

nel 1=0.25V, Gain=4)

TPC 1— Error as a % of Reading (Gain=1)

TBD

TPC 5— Error as a % of Reading (Full-scale input for Chan-

nel 1=0.125V, Gain=8)

TPC 2— Error as a % of Reading (Gain=4)

TBD

TPC 3— Error as a % of Reading (Gain=16)

TPC 6— Test Circuits for Perform ance Curves

REV. PrF 10/02

–8 –

PRELIMINARY TECHNICAL DATA

ADE7753

ANALOG INP UTS

GAIN REGISTER*

Channel 1 and Channel 2 PGA Control

T he ADE7753 has two fully differential voltage input chan-

nels. T he maximum differential input voltage for input pairs

V1P/V1N and V2P/V2N are ±0.5V. In addition, the maxi-

mum signal level on analog inputs for V1P/V1N and V2P/

V2N are ±0.5V with respect to AGND.

7

6

5

4

3

2

1

0

ADDR: 0FH

0

PGA 1 Gain Select

000 = x1

001 = x2

010 = x4

011 = x8

Each analog input channel has a PGA (Programmable Gain

Amplifier) with possible gain selections of 1, 2, 4, 8 and 16.

T he gain selections are made by writing to the Gain regis-

ter—see Figure 2. Bits 0 to 2 select the gain for the PGA in

Channel 1 and the gain selection for the PGA in Channel 2

is made via bits 5 to 7. Figure 1 shows how a gain selection

for Channel 1 is made using the Gain register.

PGA 2 Gain Select

000 = x1

001 = x2

010 = x4

011 = x8

100 = x16

Channel 1 Full Scale Select

00 = 0.5V

01 = 0.25V

100 = x16

*Register contents show power on defaults

10 = 0.125V

Figure 2— ADE7753 Analog Gain register

GAIN[7:0]

It is also possible to adjust offset errors on Channel 1 and

C hannel 2 by writing to the Offset C orrection Registers

(CH 1OS and CH 2OS respectively). T hese registers allow

channel offsets in the range ±20mV to ±50mV (depending on

the gain setting) to be removed. Note that it is not necessary

to perform an offset correction in an Energy measurement

application if H PF in Channel 1 is switched on. Figure 3

shows the effect of offsets on the real power calculation. As

can be seen from Figure 3, an offset on Channel 1 and

Channel 2 will contribute a dc component after multiplica-

tion. Since this dc component is extracted by LPF2 to

generate the Active (Real) Power information, the offsets will

have contributed an error to the Active Power calculation.

T his problem is easily avoided by enabling HPF in Channel

1. By removing the offset from at least one channel, no error

component is generated at dc by the multiplication. Error

terms at Cos(w.t) are removed by LPF2 and by integration of

the Active Power signal in the Active Energy register (AEN-

ERGY[23:0]) – see Energy Calculation.

Gain (k)

selection

V1P

+

-

V

in

k.V

in

Σ

+

V1N

Offset

Adjust

(±50mV)

CH1OS[7:0]

Bit 0 to 5: Sign magnitude coded offset correction

Bit 6: Not used

Bit 7: Digital Integrator (On=1, Off=0; default ON)

Figure 1— PGA in Channel 1

In addition to the PGA, Channel 1 also has a full scale input

range selection for the ADC. T he ADC analog input range

selection is also made using the Gain register—see Figure 2.

As mentioned previously the maximum differential input

voltage is 1V. However, by using bits 3 and 4 in the Gain

register, the maximum ADC input voltage can be set to 0.5V,

0.25V or 0.125V. T his is achieved by adjusting the ADC

reference—see ADE7753 Reference Circuit. T able I below sum-

marizes the maximum differential input signal level on

Channel 1 for the various ADC range and gain selections.

DC component (including error term) is

extracted by the LPF for real power

calculation

V

.I

OS OS

V.I

2

I

.V

.I

OS

V

OS

ω

2ω

frequency (rad/s)

0

Figure 3— Effect of channel offsets on the real power cal-

culation

Table I

T he contents of the Offset Correction registers are 6-Bit, sign

and m agnitude coded. T he weighting of the LSB size

depends on the gain setting, i.e., 1, 2, 4, 8 or 16. T able II

below shows the correctable offset span for each of the gain

settings and the LSB weight (mV) for the Offset Correction

registers. T he maximum value which can be written to the

offset correction registers is ±31 decimal —see Figure 4.

Figure 4 shows the relationship between the Offset Correc-

tion register contents and the offset (mV) on the analog inputs

for a gain setting of one. In order to perform an offset

adjustment, T he analog inputs should be first connected to

AGND, and there should be no signal on either Channel 1

or Channel 2. A read from Channel 1 or Channel 2 using the

M aximum input signal levels for Channel 1

Max Signal

C h a n n el 1

AD C Input Range Selection

0 . 5 V

0 . 2 5 V

0 . 1 2 5 V

0.5V

0.25V

Gain = 1

—

Gain = 2 Gain = 1

0.125V

0.0625V

0.0313V

0.0156V

0.00781V

Gain = 4 Gain = 2 Gain = 1

Gain = 8 Gain = 4 Gain = 2

Gain = 16 Gain = 8 Gain = 4

—

Gain = 16 Gain = 8

Gain = 16

—

–9 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

Table II

Offset Correction range

T he current signal needs to be recovered from the di/dt signal

before it can be used. An integrator is therefore necessary to

restore the signal to its original form. T he ADE7753 has a

built-in digital integrator to recover the current signal from

the di/dt sensor. T he digital integrator on C hannel 1 is

switched off by default when the ADE7753 is powered up.

Setting the M SB of C H 1O S register will turn on the

integrator. Figures 6 to 9 show the magnitude and phase

response of the digital integrator.

G a in

Cor r ectable Span

LSB Size

1

2

4

8

± 50m V

± 37m V

± 30m V

± 26m V

± 24m V

1.61m V/LSB

1.19m V/LSB

0.97m V/LSB

0.84m V/LSB

0.77m V/LSB

16

10

Waveform register will give an indication of the offset in the

channel. T his offset can be canceled by writing an equal and

opposite offset value to the relevant offset register. T he offset

correction can be confirmed by performing another read.

Note when adjusting the offset of Channel 1, one should

disable the digital integrator and the HPF.

0

-10

-20

-30

-40

-50

CH1OS[5:0]

Sign + 5 Bits

01, 1111b

1Fh

00h

10²

10³

FREQUENCY-Hz

0mV

Figure 6– Com bined gain response of the digital integrator

and phase com pensator

-50mV

+50mV

Offset

Adjust

-88

-88.5

-89

Sign + 5 Bits

11, 1111b

3Fh

Figure 4– Channel Offset Correction Range (Gain = 1)

-89.5

-90

di/dt CURRENT SENSO R AND D IGITAL INTEGRATO R

di/dt sensor detects changes in magetic field caused by ac

current. Figure 5 shows the principle of a di/dt current

sensor.

-90.5

10²

10³

FREQUENCY-Hz

Figure 7– Com bined phase response of the digital integra-

tor and phase com pensator

Magnetic field created by current

(directly proportional to current)

-1

-1.5

-2

+

EMF (electromotive force)

induced by changes in

magnetic flux density (d/dt)

-

-2.5

-3

Figure 5– Principle of a di/dt current sensor

-3.5

-4

T he flux density of a magnetic field induced by a current is

directly proportional to the magnitude of the current. T he

changes in the magnetic flux density passing through a

conductor loop generates an electromotive force (EM F)

between the two ends of the loop. T he EMF is a voltage signal

which is proportional to the di/dt of the current. T he voltage

output from the di/dt current sensor is determined by the

mutual inductance between the current carrying conductor

and the di/dt sensor.

-4.5

-5

-5.5

-6

40

45

50

55

FREQUENCY-Hz

60

65

70

Figure 8– Com bined gain response of the digital integrator

and phase com pensator (40Hz to 70Hz)

–1 0 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

T he phase response of this filter is shown in the Channel 2

Sampling section of this data sheet. T he phase lag response of

LPF1 results in a time delay of approximately 0.97ms (@

60H z) between the zero crossing on the analog inputs of

Channel 2 and the rising or falling edge of ZX.

-89.7

-89.75

-89.8

T he zero-crossing detection also drives one flag bit in the

interrupt status register. An active low in the IRQ output will

also appear if the corresponding bit in the Interrupt Enable

register is set to logic one.

T he flag in the Interrupt status register as well as the IRQ

output are reset to their default value when the Interrupt

Status register with reset (RST ST AT US) is read.

-89.85

-89.9

-89.95

-90

-90.05

Zero Crossing Tim eout

40

45

50

55

FREQUENCY-Hz

60

65

70

T he zero crossing detection also has an associated time-out

register ZXT O U T . T his u n sign ed , 12-bit register is

decremented (1 LSB) every 128/CLKIN seconds. T he reg-

ister is reset to its user programmed full scale value every time

a zero crossing on Channel 2 is detected. T he default power

on value in this register is FFFh. If the register decrements

to zero before a zero crossing is detected and the DISSAG bit

in the Mode register is logic zero, the SAG pin will go active

low. T he absence of a zero crossing is also indicated on the

IRQ pin if the ZXT O enable bit in the Interrupt Enable

register is set to logic one. Irrespective of the enable bit

setting, the ZXT O flag in the Interrupt Status register is

always set when the ZXT OUT register is decremented to

zero - see ADE7753 Interrupts.

Figure 9– Com bined phase response of the digital integra-

tor and phase com pensator (40Hz to 70Hz)

N ote that the integrator has a -20dB/dec attenuation and

approximately -90° phase shift. When combined with a di/dt

sensor, the resulting magnitude and phase response should be

a flat gain over the frequency band of interest. However, the

di/dt sensor has a 20dB/dec gain associated with it, and

generates significant high frequency noise, a more effective

anti-aliasing filter is needed to avoid noise due to aliasing—

see Antialias Filter.

When the digital integrator is switched off, the ADE7753 can

be used directly with a conventional current sensor such as

current transformer (CT ) or a low resistance current shunt.

T he Zerocross T ime-out register can be written/read by the

user and has an address of 1Dh - see Serial Interface section. T he

resolution of the register is 128/CLKIN seconds per LSB.

T hus the maximum delay for an interrupt is 0.15 second

(128/CLKIN × 2¹²).

ZERO CRO SSING D ETECTIO N

T he AD E7753 has a zero crossing detection circuit on

Channel 2. T his zero crossing is used to produce an external

zero cross signal (ZX) and it is also used in the calibration

mode - see Energy Calibration. T he zero crossing signal is also

used to initiate a temperature measurement on the ADE7753

- see Temperature Measurement.

Figure 11 shows the mechanism of the zero crossing time out

detection when the line voltage stays at a fixed DC level for

more than CLKIN/128 x ZXT OUT seconds.

16-bit internal

register value

ZXTOUT

Figure 10 shows how the zero cross signal is generated from

the output of LPF1.

REFERENCE

x1, x2, x4,

x8, x16

TO

Channel 2

V2P

V2N

GAIN[7:5]

MULTIPLIER

1

-63% to + 63% FS

V2

PGA2

ADC 2

ZXTO

detection bit

ZERO

CROSS

ZX

LPF1

f

= 140Hz

-3dB

23.2 8@ 60Hz

1.0

0.92

Figure 11 - Zero crossing Tim e out detection

ZX

P ERIOD MEASUREMENT

V2

LPF1

T he ADE7753 provides also the period measurement of the

line. T he period register is an unsigned 15-bit register and is

updated every period.

Figure 10– Zero cross detection on Channel 2

T he ZX signal will go logic high on a positive going zero

crossing and logic low on a negative going zero crossing on

Channel 2. T he zero crossing signal ZX is generated from the

output of LPF1. LPF1 has a single pole at 156Hz (at CLKIN

= 3.579545M H z). As a result there will be a phase lag

between the analog input signal V2 and the output of LPF1.

T he resolution of this register is 2.2m s/LSB when

CLKIN=3.579545MHz, which represents 0.013% when the

line frequency is 60Hz. When the line frequency is 60Hz, the

value of the Period register is approximately 7576d. T he

length of the register enables the measurement of line

frequencies as low as 13.9Hz.

–1 1 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

P OWER SUP P LYMONITOR

T he ADE7753 also contains an on-chip power supply moni-

tor. T he Analog Supply (AV ) is continuously monitored

by the ADE7753. If the supply is less than 4V ± 5% then the

ADE7753 will go into an inactive state, i.e. no energy will be

accumulated when the supply voltage is below 4V. T his is

useful to ensure correct device operation at power up and

during power down. T he power supply monitor has built-in

hysteresis and filtering. T his gives a high degree of immunity

to false triggering due to noisy supplies.

tains 03h the SAG pin will go active low at the end of the fifth

line cycle for which the line voltage falls below the threshold,

if the DISSAG bit in the Mode register is logic zero. As is

the case when zero-crossings are no longer detected, the sag

event is also recorded by setting the SAG flag in the Interrupt

Status register. If the SAG enable bit is set to logic one, the

IRQ logic output will go active low - see ADE7753 Interrupts.

T he SAG pin will go logic high again when the absolute value

of the signal on Channel 2 exceeds the sag level set in the Sag

Level register. T his is shown in Figure 13 when the SAG pin

goes high during the tenth line cycle from the time when the

signal on Channel 2 first dropped below the threshold level.

DD

AV

DD

Sag LevelSet

5V

4V

T he contents of the Sag Level register (1 byte) are compared

to the absolute value of the most significant byte output from

LPF1, after it is shifted left by one bit. T hus for example the

nominal maximum code from LPF1 with a full scale signal

on Channel 2 is 2518h—see Channel 2 sampling. Shifting one

bit left will give 4A30h. T herefore writing 4Ah to the SAG

Level register will put the sag detection level at full scale.

Writing 00h will put the sag detection level at zero. T he Sag

Level register is compared to the most significant byte of a

waveform sample after the shift left and detection is made

when the contents of the sag level register are greater.

0V

Time

ADE7753

Power-on

Inactive

State

Inactive

Active

Inactive

SAG

P EAK DETECTION

Figure 12 - On-Chip power supply m onitor

T he ADE7753 can also be programmed to detect when the

absolute value of the voltage or the current channel of one

phase exceeds a certain peak value. Figure 14 illustrates the

behavior of the peak detection for the voltage channel.

As can be seen from Figure 12 the trigger level is nominally

set at 4V. T he tolerance on this trigger level is about ±5%.

T he SAG pin can also be used as a power supply monitor

input to the MCU. T he SAG pin will go logic low when the

AD E7753 is in its inactive state. T he power supply and

decoupling for the part should be such that the ripple at

V

2

VPKLVL[7:0]

AV

does not exceed 5V± 5% as specified for normal

D D

operation.

LINE VO LTAGE SAG D E TE CTIO N

PKV reset low

when RSTSTATUS register

is read

In addition to the detection of the loss of the line voltage

signal (zero crossing), the AD E7753 can also be pro-

grammed to detect when the absolute value of the line voltage

drops below a certain peak value, for a number of line cycles.

T his condition is illustrated in Figure 13 below.

PKV Interrupt Flag

(Bit 8 of STATUS register)

Read RSTSTATUS register

Channel 2

Full Scale

Figure 14 - ADE7753 Peak detection

SAGLVL[7:0]

Both channel 1 and channel 2 are monitored at the same time.

Figure 14 shows a line voltage exceeding a threshold which

is set in the Voltage peak register (VPKLVL[7:0]). T he

Voltage Peak event is recorded by setting the PKV flag in the

Interrupt Status register. If the PKV enable bit is set to logic

one in the Interrupt Mask register, the IRQ logic output will

go active low. Similarly, the Current Peak event is recorded

by setting the PKI flag in the Ineterrupt Status register—see

ADE7753 Interrupts.

SAG reset high

when Channel 2

exceeds SAGLVL[7:0]

SAGCYC[7:0] = 06H

6 half cycles

SAG

PeakLevelSet

T he contents of the VPKLVL and IPKLVL registers are

respectively compared to the absolute value of channel 1 and

channel 2, after they are multiplied by 2.

Figure 13– ADE7753 Sag detection

Figure 13 shows the line voltage fall below a threshold which

is set in the Sag Level register (SAGLVL[7:0]) for five line

cycles. Since the Sag Cycle register (SAGCYC[7:0]) con-

–1 2 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

T hus, for example, the nominal maximum code from the

channel 1 ADC with a full scale signal is 2851ECh —see

Channel 1 Sampling. Multiplying by 2 will give 50A3D8h.

T herefore, writing 50h to the IPKLVL register will put the

channel 1 peak detection level at full scale and set the current

peak detection to its least sensitive value.

Writing 00h will put the channel 1 detection level at zero.

T he detection is done when the content of the IPKLVL

register is smaller than the incoming channel 1 sample.

read command—see Interrupt timing. When carrying out a read

with reset, the AD E7753 is designed to ensure that no

interrupt events are missed. If an interrupt event occurs just

as the Status register is being read, the event will not be lost

and the IRQ logic output is guaranteed to go high for the

duration of the Interrupt Status register data transfer before

going logic low again to indicate the pending interrupt. See

the next section for a more detailed description.

Using the AD E7753 Interrupts with an MCU

P eak Level Recor d

Shown in Figure 15 is a timing diagram which shows a

suggested implementation of AD E7753 interrupt manage-

ment using an MCU. At time t₁the IRQ line will go active

low indicating that one or more interrupt events have oc-

curred in the ADE7753. T he IRQ logic output should be tied

to a negative edge triggered external interrupt on the MCU.

On detection of the negative edge, the M C U should be

configured to start executing its Interrupt Service Routine

(ISR). On entering the ISR, all interrupts should be disabled

using the global interrupt enable bit. At this point the MCU

external interrupt flag can be cleared in order to capture

interrupt events which occur during the current ISR. When

the MCU interrupt flag is cleared a read from the Status

register with reset is carried out. T his will cause the IRQ line

to be reset logic high (t₂)—see Interrupt timing. T he Status

register contents are used to determine the source of the

interrupt(s) and hence the appropriate action to be taken. If

a subsequent interrupt event occurs during the ISR, that event

will be recorded by the MCU external interrupt flag being set

again (t₃). On returning from the ISR, the global interrupt

mask will be cleared (same instruction cycle) and the external

interrupt flag will cause the MCU to jump to its ISR once

again. T his will ensure that the MCU does not miss any

external interrupts.

T he ADE7753 records the maximum absolute value reached

by channel 1 and channel 2 in two different registers - IPEAK

and VPEAK respectively. VPEAK and IPEAK are 24-bit

unsigned registers. T hese registers are updated each time the

absolute value of the Waveform sample from the correspond-

ing channel is above the value stored in the VPEAK or IPEAK

register. T he contents of the VPEAK register corresponds to

2 times the maximum absolute value observed on the channel

2 input. T he contents of IPEAK represents the max absolute

value observed on the channel 1 input. Reading the

RST VPEAK and RST IPEAK registers will clear their re-

spective contents after the read operation.

AD E7753 INTERRUP TS

AD E7753 Interrupts are managed through the Interrupt

Status register (ST AT US[15:0]) and the Interrupt Enable

register (IRQEN[15:0]). When an interrupt event occurs in

the ADE7753, the corresponding flag in the Status register

is set to a logic one - see Interrupt Status register. If the enable

bit for this interrupt in the Interrupt Enable register is logic

one, then the IRQ logic output goes active low. T he flag bits

in the Status register are set irrespective of the state of the

enable bits.

In order to determine the source of the interrupt, the system

master (M C U ) should perform a read from the Status

register with reset (RST ST AT US[15:0]). T his is achieved

by carrying out a read from address 0Ch. T he IRQ output will

go logic high on completion of the Interrupt Status register

Interrupt tim ing

T he ADE7753 Serial Interface section should be reviewed first

before reviewing the interrupt timing. As previously de-

MCU

int. flag set

t

3

t

2

t

1

IRQ

Read

Status with

Reset (05h)

ISR Return

Global int. Mask

Reset

ISR Action

Jump to

MCU Program

Sequence

Global int.

Mask Set

Clear MCU

int. flag

Jump to

ISR

(Based on Status contents)

ISR

Figure 15– ADE7753 interrupt m anagem ent

CS

t

1

t

9

SCLK

DIN

0

1

0

1

t

11

DB0

DB7

DB0

DB7

DOUT

Read Status Register Command

Status Register Contents

IRQ

Figure 16– ADE7753 interrupt tim ing

–1 3 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

scribed, when the IRQ output goes low the MCU ISR must

read the Interrupt Status register in order to determine the

source of the interrupt. When reading the Status register

contents, the IRQ output is set high on the last falling edge

of SCLK of the first byte transfer (read Interrupt Status

register command). T he IRQ output is held high until the last

bit of the next 15-bit transfer is shifted out (Interrupt Status

register contents)— see Figure 16. If an interrupt is pending

at this time, the IRQ output will go low again. If no interrupt

is pending the IRQ output will stay high.

the 1-bit ADC is virtually meaningless. Only when a large

number of samples are averaged will a meaningful result be

obtained. T his averaging is carried out in the second part of

the ADC, the digital low pass filter. By averaging a large

number of bits from the modulator the low pass filter can

produce 24-bit data words which are proportional to the input

signal level.

T he sigma-delta converter uses two techniques to achieve

high resolution from what is essentially a 1-bit conversion

technique. T he first is over-sampling. By over sampling we

mean that the signal is sampled at a rate (frequency) which is

many times higher than the bandwidth of interest. F or

example the sampling rate in the AD E7753 is C LKIN /4

(894kHz) and the band of interest is 40Hz to 2kHz. Over-

sampling has the effect of spreading the quantization noise

(noise due to sampling) over a wider bandwidth. With the

noise spread more thinly over a wider bandwidth, the

quantization noise in the band of interest is lowered—see

Figure 18. However, oversampling alone is not an efficient

enough method to improve the signal to noise ratio (SNR) in

the band of interest. For example, an oversampling ratio of

4 is required just to increase the SNR by only 6dB (1-Bit). T o

keep the oversampling ratio at a reasonable level, it is

possible to shape the quantization noise so that the majority

of the noise lies at the higher frequencies. T his is what

happens in the sigma-delta modulator, the noise is shaped by

the integrator which has a high pass type response for the

quantization noise. T he result is that most of the noise is at

the higher frequencies where it can be removed by the digital

low pass filter. T his noise shaping is also shown in Figure 18.

TEMP ERATURE MEASUREMENT

ADE7753 also includes an on-chip temperature sensor. A

temperature measurement can be made by setting bit 5 in the

Mode register. When bit 5 is set logic high in the Mode

register, the ADE7753 will initiate a temperature measure-

ment on the next zero crossing. When the zero crossing on

Channel 2 is detected the voltage output from the tempera-

ture sensing circuit is connected to ADC1 (Channel 1) for

digitizing. T he resultant code is processed and placed in the

T emperature register (T EMP[7:0]) approximately 26µs later

(24 C LKIN cycles). If enabled in the Interrupt Enable

register (bit 5), the IRQ output will go active low when the

temperature conversion is finished. Please note that tempera-

ture conversion will introduce a small amount of noise in the

energy calculation. If temperature conversion is performed

frequently (e.g. multiple times per second), a noticeable

error will accumulate in the resulting energy calculation over

time.

T he contents of the T emperature register are signed (2's

complement) with a resolution of approximately 1 LSB/°C.

T he temperature register will produce a code of 00h when the

ambient temperature is approximately 70°C. T he tempera-

ture measurement is uncalibrated in the ADE7753 and has an

offset tolerance that could be as high as ±20°C.

Antialias filter (RC)

Sampling

Digital filter

Shaped

Frequency

Signal

Noise

AD E7753 ANALO G TO D IGITAL CO NVERSIO N

T he analog-to-digital conversion in the ADE7753 is carried

out using two second order sigma-delta ADCs. For simplic-

ity reason, the block diagram in Figure 17 shows a first order

sigma-delta ADC. T he converter is made up of two parts: the

sigma-delta modulator and the digital low pass filter.

Noise

0

2kHz

447kHz

894kHz

Frequency (Hz)

MCLK/4

High resolution

Signal

INTEGRATOR

Digital Low Pass Filter

output from Digital

LPF

Analog Low Pass Filter

LATCHED

COMPARATOR

+

-

e

Σ

-

R

V

REF

24

Noise

C

....10100101......

1-Bit DAC

0

2kHz

447kHz

894kHz

Frequency (Hz)

Figure 17– First Order Sigm a-Delta (Σ−∆) ADC

Figure 18– Noise reduction due to Oversam pling & Noise

shaping in the analog m odulator

A sigma-delta modulator converts the input signal into a

continuous serial stream of 1's and 0's at a rate determined by

the sampling clock. In the ADE7753 the sampling clock is

equal to CLKIN/4. T he 1-bit DAC in the feedback loop is

driven by the serial data stream. T he DAC output is sub-

tracted from the input signal. If the loop gain is high enough

the average value of the DAC output (and therefore the bit

stream) will approach that of the input signal level. For any

given input value in a single sampling interval, the data from

AntialiasFilter

Figure 17 also shows an analog low pass filter (RC) on the

input to the modulator. T his filter is present to prevent

aliasing. Aliasing is an artifact of all sampled systems.

Basically it means that frequency components in the input

signal to the ADC which are higher than half the sampling

rate of the AD C will appear in the sampled signal at a

–1 4 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

Output

Impedance

frequency below half the sampling rate. Figure 19 illustrates

the effect. Frequency components (arrows shown in black)

above half the sampling frequency (also know as the Nyquist

frequency, i.e., 447kH z) get imaged or folded back down

below 447kHz (arrows shown in grey). T his will happen with

all AD C s regardless of the architecture. In the example

shown, only frequencies near the sampling frequency, i.e.,

894kHz, will move into the band of interest for metering, i.e,

40Hz - 2kHz. T his allows the usage of very simple LPF (Low

Pass Filter) to attenuate high frequency (near 900kHz) noise

and prevents distortion in the band of interest. For conven-

tional current sensor, a simple RC filter (single pole LPF)

with a corner frequency of 10kHz will produce an attenuation

of approximately 40dBs at 894kH z—see Figure 18. T he

20dB per decade attenuation is usually sufficient to eliminate

the effects of aliasing for conventional current sensor.

For di/dt sensor such as Rogowski coil, however, the sensor

has 20dB per decade gain. T his will neutralize the -20dB per

decade attenuation produced by the simple LPF. T herefore,

when using a di/dt sensor, care should be taken to offset the

20dB per decade gain coming from the di/dt sensor. One

simple approach is to cascade two RC filters to produce the

-40dB per decade attenuation needed.

Maximum

Load = 10µA

6kΩ

REF_IN/OUT

2.42V

PTAT

60µA

2.5V

1.7kΩ

12.5kΩ

Reference input to ADC

Channel 1 (Range Select)

2.42V, 1.21V, 0.6V

12.5kΩ

Figure 20 —ADE7753 Reference Circuit Ouput

T he REF_IN/OUTpin can be overdriven by an external source,

e.g., an external 2.5V reference. N ote that the nominal

reference value supplied to the ADCs is now 2.5V not 2.42V.

T his has the effect of increasing the nominal analog input

signal range by 2.5/2.42×100% = 3% or from 0.5V to

0.5165V.

T he voltage of AD E7753 reference drifts slightly with

temperature—see ADE7753 Specifications for the temperature

coefficient specification (in ppm/°C ) . T he value of the

temperature drift varies from part to part. Since the reference

is used for the ADCs in both Channel 1 and 2, any x% drift

in the reference will result in 2x% deviation of the meter

accuracy. T he reference drift resulting from temperature

changes is usually very small and it is typically much smaller

than the drift of other components on a meter. However, if

guaranteed temperature performance is needed, one needs to

use an external voltage reference. Alternatively, the meter can

be calibrated at multiple temperatures. Real time compensa-

tion can be easily achieved using the on the on-chip temperature

sensor.

Aliasing Effects

Sampling Frequency

image

frequencies

894kHz

0

2kHz

447kHz

Frequency (Hz)

Figure 19 —ADC and signal processing in Channel 1

ADC transfer function

Below is an expression which relates the output of the LPF

in the sigma-delta ADC to the analog input signal level. Both

ADCs in the ADE7753 are designed to produce the same

output code for the same input signal level.

C H ANNE L 1 AD C

V_in

=

×

262,144

Code (ADC) 3.0492

Figure 21 shows the ADC and signal processing chain for

Channel 1. In waveform sampling mode the ADC outputs a

signed 2’s Complement 24-bit data word at a maximum of

27.9kSPS (CLKIN/128). With the specified full scale ana-

log input signal of 0.5V (or 0.25V or 0.125V – see Analog

Inputs section) the ADC will produce an output code which is

approximately between 2851EC h (+ 2,642,412 D ecimal)

and D7AE14h (-2,642,412 Decimal). T his is illustrated in

Figure 21.

V_out

T herefore with a full scale signal on the input of 0.5V and an

internal reference of 2.42V, the ADC output code is nomi-

nally 165,151 or 2851Fh. T he maximum code from the

ADC is ±262,144, this is equivalent to an input signal level

of ± 0.794V. H owever for specified performance it is not

recommended that the full-scale input signal level of 0.5V be

exceeded.

Channel1Sam pling

ADE7753Reference circuit

T he waveform samples may also be routed to the WAVE-

FORM register (M OD E[14:13] = 1,0) to be read by the

system master (M C U ). In waveform sampling mode the

WSMP bit (bit 3) in the Interrupt Enable register must also

be set to logic one. T he Active, Apparent Power and Energy

calculation will remain uninterrupted during waveform sam-

plin g.

When in waveform sample mode, one of four output sample

rates may be chosen by using bits 11 and 12 of the Mode

register (WAVSEL1,0). T he output sample rate may be

27.9kSPS, 14kSPS, 7kSPS or 3.5kSPS—see Mode Register.

T he interrupt request output IRQ signals a new sample

Shown below in Figure 20 is a simplified version of the

reference output circuitry. T he nominal reference voltage at

the REF_IN/OUTpin is 2.42V. T his is the reference voltage used

for the ADCs in the ADE7753. H owever, Channel 1 has

three input range selections which are selected by dividing

down the reference value used for the ADC in Channel 1. T he

reference value used for Channel 1 is divided down to ½ and

¼ of the nominal value by using an internal resistor divider

as shown in Figure 20.

–1 5 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

availability by going active low. T he timing is shown in

Figure 22. T he 24-bit waveform samples are transferred

from the ADE7753 one byte (8-bits) at a time, with the most

significant byte shifted out first. T he 24-bit data word is right

justified - see ADE7753 Serial Interface.

RM S register is equivalent to one LSB of a channel 1

waveform sample. T he update rate of the channel 1 RMS

measurement is CLKIN /4.

Current Signal - i(t)

2851ECh

I

(t)

rms

IRMSOS[11:0]

00h

1C82B3h

00h

D7AE14h

2²⁵2²⁶

2²⁷

2¹⁷2¹⁶2¹⁵

SIGN

IRQ

SCLK

+

LPF3

HPF

Read from WAVEFORM

24

IRMS

Channel 1

0

01 Hex

DIN

Σ

Sign

DOUT

Channel 1 DATA - 24 bits

Figure 23 - Channel 1 RMS signal processing

Figure 22 – Waveform sam pling Channel 1

With the specified full scale analog input signal of 0.5V, the

ADC will produce an output code which is approximately

±2,642,412d—see Channel 1 ADC. T he equivalent RMS val-

ues of a full-scale AC signal is 1,868,467d (1C82B3h).

T he interrupt request output IRQ stays low until the interrupt

routine reads the Reset Status register - see ADE7753 Interrupt.

Channel1RMS calculation

Channel 1RMS offset com pensation

Root Mean Square (RMS) value of a continuous signal V(t)

is defined as:

T he ADE7753 incorporates a channel 1 RMS offset compen-

sation register (IRM SOS). T his is 12-bit signed registers

which can be used to remove offset in the channel 1 RMS

calculation. An offset may exist in the RMS calculation due

to input noises that are integrated in the DC component of

V²(t). T he offset calibration will allow the content of the

IRMS register to be maintained at zero when no input is

present on channel 1.

T

1

2

()

=

V_rms

V t dt

∫

(1)

T

0

For time sampling signals, rms calculation involves squaring

the signal, taking the average and obtaining the square root:

1 LSB of the Channel 1 RMS offset are equivalent to 32,768

LSB of the square of the Channel 1 RMS register. Assuming

that the maximum value from the Channel 1 RMS calcula-

tion is 1,868,467d with full scale AC inputs, then 1 LSB of

the channel 1 RMS offset represents 0.46% of measurement

error at -60dB down of full scale.

N

1

V_rms

V ²(i)

=

∑

(2)

N

=

i

1

AD E7753 calculates simultaneously the RM S values for

Channel 1 and Channel 2 in different register. Figure 23

shows the detail of the signal processing chain for the RMS

calculation on channel 1. T he channel 1 RM S value is

processed from the samples used in the channel 1 waveform

sampling mode. T he channel 1 RMS value is stored in an

unsigned 24-bit register (IRMS). One LSB of the channel 1

2

=

+ ×

IRMSOS 32768

I_rms

0

where I_rmsois the RMS measurement without offset correc-

tion.

CURRENT RMS (IRMS)

CALCULATION

2.42V, 1.21V, 0.6V

REFERENCE

x8, x16

GAIN[4:3]

x1, x2, x4,

WAVEFORM SAMPLE

REGISTER

DIGITAL

INTEGRATOR*

GAIN[2:0]

V1P

V1N

HPF

ACTIVE AND REACTIVE

POWER CALCULATION

V1

PGA1

ADC 1

∫

Channel 1 (Current Waveform)

Data Range After integrator (50Hz)

50Hz

60Hz

1EF73Ch

000000h

E108C4h

V1

0.5V, 0.25V,

0.125V, 62.5mV,

31.3mV, 15.6mV,

2851ECh

Channel 1 (Current Waveform)

Data Range

000000h

0V

2851ECh

000000h

D7AE14h

ADC Output

word Range

Analog

Input

Range

Channel 1 (Current Waveform)

Data Range After Integrator (60Hz)

19CE08h

000000h

E631F8h

*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED

DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A -20dB/DECADE

FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.

Figure 21 —ADC and signal processing in Channel 1

–1 6 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

C H ANNE L 2 AD C

directly to the multiplier and is not filtered. A HPF is not

required to remove any DC offset since it is only required to

remove the offset from one channel to eliminate errors due to

offsets in the power calculation. When in waveform sample

mode, one of four output sample rates can be chosen by using

bits 11 and 12 of the Mode register. T he available output

sample rates are 27.9kSPS, 14kSPS, 7kSPS or 3.5kSPS—

see Mode Register. T he interrupt request output IRQ signals a

sample availability by going active low. T he timing is the

same as that for Channel 1 and is shown in Figure 22.

Channel2Sam pling

In Channel 2 waveform sampling mode (MODE[14:13] =

1,1 and WSM P = 1) the AD C output code scaling for

Channel 2 is not the same as Channel 1. Channel 2 waveform

sample is a 16-bit word and sign extended to 24 bits. For

normal operation, the differential voltage signal between

V2P and V2N should not exceed 0.5V. With maximum

voltage input (±0.5V at PGA gain of 1), the outputs from the

AD C swings between 2852h and D 7AEh (± 10,322 D eci-

mal). However, before being passed to the Waveform register,

the ADC output is passed through a single pole, low pass

filter with a cutoff frequency of 140Hz. T he plots in Figure

24 shows the magnitude and phase response of this filter.

Channel2RMS calculation

Figure 26 shows the details of the signal processing chain for

the RMS calculation on Channel 2. T he channel 2 RMS

value is processed from the samples used in the channel 2

waveform sampling mode. T he RMS value will be slightly

attenuated because of LPF1. Channel 2 RMS value is stored

in the unsigned 24-bit VRMS register. T he update rate of the

channel 2 RMS measurement is CLKIN/4.

With the specified full scale AC analog input signal of 0.5V,

the outputs from the LPF 1 swings between 2518h and

DAE8h at 60 Hz- see Channel 2 ADC. T he equivalent RMS

value of this full-scale AC signal is approximately 1,561,400

(17D338h) in the VRMS register.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

0

60 Hz, -0.73dB

50 Hz, -0.52dB

-2

-4

50 Hz, -19.7°

-6

60 Hz, -23.2°

-8

-10

-12

-14

-16

-18

Voltage Signal - V(t)

2518h

VRMSOS[11:0]

9

8

2

1

0

2

0h

SGN

2

10¹

10²

10³

DAE8h

VRMS[23:0]

Frequency (Hz)

LPF3

LPF1

17D338h

+

Channel 2

00h

S

Figure 24 – Magnitude & Phase response of LPF1

T he LPF1 has the effect of attenuating the signal. For

example if the line frequency is 60Hz, then the signal at the

output of LPF1 will be attenuated by about 8%.

Figure 26 - Channel 2 RMS signal processing

Channel 2RMS offset com pensation

T he ADE7753 incorporates a channel 2 RMS offset compen-

sation register (VRMSOS). T his is a 12-bit signed registers

which can be used to remove offset in the channel 2 RMS

calculation. An offset may exist in the RMS calculation due

to input noises and dc offset in the input samples. T he offset

calibration allows the contents of the VRMS register to be

maintained at zero when no voltage is applied.

1 LSB of the channel 2 RMS offset are equivalent to 1 LSB

of the RMS register. Assuming that the maximum value from

the channel 2 RMS calculation is 1,561,400d with full scale

AC inputs, then 1 LSB of the channel 2 RMS offset represents

0.064% of measurement error at -60dB down of full scale.

1

=

= −

0.919 0.73dB

H(f)

2

60Hz

(

)

+

1

140Hz

Note LPF1 does not affect the power calculation. T he signal

processing chain in Channel 2 is illustrated in Figure 25.

2.42V

REFERENCE

x1, x2, x4,

x8, x16

V2P

V2N

GAIN[7:5]

ACTIVE AND REACTIVE

ENERGY CALCULATION

V2

PGA2

ADC 2

LPF1

VRMS CALCULATION

AND WAVEFORM

SAMPLING

Analog

V1

=

+

V_rmsV_rmsoVRMSOS

(PEAK/SAG/ZX)

Input Range

0.5V, 0.25V, 0.125V,

62.5mV, 31.25mV

LPF Output

word Range

2852h

2518h

where V_rmsois the RMS measurement without offset correc-

tion.

0V

0000h

DAE8h

D7AEh

P HASE COMP ENSATION

When the HPF is disabled, the phase error between Channel

1 and Channel 2 is zero from DC to 3.5kHz. When HPF is

enabled, C hannel 1 has a phase response illustrated in

Figures 28 & 29. Also shown in Figure 30 is the magnitude

response of the filter. As can be seen from the plots, the phase

response is almost zero from 45Hz to 1kHz, T his is all that

is required in typical energy measurement applications.

Figure 25 – ADC and Signal Processing in Channel 2

Unlike Channel 1, Channel 2 has only one analog input range

(1V differential). However like Channel 1, Channel 2 does

have a PGA with gain selections of 1, 2, 4, 8 and 16. For

energy measurement, the output of the AD C is passed

–1 7 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

H owever, despite being internally phase compensated the

AD E7753 must work with transducers which may have

inherent phase errors. For example a phase error of 0.1° to

0.3° is not uncommon for a CT (Current T ransformer).

T hese phase errors can vary from part to part and they must

be corrected in order to perform accurate power calculations.

T he errors associated with phase mismatch are particularly

noticeable at low power factors. T he ADE7753 provides a

means of digitally calibrating these small phase errors. T he

ADE7753 allows a small time delay or time advance to be

introduced into the signal processing chain in order to

compensate for small phase errors. Because the compensa-

tion is in time, this technique should only be used for small

phase errors in the range of 0.1° to 0.5°. Correcting large

phase errors using a time shift technique can introduce

significant phase errors at higher harmonics.

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-0.1

10²

10³

10⁴

FREQUENCY-Hz

T he Phase C alibration register (PH C AL[5:0]) is a 2’s

complement signed single byte register which has values

ranging from 21h (-31 in Decimal) to 1Fh (31 in Decimal).

T he register is centered at 0Dh, so that writing 0Dh to the

register gives zero delay. By changing the PHCAL register,

the time delay in the Channel 2 signal path can change from

–100.8µs to +33.6µs (CLKIN = 3.579545MHz). One LSB

is equivalent to 2.22µs time delay or advance. With a line

frequency of 60Hz this gives a phase resolution of 0.048° at

the fundamental (i.e., 360° × 2.22µs × 60H z). Figure 27

illustrates how the phase compensation is used to remove a

0.1° phase lead in Channel 1 due to the external transducer.

In order to cancel the lead (0.1°) in Channel 1, a phase lead

must also be introduced into Channel 2. T he resolution of the

phase adjustment allows the introduction of a phase lead in

increment of 0.048°. T he phase lead is achieved by introduc-

ing a time advance into Channel 2. A time advance of 4.48µs

is made by writing -2 (0Bh) to the time delay block, thus

reducing the amount of time delay by 4.48µs, or equivalently,

a phase lead of approximately 0.1° at line frequency of 60Hz.

0Bh represents -2 because the register is centered with zero

at 0Dh.

Figure 28 – Com bined Phase Response of the HPF & Phase

Com pensation (10Hz to 1kHz)

0.2

0.15

0.1

0.05

-0.05

-0.1

-0.15

-0.2

40

45

50

55

60

65

70

FREQUENCY-Hz

Figure 29 – Com bined Phase Response of the HPF & Phase

Com pensation (40Hz to 70Hz)

0.2

0.18

0.16

0.14

0.12

0.1

V1P

HPF

24

V1

PGA1

ADC 1

LPF2

V1N

V2P

24

1

Channel 2 delay

reduced by 4.48µs

(0.18lead at 60Hz)

Delay Block

4.48µs / LSB

V2

PGA2

ADC 2

V2

V1

V2N

V1

0.08

0.06

0.04

0.02

0

0Bh in PHCAL[5:0]

0

5

V2

0.18

0

1 0 1 1

PHCAL[5:0]

-100µs to +34µs

60Hz

40

45

50

55

60

65

70

FREQUENCY-Hz

60Hz

Figure 30 – Com bined Gain Response of the

HPF & Phase Com pensation

Figure 27 – Phase Calibration

AC T IVE P O WE R C ALC U LAT IO N

Power is defined as the rate of energy flow from source to

load. It is defined as the product of the voltage and current

waveforms. T he resulting waveform is called the instanta-

neous power signal and it is equal to the rate of energy flow

at every instant of time. T he unit of power is the watt or joules/

–1 8 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

sec. Equation 3 gives an expression for the instantaneous

power signal in an ac system.

Since LPF2 does not have an ideal “brick wall” frequency

response—see Figure 32, the Active Power signal will have

some ripple due to the instantaneous power signal. T his

ripple is sinusoidal and has a frequency equal to twice the line

frequency. Since the ripple is sinusoidal in nature it will be

removed when the Active Power signal is integrated to

calculate Energy – see Energy Calculation.

(1)

_v(_t)₌

_i(_t)₌

( )

ω

2V sin

t

(2)

( )

ω

t

2I sin

where V = rms voltage,

I = rms current.

0

_p(_t)₌()_×()

i t

v t

-4

(3)

_p(_t)₌

( )

−

ω

VI VI cos t

-8

T he average power over an integral number of line cycles (n)

is given by the expression in Equation 4.

-12

-16

-20

-24

1

nT

_p(_t)_{dt VI}

=

P

∫

(4)

0

nT

3.0Hz

10Hz

30Hz

100Hz

1.0Hz

Frequency

where T is the line cycle period.

P is referred to as the Active or Real Power. Note that the

active power is equal to the dc component of the instanta-

neous power signal p(t) in Equation 3 , i.e., VI. T his is the

relationship used to calculate active power in the ADE7753.

T he instantaneous power signal p(t) is generated by multiply-

ing the current and voltage signals. T he dc component of the

instantaneous power signal is then extracted by LPF2 (Low

Pass Filter) to obtain the active power information. T his

process is illustrated graphically in Figure 31.

Figure 32 —Frequency Response of LPF2

F igure 33 shows the signal processing chain for the

ActivePower calculation in the ADE7753. As explained, the

Active Power is calculated by low pass filtering the instanta-

neous power signal. Note that for when reading the waveform

samples from the output of LPF2,

T he gain of the Active Energy can be adjusted by using the

multiplier and Watt G ain register (WG AIN [11:0]). T he

gain is adjusted by writing a 2’s complement 12-bit word to

the Watt Gain register. Below is the expression that shows

how the gain adjustment is related to the contents of the Watt

Gain register.

Instantaneous

Power Signal

p(t) = V×I-V×I×cos(2ωt)

19999Ah

Active Real Power

Signal = V x I

WGAIN

2¹²

=

×

+

1

Output WGAIN

Active Power

V. I.

CCCCDh

For example when 7FFh is written to the Watt Gain register

the Power output is scaled up by 50%. 7FFh = 2047d,

2047/2¹²= 0.5. Similarly, 800h = -2048 D ec (signed 2’s

Complement) and power output is scaled by –50%.

00000h

Current

Shown in Figure 34 is the maximum code (in hex) output

range for the Active Power signal (LPF2). N ote that the

output range changes depending on the contents of the Watt

Gain register. T he minimum output range is given when the

Watt G ain register contents are equal to 800h, and the

i(t) = √2×I×sin(ωt)

Voltage

v(t) = √2×V×sin(ωt)

Figure 31– Active Power Calculation

For Waveform

HPF

APOS[15:0]

Sampling

24

2⁶2⁵

2^-62^-72^-8

sgn

I

19999h

Current Signal - i(t)

LPF2

+

24

32

+

For Energy

Accumulation

Active Power

Signal - P

MULTIPLIER

Σ

Instantaneous

Power Signal - p(t)

19999Ah

WGAIN[11:0]

CCCCDh

V

Voltage Signal - v(t)

000000h

Figure 33– Active Power Signal Processing

–1 9 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

maximum range is given by writing 7FFh to the Watt Gain

register. T his can be used to calibrate the Active Power (or

Energy) calculation in the ADE7753.

Figure 35 shows a graphical representation of this discrete

time integration or accumulation. T he Active Power signal

in the Waveform register is continuously added to the internal

Active Energy register. T his addition is a signed addition,

therefore negative energy will be subtracted from the Active

Energy contents.

133333h

T he output of the multiplier is divided by WDIV. If the value

in the WDIV register is equal to 0 then the internal Active

Energy register is divided by 1. WDIV is an 8-bit unsigned

register. After dividing by WD IV, the active energy is

accumulated in a 48-bit internal energy accumulation regis-

ter. T he upper 24 bit of this register is accessible through a

read to the Active Energy register (AEN ERGY[23:0]). A

read to the RAENERGY register will return the content of

the AENERGY register and the upper 24-bit of the internal

register is clear after a read to AENERGY register.

As shown in Figure 35, the Active Power signal is accumu-

Positive

Power

CCCCDh

66666h

00000h

F9999Ah

F33333h

ECCCCDh

Negative

Power

000h

WGAIN[11:0]

Active Power

7FFh 800h

Calibration Range

Figure 34 – Active Power Calculation Output Range

lated

in

an

internal

48-bit

signed

register.

E NE R G Y C ALC U LAT IO N

T he Active Power signal can be read from the Waveform

register by setting M OD E[14:13] = 0,0 and setting the

WSMP bit (bit 3) in the Interrupt Enable register to 1. Like

the Channel 1 and Channel 2 waveform sampling modes the

waveform date is available at sample rates of 27.9kSPS,

14kSPS, 7kSPS or 3.5kSPS—see Figure 22.

Figure 36 shows this energy accumulation for full scale

signals (sinusoidal) on the analog inputs. T he three curves

displayed, illustrate the minimum period of time it takes the

energy register to roll-over when the Active Power Gain

register contents are 7FFh, 000h and 800h. T he Watt Gain

register is used to carry out power calibration in the ADE7753.

As shown, the fastest integration time will occur when the

Watt Gain register is set to maximum full scale, i.e., 7FFh.

As stated earlier, power is defined as the rate of energy flow.

T his relationship can be expressed m athem atically as

Equation 5.

dE

P =

(5)

dt

Where P = Power and E = Energy.

Conversely Energy is given as the integral of Power.

=

E

Pdt

(6)

∫

T he ADE7753 achieves the integration of the Active Power

signal by continuously accumulating the Active Power signal

in an internal non-readable 56-bit Energy register. T he

Active Energy register (AEN ERG Y[23:0]) represents the

upper 24 bits of this internal register. T his discrete time

accumulation or summation is equivalent to integration in

continuous time. Equation 7 below expresses the relationship

AENERGY[23:0]

7F,FFFFh

WGAIN = 7FFh

WGAIN = 000h

WGAIN = 800h

3F,FFFFh

∞

=

×

p(nT) T

E

p(t)dt

∑

∫

Time

(minutes)

(7)

Lim

00,0000h

8

4

6.2

12.5

→

=

t

0

n

1

Where n is the discrete time sample number and T is the

sample period.

40,0000h

80,0000h

UPPER 24 BITS ARE

AENERGY[23:0]

ACCESSIBLE THROUGH

0

23

AENERGY[23:0] REGISTER

Current Channel

Voltage Channel

APOS [15:0]

+

WDIV[7:0]

46

LPF2

Figure 36 - Energy register roll-over tim e for full-scale

power (Minim um & Maxim um Power Gain)

0

+

Σ

WGAIN[11:0]

Note that the energy register contents will roll over to full-

scale negative (800000h) and continue increasing in value

when the power or energy flow is positive - see Figure 36.

Conversely if the power is negative the energy register would

under flow to full scale positive (7FFFFFh) and continue

decreasing in value.

Active Power

Signal - P*

OUTPUTS FROM THE LPF2 ARE

ACCUMULATED (INTEGRATED) IN

THE INTERNAL ACTIVE ENERGY REGISTER

T

4

WAVEFORM

REGISTER

VALUES

CLKIN

time (nT)

By using the Interrupt Enable register, the ADE7753 can be

configured to issue an interrupt (IRQ) when the Active

Energy register is half-full (positive or negative) or when an

over/under flow occurs.

Figure 35 – ADE7753 Active Energy Calculation

T he discrete time sample period (T ) for the accumulation

register in the AD E7753 is 1.1µs (4/CLKIN ). As well as

calculating the Energy this integration removes any sinusoi-

dal components which may be in the Active Power signal.

Integration tim e under steady load

As mentioned in the last section, the discrete time sample

period (T ) for the accumulation register is 1.1µs (4/CLKIN).

–2 0 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

With full-scale sinusoidal signals on the analog inputs and the

WGAIN register set to 000h, the average word value from

each LPF2 is CCCCD h - see Figure 31. T he maximum

positive value which can be stored in the internal 47-bit

register is 2⁴⁶- 1 or 7FFF,FFFF,FFFFh before it overflows,

the integration time under these conditions with WDIV=0 is

calculated as follows:

output pulse is generated when (CFDEN+1)/(CFNUM+1)

number of pulses are generated at the DFC output. Under

steady load conditions the output frequency is proportional to

the Active Power.

T he maximum output frequency, with AC input signals at

full-scale and CFN UM =00h & CFD EN =00h, is approxi-

mately 23 kH z.

T he AD E7753 incorporates two registers, CFN UM [11:0]

and C FD EN [11:0], to set the C F frequency. T hese are

unsigned 12-bit registers which can be used to adjust the CF

frequency to a wide range of values. T hese frequency scaling

registers are 12-bit registers which can scale the output

3FFF, FFFF, FFFFh

Time =

×1.12µs = 187.5s = 3.12min s

CCCCDh

When WDIV is set to a value different from 0, the integration

time varies as shown on Equation 8.

frequency by 1/2¹²to 1 with a step of 1/2¹²

.

If the value zero is written to any of these registers, the value

one would be applied to the register. T he ratio (CFNUM+1)/

(CFDEN+1) should be smaller than one to assure proper

operation . If the ratio of the registers (C F N U M + 1)/

(CFDEN+1) is greater than one, the register values would

be adjust to a ratio (CFNUM+1)/(CFDEN+1) of one.

For example if the output frequency is 1.562kHz while the

contents of CFDENare zero (000h), then the output frequency

can be set to 6.1Hz by writing FFh to the CFDEN register.

N ote that for valu es where C F D EN > C F N U M , the

performance of the CF frequency is not guaranteed. CFNUM

should always be set to a value less than CFDEN.

T ime = T ime_{WD IV=0}x WD IV

(8)

P OWER OFFSET CALIBRATION

T he AD E7753 also incorporates an Active Power Offset

register (APOS[15:0]). T his is a signed 2’s complement 16-

bit register which can be used to remove offsets in the active

power calculation—see Figure 33. An offset may exist in the

power calculation due to cross talk between channels on the

PCB or in the IC itself. T he offset calibration will allow the

contents of the Active Power register to be maintained at zero

when no power is being consumed.

T wo hundred fifty six LSBs (APOS=0100h) written to the

Active Power Offset register are equivalent to 1 LSB in the

Waveform Sample register. Assuming the average value

outputs from LPF2 is CCCCDh (838,861 in Decimal) when

inputs on Channels 1 and 2 are both at full-scale. At -60dB

down on Channel 1 (1/1000 of the Channel 1 full-scale

input), the average word value outputs from LPF2 is 838.861

(838,861/1,000). 1 LSB in the LPF2 output has a measure-

ment error of 1/838.861 × 100% = 0.119% of the average

value. T he Active Power Offset register has a resolution

equal to 1/256 LSB of the Waveform register, hence the

power offset correction resolution is 0.00047%/LSB (0.119%/

256) at -60dB.

T he output frequency will have a slight ripple at a frequency

equal to twice the line frequency. T his is due to imperfect

filtering of the instantaneous power signal to generate the

Active Power signal – see Active Power Calculation. Equation 3

gives an expression for the instantaneous power signal. T his

is filtered by LPF2 which has a magnitude response given by

Equation 9.

1

=

H(f )

f ²

8.9²

+

1

ENERGYTO FREQUENCYCO NVERSIO N

(9)

ADE7753 also provides energy to frequency conversion for

calibration purposes. After initial calibration at manufactur-

ing, the manufacturer or end customer will often verify the

energy meter calibration. One convenient way to verify the

meter calibration is for the manufacturer to provide an output

frequency which is proportional to the energy or active power

under steady load conditions. T his output frequency can

provide a simple, single wire, optically isolated interface to

external calibration equipment. Figure 37 illustrates the

Energy-to-Frequency conversion in the AD E7753.

T he Active Power signal (output of LPF2) can be rewritten

as.

VI

( )

π

cos 4 f_lt

=

−

p(t) VI

2

(10)

2f_l

+

1

8.9

where f

l

is the line frequency (e.g., 60Hz)

From Equation 6

CFNUM[11:0]

11

0

VI

Energy

( )

π

sin 4 f_lt

DFC

CF

=

−

E(t) VIt

2

23 AENERGY[23:0]

0

(11)

2f_l

π

4 f_l

+

1

8.9

CFDEN[11:0]

11

0

Figure 37– ADE7753 Energy to Frequency Conversion

From Equation 11 it can be seen that there is a small ripple

in the energy calculation due to a sin(2ωt) component. T his

is shown graphically in F igure 38. T he Active Energy

calculation is shown by the dashed straight line and is equal

A Digital to Frequency Converter (DFC) is used to generate

the CF pulsed output. T he DFC generates a pulse each time

one LSB in the Active Energy register is accumulated. An

–2 1 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

to V x I x t. T he sinusoidal ripple in the Active Energy

calculation is also shown. Since the average value of a

sinusoid is zero, this ripple will not contribute to the energy

calculation over time. However, the ripple can be observed

in the frequency output, especially at higher output frequen-

cies. T he ripple will get larger as a percentage of the

frequency at larger loads and higher output frequencies. T he

reason is simply that at higher output frequencies the integra-

tion or averaging time in the Energy-to-Frequency conversion

process is shorter. As a consequence some of the sinusoidal

ripple is observable in the frequency output. Choosing a

lower output frequency at CF for calibration can significantly

reduce the ripple. Also averaging the output frequency by

using a longer gate time for the counter will achieve the same

results.

calibration is invalid and should be ignored. T he result of all

subsequent line cycle accumulation is correct.

From Equations 6 and 10.

nT

VI

( )

π

cos 2 f t dt

=

−

E(t)

VI dt

∫

2

(12)

f

0

+

1

8.9

where n is a integer and T is the line cycle period. Since the

sinusoidal component is integrated over a integer number of

line cycles its value is always zero.

T herefore:

nT

=

+

VIdt 0

E

(13)

(14)

∫

0

E(t)

VIt

=

E(t) VInT

+

46

0

Output from

LPF2

Σ

+

ACCUMULATE ACTIVE

ENERGY IN INTERNAL

REGISTER AND UPDATE

THE LAENERGY REGISTER

AT THE END OF LINECYC

LINE-CYCLES

R

U

VI

WDIV[7:0]

f_lt

sin(4. p. . )

W

−

S

_{/ 8.9Hz)}V

f_l

4.p. (1+ 2.

f_l

T

23

0

LAENERGY[23:0]

LPF1

FROM

CHANNEL 2

ADC

ZERO CROSS

DETECTION

CALIBRATION

CONTROL

t

Figure 38 – Output frequency ripple

LINECYC[14:0]

LINE C YC LE E NE RG Y AC C U M U LAT IO N M O D E

Figure 39 – Energy Calculation in Line Cycle Energy Accu-

m ulation Mode

In Line C ycle Energy Accumulation mode, the energy

accumulation of the ADE7753 can be synchronized to the

Channel 2 zero crossing so that active energy can be accumu-

lated over an integral number of half line cycles. T he

advantage of summing the active energy over an integer

number of half line cycles is that the sinusoidal component

in the active energy is reduced to zero. T his eliminates any

ripple in the energy calculation. Energy is calculated more

accurately and in a shorter time because integration period

can be shortened. By using the line cycle energy accumula-

tion mode, the energy calibration can be greatly simplified

and the time required to calibrate the meter can be signifi-

cantly reduced. T he ADE7753 is placed in line cycle energy

accumulation mode by setting bit 7 (CYCM OD E) in the

Mode register. In Line Cycle Energy Accumulation Mode

the AD E7753 accumulates the active power signal in the

LAENERGY register (Address 04h) for an integral number

of line cycles, as shown in Figure 39. T he number of half line

cycles is specified in the LINECYC register (Address 1Ch).

T he ADE7753 can accumulate active power for up to 65,535

half line cycles. Because the active power is integrated on an

integral number of line cycles, at the end of a line cycle energy

accumulation cycle the CYCEND flag in the Interrupt Status

register is set (bit 2). If the CYCEN D enable bit in the

Interrupt Enable register is enabled, the IRQ output will also

go active low. T hus the IRQ line can also be used to signal

the completion of the line cycle energy accumulation. An-

other calibration cycle will start as long as the CYCMODE

bit in the Mode register is set. Note that the result of the first

Note that in this mode, the 16-bit LINECYC register can

hold a maximum value of 65,535. In other words, the line

energy accumulation mode can be used to accumulate active

energy for a maximum duration over 65,535 half line cycles.

At 60Hz line frequency, it translates to a total duration of

65,535 / 120Hz = 546 seconds.

P O SITIVE O NLYACCUMULATIO N MO D E

In Positive Only Accumulation mode, the energy accumula-

tion is done only for positive power, ignoring any occurrence

of negative power above or below the no load threshold as

shown in Figure 40. T he ADE7753 is placed in positive only

Active Energy

No-load

threshold

Active Power

No-load

threshold

IRQ

PPOS

PNEG

PPOS

Interrupt Status Registers

PNEG PPOS PNEG

Figure 40 – Energy Accum ulation in Positive Only

Accum ulation Mode

–2 2 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

accumulation mode by setting the M SB of the M OD E

Instantaneous Reactive

Power Signal - Rp(t)

90 DEGREE

PHASE SHIFT

register (MODE[15]). T he default setting for this mode is

off. T ransitions in the direction of power flow, going from

negative to positive or positive to negative, set the IRQ pin

to active low if the Interrupt Enable register is enabled. T he

Interrupt Status Registers, PPOS and PNEG, show which

transition has occurred. See ADE7753 Register Descriptions.

Π

2

I

MULTIPLIER

+

47

0

+

Σ

V

ACCUMULATE ACTIVE

ENERGY IN INTERNAL

REGISTER AND UPDATE

THE LVARENERGY

REGISTER AT THE END OF

LINECYC LINE CYCLES

NO LO AD TH RESH O LD

23

0

LVARENERGY[23:0]

LPF1

T he ADE7753 includes a "no load threshold" feature that will

eliminate any creep effects in the meter. T he AD E7753

accomplishes this by not accumulating energy if the multi-

plier output is below the "no load threshold". T his threshold

is 0.001% of the full-scale output frequency of the multiplier.

Compare this value to the IEC1036 specification which states

that the meter must start up with a load equal to or less than

0.4% Ib. T his standard translates to .0167% of the full-scale

output frequency of the multiplier.

FROM

CHANNEL 2

ADC

ZERO CROSS

DETECTION

CALIBRATION

CONTROL

LINECYC[14:0]

Figure 41 - Reactive Power Signal Processing

T he features of the Reactive Energy accumulation are the

same as the Line Active Energy accumulation. T he number

of half line cycles is specified in the LIN ECYC register.

LINECYC is an unsigned 16-bit register. T he ADE7754 can

accumulate Reactive Power for up to 65535 combined half

cycles. At the end of an energy calibration cycle the CYCEND

flag in the Interrupt Status register is set. If the CYCEND

mask bit in the Interrupt Mask register is enabled, the IRQ

output will also go active low. T hus the IRQ line can also be

used to signal the end of a calibration. T he AD E7753

accumulates the Reactive Power signal in the LVARENERGY

register for an integer number of half cycles, as shown in

Figure 41.

R E AC T IVE P O W E R C ALC U LAT IO N

Reactive power is defined as the product of the voltage and

current waveforms when one of this signal is phase shifted by

90º. T he resulting waveform is called the instantaneous

reactive power signal. Equation 17 gives an expression for the

instantaneous reactive power signal in an ac system when the

phase of the current channel is shifted by +90º.

(15)

=

ω + θ

2 V sin( t

v(t)

)

π

=

ω

=

ω +

I sin( t

i( t )

I sin( t )

i'( t )

)

2

(16)

2

T he Reactive Energy accumulation in the ADE7753 not only

provides the reactive energy calculated using the phase shift

method, it is also useful to provide the sign of the reactive

power if it is desirable to use triangular method to calculate

reactive power. T he AD E7753 also provides an accurate

measurement of the apparent power. T he user can choose to

determine reactive energy through the mathematical rela-

tionship between apparent, active and reactive power. T he

sign of the reactive energy can be found by reading the result

from the LVARENERGY register at the end of a reactive

energy accumulation cycle.

Where θ is the phase difference between the voltage and

current channel, V = rms voltage and I = rms current.

=

×

Rp(t) v(t) i'(t)

(17)

=

θ +

ω + θ

Rp(t) VI sin( ) VI sin(2 t

)

T he average power over an integral number of line cycles (n)

is given by the expression in Equation 18.

nT

1

=

θ

Rp(t)dt VI sin( )

RP

∫

(18)

nT

Reactive Energy

0

2

Apparent Energy²Active Energy

−

where T is the line cycle period.

=

×

sign(Reactive Energy)

RP is referred to as the Reactive Power. Note that the reactive

power is equal to the DC component of the instantaneous

reactive power signal Rp( t) in Equation 17. T his is the

relationship used to calculate reactive power in the ADE7753.

T he instantaneous reactive power signal Rp(t) is generated by

multiplying the channel 1 and channel 2. In this case, the

phase of the channel 1 is shifted by +90º. T he DC component

of the instantaneous reactive power signal is then extracted by

a low pass filter to obtain the reactive power information.

Figure 41 shows the signal processing in the Reactive Power

calculation in the ADE7753.

AP P ARENT P OWER CALCULATION

Apparent power is defined as the amplitude of the vector sum

of the Active and Reactive powers -see Figure 42. T he angle

θ between the Active Power and the Apparent Power generally

represents the phase shift due to non-resistive loads. For

single phase applications, θ represents the angle between the

voltage and the current signals. Equation 20 gives an expres-

sion of the instantaneous power signal in an ac system with a

phase shift.

–2 3 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

writing 7FFh to the Apparent Power Gain register. T his can

be used to calibrate the Apparent Power (or Energy) calcu-

Apparent

Power

lation in the ADE7753 -see Apparent Power calculation.

Reactive

Power

Apparent Power 100% FS

Apparent Power 150% FS

Apparent Power 50% FS

θ

Active

Power

103880h

AD055h

5682Bh

Figure 42 - Power triangle

( )

ω +θ

2 I_rmssin t

=

ω

2 V sin t

00000h

v(t)

i(t)

rms

000h

7FFh 800h

(19)

(20)

(

)

=

VAGAIN[11:0]

Apparent Power

Calibration Range

Voltage and Current channel inputs: 0.5V / GAIN

=

×

p(t) v(t) i(t)

Figure 44- Apparent Power Calculation Output range

=

θ − ω + θ

p(t) V_rmsI_rmscos( ) V_rmsI_rmscos(2 t )

T he Apparent Power (AP) is defined as V_rmsx I_rms. T his

expression is independent from the phase angle between the

current and the voltage.

Apparent Power Offset Calibration

Each RM S measurement includes an offset compensation

register to calibrate and eliminate the DC component in the

RMS value -see Channel 1 RMS calculation and Channel 2 RMS

calculation. T he channel 1 and channel 2 RMS values are then

multiplied together in the Apparent Power signal processing.

As no additional offsets are created in the multiplication of

the RMS values, there is no specific offset compensation in

the Apparent Power signal processing. T he offset compensa-

tion of the Apparent Power measurement is done by calibrating

each individual RMS measurements.

Figure 43 illustrates graphically the signal processing in each

phase for the calculation of the Apparent Power in the

AD E7753.

I

Apparent Power

Signal - P

rms

Current RMS Signal - i(t)

AD055h

1C82B3h

00h

MULTIPLIER

AP P ARENT ENERGYCALCULATIO N

T he Apparent Energy is given as the integral of the Apparent

Power.

VAGAIN

V

rms

Voltage RMS Signal - v(t)

17D338h

00h

=

Apparent Energy

Apparent Power(t) dt

(21)

∫

T he AD E7753 achieves the integration of the Apparent

Power signal by continuously accumulating the Apparent

Power signal in an internal 48-bit register. T he Apparent

Energy register (VAEN ERGY[23:0]) represents the upper

24 bits of this internal register. T his discrete time accumu-

lation or summation is equivalent to integration in continuous

time. Equation 23 below expresses the relationship

Figure 43 - Apparent Power Signal Processing

T he gain of the Apparent Energy can be adjusted by using the

multiplier and VA Gain register (VAGAIN[11:0]). T he gain

is adjusted by writing a 2’s complement, 12-bit word to the

VAGAIN register. Below is the expression that shows how

the gain adjustment is related to the contents of the VA Gain

register.

∞

=

×

Apparent Power(nT) T

(22)

Apparent Energy Lim

∑

→

0

T

=

n

0

VAGAIN

=

×

+

1

Output VAGAIN

Apparent Power

2¹²

Where n is the discrete time sample number and T is the

sample period.

For example when 7FFh is written to the VA Gain register

the Power output is scaled up by 50%. 7FFh = 2047d,

2047/2¹²= 0.5. Similarly, 800h = -2047 D ec (signed 2’s

Complement) and power output is scaled by –50%.

T he Apparent Power is calculated with the C urrent and

Voltage RM S values obtained in the RM S blocks of the

AD E7753. Shown in F igure 44 is the m axim um code

(H exadecimal) output range of the Apparent Power signal.

Note that the output range changes depending on the contents

of the Apparent Power Gain registers. T he minimum output

range is given when the Apparent Power G ain register

content is equal to 800h and the maximum range is given by

T he discrete time sample period (T ) for the accumulation

register in the ADE7753 is 1.1µs (4/CLKIN).

Figure 44 shows a graphical representation of this discrete

time integration or accumulation. T he Apparent Power

signal is continuously added to the internal register. T his

addition is a signed addition even if the Apparent Energy

remains theoretically always positive.

–2 4 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

VAENERGY[23:0]

Integr ation tim es under steady load

23

0

As mentioned in the last section, the discrete time sample

period (T ) for the accumulation register is 1.1µs (4/CLKIN).

With full-scale sinusoidal signals on the analog inputs and the

VAGAIN register set to 000h, the average word value from

Apparent Power stage is AD055h - see Apparent Power output

range. T he maximum value which can be stored in the

Apparent Energy register before it over-flows is 2²⁴or

F F ,F F F F h. As the average word value is added to the

internal register which can store 2⁴⁸- 1 or 7FFF,FFFF,FFFFh

before it overflows, the integration time under these condi-

tions with VADIV=0 is calculated as follows:

47

0

VADIV

46

T

0

APPARENT POWER

+

Σ

+

Apparent Power

Signal - P

APPARENT POWER ARE

ACCUMULATED (INTEGRATED) IN

THE APPARENT ENERGY REGISTER

T

AD055h

7FFF,FFFF,FFFFh

AD055h

Time =

×1.2µs = 888s = 14.8min

00000h

time (nT)

When VADIV is set to a value different from 0, the integra-

tion time varies as shown on Equation 23.

Figure 45- ADE7753 Apparent Energy calculation

T ime = T ime_WDIV=0x VADIV

(23)

T he upper 52-bit of the internal register are divided by

VADIV. If the value in the VADIV register is equal to 0 then

the internal active Energy register is divided by 1. VADIV is

an 8-bit unsigned register. T he upper 24-bit are then written

in the 24-bit Apparent Energy register (VAENERGY[23:0]).

RVAENERGY register (24 bits long) is provided to read the

Apparent Energy. T his register is reset to zero after a read

operation.

LINE AP P ARENT ENERGYACCUMULATIO N

T he ADE7753 is designed with a special Apparent Energy

accumulation mode which simplifies the calibration process.

By using the on-chip zero-crossing detection, the ADE7753

accumulates the Apparent Power signal in the LVAENERGY

register for an integral number of half cycles, as shown in

Figure 47. T he line Apparent energy accumulation mode is

always active.

Figure 45 shows this Apparent Energy accumulation for full

scale signals (sinusoidal) on the analog inputs. T he three

curves displayed, illustrate the minimum time it takes the

energy register to roll-over when the VA G ain registers

content is equal to 7FFh, 000h and 800h. T he VA Gain

register is used to carry out an apparent power calibration in

the ADE7753. As shown, the fastest integration time will

occur when the VA Gain register is set to maximum full scale,

i.e., 7FFh.

T he number of half line cycles is specified in the LINCYC

register. LIN C YC is an unsigned 16-bit register. T he

ADE7753 can accumulate Apparent Power for up to 65535

combined half cycles. Because the Apparent Power is inte-

grated on the same integral number of line cycles as the Line

Active Energy register, these two values can be compared

easily. T he active and apparent Energy are calculated more

accurately because of this precise timing control and provide

all the information needed for Reactive Power and Power

Factor calculation. At the end of an energy calibration cycle

the CYCEND flag in the Interrupt Status register is set. If the

CYCEND mask bit in the Interrupt Mask register is enabled,

the IRQ output will also go active low. T hus the IRQ line can

also be used to signal the end of a calibration.

VAENERGY[23:0]

FF,FFFFh

VAGAIN = 7FFh

VAGAIN = 000h

VAGAIN = 800h

80,0000h

T he Line Apparent Energy accumulation uses the same

signal path as the Apparent Energy accumulation. T he LSB

size of these two registers is equivalent.

40,0000h

+

0

46

20,0000h

+

Apparent Power

Σ

LVAENERGY REGISTER IS

UPDATED EVERY LINECYC

ZERO-CROSSINGS WITH THE

TOTAL APPARENT ENERGY

DURING THAT DURATION

Time

(minutes)

VADIV[7:0]

00,0000h

4.9

7.4

11.1

14.8

LPF1

ZERO

CROSSING

DETECTION

FROM

CHANNEL 2

ADC

0

23

CALIBRATION

CONTROL

LVAENERGY[23:0]

Figure 46- Energy register roll-over tim e for full-scale

power (Minim um & Maxim um Power Gain)

LINECYC[15:0]

Note that the Apparent Energy register contents roll-over to

full-scale negative (80,0000h) and continue increasing in

value when the power or energy flow is positive - see Figure

46.

Figure 47 - ADE7753 Apparent Energy Calibration

By using the Interrupt Enable register, the ADE7754 can be

configured to issue an interrupt (IRQ) when the Apparent

Energy register is half full (positive or negative) or when an

over/under flow occurs.

–2 5 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

C ALIBRAT ING T H E E NE RG Y M E T E R

2971.4 × 2 × 60

255

Frequency (CF)=

= 1398.3Hz

When calibrating the ADE7753, the first step is to calibrate

the frequency on CF to some required meter constant, e.g.,

3200 imp/kWh.

Alternatively, the average value from LPF2 under this con-

dition is approximately 1/16 of the full-scale level. As

described previously, the average LPF2 output at full-scale

ac input is CCCCD (hex) or 838,861 (decimal). At 1/16 of

full-scale, the LPF2 output is then 52,428.81. T hen using

Digital to Frequency Conversion, the frequency under this

load is calculated as:

A convenient way to to determine the output frequency on CF

is to use the line cycle energy accumulation mode. As shown

in Figure 37, DFC generates a pulse each time a LSB in the

LAENERGY register is accumulated. CF frequency (before

the CF frequency divider) can be conveniently determined by

the following expression:

52428.81× 3.579545MHz

Frequency(CF) =

= 1398.3Hz

2²⁷

Content of LAENERGY[23 : 0] Register

=

CF Frequency

T his is the frequency with the contents of the CFNUM and

CFDEN registers equal to 000h. T he desired frequency out

is 3.9111Hz. T herefore, the CF frequency must be divided

by 2797/3.9111H z or 357.5 decimal. T his is achieved by

loading the pair of CF D ivider registers with the closest

rational number. In this case, the closest rational number is

found to be 1/358 (or 1h/166h). T herefore, 0h and 165h

should be written to the CFN UM and CFD EN registers

respectively. Note that the CF frequency is multiplied by the

contents of (CFNUM + 1) / (CFDEN + 1). With the CF

D ivide registers contents equal to 1h/166h, the output

frequency is given as 2797Hz / 358 = 3.905Hz. T his setting

has an error of -0.1%.

Elasped Time

When the CYCMODE (bit 7) bit in the Mode register is set

to a logic one, energy is accumulated over an integer number

of half line cycles. If the line frequency is fixed and the

number of half cycles of integration is specified, the total

elasped time can be calculated by the following:

1

=

×

number of half cycles

Elasped Time

×

2

f_l

For example, at 60Hz line frequency, the elasped time for

255 half cycles will be 2.125 seconds. Rewriting the above in

terms of contents of various AD E7753 registers and line

frequencies (fl):

Calibrating CF is made easy by using the Calibration mode

on the ADE7753. T he critical part of this approach is that the

line frequency needs to be exactly known. If this is not

possible, the frequency can be measured by using the PE-

RIOD register of the ADE7753.

LAENERGY[2 3 : 0] × 2 × fl

CF Frequency =

(24)

LINECYC[15 : 0]

where fl is the line frequency.

Alternatively, CF frequency can be calculated based on the

average LPF2 output.

N ote that changing WGAIN [11:0] register will also affect

the output frequency from CF. T he WGAIN register has a

gain adjustment of 0.0244% / LSB.

AverageLPF2Output× CLKIN

CF Frequency=

(25)

2²⁷

D eter m in e th e kWH r /LSB C a libr a tion C oefficien t

T he Active Energy register (AEN ERGY) can be used to

calculate energy. A full description of this register can be

found in the Energy Calculation section. T he AENERGY reg-

ister gives the user both sign and magnitude information

regarding energy consumption. On completion of the CF

frequency output calibration, i.e., after adjusting the C F

Frequency divider and the Watt Gain (WGAIN) register, the

second stage of the calibration is to determine the kWh/LSB

coefficient for the AENERGY register. Equation 26 below

shows how LAENERGY can be used to calculate the calibra-

tion coefficient.

C alibr ating the F r equency at C F

When the frequency before frequency division is known, the

pair of C F F requency D ivider registers (C F N U M and

CFDEN) can be adjusted to produce the required frequency

on CF. In this example a meter constant of 3200 imp/kWh

is chosen as an appropriate constant. T his means that under

a steady load of 1kW, the output frequency on CF would be,

3200 imp / kWh 3200

=

0.8888 Hz

Frequency (CF )

×

60 min 60 sec 3600

Assuming the meter is set up with a test current (basic

current) of 20A and a line voltage of 220V for calibration, the

load is calculated as 220V × 20A = 4.4kW. T herefore the

expected output frequency on CF under this steady load

=

kWHr/LSB

Calibration Power (in kW)

3600 seconds/Hr

LINECYC[15 : 0]

× ×

×

(26)

LAENERGY[23 : 0] 2 fl

condition would be 4.4

×

0.8888H z

=

3.9111H z.

Once the coefficient is determined, the MCU can compute

the energy consumption at any time by reading the AENERGY

contents and multiplying by the coefficient to calculate kWh.

In the above example, at 4.4kW, after 255 half cycles (at

60H z), the resulting LAEN ERG Y is approximately 2971

decimal. T he kWHr/LSB can therefore be calculated to be

8.74×10^-7kWH r/LSB using the above equation.

Under these load conditions the transducers on Channel 1

and Channel 2 should be selected such that the signal on the

voltage channel should see approximately half scale and the

signal on the current channel about 1/8 of full scale (assuming

a maximum current of 80A). Assuming at line frequency of

60Hz, energy is accumulated over FFh number of half line

cycles, the resulting content of the LAENERGY register will

be approximately 2971.4 (decimal). CF frequency is there-

fore calculated to be:

–2 6 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

C LKIN F R E Q U E NC Y

C H E C KS U M R E G IS T E R

T he ADE7753 has a Checksum register (CHECKSUM[5:0])

to ensure the data bits received in the last serial read operation

are not corrupted. T he 6-bit C hecksum register is reset

before the first bit (MSB of the register to be read) is put on

the DOUT pin. During a serial read operation, when each

data bit becomes available on the rising edge of SCLK, the

bit will be added to the Checksum register. In the end of the

serial read operation, the content of the Checksum register

will equal to the sum of all ones in the register previously

read. Using the Checksum register, the user can determine

if an error has occured during the last read operation.

Note that a read to the Checksum register will also generate

a checksum of the Checksum register itself.

In this datasheet, the characteristics of the ADE7753 is shown

with CLKIN frequency equals 3.579545 MHz. However, the

AD E7753 is designed to have the same accuracy at any

CLKIN frequency within the specified range. If the CLKIN

frequency is not 3.579545M H z, various timing and filter

characteristics will need to be redefined with the new CLKIN

frequency. For example, the cut-off frequencies of all digital

filters (LPF1, LPF2, HPF1, etc.) will shift in proportion to

the change in CLKIN frequency according to the following

equation:

CLKIN Frequency

=

×

New Frequency Original Frequency

(27)

3.579545 MHz

T he change of CLKIN frequency does not affect the timing

characteristics of the serial interface because the data transfer

is synchronized with serial clock signal (SCLK). But one

needs to observe the read/write timing of the serial data

transfer-see ADE7753 Timing Characteristics. T able III lists

various timing changes that are affected by C LKIN fre-

quency.

DOUT

CONTENT OF REGISTER (n-bytes)

+

ADDR: 3Eh

CHECKSUM REGISTER

Σ

+

Figure 48– Checksum register for Serial Interface Read

TableIII

Frequency dependencies of the ADE7753 parameters

P ar am eter

CLKIN dependency

Nyquist frequency for CH 1&2 ADCs

PH CAL resolution (seconds per LSB)

C L K IN /8

4/C L K IN

Active Energy register update rate (Hz) C L K IN /4

Waveform sampling rate (Number of samples per second)

WAVSEL 1,0 =

0

1

0

1

0

1

C LK IN /128

C LK IN /256

C LK IN /512

C LK IN /1024

524,288/C LKIN

M aximum ZXT OU T period

SU SP E ND ING T H E AD E 7753 F U NC T IO NALIT Y

T he analog and the digital circuit can be suspended sepa-

rately. T he analog portion of the ADE7753 can be suspended

by setting the ASUSPEND bit (bit 4) of the Mode register

to logic high

See Mode Register. In suspend mode, all

waveform samples from the ADCs will be set to zeros. T he

digital circuitry can be halted by stopping the CLKIN input

and maintaining a logic high or low on CLKIN pin. T he

ADE7753 can be reactivated by restoring the CLKIN input

and setting the ASUSPEND bit to logic low.

–2 7 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

T he Serial Interface of the ADE7753 is made up of four

signals SCLK, DIN, DOUT and CS. T he serial clock for a

data transfer is applied at the SCLK logic input. T his logic

input has a schmitt-trigger input structure, which allows slow

rising (and falling) clock edges to be used. All data transfer

operations are synchronized to the serial clock. D ata is

shifted into the ADE7753 at the DIN logic input on the

falling edge of SCLK. Data is shifted out of the ADE7753 at

the DOUT logic output on a rising edge of SCLK. T he CS

logic input is the chip select input. T his input is used when

multiple devices share the serial bus. A falling edge on CS

also resets the serial interface and places the ADE7753 in

communications mode. T he CS input should be driven low

for the entire data transfer operation. Bringing CS high

during a data transfer operation will abort the transfer and

place the serial bus in a high impedance state. T he CS logic

input may be tied low if the ADE7753 is the only device on

the serial bus. However with CS tied low, all initiated data

transfer operations must be fully completed, i.e., the LSB of

each register must be transferred as there is no other way of

bringing the AD E7753 back into communications mode

without resetting the entire device, i.e., using RESET.

AD E 7753 SE RIAL INT E RF AC E

All ADE7753 functionality is accessible via several on-chip

registers – see Figure 49. T he contents of these registers can

be updated or read using the on-chip serial interface. After

power-on or toggling the RESET pin low or a falling edge

on CS, the ADE7753 is placed in communications mode. In

communications mode the ADE7753 expects a write to its

Communications register. T he data written to the communi-

cations register determines whether the next data transfer

operation will be read or a write and also which register is

accessed. T herefore all data transfer operations with the

ADE7753, whether a read or a write, must begin with a write

to the Communications register.

DIN

COMMUNICATIONS REGISTER

REGISTER # 1

IN

OUT

DOUT

IN

OUT

REGISTER # 2

IN

OUT

REGISTER # 3

AD E7753 Ser ial Wr ite O per ation

IN

OUT

T he serial write sequence takes place as follows. With the

ADE7753 in communications mode (i.e. the CS input logic

low), a write to the communications register first takes place.

T he MSB of this byte transfer is a 1, indicating that the data

transfer operation is a write. T he LSBs of this byte contain

the address of the register to be written to. T he ADE7753

starts shifting in the register data on the next falling edge of

SCLK. All remaining bits of register data are shifted in on the

falling edge of subsequent SCLK pulses – see Figure 51.

As explained earlier the data write is initiated by a write to the

communications register followed by the data. During a data

write operation to the ADE7753, data is transferred to all on-

chip registers one byte at a time. After a byte is transferred

into the serial port, there is a finite time before it is transferred

to one of the ADE7753 on-chip registers. Although another

byte transfer to the serial port can start while the previous byte

is being transferred to an on-chip register, this second byte

transfer should not finish until at least 4µs after the end of the

previous byte transfer. T his functionality is expressed in the

timing specification t₆- see Figure 51. If a write operation is

aborted during a byte transfer (CS brought high), then that

byte will not be written to the destination register.

Destination registers may be up to 3 bytes wide – see ADE7753

Register Descriptions. Hence the first byte shifted into the serial

port at DIN is transferred to the MSB (Most significant Byte)

of the destination register. If the addressed register is 12 bits

wide, for example, a two-byte data transfer must take place.

T he data is always assumed to be right justified, therefore in

this case, the four MSBs of the first byte would be ignored and

the 4 LSBs of the first byte written to the ADE7753 would be

the 4M SBs of the 12-bit word. Figure 52 illustrates this

exam ple.

REGISTER # n-1

REGISTER # n

IN

OUT

Figure 49– Addressing ADE7753 Registers via the

Com m unications Register

T he Communications register is an eight bit wide register.

T he MSB determines whether the next data transfer opera-

tion is a read or a write. T he 5 LSBs contain the address of

the register to be accessed. See ADE7753 Communications Register

for a more detailed description.

Figure 50 and 51 show the data transfer sequences for a read

and write operation respectively.

On completion of a data transfer (read or write) the ADE7753

once again enters communications mode.

CS

SCLK

COMMUNICATIONS REGISTER WRITE

DIN

0

0 0

ADDRESS

MULTIBYTE READ DATA

DOUT

Figure 50– Reading data from the ADE7753 via the serial

interface

CS

SCLK

COMMUNICATIONS REGISTER WRITE

DIN

1

0 0

MULTIBYTE WRITE DATA

ADDRESS

Figure 51– Writing data to the ADE7753 via the serial inter-

face

A data transfer is complete when the LSB of the ADE7753

register being addressed (for a write or a read) is transferred

to or from the ADE7753.

–2 8 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

t

8

CS

t

1

6

2

3

t

7

SCLK

DIN

t

4

t

5

DB0

Most Significant Byte

DB7

0

DB7

DB0

A1

1

A4 A3 A2

Command Byte

A0

Least Significant Byte

Figure 52 – Serial Interface Write Tim ing Diagram

SCLK

DIN

DB9

DB11

DB8

DB4

DB10

DB5

DB0

DB6

DB3

DB1

X

DB7

DB2

Most Significant Byte

Least Significant Byte

Figure 53—12 bit Serial Write Operation

AD E 7753 Ser ial Read O per ation

D uring a data read operation from the AD E7753 data is

shifted out at the DOUT logic output on the rising edge of

SCLK. As was the case with the data write operation, a data

read must be preceded with a write to the Communications

register.

output enters a high impedance state on the falling edge of the

last SCLK pulse. T he read operation may be aborted by

bringing the CS logic input high before the data transfer is

complete. T he DOUT output enters a high impedance state

on the rising edge of CS.

With the ADE7753 in communications mode (i.e. CS logic

low) an eight bit write to the Communications register first

takes place. T he MSB of this byte transfer is a 0, indicating

that the next data transfer operation is a read. T he LSBs of

this byte contain the address of the register which is to be

read. T he ADE7753 starts shifting out of the register data on

the next rising edge of SCLK – see Figure 54. At this point

the DOUT logic output leaves its high impedance state and

starts driving the data bus. All remaining bits of register data

are shifted out on subsequent SCLK rising edges. T he serial

interface also enters communications mode again as soon as

the read has been completed. At this point the DOUT logic

When an ADE7753 register is addressed for a read operation,

the entire contents of that register are transferred to the serial

port. T his allows the AD E7753 to m odify its on-chip

registers without the risk of corrupting data during a multi

byte transfer.

Note when a read operation follows a write operation, the

read command (i.e., write to communications register)

should not happen for at least 4µs after the end of the write

operation. If the read command is sent within 4µs of the write

operation, the last byte of the write operation may be lost.

T he is given as timing specification t .

9

CS

t

1

t

13

t

10

9

SCLK

DIN

0

A1

A4 A3 A2 A0

t

12

t

11

DB0

DB7

DB0

DB7

Least Significant Byte

DOUT

Most Significant Byte

Command Byte

Figure 54– Serial Interface Read Tim ing Diagram

–2 9 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

AD E7753 REGISTER LIST

D efault D escr iption

Ad d r ess Na m e

R/W # of Bits

01h

W AVE F O R M

R

24 bits

0h

T he Waveform register is a read-only register. T his register

contains the sampled waveform data from either Channel 1,

Channel 2 or the Active Power signal. T he data source and the

length of the waveform registers are selected by data bits 14 and

13 in the Mode Register - see Channel 1 & 2 Sampling.

02h

AE N E RG Y

R

24 bits

0h

T he Active Energy register. Active Power is accumulated

(Integrated) over time in this 24-bit, read-only register. T he

energy register can hold a minimum of 6 seconds of Active

Energy information with full scale analog inputs before it

overflows - see Energy Calculation.

03h

04h

RAE N E RG Y

L AE N E RG Y

R

24 bits

0h

Same as the Active Energy register except that the register is

reset to zero following a read operation

Line Accumulation Active Energy register. T he instantaneous

active power is accumulated in this read-only register over the

LINCYC number of half line cycles.

05h

06h

07h

VAE N E RG Y

R

24 bits

0h

Apparent Energy register. Apparent power is accumulated over

time in this read-only register.

RVAEN ERG Y R

L VAE N E RG Y R

Same as the VAENERGY register except that the register is reset

to zero following a read operation.

Apparent Energy register. T he instantaneous real power is

accumulated in this read-only register over the LINECYC

number of half line cycles

08h

09h

LVARENERGY R

24 bits

0h

Reactive Energy register. T he instantaneous reactive power is

accumulated in this read-only register over the LINECYC

number of half line cycles.

M O D E

R /W 16 bits

000C h

T he Mode register. T his is a 16-bit register through which most

of the ADE7753 functionality is accessed. Signal sample rates,

filter enabling and calibration modes are selected by writing to

this register. T he contents may be read at any time—see Mode

Register.

0Ah

IRQ E N

S T AT U S

40h

Interrupt Enable register. ADE7753 interrupts may be

deactivated at any time by setting the corresponding bit in this 8-

bit Enable register to logic zero. T he Status register will

continue to register an interrupt event even if disabled. However,

the IRQ output will not be activated—see ADE7753 Interrupts.

0Bh

0C h

0D h

R

16 bits

0h

T he Interrupt Status register. T his is an 8-bit read-only register.

T he Status Register contains information regarding the source of

ADE7753 interrupts - see ADE7753 Interrupts.

R ST ST AT U S R

0h

Same as the Interrupt Status register except that the register

contents are reset to zero (all flags cleared) after a read

operation.

C H 1 O S

R /W 8 bits

00h

Channel 1 Offset Adjust. Bit 6 is not used. Writing to bits 0 to 5

allows offsets on Channel 1 to be removed – see Analog Inputs

and CH1OS Register. Writing a logic one to the MSB of this

register enables the digital integrator on Channel 1, a zero

disables the integrator. T he default value of this bit is zero.

0Eh

0F h

C H 2 O S

G AIN

R /W 8 bits

0h

Channel 2 Offset Adjust. Bit 6 and 7 not used. Writing to bits 0

to 5 of this register allows any offsets on Channel 2 to be

removed - see Analog Inputs.

PGA Gain Adjust. T his 8-bit register is used to adjust the gain

selection for the PGA in Channel 1 and 2 - see Analog Inputs.

–3 0 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

Ad d r ess Na m e

R/W # of Bits

D efault D escr iption

10h

P H C AL

R /W 6 bits

0D h

Phase Calibration register. T he phase relationship between

Channel 1 and 2 can be adjusted by writing to this 6-bit register.

T he valid content of this 2's compliment register is between 1Dh

to 21h. At line frequency of 60Hz, this is a range from -2.06 to

+0.7 degrees. —see Phase Compensation.

11h

12h

AP O S

R /W 16 bits

R /W 12 bits

0h

Active Power Offset Correction. T his 16-bit register allows small

offsets in the Active Power Calculation to be removed – see

Active Power Calculation.

W G AIN

Power Gain Adjust. T his is a 12-bit register. T he Active Power

calculation can be calibrated by writing to this register. T he

calibration range is ±50% of the nominal full scale active power.

T he resolution of the gain adjust is 0.0244% / LSB—see Channel

1 ADC Gain Adjust.

13h

14h

15h

W D IV

R /W 8 bits

R /W 12 bits

0h

Active Energy divider register. T he internal active energy register

is divided by the value of this register before being stored in the

AEN ERG Y register.

C F N U M

C F D E N

3F h

CF Frequency Divider Numerator register. T he output frequency

on the CF pin is adjusted by writing to this 12-bit read/write

register – see Energy to Frequency Conversion.

CF Frequency Divider Denominator register. T he output

frequency on the CF pin is adjusted by writing to this 12-bit

read/write register – see Energy to Frequency Conversion.

16h

17h

18h

19h

1Ah

IRM S

R

24 bits

0h

Channel 1 RMS value (current channel).

Channel 2 RMS value (voltage channel).

Channel 1 RMS offset correction register

Channel 2 RMS offset correction register

VRM S

I R M SO S

VR M S O S

VAG AIN

R /W 12 bits

Apparent Gain register. Apparent power calculation can be

calibrated by writing this register. T he calibration range is 50%

of the nominal full scale real power. T he resolution of the gain

adjust is 0.02444% / LSB.

1Bh

1C h

VAD IV

R /W 8 bits

0h

Apparent Energy divider register. T he internal apparent energy

register is divided by the value of this register before being stored

in the VAENERGY register.

L IN E C YC

R/W 15 bits

F F F h

Line Cycle Energy Accumulation Mode Line-Cycle register.

T his 15-bit register is used during line cycle energy

accumulation mode to set the number of half line cycles for

energy accumulation - see Line Cycle Energy Accumulation Mode.

1D h

1Eh

1F h

Z X T O U T

SAG C YC

SAG L VL

R /W 12 bits

R/W 8 bits

R /W 8 bits

F F F h

F F h

0h

Zero-cross T ime Out. If no zero crossings are detected on

Channel 2 within a time period specified by this 12-bit register,

the interrupt request line (IRQ) will be activated. T he maximum

time-out period is 0.15 second - see Zero Crossing Detection.

Sag line Cycle register. T his 8-bit register specifies the number

of consecutive line cycles the signal on Channel 2 must be below

SAGLVL before the SAG output is activated - see Voltage Sag

Detection

Sag Voltage Level. An 8-bit write to this register determines at

what peak signal level on Channel 2 the SAG pin will become

active. T he signal must remain low for the number of cycles

specified in the SAGCYC register before the SAG pin is

activated—see Line Voltage Sag Detection.

20h

IP K L VL

R /W 8 bits

F F h

Channel 1 Peak Level threshold (current channel). T his register

sets the level of the current peak detection. If the channel 1 input

exceeds this level, the PKI flag in the status register is set.

–3 1 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

Ad d r ess Na m e

R/W # of Bits

D efault D escr iption

21h

VP K L VL

R /W 8 bits

F F h

Channel 2 Peak Level threshold (voltage channel). T his register

sets the level of the voltage peak detection. If the channel 2 input

exceeds this level, the PKV flag in the status register is set.

22h

IPEAK

R

24 bits

0h

Channel 1 peak register. T he maximum input value of the

Current channel since the last read of the register is stored in this

register.

23h

24h

RST IP EAK

VPEAK

R

24 bits

0h

Same as Channel 1 peak register except that the register contents

are reset to 0 after read.

Channel 2 peak register. T he maximum input value of the

Voltage channel since the last read of the register is stored in this

register.

25h

26h

RST VP EAK

T E M P

R

24 bits

8 bits

0h

Same as Channel 2 peak register except that the register contents

are reset to 0 after a read.

T emperature register. T his is an 8-bit register which contains the

result of the latest temperature conversion – see Temperature

M easurement.

27h

P E R IO D

R

15 bits

0h

Period of the channel 2 (volatge channel) input estimated by

Zero-crossing processing.

28h-

3C h

3D h

3Eh

Reserved

T M O D E

R /W 8 bits

-

T est mode register

C H K SU M

R

6 bits

0h

Checksum Register. T his 6-bit read only register is equal to the

sum of all the ones in the previous read – see ADE7753 Serial Read

Operation.

3F h

D IE RE V

R

8 bits

-

Die Revision Register. T his 8-bit read only register contains the

revision number of the silicon.

AD E 7753 RE G IST E R D E SC RIP T IO NS

All AD E7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the

communications register and then transferring the register data. A full description of the serial interface protocol is given in

the Serial Interface section of this data sheet.

C om m u n ica tion s R egister

T he Communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753

and the host processor. All data transfer operations must begin with a write to the communications register. T he data written

to the communications register determines whether the next operation is a read or a write and which register is being accessed.

T able IV below outlines the bit designations for the Communications register.

Table V. Com m unications Register

DB6

0

DB5

A5

DB4

A4

DB1

A1

DB0

A0

DB7

W/R

DB3

A3

DB2

A2

Bit

D escr iption

Loca tion

M n em on ic

0 to 5

A0 to A5

T he six LSBs of the Communications register specify the register for the data transfer

operation. T able III lists the address of each ADE7753 on-chip register.

6

7

RE SE RVE D

T his bit is unused and should be set to zero.

W /R

When this bit is a logic one the data transfer operation immediately following the write to

the Communications register will be interpreted as a write to the ADE7753. When this bit

is a logic zero the data transfer operation immediately following the write to the

Communications register will be interpreted as a read operation.

–3 2 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

Mode Register (09H )

T he ADE7753 functionality is configured by writing to the MODE register. T able VI below summarizes the functionality

of each bit in the MODE register .

Table VI : Mode Register

Bit

Default

Location Mnem onic

Value Description

0

1

2

3

4

D ISH P F

D ISL P F 2

D ISC F

0

1

0

T he HPF (High Pass Filter) in Channel 1 is disabled when this bit is set.

T he LPF (Low Pass Filter) after the multiplier (LPF2) is disabled when this bit is set.

T he Frequency output CF is disabled when this bit is set

D ISSAG

ASU SP E N D

T he line voltage Sag detection is disabled when this bit is set

By setting this bit to logic one, both ADE7753's A/D converters can be turned off. In

normal operation, this bit should be left at logic zero. All digital functionality can be

stopped by suspending the clock signal at CLKIN pin.

5

6

T E M P SE L

SW R ST

0

T he T emperature conversion starts when this bit is set to one. T his bit is automatically

reset to zero when the T emperature conversion is finished.

Software chip reset. A data transfer should not take place to the ADE7753 for at least 18µs

after a software reset.

7

C YC M O D E

D ISC H 1

D ISC H 2

SWAP

0

Setting this bit to a logic one places the chip in line cycle energy accumulation mode.

ADC 1 (Channel 1) inputs are internally shorted together.

8

9

ADC 2 (Channel 2) inputs are internally shorted together.

10

By setting this bit to logic 1 the analog inputs V2P and V2N are connected to ADC 1 and

the analog inputs V1P and V1N are connected to ADC 2.

12, 11

14, 13

15

D T RT 1,0

00

T hese bits are used to select the Waveform Register update rate

D T RT

1

D T RT 0

Update Rate

0

1

0

1

0

1

27.9kSPS (C LKIN /128)

14kSPS (C LKIN /256)

7kSPS (C LKIN /512)

3.5kSPS (C LKIN /1024)

WAVSEL1,0 00

T hese bits are used to select the source of the sampled data for the Waveform Register

WAVSEL1,0 Length Source

0

1

0

1

0

1

24 bits Active Power signal (output of LPF2)

Reserved

24 bits Channel 1

24 bits Channel 2

P O AM

0

Writing a logic one to this bit will allow only positive power to be accumulated in the

ADE7753. T he default value of this bit is 0.

MODE REGISTER*

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

ADDR: 09H

DISHPF

0

1

0

POAM

(Positive Only Accumulation)

(Disable HPF in Channel 1)

WAVSEL

DISLPF2

(Wave form selection for sample mode)

(Disable LPF2 after multiplier)

00 = LPF2

01= Reserved

10 = CH1

DISCF

(Disable Frequency output CF)

11 = CH2

DISSAG

(Disable SAG output)

DTRT

(Waveform samples output data rate)

00 = 27.9kSPS (CLKIN/128)

ASUSPEND

(Suspend CH1&CH2 ADC’s)

01 = 14.4 kSPS (CLKIN/256)

10 = 7.2 kSPS (CLKIN/512)

STEMP

(Start temperature sensing)

11 = 3.6 kSPS (CLKIN/1024)

SWRST

(Software chip reset)

SWAP

(Swap CH1 & CH2 ADCs)

CYCMODE

(Line Cycle Energy Accumulation Mode)

DISCH2

(Short the analog inputs on Channel 2)

DISCH1

(Short the analog inputs on Channel 1)

*Register contents show power on defaults

–3 3 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

Interrupt Status Register (0BH) /Reset Interrupt Status Register (0CH) /Interrupt Enable Register (0Ah)

T he Status Register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs

in the ADE7753, the corresponding flag in the Interrupt Status register is set logic high. If the enable bit for this flag is logic

one in the Interrupt Enable register, the IRQ logic output goes active low. When the MCU services the interrupt it must first

carry out a read from the Interrupt Status Register to determine the source of the interrupt.

Table VII: Inter r upt Status Register , Reset Inter r upt Status Register & Inter r upt E nable Register

Bit

Loca tion

Interrupt

F la g

D escr iption

0h

1h

2h

AE H F

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Active

Energy register (i.e. the AENERGY register is half full)

S AG

Indicates that an interrupt was caused by a SAG on the line voltage or no zero crossings were

detected.

C YC E N D

Indicates the end of energy accumulation over an integer number of half line cycles as

defined by the content of the LINECYC Register—see Line Cycle Energy Accumulation Mode

3h

4h

5h

6h

W SM P

Z X

Indicates that new data is present in the Waveform Register.

T his status bit reflects the status of the ZX logic ouput—see Zero Crossing Detection

Indicates that a temperature conversion result is available in the T emperature Register.

T E M P

RE SE T

Indicates the end of a reset (for both software or hardware reset). T he corresponding

enable bit has no function in the Interrupt Enable Register, i.e. this status bit is set at

the end of a reset, but it cannot be enabled to cause an interrupt.

7h

8h

9h

Ah

AE O F

P K V

Indicates that the Active Energy register has overflowed.

Indicates that waveform sample from Channel2 has exceeded the VPKLVL value.

Indicates that waveform sample from Channel1 has exceeded the IPKLVL value.

PKI

VAE H F

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Apparent

Energy register (i.e. the VAENERGY register is half full)

Bh

C h

VAE O F

Z X T O

Indicates that the Apparent Enrgy register has overflowed.

Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the

specified number of line cycles—see Zero Crossing Time Out

Indicates that the power has gone from negative to positive.

Indicates that the power has gone from positive to negative.

Reserved

D h

E h

F h

P P O S

P N E G

RE SE RVE D

–3 4 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

O U T LINE D IM E NS IO NS

D imensions shown in inches and (mm)

20- Sh r in k Sm a ll O u tlin e P a cka ge

(RS-20)

0 .2 9 5 (7 .5 0 )

0 .2 7 1 (6 .9 0 )

2 0

1 1

1

1 0

0 .0 7 (1 .7 8 )

0 .0 7 8 (1 .9 8 )

P IN 1

0 .0 6 6 (1 .6 7 )

0 .0 6 8 (1 .7 3 )

0 .0 3 7 (0 .9 4 )

8 °

0 °

0 .0 2 5 6

(0 .6 5 )

BS C

0 .0 2 2 (0 .5 5 9 )

0 .0 0 8 (0 .2 0 3 )

0 .0 0 2 (0 .0 5 0 )

SEATING 0 .0 0 9 (0 .2 2 9 )

PLANE

0 .0 0 5 (0 .1 2 7 )

–3 5 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

AD E7753 ERRATA (REV1.0)

T he following is a list of known issues with the first revision

of the AD E7753 silicon (rev 1.0). T hese issues will be

resolved in the next version. Samples of this version of the

silicon can be identified from the content of the DIEREV

regsiter (Address 3Fh). T he content of DIEREV register is

2 for Rev 1.2 silicon. In addition, the branding on top of the

package for Rev 1.2 should be as shown below:

2 0

1 1

AD7753

XRS

0240

K58207

1 0

1

E R R AT A

1. SAGCYC

T he conten ts of SAG C YC register is equ ivalen t to

(SAG C YC -1). For example, if the desired number of

linecycles for SAG detection is 20d line cycles, one should

write 21d to the SAGCYC Register. T his is not a silicon

bug.

2. CFNUM and CFD EN

CFNUM should always be less than CFDEN. T he behav-

ior of the output frequency is not guaranteed for CF. T his

is not a silicon bug.

–3 6 –

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA

ADE7753

R E VIS IO N H IS T O R Y

Page 26

T he main reason for revising the datasheet from version Pr.D

to Pr.F is to correct some of the mistakes contained in the

Pr.D and Pr.E version. In addition, changes were made to the

silicon to fix bugs noted in the Errata list and to modify the

product definition. T he list below highlights the important

changes from Pr.D to Pr.F. Note that all page numbers are

referring to that of Pr.F.

1. Equation 25 changed to have 2^27 bits for the denomina-

tor.

2. Content of LAENERGY register is 2971.4, and the CF

frequency output in the example calculation is 1398.3 Hz.

3. T he calculation of C F N U M and C F D EN changed

according to the effect of the abovementioned changes.

Page 4

Read timing t₉is determined to be 3.1us.

Page 31

1. T he definition of the SAGCYC a register has changed to

full line cycles. LIN ECYC corrected to say 15 bits and

remains half line cycles.

Page 12

T he SAGCYC register value represents full-line cycles and

not half-line cycles. T he line voltage SAG detection section

text was changed to reflect this design update.

shows 3 line cycles, 3h in the SAGCYC register, changed

from 6 half line cycles, 6h in the SAGCYC register. T he

section explaining Figure 13 has also changed accordingly.

2. T he PH CAL register description changed to reflect the

new effective length and resolution of the register and default

value of 0D.

Figure 13

Page 13

Peak Level record section was changed to show that the

quantity stored in VPEAK register is 2 times the absolute

value of the WAVEFORM register contents for CH2. IPEAK

is 1 times the absolute value of the CH1 Waveform.

Page 18

1. T he phase calibration register resolution has changed to

0.048 from 0.024. T his section calculations have been

changed to reflect this new resolution.

2. Figure 27 updated with new PH CAL range and delay

block rate.

Page 20

Figure 36 T iming was updated.

Page 21

1. T he internal active energy accumulation register is 47 bits

instead of 53 bits. T he equation also shows this change. T his

change is also implemented in the equations of page 25 as

well as Figures 45 and 47 on page 25.

2. T he maximum output frequency is changed to 23Hz.

3. T ext added to explain C F N U M m ust be less than

C F D E N .

Page 22

1. Figure 39 shows the actual internal register length to be 47

bits. T his change is also on page 23, Figure 41.

2. Line Cycle Energy accumulation mode section changed to

15 bits for LINECYC Register.

–3 7 –

REV. PrF 10/02

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.


型号：	ADE7753
厂家：	ADI
描述：	Active and Apparent Energy Metering IC with di/dt sensor interface 有功功率和视在电能计量IC与di / dt传感器接口传感器
文件：	总38页 (文件大小：449K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADE7753 [ADI]

相关型号：

ADE7753ARS

ADE7753ARSRL

ADE7753ARSZ

ADE7753ARSZRL

ADE7753_10

ADE7754

ADE7754AR

ADE7754ARRL

ADE7754ARW

ADE7754ARZ

ADE7754ARZRL

ADE7754BR