ADCMP606 [ADI]
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators; 轨到轨，速度非常快， 2.5 V至5.5 V ，单电源CML比较
| 型号： | ADCMP606 |
| 厂家： | 
ADI |
| 描述： | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators |
| 文件： | 总16页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply CML Comparators
Preliminary Technical Data
ADCMP606/ADCMP607
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
10 mV sensitivity rail to rail at VCC = 2.5 V
Input common-mode voltage from −0.2 V to VCC + 0.2 V
CML-compatible output stage
1 ns propagation delay
CCO
V
(ADCMP607 Only)
CCI
V
NONINVERTING
INPUT
P
50 mW at 2.5 V
Q OUTPUT
Q OUTPUT
Shutdown pin (ADCMP607 only)
Single-pin control for programmable hysteresis and latch
(ADCMP607 only)
CML
ADCMP606/
ADCMP607
V
INVERTING
INPUT
N
Power supply rejection > 60 dB
−40°C to +125°C operation
LE/HYS INPUT (ADCMP607 Only)
INPUT (ADCMP607 Only)
S
DN
APPLICATIONS
Figure 1.
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
PIN 1
INDICATOR
9
8
7
V
EE
V
1
2
3
CCO
ADCMP607
TOP VIEW
(Not to Scale)
LE/HYS
V
CCI
V
S
DN
EE
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
Figure 2.LFCSP Pin Configuration
GENERAL DESCRIPTION
to +6 V input signal range. The ADCMP607 features split
input/output supplies with no sequencing restrictions to support
a wide input signal range with independent output level control
and power savings.
The ADCMP606/ADCMP607 are very fast comparators
fabricated on Analog Devices’ proprietary XFCB2 process.
These comparators are exceptionally versatile and easy to use.
Features include an input range from VEE − 0.5 V to VCC + 0.5 V,
low noise CML-compatible output drivers, and TTL-/CMOS-
compatible latch inputs with adjustable hysteresis and/or
shutdown inputs.
The CML-compatible output stage is fully back-matched for
superior performance. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. On
the ADCMP607, high speed latch and programmable hysteresis
features are also provided with a unique single-pin control option.
The device offers 1 ns propagation delay with 2 ps RMS random
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 50 ps.
The ADCMP606 is available in a 6-lead SC70 package, and the
ADCMP607 is available in a 12-lead LSCFP package.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +3.0 V
input signal range up to a +5.5 V positive supply with a −0.5 V
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADCMP606/ADCMP607
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Application Information...................................................................9
Power/Ground Layout and Bypassing........................................9
CML-Compatible Output Stage ..................................................9
Using/Disabling the Latch Feature..............................................9
Optimizing Performance........................................................... 10
Comparator Propagation Delay Dispersion ........................... 10
Comparator Hysteresis .............................................................. 10
Crossover Bias Point .................................................................. 11
Minimum Input Slew Rate Requirement................................ 11
Typical Application Circuits ......................................................... 12
Timing Information ....................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Electrical Characteristics................................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
3/06—Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 16
Preliminary Technical Data
ADCMP606/ADCMP607
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 3.0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC INPUT CHARACTERISTICS
Voltage Range
Common-Mode Range
Differential Voltage
Offset Voltage
Bias Current
Offset Current
Capacitance
VP, VN
VCC = 2.5 V to 5.5 V
VCC = 2.5 V to 5.5 V
VCC = 2.5 V to 5.5 V
−0.5
−0.2
VCC + 0.5 V
VCC + 0.2 V
VCC
+5.0
+5.0
V
V
V
VOS
IP, IN
−5.0
−5.0
2.0
mV
μA
μA
pF
kΩ
kΩ
dB
dB
2
2.0
CP, CN
TBD
100
100
54
Resistance, Differential Mode
Resistance, Common Mode
Active Gain
0.1 V to VCC
−0.5 V to VCC + 0.5 V
AV
CMRR
Common-Mode Rejection
VCCI = 2.5 V, VCCO = 2.5 V,
50
V
CM = −0.2 V to 2.7 V
VCCI = 5.5 V, VCCO = 5.5 V,
VCM = −0.2 V to 5.7 V
60
dB
Hysteresis
RHYS = ∞
0.1
mV
LATCH ENABLE PIN CHARACTERISTICS
(ADCMP606 Only)
VIH
VIL
IIH
IOL
Hysteresis is shut off
Latch mode guaranteed
VIH = VCC
2.0
−0.2
VCC
+0.8
0.2
V
V
mA
mA
+0.4
VIL = 0.4 V
−0.2
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage
Minimum Resistor Value
Latch Setup Time
Latch Hold Time
Current sink 0 ꢀA
Hysteresis = 16 mV
VOD = 100 mV
1.145
150
1.25
1.35
V
kΩ
ns
ns
ns
ns
tS
tH
8
5
1
1
VOD = 100 mV
Latch-to-Output Delay
Latch Minimum Pulse Width
tPLOH, tPLOL VOD = 100 mV
tPL
VOD = 100 mV
SHUTDOWN PIN CHARACTERISTICS
(ADCMP607 Only)
VIH
VIL
IIH
IOL
Comparator is operating
Shutdown guaranteed
VIH = VCC
VIL = 0 V
ICC < 500 ꢀA
VOD = 10 mV, output valid
VCCO = 2.5 V to 5.5 V
RI = 50 Ω, VCCO = 2.5 V
RI = 50 Ω, VCCO = 2.5 V
2.0
−0.2
VCCO
+0.6
0.3
V
V
mA
mA
ns
ns
+0.4
−0.3
Sleep Time
Wake-Up Time
tSD
tH
50
80
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage Low Level
VOH
VOL
VCC − 0.1
VCC − 0.35
VCC + 0.1
VCC − 0.5
V
V
Minimum Output Low Level
(ADCMP607)
VCCI = 2.5 V, TA = −40°C
(internal termination only)
TBD
Rev. PrA | Page 3 of 16
ADCMP606/ADCMP607
Preliminary Technical Data
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
AC PERFORMANCE
Propagation Delay
tPD
VCC = 2.5 V to 5.5 V,
VOD = 5 mV
VCC = 2.5 V to 5.5 V,
1
ns
ns
ps
1
V
OD = 200 mV
Propagation Delay Skew—Rising to
Falling Transition
VOD = 5 mV
40
Overdrive Dispersion
10 mV < VOD < 2.5 V
5 mV < VOD < 2.5 V
0.05 V/ns to 2.5 V/ns
300 ps to 20 ns
1 V/ns, VCM = 2.5 V
0 < VCM < VCC
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
ps
ps
ps
ps
ps
Gbps
ps
Slew Rate Dispersion
Pulse-Width Dispersion
10% to 90% Duty Cycle Dispersion
Common-Mode Dispersion
Toggle Rate
Deterministic Jitter
CML Outputs
>50% output swing
DJ
RJ
VOD = 200 mV, 5 V/ns,
PRBS31 − 1 NRZ, 0.25 Gbps
RMS Random Jitter
VOD = 200 mV, 5 V/ns,
TBD
ps
PRBS31 − 1 NRZ, 0.525 Gbps
Minimum Pulse Width
Rise Time
Fall Time
PWMIN
tR
tF
∆tPD/∆PW < 50 ps
10% to 90%
10% to 90%
50%
300
150
150
20
ps
ps
ps
ps
Output skew
tSKEW
POWER SUPPLY
Input Supply Voltage Range
Output Supply Voltage Range
Positive Supply Differential
(ADCMP607)
VCCI
VCCO
VCCI
VCCO
2.5
2.5
−3.0
5.5
5.5
+3.0
V
V
V
−
Operating
Positive Supply Differential
(ADCMP607)
VCCI
VCCO
−
Nonoperating
−5.5
+5.5
V
Positive Supply Current
Positive Supply Current
Input Section Supply Current
(ADCMP607)
IVCC
IVCC
IVCCI
VCC = 2.5 V
VCC = 5.5 V
VCCI = 2.5 V to 5 V
23
25
0.8
mA
mA
mA
Output Section Supply Current
(ADCMP607)
IVCCO
VCCI = 2.5 V to 5.5 V
22.5
mA
Power Dissipation
PD
PD
PSRR
VCC = 2.5 V
VCC = 5.5 V
VCCI = 2.5 V to 5 V
57
125
−50
mW
mW
dB
Power Supply Rejection
Rev. PrA | Page 4 of 16
Preliminary Technical Data
ADCMP606/ADCMP607
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltages
Input Supply Voltage (VCCI to GND)
Output Supply Voltage
(VCCO to GND)
Positive Supply Differential
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.5 V to +6.0 V
−0.5 V to +6.0 V
−6.0 V to +6.0 V
(VCCI − VCCO
)
Input Voltages
Input Voltage
THERMAL RESISTANCE
−0.5 V to VCCI + 0.5 V
(VCCI + 0.5 V)
50 mA
JA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Differential Input Voltage
Maximum Input/Output Current
Shutdown Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Latch/Hysteresis Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Output Current
Table 3. Thermal Resistance
Package Type
1
−0.5 V to VCCO + 0.5 V
50 mA
θJA
426
62
Unit
°C/W
°C/W
ADCMP606 SC70 6-lead
ADCMP607 LSCFP 12-lead
−0.5 V to VCCO + 0.5 V
50 mA
50 mA
1 Measurement in still air.
Temperature
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
−40°C to +125°C
150°C
−65°C to +150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 5 of 16
ADCMP606/ADCMP607
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
9
8
7
V
EE
V
1
2
3
CCO
ADCMP607
TOP VIEW
(Not to Scale)
LE/HYS
V
CCI
Q
1
2
3
6
5
4
Q
V
V
S
DN
EE
ADCMP606
V
/V
TOP VIEW
EE
CCI CCO
(Not to Scale)
V
V
P
N
Figure 3. ADCMP606 Pin Configuration
Figure 4. ADCMP607 Pin Configuration
Table 4. ADCMP606 (SC70-6) Pin Function Descriptions
Pin No.
Mnemonic
Description
1
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater
than the analog voltage at the inverting input, VN.
2
3
4
5
6
VEE
VP
VN
VCCI/VCCO
Q
Negative Supply Voltage.
Noninverting Analog Input.
Inverting Analog Input.
Input Section Supply/Output Section Supply. Shared pin.
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VN.
Table 5. ADCMP607 (LSCFP-12) Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
VCCO
VCCI
VEE
Output Section Supply.
Input Section Supply.
Negative Supply Voltage.
4
VP
Noninverting Analog Input.
5
VEE
Negative Supply Voltage.
6
VN
Inverting Analog Input.
7
8
9
SDN
LE/HYS
VEE
Shutdown. Drive this pin low to shut down the device.
Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.
Negative Supply Voltage.
10
Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, provided that the comparator is in compare mode.
Negative Supply Voltage.
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VN, provided that the comparator is in compare mode.
11
12
VEE
Q
Heat Sink
Paddle
VEE
The metallic back surface of the package is electrically connected to VEE. It can be left floating because
Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the
application board if improved thermal and/or mechanical stability is desired.
Rev. PrA | Page 6 of 16
Preliminary Technical Data
ADCMP606/ADCMP607
TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 3.3 V, TA = 25°C, unless otherwise noted.
Figure 5. Propagation Delay vs. Input Overdrive
Figure 8. Rise/Fall Time vs. Temperature
Figure 6. Propagation Delay vs. Input Common Mode
Figure 9.
Figure 7. Propagation Delay vs. Temperature
Figure 10. Input Bias Current vs. Input Common Mode
Rev. PrA | Page 7 of 16
ADCMP606/ADCMP607
Preliminary Technical Data
Figure 11. Input Bias Current vs. Temperature
Figure 13. Input Offset Voltage vs. Temperature
Figure 12. Hysteresis vs. VCC
Rev. PrA | Page 8 of 16
Preliminary Technical Data
ADCMP606/ADCMP607
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
If these high speed signals must be routed more than a
centimeter, then either microstrip or strip line techniques are
required to ensure proper transition times and to prevent
excessive output ringing and pulse-width-dependent
propagation delay dispersion.
The ADCMP606 and ADCMP607 comparators are very high
speed devices. Despite the low noise output stage, it is essential
to use proper high speed design techniques to achieve the
specified performance. Because comparators are
uncompensated amplifiers, feedback in any phase relationship is
likely to cause oscillations or undesired hysteresis. Of critical
importance is the use of low impedance supply planes,
particularly the output supply plane (VCCO) and the ground
plane (GND). Individual supply planes are recommended as
part of a multilayer board. Providing the lowest inductance
return path for switching currents ensures the best possible
performance in the target application.
It is also possible to operate the outputs with only the internal
termination if greater output swing is desired. This can be
especially useful for driving inputs on CMOS devices intended
for full swing ECL and PECL. VCCO must be kept high enough
that the specified minimum output low level (see the Electrical
Characteristics section) is not violated and the line length
driven is as short as possible.
USING/DISABLING THE LATCH FEATURE
It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the VCCI and VCCO supply
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the VCC pin. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.
The latch input of the ADCMP607 is designed for maximum
versatility. It can safely be left floating, or it can be driven low by
any standard TTL/CMOS device as a high speed latch.
In addition, the pin can be operated as a hysteresis control pin
with a bias voltage of 1.25 V nominal and an input resistance of
approximately 7000 Ω, allowing the comparator hysteresis to be
easily controlled by either a resistor or an inexpensive CMOS DAC.
Driving this pin high or floating the pin removes all hysteresis.
Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected
parallel to the hysteresis control resistor or current source.
CML-COMPATIBLE OUTPUT STAGE
Specified propagation delay dispersion performance can be
achieved by using proper transmission line terminations. The
outputs of the ADCMP606 and ADCMP607 are designed to drive
400 mV directly into a 50 Ω cable or into transmission lines
terminated using either microstrip or strip line techniques with
50 Ω referenced to VCC. The CML output stage is shown in the
simplified schematic diagram in Figure 14. Each output is back-
terminated with 50 Ω for best transmission line matching.
Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V regardless of VCC
.
V
CCO
50Ω
Q
Q
16mA
GND
Figure 14. Simplified Schematic Diagram of
CML-Compatible Output Stage
Rev. PrA | Page 9 of 16
ADCMP606/ADCMP607
Preliminary Technical Data
INPUT VOLTAGE
OPTIMIZING PERFORMANCE
1V/ns
As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulse-
width dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals; higher impedances encourage undesired
coupling.
V
± V
OS
N
10V/ns
DISPERSION
Q/Q OUTPUT
Figure 16. Propagation Delay—Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. Figure 17 shows the transfer
function for a comparator with hysteresis. As the input voltage
approaches the threshold (0.0 V, in this example) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +VH/2, and the
new switching threshold becomes −VH/2. The comparator remains
in the high state until the new threshold, −VH/2, is crossed from
below the threshold region in a negative direction. In this manner,
noise or feedback output signals centered on 0.0 V input cannot
cause the comparator to switch states unless it exceeds the region
bounded by VH/2.
COMPARATOR PROPAGATION
DELAY DISPERSION
The ADCMP606/ADCMP607 comparators are designed to
reduce propagation delay dispersion over a wide input overdrive
range of 5 mV to VCCI – 1 V. Propagation delay dispersion is the
variation in propagation delay that results from a change in the
degree of overdrive or slew rate (that is, how far or how fast the
input signal exceeds the switching threshold).
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instru-
mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (Figure 15
and Figure 16).
OUTPUT
V
OH
V
OL
ADCMP606/ADCMP607 dispersion is typically <TBD ps as the
overdrive varies from 10 mV to 500 mV and the input slew rate
varies from 2 V/ns to 10 V/ns. This specification applies to both
positive and negative signals because each device has very closely
matched delays for positive-going and negative-going inputs, as
well as very low output skews.
INPUT
0
–V
2
+V
2
H
H
Figure 17. Comparator Hysteresis Transfer Function
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and induce
oscillation in some cases.
500mV OVERDRIVE
INPUT VOLTAGE
10mV OVERDRIVE
V
± V
OS
N
The ADCMP607 comparator offers a programmable hysteresis
feature that can significantly improve accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND, varies the amount of hysteresis
in a predictable, stable manner. Leaving the LE/HYS pin
disconnected or driving it high removes the hysteresis. The
DISPERSION
Q/Q OUTPUT
Figure 15. Propagation Delay—Overdrive Dispersion
Rev. PrA | Page 10 of 16
Preliminary Technical Data
ADCMP606/ADCMP607
maximum hysteresis that can be applied using this pin is
approximately 160 mV. Figure 18 illustrates the amount of
hysteresis applied as a function of the external resistor value,
and Figure TBD illustrates hysteresis as a function of the current.
CROSSOVER BIAS POINT
In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
VCC rail and others are active near the VEE rail. At some predeter-
mined point in the common-mode range, a crossover occurs. At
this point, normally VCC/2, the direction of the bias current reverses
and the measured offset voltages and currents change.
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7k 20% throughout the hysteresis
control range. The advantages of applying hysteresis in this manner
are improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
As described in the Using/Disabling the Latch Feature section,
hysteresis control need not compromise the latch function.
The ADCMP606/ADCMP607 slightly elaborate on this scheme.
With VCC less than 4 V, this crossover is at the expected VCC/2,
but with VCC greater than 4 V, the crossover point instead follows
VCC 1:1, bringing it to approximately 3 V with VCC at 5 V. This
means that at any voltage, the comparator input characteristics
more closely resemble the inputs of nonrail-to-rail ground
sensing comparators, such as the AD8611.
MINIMUM INPUT SLEW RATE REQUIREMENT
(Remove if device is stable.)
As with most high speed comparators without hysteresis, a
minimum slew rate must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This oscillation
is due in part to the high input bandwidth of the comparator in
combination with feedback parasitics inherent in the package
and PC board. A minimum slew rate of TBD V/μs ensures clean
output transitions from the ADCMP606/ADCMP607 comparators
unless hysteresis is programmed. In many applications, chattering
due to the absence of hysteresis is not harmful.
Figure 18. Hysteresis vs. RHYS Control Resistor
Rev. PrA | Page 11 of 16
ADCMP606/ADCMP607
Preliminary Technical Data
TYPICAL APPLICATION CIRCUITS
5V
2.5V TO 5V
50Ω 50Ω
0.1µF
50Ω 50Ω
CML
INPUT
PWM
ADCMP606
2kΩ
CML
OUTPUT
OUTPUT
2kΩ
ADCMP606
INPUT
2.5V
±50mV
0.1µF
INPUT
2.5V
REF
Figure 19. Self-Biased, 50% Slicer
10kΩ
10kΩ
3.3V
ADCMP601
LE/HYS
100kΩ
10kΩ
150pF
50Ω 50Ω
CML
OUTPUT
LVDS
100Ω
ADCMP606
Figure 23. Oscillator and Pulse-Width Modulator
Figure 20. LVDS to CML
2.5V TO 5V
50Ω 50Ω
5V
ADCMP607
10kΩ
50Ω 50Ω
CML
OUTPUT
LE/HYS
82pF
DIGITAL
74 VHC
ADCMP607
INPUT
1G07
LE/HYS
150kΩ
CONTROL
VOLTAGE
0V TO 2.5V
10kΩ
150kΩ
CONTROL
VOLTAGE
10kΩ
Figure 24. Hysteresis Adjustment with Latch
Figure 21. Current-Controlled Oscillator
+2.5V
V
CCI
V
CCO
50Ω 50Ω
3.3V
OUTPUT
ADCMP607
1N4001
V
V
CCO
CCI
50Ω 50Ω
3.3V
PECL
–2.5V
EE
LVDS
100Ω
ADCMP607
V
Figure 25.Ground-Referenced CML with 3 V Input Range
Figure 22.Fake PECL Levels Using a Series Diode
Rev. PrA | Page 12 of 16
Preliminary Technical Data
TIMING INFORMATION
ADCMP606/ADCMP607
Figure 26 illustrates the ADCMP606/ADCMP607 timing relationships. Table 6 provides definitions of the terms shown in the figure.
1.1V
LATCH ENABLE
tS
tPL
tH
V
IN
DIFFERENTIAL
INPUT VOLTAGE
V
± V
OS
N
V
OD
tPDL
tPLOH
Q OUTPUT
50%
50%
tF
tPDH
Q OUTPUT
tPLOL
tR
Figure 26. System Timing Diagram
Table 6. Timing Descriptions
Symbol Timing
Description
tPDH
tPDL
tR
Input to output high delay
Input to output low delay
Output rise time
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50% point of an output high-to-low transition.
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
tF
Output fall time
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
VOD
Voltage overdrive
Difference between the input voltages VA and VB.
Rev. PrA | Page 13 of 16
ADCMP606/ADCMP607
NOTES
Preliminary Technical Data
Rev. PrA | Page 14 of 16
Preliminary Technical Data
NOTES
ADCMP606/ADCMP607
Rev. PrA | Page 15 of 16
ADCMP606/ADCMP607
NOTES
Preliminary Technical Data
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05917-0-3/06(PrA)
Rev. PrA | Page 16 of 16
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