ADAU1966WBSTZ [ADI]
16-Channel High Performance; 16通道高性能型号: | ADAU1966WBSTZ |
厂家: | ADI |
描述: | 16-Channel High Performance |
文件: | 总52页 (文件大小:2329K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
16-Channel High Performance
Differential Output, 192 kHz, 24-Bit DAC
ADAU1966
GENERAL DESCRIPTION
FEATURES
The ADAU1966 is a high performance, single-chip DAC that
provides 16 digital-to-analog converters (DACs) with differen-
tial output using the Analog Devices, Inc., patented multibit
sigma-delta (Σ-Δ) architecture. An SPI/I2C port is included,
allowing a microcontroller to adjust volume and many other
parameters. The ADAU1966 operates from 2.5 V digital and
3.3 V or 5 V analog supplies. A linear regulator is included to
generate the digital supply voltage from the analog supply volt-
age. The ADAU1966 is available in an 80-lead LQFP package.
118 dB DAC dynamic range and SNR
−98 dB THD + N
Differential voltage DAC output
2.5 V digital and 3.3 V or 5 V analog and IO supplies
299 mW total (19 mW/channel) quiescent power at AVDD = 3.3 V
PLL generated or direct MCLK master clock
Low EMI design
Linear regulator driver to generate digital supply
Supports 24-bit and 32 kHz to 192 kHz sample rates
Low propagation 192 kHz sample rate mode
Log volume control with autoramp function
Temperature sensor with digital readout 3°C accuracy
SPI and I2C controllable for flexibility
The ADAU1966 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the internal master clock
from an external LRCLK, the ADAU1966 can eliminate the
need for a separate high frequency master clock and can be
used with or without a bit clock. The DACs are designed using
the latest Analog Devices continuous time architectures to
further minimize EMI. By using 2.5 V digital supplies, power
consumption is minimized, and the digital waveforms are a
smaller amplitude, further reducing emissions.
Software-controllable clickless mute
Software power-down
Right-justified, left-justified, I2S, and TDM modes
Master and slave modes with up to 16-channel input/output
80-lead LQFP package
Qualified for automotive applications
APPLICATIONS
Automotive audio systems
Home theater systems
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT
ADAU1966
DAC
SERIAL DATA PORT
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
SDATA
IN
SDATA
IN
DAC
DIGITAL
DIGITAL
FILTER
AND
VOLUME
CONTROL
DIFFERENTIAL
ANALOG
DIFFERENTIAL
ANALOG
DAC
DAC
DAC
DAC
DAC
CLOCKS
FILTER
AND
AUDIO
AUDIO
VOLUME
CONTROL
OUTPUTS
OUTPUTS
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
2
SPI/I C
CONTROL PORT
PRECISION
VOLTAGE
REFERENCE
INTERNAL
TEMP
SENSOR
CONTROL DATA
INPUT/OUTPUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADAU1966
TABLE OF CONTENTS
Features .............................................................................................. 1
Block Power-Down and Thermal Sensor Control 1 Register26
Power-Down Control 2 Register.............................................. 27
Power-Down Control 3 Register.............................................. 28
Thermal Sensor Temperature Readout Register.................... 29
DAC Control 0 Register ............................................................ 30
DAC Control 1 Register ............................................................ 31
DAC Control 2 Register ............................................................ 32
DAC Individual Channel Mutes 1 Register ............................ 33
DAC Individual Channel Mutes 2 Register ............................ 34
Master Volume Control Register.............................................. 35
DAC 1 Volume Control Register.............................................. 35
DAC 2 Volume Control Register.............................................. 36
DAC 3 Volume Control Register.............................................. 36
DAC 4 Volume Control Register.............................................. 37
DAC 5 Volume Control Register.............................................. 37
DAC 6 Volume Control Register.............................................. 38
DAC 7 Volume Control Register.............................................. 38
DAC 8 Volume Control Register.............................................. 39
DAC 9 Volume Control Register.............................................. 39
DAC 10 Volume Control Register............................................ 40
DAC 11 Volume Control Register............................................ 40
DAC 12 Volume Control Register............................................ 41
DAC 13 Volume Control Register............................................ 41
DAC 14 Volume Control Register............................................ 42
DAC 15 Volume Control Register............................................ 42
DAC 16 Volume Control Register............................................ 43
Common-Mode and Pad Strength Register ........................... 43
DAC Power Adjust 1 Register................................................... 44
DAC Power Adjust 2 Register................................................... 45
DAC Power Adjust 3 Register................................................... 46
DAC Power Adjust 4 Register................................................... 47
Outline Dimensions....................................................................... 51
Ordering Guide .......................................................................... 51
Automotive Products................................................................. 51
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Analog Performance Specifications........................................... 3
Crystal Oscillator Specifications................................................. 5
Digital Input/Output Specifications........................................... 6
Power Supply Specifications........................................................ 6
Digital Filters................................................................................. 7
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 13
Application Circuits ....................................................................... 14
Theory of Operation ...................................................................... 15
Digital-to-Analog Converters (DACs) .................................... 15
Clock Signals............................................................................... 15
RST
Power-Up and
..................................................................... 16
Standalone Mode........................................................................ 17
I2C Control Port.......................................................................... 17
Serial Control Port: SPI Control Mode ................................... 19
Power Supply and Voltage Reference....................................... 19
Serial Data Ports—Data Format............................................... 19
Time-Division Multiplexed (TDM) Modes............................ 19
Temperature Sensor ................................................................... 20
Additional Modes....................................................................... 22
Register Summary .......................................................................... 23
Register Details ............................................................................... 24
PLL and Clock Control 0 Register ........................................... 24
PLL and Clock Control 1 Register ........................................... 25
REVISION HISTORY
9/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 52
ADAU1966
SPECIFICATIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word
width = 24 bits, load capacitance (digital output) = 20 pF, load current (digital output) = 1 mꢀ or 1.5 kΩ to ½ DVDD supply, input
voltage high = 2.0 V, input voltage low = 0.8 V, unless otherwise noted.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at ꢀVDDx = 5 V and an ambient temperature of 25°C. Supply voltages = ꢀVDDx = 5 V, DVDD = 2.5 V,
ambient temperature1 (Tꢀ) = 25°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
20 Hz to 20 kHz, −60 dB input
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
105
108
115.5
118
−90
dB
dB
dB
0 dBFS
Two channels running, −1 dBFS
16 channels running, −1 dBFS
AVDDx = 5.0 V
−98
−98
3.00 ( 8.ꢀ9)
dB
dB
−85
Full-Scale Differential Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE VOLTAGES
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
−10
−25
−30
+10
+25
+30
−6
100
0
0.375
95.25
0.6
100
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
TEMPERATURE SENSOR
Temperature Accuracy
Temperature Readout Range
Temperature Readout Step Size
Temperature Sample Rate
REGULATOR
TS_REF pin, AVDDx = 5.0 V
CM pin, AVDDx = 5.0 V
CM pin, AVDDx = 5.0 V
1.50
2.25
2.25
V
V
V
2.1ꢀ
2.29
−3
−60
+3
+1ꢀ0
°C
°C
°C
Hz
1
0.25
6
Input Supply Voltage
Regulated Output Voltage
VSUPPLY pin
VSENSE pin
3.0
2.26
5
2.50
5.5
2.59
V
V
1 Functionally guaranteed at −ꢀ0°C to +125°C case temperature.
Rev. 0 | Page 3 of 52
ADAU1966
Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 5 V, DVDD = 2.5 V,
ambient temperature1 (TA) = 105°C, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
20 Hz to 20 kHz, −60 dB input
No Filter (RMS)
109
113.5
dB
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
110.5
116
−85
dB
dB
0 dBFS
Two channels running
Eight channels running
AVDDx = 5.0 V
−92.5
−92.5
3.00 ( 8.49)
dB
dB
−85
Full-Scale Differential Output Voltage
Gain Error
Offset Error
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
−10
−25
−30
+10
+25
+30
−6
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
100
0
0.375
95.25
0.6
100
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
TS_REF pin, AVDDx = 5.0 V
CM pin, AVDDx = 5.0 V
CM pin, AVDDx = 5.0 V
1.50
2.25
2.25
V
V
V
2.14
2.29
Input Supply Voltage
Regulated Output Voltage
VSUPPLY pin
VSENSE pin
3.0
2.25
5
2.50
5.5
2.55
V
V
1 Functionally guaranteed at −40°C to +125°C case temperature.
Specifications guaranteed at AVDDx = 3.3 V and an ambient temperature of 25°C. Supply voltages = AVDDx = 3.3 V, DVDD = 2.5 V,
ambient temperature1 (TA) = 25°C, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
20 Hz to 20 kHz, −60 dB input
No Filter (RMS)
109
111
dB
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
111.5
113.5
−90
dB
dB
0 dBFS
Two channels running
Eight channels running
AVDDx = 3.3 V
−97
−97
2.00 ( 5.66)
dB
dB
−85
Full-Scale Differential Output Voltage
Gain Error
Offset Error
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
−10
−25
−30
+10
+25
+30
−6
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-Emphasis Gain Error
Output Resistance at Each Pin
100
0
0.375
95.25
0.6
100
Rev. 0 | Page 4 of 52
ADAU1966
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
REFERENCE
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
TS_REF pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
1.50
1.50
1.50
V
V
V
1.43
1.56
Input Supply Voltage
Regulated Output Voltage
VSUPPLY pin
VSENSE pin
3.0
2.26
5
2.50
5.5
2.59
V
V
1 Functionally guaranteed at −40°C to +125°C case temperature.
Specifications guaranteed at AVDDx = 3.3 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 3.3 V, DVDD = 2.5 V,
ambient temperature1 (TA) = 105°C, unless otherwise noted.
Table 4.
Parameter
Conditions/Comments
Min
Typ
Max
Unit
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
20 Hz to 20 kHz, −60 dB input
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
108
110
109
112
−85
dB
dB
dB
0 dBFS
Two channels running
Eight channels running
AVDDx = 3.3 V
−92
−92
2.00 (5.66)
dB
dB
−83
Full-Scale Differential Output Voltage
Gain Error
Offset Error
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
−10
−25
−30
+10
+25
+30
−6
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
100
0
0.375
95.25
0.6
100
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
TS_REF pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
1.50
1.50
1.50
V
V
V
1.43
1.56
Input Supply Voltage
Regulated Output Voltage
VSUPPLY pin
VSENSE pin
3.0
2.25
5
2.50
5.5
2.55
V
V
1 Functionally guaranteed at −40°C to +125°C case temperature.
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 5.
Parameter
Min
Typ
Max
14
12
Unit
Transconductance, TA = 25°C
Transconductance, TA = 105°C
6.4
5.2
7 to 10
7.5 to 8.5
mmhos
mmhos
Rev. 0 | Page 5 of 52
ADAU1966
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +105°C, IOVDD = 5.0 V and 3.3 V 10ꢀ.
Table 6.
Parameter
Test Conditions/Comments
Min
3.7
2.5
Typ
Max
Unit
V
V
V
V
μA
μA
V
V
pF
High Level Input Voltage (VIH)
IOVDD = 5.0 V
IOVDD = 3.3 V
IOVDD = 5.0 V
IOVDD = 3.3 V
IIH at VIH = 2.4 V
IIL at VIL = 0.8 V
IOH = 1 mA
Low Level Input Voltage (VIL)
Input Leakage
1.3
0.8
10
10
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Input Capacitance
IOVDD − 0.60
IOL = 1 mA
0.4
5
POWER SUPPLY SPECIFICATIONS
Table 7.
Parameter
SUPPLIES
Voltage
Test Conditions/Comments
Min
Typ
Max
Unit
AVDD
DVDD
PLLVDD
IOVDD
VSUPPLY
3.0
5.0
2.5
2.5
5.0
5.0
5.5
3.6
3.6
5.5
5.5
V
V
V
V
V
2.25
2.25
3.0
3.0
Analog Current—AVDD = 5.0 V
Normal Operation
Power-Down
82
1
mA
μA
Analog Current—AVDD = 3.3 V
Normal Operation
Power-Down
60
1
mA
μA
Digital Current—DVDD = 2.5 V
Normal Operation
Power-Down
fS = 48 kHz to 192 kHz
No MCLK or I2S
30
4
mA
μA
PLL Current—PLLVDD = 2.5 V
Normal Operation
Power-Down
fS = 48 kHz to 192 kHz
5
1
mA
μA
IO Current—IOVDD = 3.3 V
Normal Operation
Power-Down
4
1
mA
μA
QUIESCENT DISSIPATION—DITHER INPUT
Operation
MCLK = 256 × fS, 48 kHz
All Supplies
All Supplies
Analog Supply
Analog Supply
Digital Supply
PLL Supply
I/O Supply
AVDDx = 5.0 V, DVDD/PLLVDD = 2.5 V, IOVDD = 3.3 V
AVDDx = 3.3 V, DVDD/PLLVDD = 2.5 V, IOVDD = 3.3 V
511
299
410
198
75
13
13
0
mW
mW
mW
mW
mW
mW
mW
mW
AVDDx = 5.0 V
AVDDx = 3.3 V
DVDD = 2.5 V
PLLVDD= 2.5 V
IOVDD = 3.3 V
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
85
85
dB
dB
Rev. 0 | Page 6 of 52
ADAU1966
DIGITAL FILTERS
Table 8.
Parameter
Mode
Factor
Min
Typ
22
Max
Unit
DAC INTERPOLATION FILTER
Pass Band
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
192 kHz low delay mode, typical at 192 kHz
0.4535 × fS
0.3646 × fS
0.3646 × fS
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
μs
μs
μs
μs
35
70
Pass-Band Ripple
Transition Band
Stop Band
0.01
0.05
0.1
0.5 × fS
0.5 × fS
0.5 × fS
0.5465 × fS
0.6354 × fS
0.6354 × fS
24
48
96
26
61
122
Stop-Band Attenuation
Propagation Delay
68
68
68
25/fS
11/fS
8/fS
521
115
42
2/fS
10
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 2.5 V 10ꢀ.
Table 9.
Parameter
Description
Min Typ Max Unit
INPUT MASTER CLOCK (MCLK) AND RESET
tMH
MCLK duty cycle, DAC clock source = PLL clock at
256 × fS, 384 × fS, 512 × fS, and 768 × fS
DAC clock source = direct MCLK at 512 × fS (bypass
on-chip PLL)
MCLKI frequency, PLL mode
Direct MCLK 512 × fS mode
DBCLK frequency, PLL mode
Low
40
40
6.9
60
60
%
%
tMH
fMCLK
fMCLK
fBCLK
tPDR
40.5 MHz
27.1 MHz
27.0 MHz
ns
15
tPDRR
Recovery, reset to active output
300
ms
PLL
Lock Time
Lock Time
MCLK input
DLRCLK input
10
50
60
ms
ms
%
256 × fS VCO Clock, Output Duty Cycle, MCLKO Pin
40
SPI PORT
tCCH
tCCL
See Figure 14
CCLK high
CCLK low
35
35
ns
ns
fCCLK
tCDS
tCDH
tCLS
CCLK frequency, fCCLK = 1/tCCP; only tCCP shown in Figure 14
CDATA setup, time to CCLK rising
CDATA hold, time from CCLK rising
10
MHz
ns
ns
10
10
10
10
10
CLATCH setup, time to CCLK rising
ns
tCLH
CLATCH hold, time from CCLK falling
CLATCH high, not shown in Figure 14
ns
tCLHIGH
ns
Rev. 0 | Page 7 of 52
ADAU1966
Parameter
tCOE
tCOD
tCOH
tCOTS
I2C
fSCL
tSCLL
tSCLH
tSCS
Description
Min Typ Max Unit
COUT enable from CCLK falling
COUT delay from CCLK falling
COUT hold from CCLK falling, not shown in Figure 14
COUT tristate from CCLK falling
See Figure 2 and Figure 13
SCL clock frequency
30
30
ns
ns
ns
ns
30
30
400
kHz
μs
SCL low
SCL high
1.3
0.6
μs
Setup time (start condition), relevant for repeated start 0.6
condition
μs
tSCH
Hold time (start condition), first clock generated after
this period
0.6
μs
tSSH
tDS
tSR
tSF
Setup time (stop condition)
Data setup time
SDA and SCL rise time
SDA and SCL fall time
Bus-free time between stop and start
See Figure 16
0.6
100
μs
ns
ns
ns
μs
300
300
tBFT
1.3
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDLS
tDDS
tDDH
DBCLK high, slave mode
DBCLK low, slave mode
10
10
10
5
−8
10
5
ns
ns
ns
ns
ns
ns
ns
DLRCLK setup, time to DBCLK rising, slave mode
DLRCLK hold from DBCLK rising, slave mode
DLRCLK skew from DBCLK falling, master mode
DSDATAx setup to DBCLK rising
DSDATAx hold from DBCLK rising
+8
tDS
tSCH
tSCH
SDA
SCL
tSR
tSCLH
tSCS
tBFT
tSCLL
tSF
Figure 2. I2C Timing Diagram
Rev. 0 | Page 8 of 52
ADAU1966
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 10.
θJA represents junction-to-ambient thermal resistance; θJC repre-
sents the junction-to-case thermal resistance. All characteristics
are for a 4-layer board with a solid ground plane.
Parameter
Rating
Analog (AVDD)
I/O (IOVDD)
Digital (DVDD)
PLL (PLLVDD)
−0.3 V to +5.5 V
−0.3 V to +5.5 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +6.0 V
20 mA
Table 11. Thermal Resistance
Package Type
θJA
θJC
Unit
VSUPPLY
80-Lead LQFP
42.3
10.0
°C/W
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
–0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
ESD CAUTION
Operating Temperature Range (Case) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 9 of 52
ADAU1966
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
DAC_BIAS3
DAC_BIAS4
AVDD3
DAC_BIAS2
DAC_BIAS1
AVDD2
PIN 1
INDICATOR
3
4
DAC13P
DAC13N
DAC14P
DAC14N
DAC15P
DAC15N
DAC16P
DAC16N
AVDD4
DAC4N
5
DAC4P
6
DAC3N
7
DAC3P
8
DAC2N
ADAU1966
9
DAC2P
TOP VIEW
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
DAC1N
DAC1P
AVDD1
AGND4
AGND1
PLLGND
LF
PU/RST
SA_MODE
CLATCH/ADDR0/SA*
CCLK/SCL/SA*
COUT/SDA/SA*
CDATA/ADDR1/SA*
DVDD
PLLVDD
MCLKI/XTALI
XTALO
MCLKO
DVDD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
*SEE TABLE 15 FOR SA_MODE SETTINGS.
Figure 3. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
Type1
Mnemonic
DAC_BIAS3
DAC_BIAS4
AVDD3
DAC13P
DAC13N
DAC14P
DAC14N
DAC15P
DAC15N
DAC16P
DAC16N
AVDD4
AGND4
PLLGND
LF
PLLVDD
MCLKI/XTALI
XTALO
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I
I
DAC Bias 3. AC couple with 470 nF to AGND3.
DAC Bias 4. AC couple with 470 nF to AVDD3.
Analog Power.
PWR
O
O
O
O
O
O
O
O
PWR
GND
GND
O
PWR
I
DAC13 Positive Output.
DAC13 Negative Output.
DAC14 Positive Output.
DAC14 Negative Output.
DAC15 Positive Output.
DAC15 Negative Output.
DAC16 Positive Output.
DAC16 Negative Output.
Analog Power.
Analog Ground.
PLL Ground.
PLL Loop Filter, Reference to PLLVDD.
Apply 2.5 V to power PLL.
Master Clock Input, Input to Crystal Inverter.
Output from Crystal Inverter.
Master Clock Output.
17
18
19
O
O
MCLKO
20, 29, 41
PWR
DVDD
Digital Power, 2.5 V.
21, 26, 30, 40 GND
DGND
Digital Ground.
Rev. 0 | Page 10 of 52
ADAU1966
Pin No.
22, 39
23
Type1
PWR
I
Mnemonic
IOVDD
VSENSE
Description
Power for Digital Input and Output Pins, 3.3 V to 5 V.
2.5 V Output of Regulator, Collector of Pass Transistor. Bypass with 10 μF in parallel
with 100 nF.
24
25
O
I
VDRIVE
VSUPPLY
Drive for Base of Pass Transistor.
5 V Input to Voltage Regulator, Emitter of Pass Transistor. Bypass with 10 μF in parallel
with 100 nF.
27
28
31
I/O
I/O
I
DBCLK
DLRCLK
DSDATA8/SA
Bit Clock for DACs.
Frame Clock for DACs.
DAC15 and DAC 16 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 15, and Table 16).
32
I
DSDATA7/SA
DAC13 and DAC 14 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 15, and Table 16).
33
34
35
36
37
38
42
I
I
I
I
I
I
I
DSDATA6
DSDATA5
DSDATA4
DSDATA3
DSDATA2
DSDATA1
CDATA/ADDR1/SA
DAC11 and DAC 12 Serial Data Input.
DAC9 and DAC 10 Serial Data Input.
DAC7 and DAC 8 Serial Data Input.
DAC5 and DAC 6 Serial Data Input.
DAC3 and DAC 4 Serial Data Input.
DAC1 and DAC 2 Serial Data Input.
Control Data Input (SPI)/Address 1 (I2C)/SA_MODE State (see the Standalone Mode
section and Table 15).
43
44
45
46
I/O
COUT/SDA/SA
CCLK/SCL/SA
CLATCH/ADDR0/SA
SA_MODE
Control Data Output (SPI)/Control Data Input (I2C)/SA_MODE State (see the
Standalone Mode section and Table 15).
Control Clock Input (SPI)/Control Clock Input (I2C)/SA_MODE State (see the Standalone
Mode section and Table 15).
Control Chip Select (SPI) (Low Active)/Address 0 (I2C)/SA_MODE State (see the
Standalone Mode section and Table 15).
Standalone Mode. This pin allows mode control of ADAU1966 using Pin 42 to Pin 45,
Pin 31, and Pin 32 (high active, see Table 15 and Table 16).
I
I
I
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
I
PU/RST
AGND1
AVDD1
DAC1P
DAC1N
DAC2P
DAC2N
DAC3P
DAC3N
DAC4P
DAC4N
AVDD2
DAC_BIAS1
DAC_BIAS2
AGND2
CM
Power-Up/Reset (Low Active).
Analog Ground.
Analog Power.
GND
PWR
O
O
O
O
O
O
O
DAC1 Positive Output.
DAC1 Negative Output.
DAC2 Positive Output.
DAC2 Negative Output.
DAC3 Positive Output.
DAC3 Negative Output.
DAC4 Positive Output.
DAC4 Negative Output.
Analog Power.
DAC Bias 1. AC couple with 470 nF to AVDD2.
DAC Bias 2. AC couple with 470 nF to AGND2.
Analog Ground.
Common-Mode Reference Filter Capacitor Connection. Bypass with 10 μF in parallel
with 100 nF to AGND2. This reference can be shut off in the PLL_CLK_CTRL1 register
and the pin can be driven with an outside voltage source.
O
PWR
I
I
GND
O
63
O
TS_REF
Voltage Reference Filter Capacitor Connection. Bypass with 10 μF in parallel with
100 nF to AGND2.
64
65
66
67
68
69
70
O
O
O
O
O
O
O
DAC5P
DAC5N
DAC6P
DAC6N
DAC7P
DAC7N
DAC8P
DAC5 Positive Output.
DAC5 Negative Output.
DAC6 Positive Output.
DAC6 Negative Output.
DAC7 Positive Output.
DAC7 Negative Output.
DAC8 Positive Output.
Rev. 0 | Page 11 of 52
ADAU1966
Pin No.
71
72
73
74
75
76
77
78
Type1
Mnemonic
DAC8N
DAC9P
Description
O
O
O
O
O
O
O
O
DAC8 Negative Output.
DAC9 Positive Output.
DAC9 Negative Output.
DAC10 Positive Output.
DAC10 Negative Output.
DAC11 Positive Output.
DAC11 Negative Output.
DAC12 Positive Output.
DAC12 Negative Output.
Analog Ground.
DAC9N
DAC10P
DAC10N
DAC11P
DAC11N
DAC12P
DAC12N
AGND3
79
80
O
GND
1 I = input, O = output, I/O = input/output, PWR = power, GND = ground.
Rev. 0 | Page 12 of 52
ADAU1966
TYPICAL PERFORMANCE CHARACTERISTICS
0.05
0.20
0.15
0.10
0.05
0
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.05
–0.10
–0.15
–0.20
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (FACTORED TO fS
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
)
FREQUENCY (FACTORED TO fS
)
Figure 4. DAC Pass-Band Filter Response, 48 kHz
Figure 6. DAC Pass-Band Filter Response, 96 kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
FREQUENCY (FACTORED TO fS
)
FREQUENCY (FACTORED TO fS
)
Figure 5. DAC Stop-Band Filter Response, 48 kHz
Figure 7. DAC Stop-Band Filter Response, 96 kHz
Rev. 0 | Page 13 of 52
ADAU1966
APPLICATION CIRCUITS
Typical application circuits are shown in Figure 8 to Figure 11. Recommended loop filters for DLRCLK and MCLKI/XTALI modes of the
PLL reference are shown in Figure 8. Output filters for the DAC outputs are shown in Figure 9 and Figure 10, and an external regulator
circuit is shown in Figure 11.
DLRCLK
MCLKI/XTALI
LF
LF
39nF
5.6nF
2.2nF
390pF
3.32kΩ
562Ω
PLLVDD
PLLVDD
Figure 8. Recommended Loop Filters for DLRCLK or MCLKI/XTALI PLL Reference Modes
10µF
+
237Ω
DACP
DACN
OUTP
OUTN
2.7nF
237Ω
10µF
+
49.9kΩ
49.9kΩ
Figure 9. Typical DAC Output Passive Filter Circuit (Differential)
1.1nF
AD8672ARZ
1.50kΩ
1.54kΩ
5
4.7µF
+
DAC1P
+12V DC
100Ω
7
OUTPUT1P
6
422Ω
2.49kΩ
100kΩ
100kΩ
+
+
+
0.1µF
0.1µF
4.7µF
1nF
1nF
4.7µF
8
V+
V–
4
+
4.7µF
4.7µF
2.49kΩ
422Ω
2
3
–12V DC
4.7µF
+
100Ω
1
OUTPUT1N
1.50kΩ
1.54kΩ
DAC1N
AD8672ARZ
1.1nF
Figure 10. Typical DAC Output Active Filter Circuit (Differential)
100nF
10µF
E
+
VSUPPLY
5V
1kΩ
B
VDRIVE
VSENSE
FZT953
C
2.5V
+
100nF
10µF
Figure 11. Recommended 2.5 V Regulator Circuit
Rev. 0 | Page 14 of 52
ADAU1966
THEORY OF OPERATION
The ADAU1966 offers control over the analog performance
DIGITAL-TO-ANALOG CONVERTERS (DACS)
of the DACs; it is possible to program the registers to reduce
the power consumption with the trade-off of lower SNR and
THD + N. The reduced power consumption is the result of
changing the internal bias current to the analog output
amplifiers.
The 16 ADAU1966 digital-to-analog converter (DAC) channels
are differential for improved noise and distortion performance
and are voltage output for simplified connection. The DACs
include on-chip digital interpolation filters with 68 dB stop-band
attenuation and linear phase response, operating at an over-
sampling ratio of 256× (48 kHz range), 128× (96 kHz range), or
64× (192 kHz range). Each channel has its own independently
programmable attenuator, adjustable in 255 steps in increments
of 0.375 dB. Digital inputs are supplied through eight serial data
input pins (two channels on each pin), a common frame clock
(DLRCLK), and a bit clock (DBCLK). Alternatively, any one of the
TDM modes can be used to access up to 16 channels on a single
TDM data line.
Register DAC_POWER1 to Register DAC_POWER4 present
four basic settings for the DAC power vs. performance in each
of the 16 channels: best performance, good performance, low
power, and lowest power. Alternatively, in Register PLL_CLK_
CTRL1[7:6], the LOPWR_MODE bits offer global control over
the power and performance for all 16 channels. The default
setting is b00. This setting allows the channels to be controlled
individually using the DAC_POWERx registers. Setting b10
and Setting b11 select the low power and lowest power settings.
The data presented in Table 13 shows the result of setting all
16 channels to each of the four settings. The SNR and THD + N
specifications are shown in relation to the measured perfor-
mance of a device at the best performance setting.
The ADAU1966 has a low propagation delay mode; this mode
is an option for an fS of 192 kHz and is enabled in Register DAC_
CTRL0[2:1]. By setting these bits to b11, the propagation delay
is reduced by the amount shown in Table 8. The shorter delay is
achieved by reducing the amount of digital filtering; the nega-
tive impact of selecting this mode is reduced audio frequency
response and increased out-of-band energy.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
When AVDD is supplied with 5 V, each analog output pin has a
nominal common-mode (CM) dc level of 2.25 V and swings
8.49 V p-p (3 V rms differential) from a 0 dBFS digital input
signal. An AVDD of 3.3 V generates a CM dc voltage of 1.5 V
and allows differential audio swings of 5.66 V p-p (2 V rms)
from a 0 dBFS digital input signal. The differential analog
outputs require only a single-order passive differential RC filter
to provide the specified DNR performance; see Figure 9 for an
example filter. The outputs can easily drive differential inputs
on a separate PCB through cabling as well as differential inputs
on the same PCB.
CLOCK SIGNALS
RST
Upon powering the ADAU1966 and asserting the PU/
pin
high, the part starts in either standalone mode (SA_MODE) or
program mode, depending on the state of SA_MODE (Pin 46).
The clock functionality of SA_MODE is described in the
Standalone Mode section. In program mode, the default for the
ADAU1966 is for the MCLKO pin to feed a buffered output of
the MCLKI signal. The default for the DLRCLK and DBCLK
ports is slave mode; the DAC must be driven with a coherent set
of MCLK, LRCLK, and BCLK signals to function.
If more signal level is required or if a more robust filter is needed, a
single op amp gain stage designed as a second-order, low-pass
Bessel filter can be used to remove the high frequency out-of-
band noise present on each pin of the differential outputs. The
choice of components and design of this circuit is critical to
yield the full DNR of the DACs (see the recommended passive
and active circuits in Figure 9 and Figure 10). This filter can be
built into an active difference amplifier to provide a single-ended
output with gain, if necessary. Note that the use of op amps with
low slew rate or low bandwidth can cause high frequency noise
and tones to fold down into the audio band; exercise care when
selecting these components.
The MCLKO pin can be programmed to provide different clock
signals using Register Bits PLL_CLK_CTRL1[5:4]. The default,
b10, provides a buffered copy of the clock signal that is driving
the MCLKI pin. Two modes, b00 and b01, provide low jitter
clock signals. The b00 setting yields a clock rate between 4 MHz
and 6 MHz, and b01 yields a clock rate between 8 MHz and
12 MHz. Both of these clock frequencies are scaled as ratios of
MCLK automatically inside the ADAU1966. As an example, an
MCLK of 8.192 MHz and a setting of b00 yield an MCLKO of
(8.192/2) = 4.096 MHz. Alternatively, an MCLK of 36.864 MHz
and a setting of b01 yield an MCLKO frequency of (36.864/3) =
12.288 MHz. The setting b11 shuts off the MCLKO pin.
Table 13. DAC Power vs. Performance
Register Setting
Total AVDD Current
SNR
Best Performance
Good Performance
73 mA
−0.2 dB
Low Power
64 mA
−1.5 dB
−3.0 dB
Lowest Power
54 mA
−14.2 dB
−5.8 dB
82 mA
Reference
Reference
THD + N (−1 dbFS signal)
−1.8 dB
Rev. 0 | Page 15 of 52
ADAU1966
RST
bit in the DAC_CTRL1 register. With the BCLK_GEN bit set to
b1 (internal) and the SAI_MS bit set to b0 (slave), the ADAU1966
generate its own DBCLK; this works with the PLL input set to
either MCLKI/XTALI or DLRCLK. DLRCLK is the only required
clock in DLRCLK PLL mode.
After the PU/
pin has been asserted high, the PLL_CLK_
CTRLx registers (0x00 and 0x01) can be programmed. The
on-chip phase-locked loop (PLL) can be selected to use the
clock appearing at the MCLKI/XTALI pin at a frequency of
256, 384, 512, or 768 times the sample rate (fS), referenced to
the 48 kHz mode from the master clock select (MCS) setting,
as described in Table 14. In 96 kHz mode, the master clock fre-
quency stays at the same absolute frequency; therefore, the
actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if
the ADAU1966 is programmed in 256 × fS mode, the frequency
of the master clock input is 256 × 48 kHz = 12.288 MHz. If the
ADAU1966 is then switched to 96 kHz operation (by writing to
DAC_CTRL0 [2:1]), the frequency of the master clock should
remain at 12.288 MHz, which is 128 × fS in this example. In
192 kHz mode, MCS becomes 64 × fS.
POWER-UP AND RST
Power sequencing for the ADAU1966 should start with AVDD
and IOVDD, followed by DVDD. It is very important that
AVDD be settled at a regulated voltage and that IOVDD be
within 10ꢀ of regulated voltage before applying DVDD. When
using the ADAU1966 internal regulator, this timing occurs by
default.
RST
To guarantee proper startup, the PU/
pin should be pulled
low by an external resistor and then driven high after the power
RST
supplies have stabilized. The PU/
using a simple RC network.
can also be pulled high
The internal clock for the digital core varies by mode: 512 × fS
(48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz
mode). By default, the on-board PLL generates this internal
master clock from an external clock.
RST
Driving the PU/
state (<3 μA). All functionality of the ADAU1966 is disabled
RST
pin low puts the part into a very low power
until the PU/
pin is asserted high. Once this pin is asserted
The PLL should be powered and stable before the ADAU1966 is
used as a source for quality audio. The PLL is enabled by reset
and does not require writing to the I2C or SPI port for normal
operation.
high, the ADAU1966 requires 300 ms to stabilize. The MMUTE
bit in the DAC_CTRL0 register must be toggled for operation.
The PUP bit in the PLL_CLK_CTRL0 register can be used to
power down the ADAU1966. Engaging the master power-down
puts the ADAU1966 in an idle state while maintaining the set-
tings of all registers. Additionally, the power-down bits in the
PDN_THRMSENS_CTRL1 register (TS_PDN, PLL_PDN, and
VREG_PDN) can be used to power down individual sections of
the ADAU1966.
With the PLL enabled, the performance of the ADAU1966 is
not affected by jitter as high as a 300 ps rms time interval error
(TIE). If the internal PLL is not used, it is best to use an independ-
ent crystal oscillator to generate the master clock.
If the ADAU1966 is to be used in direct MCLK mode, the PLL
can be powered down in the PDN_THRMSENS_CTRL_1 regis-
ter. For direct MCLK mode, a 512 × fS (referenced to 48 kHz
mode) master clock must be used as MCLK, and the CLK_SEL
bit in the PLL_CLK_CTRL1 register must be set to b1.
The SOFT_RST bit in the PLL_CLK_CTRL0 register sets all of
the control registers to their default settings while maintaining
the internal clocks in default mode. The SOFT_RST bit does
not power down the analog outputs; toggling this bit does not
cause audible popping sounds at the differential analog outputs.
The ADAU1966 PLL can also be programmed to run from an
external LRCLK. When the PLLIN bits in the PLL_CLK_CTRL0
register are set to 01 and the appropriate loop filter is connected
to the LF pin (see Figure 8), the ADAU1966 PLL generates all
of the necessary internal clocks for operation with no external
MCLK. This mode reduces the number of high frequency
signals in the design, reducing EMI emissions.
Proper startup of the ADAU1966 should proceed as follows:
1. Apply power to the ADAU1966 as described previously.
RST
2. Assert the PU/
stabilized.
pin high after power supplies have
3. Set the PUP bit to b1.
4. Program all necessary registers for the desired settings.
5. Set the MMUTE bit to b0 to unmute all channels.
It is possible to further reduce EMI emissions of the circuit by
using the internal DBCLK generation setting of the BCLK_GEN
Rev. 0 | Page 16 of 52
ADAU1966
Table 14. MCS and fS Modes
Master Clock Select (MCS), PLL_CLK_CTRL0[2:1]
Setting 1, b01 Setting 2, b10
Sample Rate Select (FS)
DAC_CTRL0[2:1]
32 kHz, b00
44.1 kHz, b00
48 kHz, b00
Setting 0, b00
MCLK (MHz) Ratio
Setting 3, b11
Ratio
MCLK
Ratio
MCLK
Ratio
MCLK
256 × fS
256 × fS
256 × fS
128 × fS
128 × fS
128 × fS
64 × fS
8.192
384 × fS
384 × fS
384 × fS
192 × fS
192 × fS
192 × fS
96 × fS
12.288
16.9344
18.432
12.288
16.9344
18.432
12.288
16.9344
18.432
512 × fS
512 × fS
512 × fS
256 × fS
256 × fS
256 × fS
128 × fS
128 × fS
128 × fS
16.384
22.5792
24.576
16.384
22.5792
24.576
16.384
22.5792
24.576
768 × fS
768 × fS
768 × fS
384 × fS
384 × fS
384 × fS
192 × fS
192 × fS
192 × fS
24.576
33.8688
36.864
24.576
33.8688
36.864
24.576
33.8688
36.864
11.2896
12.288
8.192
11.2896
12.288
8.192
64 kHz, b01
88.2 kHz, b01
96 kHz, b01
128 kHz, b10 or b11
176.4 kHz, b10 or b11
192 kHz, b10 or b11
64 × fS
64 × fS
11.2896
12.288
96 × fS
96 × fS
and a data line, SDA. SDA is bidirectional, and the ADAU1966
drives SDA either to acknowledge the master (ACK) or to send
data during a read operation. The SDA pin for the I2C port is an
open-drain collector and requires a 2 kΩ pull-up resistor. A write
or read access occurs when the SDA line is pulled low while the
SCL line is high, indicated by a start in Figure 12 and Figure 13.
SDA is only allowed to change when SCL is low except when a
start or stop condition occurs, as shown in Figure 12 and Figure 13.
The first eight bits of the data-word consist of the device address
and the R/W bit. The device address consists of an internal built-in
address (0x04) and two address pins, ADDR1 and ADDR0. The
two address bits allow four ADAU1966 devices to be used in a
system. Initiating a write operation to the ADAU1966 involves
sending a start condition and then sending the device address
STANDALONE MODE
The ADAU1966 can operate without a typical I2C or SPI
connection to a microcontroller. This standalone mode is
made available by setting the SA_MODE (Pin 46) to high
(IOVDD). All registers are set to default except the options
shown in Table 15.
Table 15. SA_MODE Settings
Pin No. Setting Function
42
43
44
45
0
1
0
1
0
1
0
1
Master mode serial audio interface (SAI)
Slave mode SAI
MCLK = 256 × fS, PLL on
MCLK = 384 × fS, PLL on
AVDD = 5.0 V (CM = 2.25 V)
AVDD = 3.3 V (CM = 1.50 V)
I2S SAI format
R
with the /W bit set low. The ADAU1966 responds by issuing
an acknowledge to indicate that it has been addressed. The user
then sends a second frame telling the ADAU1966 which register
is required to be written. Another acknowledge is issued by the
ADAU1966. Finally, the user can send another frame with the
eight data bits required to be written to the register. A third
acknowledge is issued by the ADAU1966 after which the user
can send a stop condition to complete the data transfer.
TDM modes, determined by Pin 31 and Pin 32
When both SA_MODE and Pin 45 are set high, TDM mode is
selected. Table 16 shows the available TDM modes; these modes
are set by connecting Pin 31 (DSDATA8) and Pin 32 (DSDATA7)
to GND or IOVDD.
Table 16. TDM Modes
A read operation requires that the user first write to the
ADAU1966 to point to the correct register and then read the
data. This is achieved by sending a start condition followed by
Pin No.
Setting
Function
32:31
00
TDM4—DLRCLK pulse
TDM8—DLRCLK pulse
TDM16—DLRCLK pulse
TDM8—DLRCLK 50% duty cycle
01
10
11
R
the device address frame, with the /W bit low, and then the
register address frame. Following the acknowledge from the
ADAU1966, the user must issue a repeated start condition. The
R
next frame is the device address with the /W bit set high. On
When the ADAU1966 is powered up in SA_MODE and the
RST
ered version of the MCLKI pin, whether the source is a crystal
or an active oscillator.
the next frame, the ADAU1966 outputs the register data on the
SDA line. A stop condition completes the read operation.
PU/
pin is asserted high, the MCLKO pin provides a buff-
Table 17. I2C Addresses
I2C CONTROL PORT
ADDR1
ADDR0
Slave Address
0x04
0x24
0x44
0x64
The ADAU1966 has an I2C-compatible control port that per-
mits programming and reading back of the internal control
registers for the DACs and clock system. The I2C interface of the
ADAU1966 is a 2-wire interface consisting of a clock line, SCL,
0
0
1
1
0
1
0
1
Rev. 0 | Page 17 of 52
ADAU1966
SCL
SDA
AD1
AD0
0
0
1
0
0
R/W
0
0
0
0
0
1
1
0
START BY
MASTER (S)
ACK. BY
ADAU1966 (AS)
ACK. BY
ADAU1966 (AS)
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY STOP BY
ADAU1966 (AS) MASTER (P)
FRAME 3
DATA BYTE TO ADAU1966
Figure 12. I2C Write Format
SCL
SDA
AD1
AD0
0
0
1
0
0
R/W
0
0
0
0
0
1
1
0
START BY
MASTER (S)
ACK. BY
ADAU1966 (AS)
ACK. BY
ADAU1966 (AS)
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
0
0
0
0
1
AD1
AD0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
REPEATED START
BY MASTER (S)
ACK. BY
ADAU1966 (AS)
ACK. BY STOP BY
MASTER (AM) MASTER (P)
FRAME 3
CHIP ADDRESS BYTE
FRAME 4
REGISTER DATA
Figure 13. I2C Read Format
Table 18. I2C Abbreviations
Abbreviation
Condition
S
Start bit
P
Stop bit
AM
AS
Acknowledge by master
Acknowledge by slave
Table 19. Single Word I2C Write
S
Chip Address, R = 0
AS
Register Address
AS
Data-Word
AS
P
Table 20. Burst Mode I2C Write
Chip Address, R = 0
AS
S
Register Address
Register Address
AS
Data-Word 1
AS
Data-Word 2
AS
Data-Word N
AS
P
Table 21. Single Word I2C Read
Chip Address, R = 0
S
AS
AS
S
Chip Address, R = 1
AS
Data-Word
AM Data-
AM
P
Table 22. Burst Mode I2C Read
Chip Address, R AS Register
Address
S
AS
S
Chip Address, R AS Data-
Word 1
AM Data-
Word 2
AM
P
Word N
= 0
= 1
Rev. 0 | Page 18 of 52
ADAU1966
The temperature sensor internal voltage reference (VTS_REF
)
is brought out on the TS_REF pin and should be bypassed as
close as possible to the chip with a parallel combination of
10 μF and 100 nF.
SERIAL CONTROL PORT: SPI CONTROL MODE
The ADAU1966 has an SPI control port that permits program-
ming and reading back of the internal control registers for the
DACs and clock system. A standalone mode is also available for
operation without serial control; it is configured at reset using the
SA_MODE pin. See the Standalone Mode section for details
about SA_MODE.
The internal band gap reference can be disabled in the
PLL_CLK_CTRL1 register by setting VREF_EN to 0; the CM
pin can be then be driven from an external source. This can be
used to scale the DAC output to the clipping level of a power
amplifier based on its power supply voltage.
By default, the ADAU1966 is in I2C mode, but it can be put into
CLATCH
SPI control mode by pulling
low three times. This
The CM pin is the internal common-mode reference. It should
be bypassed as close as possible to the chip, with a parallel
combination of 10 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the
analog input and output signal pins. The output current should
be limited to less than 0.5 mA source and 2 mA sink.
is done by performing three dummy writes to the SPI port (the
ADAU1966 does not acknowledge these three writes). Begin-
ning with the fourth SPI write, data can be written to or read
from the IC. The ADAU1966 can be taken out of SPI control
mode only by a full reset initiated by power cycling the IC.
The SPI control port of the ADAU1966 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
DACs. Figure 14 shows the format of the SPI signal. The first
byte is a global address with a read/write bit. For the ADAU1966,
SERIAL DATA PORTS—DATA FORMAT
The 16 DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The clock signals are all synchronous with the sample
rate. The normal stereo serial modes are shown in Figure 15.
The DAC serial data mode defaults to I2S (1 BCLK delay) upon
power-up and reset. The ports can also be programmed for left-
justified and right-justified (24-bit and 16-bit) operation using
DAC_CTRL0[7:6]. Stereo and TDM modes can be selected using
DAC_CTRL0[5:3]. The polarity of DBCLK and DLRCLK is
programmable according to the DAC_CTRL1[1] and DAC_
CTRL1[5] bits. The serial ports are programmable as the clock
masters according to the DAC_CTRL1[0] bit. By default, the
serial port is in slave mode.
R
the address is 0x06, shifted left one bit due to the /W bit. The
second byte is the ADAU1966 register address, and the third
byte is the data.
POWER SUPPLY AND VOLTAGE REFERENCE
The ADAU1966 is designed for 3.3 V or 5 V analog and 2.5 V
digital supplies. To minimize noise pickup, the power supply
pins should be bypassed with 100 nF ceramic chip capacitors
placed as close to the pins as possible. A bulk aluminum
electrolytic capacitor of at least 22 μF should also be provided
for each rail on the same PC board as the codec. It is important
that the analog supply be as clean as possible.
TIME-DIVISION MULTIPLEXED (TDM) MODES
The ADAU1966 serial ports also have several different TDM
serial data modes. The ADAU1966 can support a single data
line TDM16, a dual data line (TDM8), a quad data line
(TDM4), or eight data lines (TDM2). The DLRCLK can be
operated in both single-cycle pulse mode and a 50% duty
cycle mode. Both 16 DBCLKs or 32 DBCLKs per channel are
selectable for each mode.
The ADAU1966 includes a 2.5 V regulator driver that requires
only an external pass transistor and bypass capacitors to make a
2.5 V regulator from a 5 V or 3.3 V supply. The VSUPPLY and
VSENSE pins should be decoupled with no more than 10 ꢀF, in
parallel with 100 nF high frequency bypassing. If the regulator
driver is not used, connect VSUPPLY and VDRIVE to GND
and leave VSENSE unconnected.
The I/O pins of the serial ports are defined according to the
serial mode that is selected. For a detailed description of the
function of each pin in TDM and stereo modes, see Table 23.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V or 5 V IOVDD supply and
are compatible with TTL and 3.3 V CMOS levels.
Rev. 0 | Page 19 of 52
ADAU1966
conversion, placing the resulting temperature data in the
THRM_TEMP_STAT register. In continuous operation
mode, the data conversion takes place at a rate set by Bits[7:6],
THRM_RATE, with a range of 0.5 sec to 4 sec between samples.
Faster rates are possible using the one-shot mode.
TEMPERATURE SENSOR
The ADAU1966 has an on-board temperature sensor that allows
the user to read the temperature of the silicon inside the part.
The temperature sensor readout has a range of −60°C to +140°C
in 1°C steps. The PDN_THRMSENS_CTRL_1 register controls
the settings of the sensor. The temperature sensor is powered on
by default and can be shut off by setting the TS_PDN[2] bit to
b1 in PDN_THRMSENS_CTRL_1. The temperature sensor can
be run in either continuous operation or one-shot mode. The
temperature sensor conversion mode is modified using Bit 5,
THRM_MODE; the default is THRM_MODE = 1, one-shot
mode. In one-shot mode, writing a 0 followed by writing a 1 to
Bit 4, THRM_GO, results in a single reset and temperature
Once a temperature conversion has been placed in the
THRM_TEMP_STAT register, the data can be translated into
degrees Celsius (°C) using the following steps:
1. Convert the binary or hexadecimal data read from
THRM_TEMP_STAT into decimal form.
2. Subtract 60 from the converted THRM_TEMP_STAT
data; this is the temperature of the silicon in °C.
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 0, SDATA_FMT = 1
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
MSB
I S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 0, SDATA_FMT = 0
LSB
SDATA
MSB
LSB
2
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL: SAI = 0, SDATA_FMT = 2 OR 3
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
TDM MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 1, 2, 3, OR 4
1/fS
Figure 15. Serial Audio Modes
Rev. 0 | Page 20 of 52
ADAU1966
tDBH
DBCLK
tDBL
tDLS
tDLH
DLRCLK
tDDS
DSDATAx
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
tDDH
tDDS
DSDATAx
2
I S-JUSTIFIED
MSB
MODE
tDDH
tDDS
tDDS
DSDATAx
RIGHT-JUSTIFIED
MODE
MSB
LSB
tDDH
tDDH
Figure 16. DAC Serial Timing
Table 23. Pin Function Changes in Different Serial Audio Interface Modes
Stereo Modes
(SAI = 0 or 1)
TDM4 Mode
(SAI = 2)
TDM8 Mode
(SAI = 3)
TDM16 Mode
(SAI = 4)
Signal
DSDATA1
Channel 1/Channel 2
data in
Channel 1 to Channel 4
data in
Channel 1 to Channel 8
data in
Channel 1 to Channel 16
data in
DSDATA2
Channel 3/Channel 4
data in
Channel 5/Channel 6
data in
Channel 7/Channel 8
data in
Channel 9/Channel 10
data in
Channel 11/Channel 12
data in
Channel 13/Channel 14
data in
Channel 15/Channel 16
data in
Channel 5 to Channel 8
data in
Channel 9 to Channel 12
data in
Channel 13 to Channel 16 Not used
data in
Not used
Not used
Not used
Not used
Channel 9 to Channel 16
data in
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
DSDATA3
DSDATA4
DSDATA5
Not used
Not Used
Not used
Not used
DSDATA6
DSDATA7
DSDATA8
DLRCLK
DLRCLK in/DLRCLK out
DBCLK in/DBCLK out
192 kHz
TDM frame sync in/
TDM frame sync out
TDM DBCLK in/TDM
DBCLK out
TDM frame sync in/
TDM frame sync out
TDM DBCLK in/TDM
DBCLK out
TDM frame sync in/
TDM frame sync out
TDM DBCLK in/
TDM DBCLK out
DBCLK
Maximum Sample Rate
192 kHz
96 kHz
48 kHz
Rev. 0 | Page 21 of 52
ADAU1966
To relax the requirement for the setup time of the ADAU1966
in cases of high speed TDM data transmission, the ADAU1966
can latch in the data using the falling edge of DBCLK; see the
BCLK_EDGE bit in the DAC_CTRL1 register. This effectively
dedicates the entire BCLK period to the setup time. This mode
is useful in cases where the source has a large delay time in the
serial data driver. Figure 18 shows this inverted DBCLK mode
of data transmission.
ADDITIONAL MODES
The ADAU1966 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit DBCLK. See
Figure 17 for an example of a DAC TDM data transmission mode
that does not require a high speed DBCLK or an external
MCLK. This configuration is applicable when the ADAU1966
master clock is generated by the PLL with the DLRCLK as the
PLL reference frequency.
DLRCLK
32 BITS
INTERNAL
DBCLK
DSDATAx
DLRCLK
INTERNAL
DBCLK
TDM-DSDATAx
Figure 17. Serial DAC Data Transmission in TDM Format Without DBCLK
(Applicable Only If PLL Locks to DLRCLK)
DLRCLK
DBCLK
DATA MUST BE VALID
AT THIS BCLK EDGE
MSB
DSDATAx
Figure 18. Inverted DBCLK Mode in DAC Serial Data Transmission
(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission)
Rev. 0 | Page 22 of 52
ADAU1966
REGISTER SUMMARY
Table 24. ADAU1966 Register Summary
Reg Name
Bits Bit 7
Bit 6
Bit 5
Bit 4
XTAL_SET
Bit 3
Bit 2
Bit 1
MCS
Bit 0
Reset RW
0x00 PLL_CLK_CTRL0
0x01 PLL_CLK_CTRL1
[7:0]
PLLIN
SOFT_RST
PLL_MUTE
RESERVED
PUP
0x00 RW
[7:0]
LOPWR_MODE
THRM_RATE
MCLKO_SEL
PLL_LOCK
TS_PDN
VREF_EN
PLL_PDN
CLK_SEL
0x2A RW
0xA0 RW
0x02 PDN_THRMSENS_CTRL_1 [7:0]
THRM_MODE THRM_GO
VREG_PDN
0x03 PDN_CTRL2
0x04 PDN_CTRL3
0x05 THRM_TEMP_STAT
0x06 DAC_CTRL0
0x07 DAC_CTRL1
0x08 DAC_CTRL2
0x09 DAC_MUTE1
0x0A DAC_MUTE2
0x0B DACMSTR_VOL
0x0C DAC01_VOL
0x0D DAC02_VOL
0x0E DAC03_VOL
0x0F DAC04_VOL
0x10 DAC05_VOL
0x11 DAC06_VOL
0x12 DAC07_VOL
0x13 DAC08_VOL
0x14 DAC09_VOL
0x15 DAC10_VOL
0x16 DAC11_VOL
0x17 DAC12_VOL
0x18 DAC13_VOL
0x19 DAC14_VOL
0x1A DAC15_VOL
0x1B DAC16_VOL
0x1C CM_SEL_PAD_STRGTH
0x1D DAC_POWER1
0x1E DAC_POWER2
0x1F DAC_POWER3
0x20 DAC_POWER4
[7:0] DAC08_PDN DAC07_PDN DAC06_PDN DAC05_PDN DAC04_PDN DAC03_PDN
[7:0] DAC16_PDN DAC15_PDN DAC14_PDN DAC13_PDN DAC12_PDN DAC11_PDN
DAC02_PDN DAC01_PDN 0x00 RW
DAC10_PDN DAC09_PDN 0x00 RW
[7:0]
[7:0]
TEMP
0x00
R
SDATA_FMT
SAI
FS
MMUTE
SAI_MS
0x01 RW
0x00 RW
[7:0] BCLK_GEN
[7:0] RESERVED
LRCLK_MODE LRCLK_POL
VREG_CTRL
SAI_MSB
RESERVED
BCLK_RATE
BCLK_EDGE
BCLK_TDMC DAC_POL
AUTO_MUTE_EN DAC_OSR
DE_EMP_EN 0x06 RW
[7:0] DAC08_MUTE DAC07_MUTE DAC06_MUTE DAC05_MUTE DAC04_MUTE DAC03_MUTE
[7:0] DAC16_MUTE DAC15_MUTE DAC14_MUTE DAC13_MUTE DAC12_MUTE DAC11_MUTE
DAC02_MUTE DAC01_MUTE 0x00 RW
DAC10_MUTE DAC09_MUTE 0x00 RW
0x00 RW
[7:0]
DACMSTR_VOL
DAC01_VOL
DAC02_VOL
DAC03_VOL
DAC04_VOL
DAC05_VOL
DAC06_VOL
DAC07_VOL
DAC08_VOL
DAC09_VOL
DAC10_VOL
DAC11_VOL
DAC12_VOL
DAC13_VOL
DAC14_VOL
DAC15_VOL
DAC16_VOL
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0]
0x00 RW
[7:0] RESERVED
RESERVED
PAD_DRV
RESERVED
RESERVED
RESERVED
CM_SEL
RESERVED
0x02 RW
0xAA RW
0xAA RW
0xAA RW
0xAA RW
[7:0]
[7:0]
[7:0]
[7:0]
DAC04_POWER
DAC08_POWER
DAC03_POWER
DAC02_POWER
DAC06_POWER
DAC10_POWER
DAC14_POWER
DAC01_POWER
DAC07_POWER
DAC11_POWER
DAC15_POWER
DAC05_POWER
DAC09_POWER
DAC13_POWER
DAC12_POWER
DAC16_POWER
Rev. 0 | Page 23 of 52
ADAU1966
REGISTER DETAILS
PLL AND CLOCK CONTROL 0 REGISTER
Address: 0x00, Reset: 0x00, Name: PLL_CLK_CTRL0
Table 25. Bit Descriptions for PLL_CLK_CTRL0
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
PLLIN
PLL Input Select. Selects between MCLKI/XTALI or DLRCLK as the input to
the PLL.
0x0
RW
00 MCLKI or XTALI
01 DLRCLK
10 Reserved
11 Reserved
[5:4]
XTAL_SET
XTAL Oscillator Setting. XTALO pin status.
0x0
RW
00 XTAL Oscillator Enabled
01 Reserved
10 Reserved
11 XTALO Off
3
SOFT_RST
MCS
Software Reset Control. This bit resets all circuitry inside the IC, except
I2C/SPI communications. All control registers are reset to default values,
except 0x00 and 0x01. The PLL_CLK_CTRLx registers do not change state.
Normal Operation
Device in Reset
0x0
0x0
RW
RW
0
1
[2:1]
Master Clock Select. MCLKI/XTALI pin functionality (PLL active), master
clock rate setting. The following values are for the fS rate window from 32
kHz to 48 kHz. See Table 14 for details when using other fS selections.
00 256 × fS MCLK (44.1 kHz or 48 kHz)
01 384 × fS MCLK (44.1 kHz or 48 kHz)
10 512 × fS MCLK (44.1 kHz or 48 kHz)
11 768 × fS MCLK (44.1 kHz or 48 kHz)
0
PUP
Master Power-Up Control. This bit must be set to 1 as the first register
write to power up the IC.
0x0
RW
0
1
Master Power-Down
Master Power-Up
Rev. 0 | Page 24 of 52
ADAU1966
PLL AND CLOCK CONTROL 1 REGISTER
Address: 0x01, Reset: 0x2A, Name: PLL_CLK_CTRL1
B7
B6
B5
B4
B3
B2
B1
B0
0
0
1
0
1
0
1
0
[7:6] LOPWR_MODE
[0] CLK_SEL
Global Power/Performance Adjust
00: I C Register Settings
DAC Clock Select
0: MCLK from PLL
2
01: Reserved
10: Lower Power
11: Lowest Power
1: MCLK from MCLKI or XTALI
[1] VREF_EN
Internal Voltage Reference Enable
0: Disabled
[5:4] MCLKO_SEL
MCLK Output Frequency
1: Enabled
00: MCLKO = 4 MHz to 6 MHz scaled by f
s
[2] PLL_LOCK
PLL Lock Indicator
0: PLL Not Locked
1: PLL Locked
01: MCLKO = 8 MHz to 12 MHz scaled by f
10: MCLKO = Buffered MCLKI
11: MCLKO Pin Disabled
s
[3] PLL_MUTE
PLL Automute Enable/Lock
0: No DAC Automute
1: DAC Automute on PLL Unlock
Table 26. Bit Descriptions for PLL_CLK_CTRL1
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
LOPWR_MODE
Global Power/Performance Adjust. These bits adjust the power
consumption and performance level for all 16 DAC channels at once. See
the Digital-to-Analog Converters (DACs) section for more details.
0x0
RW
00 I2C Register Settings
01 Reserved
10 Low Power
11 Lowest Power
[5:4]
MCLKO_SEL
PLL_MUTE
MCLK Output Frequency. Frequency selection for MCLKO pin. See the
Clock Signals section for more details.
00 MCLKO = 4 MHz to 6 MHz scaled by fS
01 MCLKO = 8 MHz to 12 MHz scaled by fS
10 MCLKO = Buffered MCLKI
0x2
0x1
RW
RW
11 MCLKO Pin Disabled
3
PLL Automute Enable/Lock. This bit enables the PLL lock automute
function.
0
1
No DAC Automute
DAC Automute on PLL Unlock
PLL Lock Indicator.
PLL Not Locked
2
1
PLL_LOCK
VREF_EN
0x0
0x1
R
0
1
PLL Locked
Internal Voltage Reference Enable. The internal voltage reference powers
the common mode for the ADAU1966. Disabling this bit allows the user to
drive the CM pin with an outside voltage source.
RW
0
1
Disabled
Enabled
0
CLK_SEL
DAC Clock Select. Selects between PLL or Direct MCLK mode.
MCLK from PLL
MCLK from MCLKI or XTALI
0x0
RW
0
1
Rev. 0 | Page 25 of 52
ADAU1966
BLOCK POWER-DOWN AND THERMAL SENSOR CONTROL 1 REGISTER
Address: 0x02, Reset: 0xA0, Name: PDN_THRMSENS_CTRL_1
Table 27. Bit Descriptions for PDN_THRMSENS_CTRL_1
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
THRM_RATE
Conversion Time Interval. When THERM_MODE = 0, the THERM_RATE bits
control the time interval between temperature conversions.
0x2
RW
00 4 sec/Conversion
01 0.5 sec/Conversion
10 1 sec/Conversion
11 2 sec/Conversion
5
4
THRM_MODE
THRM_GO
Continuous vs. One-Shot. Determines whether the temperature
conversions occur continuously or only when commanded. To perform
one-shot temperature conversions, set this bit to 1.
Continuous Operation
One-Shot Mode
0x1
0x0
RW
RW
0
1
One-Shot Conversion Mode. When in one-shot conversion mode,
THERM_MODE = 1, the THERM_GO bit must be set to 0 followed by a write
of 1. This sequence results in a single temperature conversion. The
temperature data is available 120 ms after writing a 1 to this bit.
0
1
Reset
Convert temperature
2
1
0
TS_PDN
Temperature Sensor Power-Down.
Temperature Sensor On
Temperature Sensor Power-Down
PLL Power-Down.
PLL Normal Operation
PLL Power-Down
0x0
0x0
0x0
RW
RW
RW
0
1
PLL_PDN
VREG_PDN
0
1
Voltage Regulator Power-Down.
Voltage Regulator Normal Operation
Voltage Regulator Power-Down
0
1
Rev. 0 | Page 26 of 52
ADAU1966
POWER-DOWN CONTROL 2 REGISTER
Address: 0x03, Reset: 0x00, Name: PDN_CTRL2
Table 28. Bit Descriptions for PDN_CTRL2
Bits
Bit Name
Settings
Description
Reset
Access
7
DAC08_PDN
Channel 8 Power-Down.
Normal Operation
Power-Down Channel 8
Channel 7 Power-Down.
Normal Operation
Power-Down Channel 7
Channel 6 Power-Down.
Normal Operation
Power-Down Channel 6
Channel 5 Power-Down.
Normal Operation
Power-Down Channel 5
Channel 4 Power-Down.
Normal Operation
Power-Down Channel 4
Channel 3 Power-Down.
Normal Operation
Power-Down Channel 2
Channel 2 Power-Down.
Normal Operation
Power-Down Channel 2
Channel 1 Power-Down.
Normal Operation
0x0
RW
0
1
6
5
4
3
2
1
0
DAC07_PDN
DAC06_PDN
DAC05_PDN
DAC04_PDN
DAC03_PDN
DAC02_PDN
DAC01_PDN
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Power-Down Channel 1
Rev. 0 | Page 27 of 52
ADAU1966
POWER-DOWN CONTROL 3 REGISTER
Address: 0x04, Reset: 0x00, Name: PDN_CTRL3
Table 29. Bit Descriptions for PDN_CTRL3
Bits
Bit Name
Settings
Description
Reset
Access
7
DAC16_PDN
Channel 16 Power-Down.
Normal Operation
Power-Down Channel 16
Channel 15 Power-Down.
Normal Operation
Power-Down Channel 15
Channel 14 Power-Down.
Normal Operation
Power-Down Channel 14
Channel 13 Power-Down.
Normal Operation
Power-Down Channel 13
Channel 12 Power-Down.
Normal Operation
Power-Down Channel 12
Channel 11 Power-Down.
Normal Operation
Power-Down Channel 11
Channel 10 Power-Down.
Normal Operation
Power-Down Channel 10
Channel 9 Power-Down.
Normal Operation
0x0
RW
0
1
6
5
4
3
2
1
0
DAC15_PDN
DAC14_PDN
DAC13_PDN
DAC12_PDN
DAC11_PDN
DAC10_PDN
DAC09_PDN
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Power-Down Channel 9
Rev. 0 | Page 28 of 52
ADAU1966
THERMAL SENSOR TEMPERATURE READOUT REGISTER
Address: 0x05, Reset: 0x00, Name: THRM_TEMP_STAT
Thermal Sensor Temperature Readout. −60°C to +140°C range, 1°C step size. Read this register and convert the hexadecimal or binary
TEMP value into decimal form; then subtract 60 from this decimal conversion. The result is the temperature in degrees Celsius.
Table 30. Bit Descriptions for THRM_TEMP_STAT
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
TEMP
Thermal Sensor Temperature Readout. −60°C to +140°C range, 1°C step
size. To convert TEMP code to temperature, use the equation (TEMP − 60).
0x00
R
Rev. 0 | Page 29 of 52
ADAU1966
DAC CONTROL 0 REGISTER
Address: 0x06, Reset: 0x01, Name: DAC_CTRL0
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
1
[7:6] SDATA_FMT
SDATA Format
[0] MMUTE
DAC Master Mute
0: Normal Operation
1: All Channels Muted
2
00: I S—1-BCLK Cycle Delay
01: Left-Justified—0-BCLK Cycle Delay
10: Right-Justified 24-bit Data—
8-BCLK Cycle Delay
11: Right-Justified 16-bit Data—
16-BCLK Cycle Delay
[2:1] FS
Sample Rate Select
00: 32 kHz/44.1kHz/48kHz
01: 64 kHz/88.2kHz/96kHz
10: 128 kHz/176.4kHz/192kHz
11: 128 kHz/176.4kHz/192kHz Low Propagation Delay
[5:3] SAI
Serial Audio Interface
2
000: Stereo (I S, LJ, RJ)
001: TDM2—Octal Line
010: TDM4—Quad Line
011: TDM8—Dual Line
100: TDM16—Single Line (48 kHz)
101: Reserved
110: Reserved
111: Reserved
Table 31. Bit Descriptions for DAC_CTRL0
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
SDATA_FMT
SDATA Format. Only used when SAI = 000.
00 I2S—1-BCLK Cycle Delay
0x0
RW
01 Left-Justified—0-BCLK Cycle Delay
10 Right-Justified 24-bit Data—8-BCLK Cycle Delay
11 Right-Justified 16-bit Data—16-BCLK Cycle Delay
[5:3]
SAI
Serial Audio Interface. When SAI = 000, the SDATA_FMT bits control stereo 0x0
SDATA format.
000 Stereo (I2S, LJ, RJ)
RW
001 TDM2—Octal Line
010 TDM4—Quad Line
011 TDM8—Dual Line
100 TDM16—Single Line (48 kHz)
101 Reserved
110 Reserved
111 Reserved
[2:1]
FS
Sample Rate Select.
0x0
0x1
RW
RW
00 32 kHz/44.1 kHz/48 kHz
01 64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 128 kHz/176.4 kHz/192 kHz Low Propagation Delay
DAC Master Mute.
0
MMUTE
0
1
Normal Operation
All Channels Muted
Rev. 0 | Page 30 of 52
ADAU1966
DAC CONTROL 1 REGISTER
Address: 0x07, Reset: 0x00, Name: DAC_CTRL1
Table 32. Bit Descriptions for DAC_CTRL1
Bits
Bit Name
Settings
Description
Reset
Access
7
BCLK_GEN
DBCLK Generation. When the PLL is locked to DLRCLK, it is possible to run
the ADAU1966 without an external DBCLK.
0x0
RW
0
1
Normal Operation—DBCLK
Internal DBCLK Generation
6
5
4
2
LRCLK_MODE
LRCLK_POL
SAI_MSB
DLRCLK Mode Select. Only Valid for TDM modes.
50% Duty Cycle DLRCLK
Pulse Mode
0x0
0x0
0x0
0x0
RW
RW
RW
RW
0
1
DLRCLK Polarity. Allows the swapping of data between channels.
Left/Odd channels are DLRCLK Low (Normal)
Left/Odd channels are DLRCLK High (Inverted)
MSB Position.
MSB First DSDATA
LSB First DSDATA
0
1
0
1
BCLK_RATE
DBCLK Rate. Number of DBCLK cycles per DLRCLK Frame. Used only for
generating DBCLK in Master Mode operation (SAI_MS = 1).
0
1
32 Cycles per Frame
16 Cycles per Frame
1
0
BCLK_EDGE
SAI_MS
DBCLK Active Edge. Adjust the polarity of the DBCLK leading edge.
Latch in Rising Edge
Latch in Falling Edge
0x0
0x0
RW
RW
0
1
Serial Interface Master. Both DLRCLK and DBCLK become master when
enabled.
0
1
DLRCLK/DBCLK Slave
DLRCLK/DBCLK Master
Rev. 0 | Page 31 of 52
ADAU1966
DAC CONTROL 2 REGISTER
Address: 0x08, Reset: 0x06, Name: DAC_CTRL2
Table 33. Bit Descriptions for DAC_CTRL2
Bits
Bit Name
Settings
Description
Reset
Access
[6:5]
VREG_CTRL
Voltage Regulator Control. Select the Regulator Output Voltage.
00 Regulator Out = 2.5 V
0x0
RW
01 Regulator Out = 2.75 V
10 Regulator Out = 3.0 V
11 Regulator Out = 3.3 V
4
BCLK_TDMC
DBCLK Rate in TDM Mode. Number of DBCLK cycles per channel slot when 0x0
in TDM mode.
RW
0
1
32 BCLK cycles/channel slot
16 BCLK cycles/channel slot
3
2
DAC_POL
DAC Output Polarity. This is a global switch of DAC polarity.
Noninverted DAC Output
Inverted DAC Output
0x0
0x1
RW
RW
0
1
AUTO_MUTE_EN
Automute Enable. Automatically mutes the DACs when 1024 consecutive
zero input samples are received. This is independent per channel.
0
1
Auto-Zero Input Mute Disabled
Auto-Zero Input Mute Enabled
DAC Oversampling Rate. OSR Selection.
256 × fS DAC Oversampling
128 × fS DAC Oversampling
De-Emphasis Enable.
1
0
DAC_OSR
0x1
0x0
RW
RW
0
1
DE_EMP_EN
0
1
No De-Emphasis/Flat
De-Emphasis Enabled
Rev. 0 | Page 32 of 52
ADAU1966
DAC INDIVIDUAL CHANNEL MUTES 1 REGISTER
Address: 0x09, Reset: 0x00, Name: DAC_MUTE1
Table 34. Bit Descriptions for DAC_MUTE1
Bits
Bit Name
Settings
Description
Reset
Access
7
DAC08_MUTE
DAC8 Soft Mute.
DAC8 Normal Operation
DAC8 Mute
0x0
RW
0
1
6
5
4
3
2
1
0
DAC07_MUTE
DAC06_MUTE
DAC05_MUTE
DAC04_MUTE
DAC03_MUTE
DAC02_MUTE
DAC01_MUTE
DAC7 Soft Mute.
DAC7 Normal Operation
DAC7 Mute
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
DAC6 Soft Mute.
DAC6 Normal Operation
DAC6 Mute
0
1
DAC5 Soft Mute.
DAC5 Normal Operation
DAC5 Mute
0
1
DAC4 Soft Mute.
DAC4 Normal Operation
DAC4 Mute
0
1
DAC3 Soft Mute.
DAC3 Normal Operation
DAC3 Mute
0
1
DAC2 Soft Mute.
DAC2 Normal Operation
DAC2 Mute
0
1
DAC1 Soft Mute.
DAC1 Normal Operation
DAC1 Mute
0
1
Rev. 0 | Page 33 of 52
ADAU1966
DAC INDIVIDUAL CHANNEL MUTES 2 REGISTER
Address: 0x0A, Reset: 0x00, Name: DAC_MUTE2
Table 35. Bit Descriptions for DAC_MUTE2
Bits
Bit Name
Settings
Description
Reset
Access
7
DAC16_MUTE
DAC16 Soft Mute.
DAC16 Normal Operation
DAC16 Mute
0x0
RW
0
1
6
5
4
3
2
1
0
DAC15_MUTE
DAC14_MUTE
DAC13_MUTE
DAC12_MUTE
DAC11_MUTE
DAC10_MUTE
DAC09_MUTE
DAC15 Soft Mute.
DAC15 Normal Operation
DAC15 Mute
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
DAC14 Soft Mute.
DAC14 Normal Operation
DAC14 Mute
0
1
DAC13 Soft Mute.
DAC13 Normal Operation
DAC13 Mute
0
1
DAC12 Soft Mute.
DAC12 Normal Operation
DAC12 Mute
0
1
DAC11 Soft Mute.
DAC11 Normal Operation
DAC11 Mute
0
1
DAC10 Soft Mute.
DAC10 Normal Operation
DAC10 Mute
0
1
DAC9 Soft Mute.
0
1
DAC9 Normal Operation
DAC9 Mute
Rev. 0 | Page 34 of 52
ADAU1966
MASTER VOLUME CONTROL REGISTER
Address: 0x0B, Reset: 0x00, Name: DACMSTR_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 36. Bit Descriptions for DACMSTR_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DACMSTR_VOL
Master Volume Control.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
DAC 1 VOLUME CONTROL REGISTER
Address: 0x0C, Reset: 0x00, Name: DAC01_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 37. Bit Descriptions for DAC01_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC01_VOL
DAC Volume Control Channel 1.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Rev. 0 | Page 35 of 52
ADAU1966
DAC 2 VOLUME CONTROL REGISTER
Address: 0x0D, Reset: 0x00, Name: DAC02_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 38. Bit Descriptions for DAC02_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC02_VOL
DAC Volume Control Channel 2.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
DAC 3 VOLUME CONTROL REGISTER
Address: 0x0E, Reset: 0x00, Name: DAC03_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 39. Bit Descriptions for DAC03_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC03_VOL
DAC Volume Control Channel 3.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Rev. 0 | Page 36 of 52
ADAU1966
DAC 4 VOLUME CONTROL REGISTER
Address: 0x0F, Reset: 0x00, Name: DAC04_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 40. Bit Descriptions for DAC04_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC04_VOL
DAC Volume Control Channel 4.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
DAC 5 VOLUME CONTROL REGISTER
Address: 0x10, Reset: 0x00, Name: DAC05_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 41. Bit Descriptions for DAC05_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC05_VOL
DAC Volume Control Channel 5.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Rev. 0 | Page 37 of 52
ADAU1966
DAC 6 VOLUME CONTROL REGISTER
Address: 0x11, Reset: 0x00, Name: DAC06_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 42. Bit Descriptions for DAC06_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC06_VOL
DAC Volume Control Channel 6.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
DAC 7 VOLUME CONTROL REGISTER
Address: 0x12, Reset: 0x00, Name: DAC07_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 43. Bit Descriptions for DAC07_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC07_VOL
DAC Volume Control Channel 7.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Rev. 0 | Page 38 of 52
ADAU1966
DAC 8 VOLUME CONTROL REGISTER
Address: 0x13, Reset: 0x00, Name: DAC08_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 44. Bit Descriptions for DAC08_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC08_VOL
DAC Volume Control Channel 8.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
DAC 9 VOLUME CONTROL REGISTER
Address: 0x14, Reset: 0x00, Name: DAC09_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 45. Bit Descriptions for DAC09_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC09_VOL
DAC Volume Control Channel 9.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Rev. 0 | Page 39 of 52
ADAU1966
DAC 10 VOLUME CONTROL REGISTER
Address: 0x15, Reset: 0x00, Name: DAC10_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 46. Bit Descriptions for DAC10_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC10_VOL
DAC Volume Control Channel 10.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
DAC 11 VOLUME CONTROL REGISTER
Address: 0x16, Reset: 0x00, Name: DAC11_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 47. Bit Descriptions for DAC11_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC11_VOL
DAC Volume Control Channel 11.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Rev. 0 | Page 40 of 52
ADAU1966
DAC 12 VOLUME CONTROL REGISTER
Address: 0x17, Reset: 0x00, Name: DAC12_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 48. Bit Descriptions for DAC12_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC12_VOL
DAC Volume Control Channel 12.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
DAC 13 VOLUME CONTROL REGISTER
Address: 0x18, Reset: 0x00, Name: DAC13_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 49. Bit Descriptions for DAC13_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC13_VOL
DAC Volume Control Channel 13.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Rev. 0 | Page 41 of 52
ADAU1966
DAC 14 VOLUME CONTROL REGISTER
Address: 0x19, Reset: 0x00, Name: DAC14_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 50. Bit Descriptions for DAC14_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC14_VOL
DAC Volume Control Channel 14.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
DAC 15 VOLUME CONTROL REGISTER
Address: 0x1A, Reset: 0x00, Name: DAC15_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 51. Bit Descriptions for DAC15_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC15_VOL
DAC Volume Control Channel 15.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
Rev. 0 | Page 42 of 52
ADAU1966
DAC 16 VOLUME CONTROL REGISTER
Address: 0x1B, Reset: 0x00, Name: DAC16_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 52. Bit Descriptions for DAC16_VOL
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC16_VOL
DAC Volume Control Channel 16.
0x00
RW
00000000 0 dB (default)
00000001 −0.375 dB
00000010 −0.750 dB
11111110 −95.250 dB
11111111 −95.625 dB
COMMON-MODE AND PAD STRENGTH REGISTER
Address: 0x1C, Reset: 0x02, Name: CM_SEL_PAD_STRGTH
Table 53. Bit Descriptions for CM_SEL_PAD_STRGTH
Bits
Bit Name
Settings
Description
Reset
Access
5
PAD_DRV
Output Pad Drive Strength Control. Pad strength is stated for IOVDD = 5 V. 0x0
RW
0
1
4 mA Drive for All Pads
8 mA Drive for All Pads
1
CM_SEL
Common Mode Generation Selection.
Fixed 3.3 V AVDD CM Generation
Fixed 5 V AVDD CM Generation
0x1
RW
0
1
Rev. 0 | Page 43 of 52
ADAU1966
DAC POWER ADJUST 1 REGISTER
Address: 0x1D, Reset: 0xAA, Name: DAC_POWER1
Table 54. Bit Descriptions for DAC_POWER1
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
DAC04_POWER
DAC Power Control Channel 4.
0x2
RW
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 3.
00 Low Power
[5:4]
[3:2]
[1:0]
DAC03_POWER
DAC02_POWER
DAC01_POWER
0x2
0x2
0x2
RW
RW
RW
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 2.
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 1.
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
Rev. 0 | Page 44 of 52
ADAU1966
DAC POWER ADJUST 2 REGISTER
Address: 0x1E, Reset: 0xAA, Name: DAC_POWER2
Table 55. Bit Descriptions for DAC_POWER2
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
DAC08_POWER
DAC Power Control Channel 8.
0x2
RW
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 7.
00 Low Power
[5:4]
[3:2]
[1:0]
DAC07_POWER
DAC06_POWER
DAC05_POWER
0x2
0x2
0x2
RW
RW
RW
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 6.
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 5.
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
Rev. 0 | Page 45 of 52
ADAU1966
DAC POWER ADJUST 3 REGISTER
Address: 0x1F, Reset: 0xAA, Name: DAC_POWER3
Table 56. Bit Descriptions for DAC_POWER3
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
DAC12_POWER
DAC Power Control Channel 12.
0x2
RW
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 11.
00 Low Power
[5:4]
[3:2]
[1:0]
DAC11_POWER
DAC10_POWER
DAC09_POWER
0x2
0x2
0x2
RW
RW
RW
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 10.
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 9.
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
Rev. 0 | Page 46 of 52
ADAU1966
DAC POWER ADJUST 4 REGISTER
Address: 0x20, Reset: 0xAA, Name: DAC_POWER4
Table 57. Bit Descriptions for DAC_POWER4
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
DAC16_POWER
DAC Power Control Channel 16.
0x2
RW
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 15.
00 Low Power
[5:4]
[3:2]
[1:0]
DAC15_POWER
DAC14_POWER
DAC13_POWER
0x2
0x2
0x2
RW
RW
RW
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 14.
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
DAC Power Control Channel 13.
00 Low Power
01 Lowest Power
10 Best Performance
11 Good Performance
Rev. 0 | Page 47 of 52
ADAU1966
Table 58. Volume Table
Binary Value
Volume Attenuation (dB)
Binary Value
00101110
00101111
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111
01000000
01000001
01000010
01000011
01000100
01000101
01000110
01000111
01001000
01001001
01001010
01001011
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
01010110
01010111
01011000
01011001
01011010
01011011
Volume Attenuation (dB)
−17.25
−17.625
−18
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
0
−0.375
−0.75
−1.125
−1.5
−18.375
−18.75
−19.125
−19.5
−1.875
−2.25
−2.625
−3
−19.875
−20.25
−20.625
−21
−3.375
−3.75
−4.125
−4.5
−21.375
−21.75
−22.125
−22.5
−4.875
−5.25
−5.625
−6
−22.875
−23.25
−23.625
−24
−6.375
−6.75
−7.125
−7.5
−24.375
−24.75
−25.125
−25.5
−7.875
−8.25
−8.625
−9
−25.875
−26.25
−26.625
−27
−9.375
−9.75
−10.125
−10.5
−27.375
−27.75
−28.125
−28.5
−10.875
−11.25
−11.625
−12
−28.875
−29.25
−29.625
−30
−12.375
−12.75
−13.125
−13.5
−30.375
−30.75
−31.125
−31.5
−13.875
−14.25
−14.625
−15
−31.875
−32.25
−32.625
−33
−15.375
−15.75
−16.125
−16.5
−33.375
−33.75
−34.125
−16.875
Rev. 0 | Page 48 of 52
ADAU1966
Binary Value
01011100
01011101
01011110
01011111
01100000
01100001
01100010
01100011
01100100
01100101
01100110
01100111
01101000
01101001
01101010
01101011
01101100
01101101
01101110
01101111
01110000
01110001
01110010
01110011
01110100
01110101
01110110
01110111
01111000
01111001
01111010
01111011
01111100
01111101
01111110
01111111
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111
10001000
10001001
10001010
Volume Attenuation (dB)
−34.5
Binary Value
10001011
10001100
10001101
10001110
10001111
10010000
10010001
10010010
10010011
10010100
10010101
10010110
10010111
10011000
10011001
10011010
10011011
10011100
10011101
10011110
10011111
10100000
10100001
10100010
10100011
10100100
10100101
10100110
10100111
10101000
10101001
10101010
10101011
10101100
10101101
10101110
10101111
10110000
10110001
10110010
10110011
10110100
10110101
10110110
10110111
10111000
10111001
Volume Attenuation (dB)
−52.125
−52.5
−34.875
−35.25
−35.625
−36
−52.875
−53.25
−53.625
−54
−36.375
−36.75
−37.125
−37.5
−54.375
−54.75
−55.125
−55.5
−37.875
−38.25
−38.625
−39
−55.875
−56.25
−56.625
−57
−39.375
−39.75
−40.125
−40.5
−57.375
−57.75
−58.125
−58.5
−40.875
−41.25
−41.625
−42
−58.875
−59.25
−59.625
−60
−42.375
−42.75
−43.125
−43.5
−60.375
−60.75
−61.125
−61.5
−43.875
−44.25
−44.625
−45
−61.875
−62.25
−62.625
−63
−45.375
−45.75
−46.125
−46.5
−63.375
−63.75
−64.125
−64.5
−46.875
−47.25
−47.625
−48
−64.875
−65.25
−65.625
−66
−48.375
−48.75
−49.125
−49.5
−66.375
−66.75
−67.125
−67.5
−49.875
−50.25
−50.625
−51
−67.875
−68.25
−68.625
−69
−51.375
−51.75
−69.375
Rev. 0 | Page 49 of 52
ADAU1966
Binary Value
10111010
10111011
10111100
10111101
10111110
10111111
11000000
11000001
11000010
11000011
11000100
11000101
11000110
11000111
11001000
11001001
11001010
11001011
11001100
11001101
11001110
11001111
11010000
11010001
11010010
11010011
11010100
11010101
11010110
11010111
11011000
11011001
11011010
11011011
11011100
Volume Attenuation (dB)
−69.75
−70.125
−70.5
Binary Value
11011101
11011110
11011111
11100000
11100001
11100010
11100011
11100100
11100101
11100110
11100111
11101000
11101001
11101010
11101011
11101100
11101101
11101110
11101111
11110000
11110001
11110010
11110011
11110100
11110101
11110110
11110111
11111000
11111001
11111010
11111011
11111100
11111101
11111110
11111111
Volume Attenuation (dB)
−82.875
−83.25
−83.625
−84
−70.875
−71.25
−71.625
−72
−84.375
−84.75
−85.125
−85.5
−72.375
−72.75
−73.125
−73.5
−85.875
−86.25
−86.625
−87
−73.875
−74.25
−74.625
−75
−87.375
−87.75
−88.125
−88.5
−75.375
−75.75
−76.125
−76.5
−88.875
−89.25
−89.625
−90
−76.875
−77.25
−77.625
−78
−90.375
−90.75
−91.125
−91.5
−78.375
−78.75
−79.125
−79.5
−91.875
−92.25
−92.625
−93
−79.875
−80.25
−80.625
−81
−93.375
−93.75
−94.125
−94.5
−81.375
−81.75
−82.125
−82.5
−94.875
−95.25
−95.625
Rev. 0 | Page 50 of 52
ADAU1966
OUTLINE DIMENSIONS
16.00
BSC SQ
0.75
0.60
0.45
1.60
MAX
80
61
60
1
SEATING
PLANE
PIN 1
14.00
BSC SQ
TOP VIEW
(PINS DOWN)
10°
6°
2°
1.45
1.40
1.35
0.20
0.09
7°
VIEW A
20
41
3.5°
0°
40
21
0.15
0.05
SEATING
PLANE
0.10 MAX
COPLANARITY
0.65
BSC
0.38
0.32
0.22
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 19. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
ADAU1966WBSTZ
ADAU1966WBSTZRL
EVAL-ADAU1966Z
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
ST-80-2
ST-80-2
80-Lead LQFP
80-Lead LQFP, 13”Tape and Reel
Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADAU1966W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. 0 | Page 51 of 52
ADAU1966
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09434-0-9/11(0)
Rev. 0 | Page 52 of 52
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