AD9823KRUZ [ADI]
Correlated Double Sampler (CDS);
| 型号： | AD9823KRUZ |
| 厂家： | 
ADI |
| 描述： | Correlated Double Sampler (CDS) CD 光电二极管 |
| 文件： | 总9页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Correlated Double Sampler (CDS)
AD9823
FEATURES
FUNCTIONAL BLOCK DIAGRAM
40 MHz correlated double sampler (CDS)
Fixed 3.5 dB CDS gain
AD9823
3.5dB FIXED GAIN
Low noise optical black clamp circuit
3 V single-supply operation
14-lead TSSOP package
OUTPUT
BUFFER
CDS
CCDIN
OUTPUT
BYP2
CLP
APPLICATIONS
Digital still cameras
Digital video camcorders
CCTV cameras
CLP
OUTPUT
BUFFER
REFOUT
PC cameras
Portable CCD imaging devices
VDD
GND
INTERNAL
REFERENCE
INTERNAL
TIMING
BYP1
BYP3
SHP
SHD
Figure 1. Functional Block Diagram
PRODUCT DESCRIPTION
The AD9823 is a correlated double sampler for digital camera
applications. It features a 40 MHz CDS amplifier with 3.5 dB of
fixed gain, an internal voltage reference supply, and timing
control for the SHP and SHD sampling clocks. Output buffers
are also included, providing drive strength for PCB traces and
direct connection to an image signal processor such as the
AD9821.
The AD9823 is ideal for applications that need to place the CDS
and VGA/ADC circuits on separate PC boards. The “pseudo
differential” outputs of the AD9823 provide good signal
integrity when interfaced with the differential input AD9821.
The AD9823 operates from a single 3 V power supply, typically
dissipates 50 mW, and is packaged in a 14-lead TSSOP package.
Rev. 0
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD9823* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DOCUMENTATION
Data Sheet
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• AD9823: Correlated Double Sampler (CDS) Data Sheet
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• MS-2210: Designing Power Supplies for High Speed ADC
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AD9823
TABLE OF CONTENTS
Specifications..................................................................................... 3
General Specifications ................................................................. 3
Analog Specifications................................................................... 3
Digital Specifications ................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics ...............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
SHP and SHD Timing ..................................................................6
Outline Dimensions..........................................................................8
Ordering Guide .............................................................................8
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 8
AD9823
SPECIFICATIONS
GENERAL SPECIFICATIONS
Table 1.
Parameter
Min
Typ
Max
Unit
Temperature Range
Operating
Storage
Power Supply Voltage
Power Consumption: fSAMP = 40 MHz, VDD = 3.0 V
Maximum Clock Rate
Minimum Clock Rate
–25
–65
2.7
+85
+150
3.6
°C
°C
V
mW
MHz
MHz
50
5
40
ANALOG SPECIFICATIONS
Table 2. TMIN to TMAX, VDD = 3.0 V, fSAMP = 40 MHz, unless otherwise noted.
Parameter
Min
Typ
Max
Unit
Notes
Analog Input (CCDIN)
Max Input Range Before Saturation1
Allowable CCD Reset Transient1
Max CCD Black Pixel Amplitude1
Gain
850
500
100
3.5
mV p-p
mV
mV
2.5
4.5
dB
Nonlinearity, 500 mV Input
Input Referred Noise
Clamp Time Constant
Analog Outputs
1.0
100
190
%
µV rms
µsec
Max deviation from ideal straight line
Output noise divided by 3.5 dB gain
0.1 µF BYP2 capacitor (proportional to capacitor value)
Typical Data Out Signal Range
REFOUT Voltage Level
0.5
1.5
V
V
0.5 V corresponds to black level
Fixed dc reference for signal output
0.5
1 Input signal characteristics defined as follows:
500mV TYP
RESET TRANSIENT
100mV TYP
OPTICAL BLACK PIXEL
850mV TYP
INPUT SIGNAL RANGE
All specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Logic Inputs (SHP, SHD, CLP)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.1
V
V
µA
µA
pF
0.6
10
10
10
Rev. 0 | Page 3 of 8
AD9823
TIMING SPECIFICATIONS
Table 4. TMIN to TMAX, VDD = 3.0 V, fSAMP = 40 MHz, unless otherwise noted.
Parameter (See Figure 3)
Symbol
Min
Typ
Max
Unit
Sample Clocks
SHP, SHD Clock Period
SHP Pulse Width
SHD Pulse Width
CLP Pulse Width1
SHP Rising Edge to SHD Rising Edge
SHD Rising Edge to SHP Rising Edge
Internal Clock Delay
tCP
25
5
5
4
12.0
12.0
ns
ns
ns
pixels
ns
tSHP
tSHD
tCOB
tS1
tS2
tID
6.25
6.25
10
12.5
12.5
3.0
ns
ns
Recommended Data CLK Timing (for AD9821)
tREC
4.5
ns
1 Minimum CLP pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to
change without notice.
Rev. 0 | Page 4 of 8
AD9823
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
With Respect To
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
Max
Unit
V
V
V
V
V
V
°C
°C
VDD
SHP, SHD
BYP1, BYP2, BYP3
CCDIN
DATAOUT, REFOUT
CLP
GND
GND
GND
GND
GND
GND
3.9
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
150
Junction Temperature
Lead Temperature (10 sec)
350
THERMAL CHARACTERISTICS
Thermal Resistance
14-Pin, TSSOP Package
θJA = 89.2°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 8
AD9823
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SHP
SHD
GND
CLP
NC
1
2
3
4
5
6
7
14
13
12
AD9823
VDD
TOP VIEW
REFOUT
DATAOUT
GND
11 CCDIN
10 NC
(Not to Scale)
9
8
BYP3
BYP2
BYP1
NC = NO CONNECT
Figure 2. Pin Configurations
Table 6. Pin Function Descriptions
Pin Number
Name
Type1
Description
1
2
3
CLP
NC
VDD
DI
NC
P
Input Clamp Clock Input (active low, not latched internally).
No connection should be connected to GND or VDD.
Analog Supply.
4
5
6
REFOUT
DATAOUT
GND
AO
AO
P
Output Reference Level.
Output Data Signal.
Analog Ground.
7
8
9
10
11
12
13
14
BYP1
BYP2
BYP3
NC
CCDIN
GND
AO
AO
AO
NC
AI
P
DI
DI
Internal Bias Level Decoupling.
Internal Bias Level Decoupling.
Internal Bias Level Decoupling.
No connection should be connected to GND or VDD.
CCD Input.
Analog Ground.
CDS Sampling Clock Input (For CCD Data Level).
CDS Sampling Clock Input (For CCD Ref Level).
SHD
SHP
1AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power, NC = No Connect.
SHP AND SHD TIMING
CCD
SIGNAL
N
N+1
N+2
N+9
N+10
tID
tID
tCP
SHP
tSHD
tSHP
tS1
tS2
SHD
DATAOUT
DATACLK
(FOR AD9821)
tREC
Figure 3. SHP and SHD Timing
Rev. 0 | Page 6 of 8
AD9823
HORIZONTAL
BLANKING
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
DUMMY PIXELS
EFFECTIVE PIXELS
CCD
SIGNAL
CLP
Figure 4. CLP Timing
3V
ANALOG
SUPPLY
4.7µF
0.1µF
CLP
NC
SHP
CLP
SHP
SHD
1
2
3
4
5
6
7
14
13
12
SHD
GND
CCDIN
NC
VDD
AD9823
TOP VIEW
(Not to Scale)
0.1µF
REFOUT
(CONNECT TO VIN– ON AD9821)
REFOUT
CCDIN
11
10
9
DATAOUT
GND
DATAOUT
(CONNECT TO VIN+ ON AD9821)
BYP3
BYP1
BYP2
8
0.1µF
0.1µF
0.1µF
NC = NO CONNECT
Figure 5. AD9823 Circuit Configuration
3V
ANALOG SUPPLY
0.1µF
1.0µF
1.0µF
3
SERIAL
INTERFACE
3V
3V
ANALOG SUPPLY ANALOG SUPPLY
48 47 46 45 44 43 42 41 40 39 38 37
CLP
SHP
SHD
D0
1
TEST
AVSS
TEST
AVDD2
BYP1
VIN–
36
35
34
33
32
31
30
29
28
27
26
25
PIN 1
D1
2
IDENTIFIER
0.1µF
0.1µF
D2
3
CLP
SHP
4.7µF
0.1µF
1
2
3
4
5
6
7
14
13
D3
NC
VDD
SHD
4
D4
5
GND
CCDIN
NC
AD9823 12
AD9821
OUTPUT
FROM
CCD
D5
IMAGER INPUT, NEGATIVE
IMAGER INPUT, POSITIVE
REFOUT
DATAOUT
GND
0.1µF
6
11
TOP VIEW
D6
7
TOP VIEW
(Not to Scale
VIN+
(Not to Scale)
10
D7
TEST
TEST
AVDD1
AVSS
AVSS
BYP3
BYP2
8
9
8
D8
9
BYP1
D9
10
0.1µF
0.1µF
D10
11
0.1µF
3V
(MSB) D11
ANALOG SUPPLY
12
0.1µF
4.7µF
12
DATA
OUTPUTS
13 14 15 16 17 18 19 20 21 22 23 24
3V
NC = INTERNALLY NOT CONNECTED
DRIVER
SUPPLY
0.1µF
3
CLOCK
INPUTS
0.1µF
3V
ANALOG SUPPLY
Figure 6. Circuit Configuration with the AD9821 12-Bit Image Signal Processor
Rev. 0 | Page 7 of 8
AD9823
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65
BSC
1.05
1.00
0.80
0.20
0.09
1.20
MAX
0.75
0.60
0.45
8°
0°
0.15
0.05
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 7. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9823BRUZ1
Temperature Range
Package Description
Package Option
–25°C to +85°C
TSSOP
RU-14
1Z = Pb-free part.
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners..
C04538-0-11/03(0)
Rev. 0 | Page 8 of 8
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