AD9816JS [ADI]
Complete 12-Bit 6 MSPS CCD/CIS Signal Processor; 完整的12位6 MSPS CCD / CIS信号处理器
| 型号： | AD9816JS |
| 厂家： | 
ADI |
| 描述： | Complete 12-Bit 6 MSPS CCD/CIS Signal Processor |
| 文件： | 总16页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete 12-Bit 6 MSPS
CCD/CIS Signal Processor
a
AD9816
PRODUCT DESCRIPTION
FEATURES
The AD9816 is a complete analog signal processor for CCD
and CIS applications. Included is all the necessary circuitry to
perform three-channel conditioning and sampling for a variety
of imaging applications.
12-Bit 6 MSPS A/D Converter
No Missing Codes Guaranteed
3-Channel or 1-Channel Operation
Correlated Double Sampling
8-Bit Programmable Gain
8-Bit Offset Adjustment
PGA Output Monitor
Input Clamp Circuitry
Internal Voltage Reference
3-Wire Serial Interface
+3.3 V/+5 V Digital Output Compatibility
44-Lead MQFP Package
The signal chain consists of an input clamp, correlated double
sampler (CDS), offset adjust DAC, programmable gain ampli-
fier and a 12-bit A/D converter. The CDS and input clamp may
be disabled for CIS applications.
The internal registers are programmed using a 3-wire serial
interface and provide adjustment of the gain, offset and operat-
ing mode.
Low Power CMOS: 420 mW Typ
The AD9816 operates from a +5 V supply, typically consumes
420 mW of power and is packaged in a 44-lead MQFP.
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
CLAMP/CDS
DVDD DVSS DRVDD DRVSS
CAPT
CAPB
CML PGAOUT VREF
1X–6X
PGA
AD9816
؎100mV
+
VINR
VING
OEB
BANDGAP
REFERENCE
DAC
12-BIT
ADC
12
DOUT
11:0
+
MUX
CLAMP/CDS
CLAMP/CDS
PGA
MUX
REGISTER
DAC
+
CONFIGURATION
REGISTER
PGA
VINB
8
SCLK
8
DAC
DIGITAL
SLOAD
SDATA
R
G
B
R
G
B
CONTROL
PORT
GAIN
REGISTERS
OFFSET
REGISTERS
OFFSET
CDSCLK1 CDSCLK2
ADCCLK
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
AD9816–SPECIFICATIONS
(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +5.0 V, CDS Mode, fADCCLK = 6 MHz,
fCDSCLK1 = 2 MHz, fCDSCLK2 = 2 MHz, PGA Gain = 1, Input Range = 3 V p-p, Input Capacitor = 1200 pF, unless otherwise noted)
ANALOG SPECIFICATIONS
Parameter
AD9816
AD9816-80010
Units
MAXIMUM CONVERSION RATE
3-Channel Mode with CDS
1-Channel Mode with CDS
6
6
6
6
MSPS min
MSPS min
ACCURACY (Includes Entire Signal Path)
ADC Resolution
12
12
Bits min
Differential Nonlinearity (DNL)
±0.4
±1.0
12
±1.5
±4.0
2.4
±0.75
LSB typ
LSB max
Bits Guaranteed
LSB typ
LSB max
No Missing Codes
Integral Nonlinearity (INL)
±2.5
Offset Error
Gain Error1
% FSR max
% FSR max
4.3
ANALOG INPUTS
Input Voltage Range2
0
3
0
3
V min
V max
V min
V max
pF typ
nA typ
Input Limits3
AVSS – 0.3
AVDD + 0.3
10
10
AVSS – 0.3
AVDD + 0.3
10
10
Input Capacitance
Input Current
AMPLIFIERS
PGA Gain Range
1
1
V/V min
V/V max
Steps
mV min
mV max
Steps
5.98
256
–100
+100
256
5.98
256
–100
+100
256
PGA Gain Resolution
Offset Range
Offset Resolution
NOISE AND CROSSTALK
Total Output Noise at Min PGA Gain4
Total Output Noise at Max PGA Gain4
Channel-to-Channel Crosstalk5
0.5
0.8
1
LSB rms typ
LSB rms typ
LSB max
POWER SUPPLY REJECTION
(AVDD = +5 V/±0.25 V)
0.28
% FSR max
VOLTAGE REFERENCE
0.75 V Reference Tolerance (@ +25°C)
1.5 V Reference Tolerance (@ +25°C)
±20
±34
mV max
mV max
TEMPERATURE RANGE
Operating
0
+70
0
+70
°C min
°C max
POWER SUPPLIES
Operating Voltages
AVDD, DVDD
+4.75
+5.25
+3.3
+5.25
84
+4.75
+5.25
+3.3
+5.25
84
V min
V max
V min
V max
mA typ
DRVDD
Operating Current
POWER CONSUMPTION
420
500
420
500
mW typ
mW max
NOTES
1Includes internal voltage reference error.
2Input voltage range is the linear region over which the input signal can be processed by the input stage of the AD9816.
3The input limits are defined as the maximum tolerable input voltage into the AD9816. This is not intended to be the linear input range of the device. Signals beyond
the input limits will turn on the overvoltage protection diodes.
4The total output noise is measured with the inputs of the AD9816 grounded.
5The channel-to-channel crosstalk is measured with one input grounded, and the other two inputs at full scale.
Specifications subject to change without notice.
–2–
REV. A
AD9816
(TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +5.0 V, fADCCLK = 6 MHz,
fCDSCLK1 = 2 MHz, fCDSCLK2 = 2 MHz, CL = 10 pF unless otherwise noted)
DIGITAL SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Units
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
3.5
V
V
µA
µA
pF
1.0
10
10
10
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
VOH
VOL
IOH
IOL
4.5
V
V
µA
µA
0.1
50
50
Specifications subject to change without notice.
(TMIN to TMAX with DVDD = +5.0 V, DRVDD = +5.0 V)
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Units
CLOCK PARAMETERS
3-Channel Conversion Rate
1-Channel Conversion Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
tCRA
tCRB
tADCLK
tC1
500
160
80
20
60
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CDSCLK2 Pulsewidth
tC2
2 tADCLK – 30
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
tC1C2
tADC2
tC2AD
tC2C1
tAD
0
30
10
10
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Set-Up Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Set-Up Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
fSCLK
tLS
tLH
tDS
tDH
tRDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
DATA OUTPUT
Output Delay
tOD
tDV
tHZ
13
15
5
ns
ns
ns
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
3 (Fixed)
ADCCLK Cycles
REV. A
–3–
AD9816
PIXEL (n+1)
PIXEL (n+m)
PIXEL n (R, G, B)
PIXEL (n+2)
ANALOG
INPUTS
tAD
tAD
tCRA
tC2C1
tC1
CDSCLK1
CDSCLK2
tC1C2
tC2
tADCLK
tADC2
tC2AD
ADCCLK
tADCLK
tOD
OUTPUT
DATA
D11:D0
R(n–2)
G(n–2)
B(n–2)
R(n–1)
R(n)
G(n–1)
B(n–1)
B(n)
R(n)
G(n)
B(n)
R(n+1)
R(n+2)
PGAOUT_T
PGAOUT_C
G(n–1)
B(n–1)
G(n)
R(n+1)
G(n+1)
B(n+1)
Figure 1. 3-Channel CDS Mode Timing
PIXEL n (R, G, B)
PIXEL (n+1)
PIXEL (n+2)
PIXEL (n+m)
ANALOG
INPUTS
tAD
tC2
tCRA
CDSCLK2
ADCCLK
tADC2
tC2AD
tADCLK
tADCLK
tOD
OUTPUT
DATA
D11:D0
R(n–2)
G(n–2)
B(n–2)
B(n–1)
R(n–1)
R(n)
G(n–1)
B(n–1)
R(n)
G(n)
B(n)
R(n+1)
R(n+2)
PGAOUT_T
PGAOUT_C
B(n+1)
G(n)
B(n)
R(n+1)
G(n+1)
G(n–1)
Figure 2. 3-Channel SHA Mode Timing
ANALOG
INPUTS
PIXEL n
PIXEL (n+m)
PIXEL (n+1)
PIXEL (n+2)
tAD
tAD
tC1
tCRB
tC2C1
CDSCLK1
CDSCLK2
tC2
tC1C2
tADC2
tC2AD
ADCCLK
tOD
tADCLK
tADCLK
OUTPUT
DATA
PIXEL (n–4)
PIXEL (n–3)
PIXEL (n–2)
PIXEL (n–1)
PIXEL (n+2)
D11:D0
PGAOUT_T
PGAOUT_C
PIXEL (n–1)
PIXEL n
PIXEL (n+1)
Figure 3. 1-Channel CDS Mode Timing
–4–
REV. A
AD9816
PIXEL n
PIXEL (n+1)
PIXEL (n+2)
PIXEL (n+m)
tAD
ANALOG
INPUTS
tC2
tCRB
CDSCLK2
ADCCLK
tADC2
tC2AD
tOD
tADCLK
tADCLK
OUTPUT
DATA
PIXEL (n–4)
PIXEL (n–3)
PIXEL (n–2)
PIXEL (n–1)
PIXEL (n+2)
ϽD11:D0Ͼ
PGAOUT_T
PGAOUT_C
PIXEL (n–1)
PIXEL n
PIXEL (n+1)
Figure 4. 1-Channel SHA Mode Timing
EFFECTIVE PIXELS
OPTICAL BLACK OR DUMMY PIXELS
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
Figure 5. Line Clamp Timing for 3-Channel CDS Mode
ADCCLK
tOD
OUTPUT
DATA
ϽD11:D0Ͼ
tHZ
tDV
OEB
Figure 6. Output Enable Timing
REV. A
–5–
AD9816
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter
To
Min Max
Units
VIN, VREF
PGA Outputs
Clock Inputs
AVDD
DVDD
DRVDD
AVSS
AVSS
DVSS
AVSS
DVSS
DRVSS
DVSS
DRVSS
DVSS
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 DVDD + 0.3
–0.5 +6.5
–0.5 +6.5
–0.5 +6.5
V
V
V
V
V
V
V
V
V
AVSS
–0.3 +0.3
Digital Outputs
Digital Inputs
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
–0.3 DRVDD + 0.3
–0.3 DVDD + 0.3
+150
°
°
C
C
–65
+150
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD9816JS
AD9816JS-80010
AD9816-EB
0°C to +70°C
0°C to +70°C
44-Lead MQFP (Metric) Plastic Quad Flatpack
44-Lead MQFP (Metric) Plastic Quad Flatpack
Evaluation Board
S-44
S-44
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9816 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. A
AD9816
PIN FUNCTION DESCRIPTIONS
Pin Name Type Description
PIN CONFIGURATION
Pin
1
AVDD
AVSS
CAPT
CAPB
VREF
CML
P
+5 V Analog Supply.
2
P
Analog Ground.
44 43 42 41 40 39 38 37 36 35 34
3, 4
5, 6
7
AO
AO
AO
AO
AI
P
Reference Decoupling.
Reference Decoupling.
Internal Reference Output.
Internal Bias Level.
PIN 1
IDENTIFIER
33
1
2
AVDD
AVSS
DRVSS
32
DB5
31
3
DB4
CAPT
CAPT
CAPB
CAPB
VREF
8
4
30
DB3
9
VINR
AVSS
VING
AVSS
VINB
AVSS
AVDD
OFFSET
Analog Input, Red Channel.
Analog Ground.
5
29
DB2
AD9816
TOP VIEW
(Not to Scale)
28
6
DB1
10
11
12
13
14
15
16
27
7
DB0 (LSB)
AI
P
Analog Input, Green Channel.
Analog Ground.
26
8
CML
DVSS
25
VINR
9
SLOAD
24
10
11
AVSS
VING
SDATA
AI
P
Analog Input, Blue Channel.
Analog Ground.
23
SCLK
12 13 14 15 16 17 18 19 20 21 22
P
+5 V Analog Supply.
AI
Clamp bias level in CDS mode.
Offset adjustment input in SHA
mode.
NC = NO CONNECT
17
18
CDSCLK1
CDSCLK2
DI
DI
CDS Reset Level Sampling
Clock.
CDS Data Level Sampling
Clock.
19
20
21
22
23
24
25
26
27
ADCCLK
DVSS
DI
P
A/D Converter Sampling Clock.
Digital Ground.
DVDD
NC
P
+5 V Digital Supply.
No Connect.
SCLK
SDATA
SLOAD
DVSS
DI
DIO
DI
P
Clock Input for Serial Interface.
Serial Data Input-Output.
Load Pulse for Serial Interface.
Digital Ground.
DB0
DO
DO
P
Data Output (LSB).
Data Outputs.
28–32 DB1–DB5
33
34
DRVSS
Digital Driver Ground.
Digital Driver Supply.
Data Outputs.
DRVDD
P
35–39 DB6–DB10
DO
DO
DI
40
41
DB11
OEB
Data Output (MSB).
Output Enable, Active Low.
42
43
NC
No Connect.
PGAOUT_C AO
PGAOUT_T AO
PGA Output, Negative. This
pin should be left unconnected
except during evaluation.
44
PGA Output, Positive. This pin
should be left unconnected
except during evaluation.
NOTES
See Applications Information for circuit configurations.
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO = Digital Input/Output, P = Power.
REV. A
–7–
AD9816
DEFINITIONS OF SPECIFICATIONS
FUNCTIONAL DESCRIPTION
The AD9816 can be operated in several different modes:
3-channel CDS mode, 3-channel SHA mode, 1-channel CDS
mode, and 1-channel SHA mode. Each mode is selected by
programming the Configuration Register through the serial
interface. For more detail on CDS or SHA mode operation, see
Circuit Descriptions section.
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity error refers to the deviation of each indi-
vidual code from a line drawn from “zero scale” through “posi-
tive full scale.” The point used as “zero scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
3-Channel CDS Mode
In 3-channel CDS mode, the AD9816 simultaneously samples
the red, green and blue input voltages from the CCD outputs.
The sampling points for each Correlated Double Sampler (CDS)
are controlled by CDSCLK1 and CDSCLK2. CDSCLK1’s fall-
ing edge clamps the reference level of the CCD waveform at the
analog inputs of the AD9816. CDSCLK2’s falling edge samples
the data level of the CCD waveform. Each CDS amplifier out-
puts the difference between the CCD reference and data levels.
Next, the output voltage of each CDS amplifier is level-shifted
by an Offset DAC. The voltages are then scaled by the three
Programmable Gain Amplifiers before being multiplexed to the
common 12-bit ADC. The ADC sequentially samples the PGA
outputs on the falling edges of ADCCLK.
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions which are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively,
must be present over all operating ranges.
OFFSET ERROR
The first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the ideal
level.
Timing for this mode is shown in Figure 1, using a 2× master
clock. Although it is not required, it is recommended that the
falling edge of CDSCLK2 be aligned with the rising edge of
ADCCLK. The rising edge of CDSCLK2 should not occur
GAIN ERROR
The last code transition should occur for an analog value
1 1/2 LSB below the nominal full scale voltage. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between the first and last
code transitions.
before the previous falling edge of ADCCLK, as shown by tADC2
.
The maximum allowable width of CDSCLK2 will be dependent
on the ADCCLK period, and equal to one ADCCLK period
minus 30 ns. The output data latency is three clock cycles.
The offset and gain values for the red, green, and blue channels
are programmed using the serial interface. The order in which
the channels are switched through the multiplexer is selected by
programming the MUX register. The rising edge of CDSCLK2
always resets the multiplexer.
TOTAL OUTPUT NOISE
An ideal ADC outputs only one code value for a dc input
voltage. A real converter has noise sources that will cause a
spread of codes at the output for a dc input voltage. The total
output noise is measured with a grounded input and is equal to
the standard deviation of the histogram of output codes.
3-Channel SHA Mode
In 3-channel SHA mode, the AD9816 simultaneously samples
the red, green, and blue input voltages. The sample-and-hold
amplifier’s sampling point is controlled by CDSCLK2. CDSCLK2’s
falling edge samples the input waveforms on each channel. The
output voltages from the three SHAs are modified by the offset
DACs and then scaled by the three PGAs. The outputs of the
PGAs are then multiplexed through the 12-bit ADC. The ADC
sequentially samples the PGA outputs on the falling edges of
ADCCLK.
CHANNEL-TO-CHANNEL CROSSTALK
In an ideal three-channel system, the signal in one channel will
not influence the signal level of another channel. The channel-
to-channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9816, one channel is grounded and the other two chan-
nels are exercised with full-scale input signals. The change in
the output codes from the first channel is measured and com-
pared with the result when all three channels are grounded. The
difference is the channel-to-channel crosstalk, stated in LSBs.
The input signal is sampled with respect to the voltage applied
to the OFFSET pin. With the OFFSET pin grounded, a zero
volt input corresponds to the ADC’s zero scale output. The
input clamp is disabled in this mode. However, the OFFSET
pin may be used as a coarse offset adjust pin. A voltage applied
to this pin will be subtracted from the voltages applied to the
red, green and blue inputs in the first amplifier stage of the
AD9816. For more information, see the Circuit Descriptions
section.
APERTURE DELAY
The aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9816 until the actual sample
of the input signal is held. For CDSCLK1, the aperture delay
represents the amount of time it takes for the clamp switch
to open after CDSCLK1 transitions from high to low. For
CDSCLK2, the aperture delay is the amount of time after the
CDSCLK2 falling edge that the input signal is sampled.
Timing for this mode is shown in Figure 2, using a 1× master
clock. CDSCLK1 should be grounded in this mode. Although
it is not required, it is recommended that the falling edge of
CDSCLK2 be aligned with the rising edge of ADCCLK. The
rising edge of CDSCLK2 should not occur before the previous
falling edge of ADCCLK, as shown by tADC2. The maximum
allowable width of CDSCLK2 will be dependent on the ADCCLK
POWER SUPPLY REJECTION
Power supply rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.
–8–
REV. A
AD9816
REGISTER OVERVIEW
period, and equal to one ADCCLK period minus 30 ns. The
output data latency is three ADCCLK cycles.
The serial interface is used to program the eight internal regis-
ters of the AD9816. The address bits A2–A0 determine the
register in the AD9816 where serial data D7–D0 is written to or
read from.
The offset and gain values for the red, green and blue channels
are programmed using the serial interface. The order in which
the channels are switched through the multiplexer is selected by
programming the MUX register. The rising edge of CDSCLK2
always resets the multiplexer.
The Configuration Register controls the operating mode of the
AD9816. Bits 7 (MSB), 6 and 0 are test mode bits and should
always be set to zero. Bit 5 is set high to enable the CDS mode.
Setting this bit low enables the SHA mode. Set Bit 4 high to
enable the 3 V input span. Set Bit 3 high to enable the 1.5 V
span. Bits 2 and 1 set the channel mode. Bit 2 enables 3-chan-
nel simultaneous sampling. Bit 1 enables single channel mode,
with the appropriate channel set in the MUX Register. At
power-on, this register defaults to 3-channel CDS mode with a
3 V input span, as shown in Table I.
1-Channel CDS Mode
This mode operates in the same way as the 3-channel CDS
mode. The difference is that the multiplexer remains fixed in
this mode, so only the channel specified in the MUX register is
processed. Because the AD9816 is still sampling all three chan-
nels, the unused inputs should be grounded through 1200 pF
capacitors.
Timing for this mode is shown in Figure 3, using a 3× master
clock. Although it is not required, it is recommended that the
falling edge of CDSCLK2 be aligned with the rising edge of
ADCCLK.
7
6 5 4 3 2 1 0
TEST MODE (LSB)
1-CHANNEL MODE
3-CHANNEL MODE
1.5 V INPUT SPAN
3 V INPUT SPAN
CDS ENABLE
1-Channel SHA Mode
This mode operates the same way as the 3-channel SHA mode,
except that the multiplexer remains stationary. Only the channel
specified in the MUX register is processed. Because the AD9816 is
still sampling all three channels, the unused inputs should be
grounded.
TEST MODE
TEST MODE (MSB)
Figure 7. Configuration Register
The input signal is sampled with respect to the voltage applied
to the OFFSET pin. With the OFFSET pin grounded, a zero
volt input corresponds to the ADC’s zero scale output. The
input clamp is disabled in this mode. However, the OFFSET
pin may be used as a coarse offset adjust pin. A voltage applied
to this pin will be subtracted from the voltages applied to the
red, green and blue inputs in the first amplifier stage of the
AD9816. For more information, see the Circuit Descriptions
section.
The MUX Register determines the order of channels that the
multiplexer will switch to in the different modes of operation.
Bit 7 and Bit 1 are test modes and should be set to zero. Bit 0 is
a test mode bit and should be set high. In 3-channel mode,
Table II shows how to set the order in which the channels are
converted. The multiplexer is always reset on the rising edge of
CDSCLK2. In 1-channel mode, the multiplexer is stationary,
and only converts the channel selected in Table III. At power-
on, this register defaults to 3-channel RGB mode.
Timing for this mode is shown in Figure 4, using a 1× master
clock. CDSCLK1 should be grounded in this mode of opera-
tion. Although it is not required, it is recommended that the
falling edge of CDSCLK2 be aligned with the rising edge of
ADCCLK.
7
6 5 4 3 2 1 0
TEST MODE (LSB)
TEST MODE
1-CHANNEL RED
1-CHANNEL GREEN
1-CHANNEL BLUE
3-CHANNEL BIT 0
3-CHANNEL BIT 1
TEST MODE (MSB)
Figure 8. MUX Register
Table I. Register Map
Register
A2
A1
A0
Power-On Default Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Configuration Register
MUX Register
0 0 1 1 0 1 0 0 (LSB)
0 0 1 0 0 0 0 1 (LSB)
Undetermined
Undetermined
Undetermined
Undetermined
Undetermined
Undetermined
Red PGA Register
Green PGA Register
Blue PGA Register
Red Offset Register
Green Offset Register
Blue Offset Register
REV. A
–9–
AD9816
Table II. 3-Channel Selection
gain. The gain of the PGA increases linearly as the gain word
increases, and can be calculated by the following equation:
MUX Register Bits
PGA Gain = 1 + (Gain Code/51.2)
6
5
Channel Sequence
where Gain Code varies from 0 to 255. For more information,
refer to the Circuit Descriptions section.
0
1
1
0
Red, Green, Blue
Blue, Green, Red
7
6 5 4 3 2 1 0
Table III. 1-Channel Selection
MUX Register Bits
D0 (LSB)
D1
D2
4
3
2
Channel
D3
0
0
1
0
1
0
1
0
0
Red
Green
Blue
D4
D5
D6
D7 (MSB)
The offset is variable from –100 mV to +100 mV, and is applied
at the output of the CDS, before the PGA. The resolution is
8 bits, and a sign magnitude coding scheme is used. Table IV
shows the offset voltage that corresponds to the register value.
Figure 10. PGA Registers for Red, Green and Blue
Channels
SERIAL TIMING
The 3-wire serial interface timing is shown below. To write to
the AD9816, SLOAD is first taken low. Next, a total of 16 bits
are sent to SDATA, which get latched into the AD9816 on the
rising edges of SCLK. Additional SCLK pulses will be ignored.
The first bit, R/W, should be low to specify a write operation.
The next three bits, A2–A0, are the address bits to specify the
destination register for the data word D7–D0. After all 16 bits
have been clocked, SLOAD is taken high, which internally
latches the data to the appropriate register. The read operation
also starts by taking SLOAD low. First, a one is written to R/W,
to specify a read operation. Next, the three Address Bits A2–A0
are written to specify the register that will be read. On the 8th
SCLK falling edge, SDATA will begin to output the informa-
tion from the desired register. After all eight data bits have been
read, SLOAD is taken back high.
7
6 5 4 3 2 1 0
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
Figure 9. Offset Registers for Red, Green and Blue
Channels
Table IV. Offset Adjustment
Offset Register
Offset Voltage
R/Wb
A2 A1 A0
D7 D6 D5 D4 D3 D2 D1
D0
0111 1111 (LSB)
+100 mV
SDATA
SCLK
.
.
.
.
.
tDH
tDS
.
+0.8 mV
0.0 mV
0.0 mV
–0.8 mV
.
tLH
tLS
0000 0001
0000 0000
1000 0000
1000 0001
SLOAD
Figure 11. Write Operation Timing
.
.
.
R/Wb
tDH
.
.
A2 A1 A0
D7 D6 D5 D4 D3 D2 D1
D0
SDATA
SCLK
tDS
tRDV
1111 1111
–100 mV
The PGA is used for correcting color imbalance and for fine
adjustment of the input span before the ADC. Gain is variable
from 1× to 6× (0 dB to 15.5 dB) with 8-bit resolution. An all
“zeros” word (00 . . . 0) corresponds to the minimum gain, and
an all “ones” word (11 . . . 1) corresponds to the maximum
tLH
tLS
SLOAD
Figure 12. Read Operation Timing
–10–
REV. A
AD9816
CIRCUIT DESCRIPTIONS
Analog Input Configuration for CDS and SHA Mode
of the AD9816 can also handle an input signal down to
AVSS – 0.3 V without any saturation recovery issues. Although
an input level below zero volts will be clipped to the ADC’s full-
scale output code, the input stage can respond quickly enough
to accurately process the next pixel that falls into the linear
input range. Any signals below AVSS – 0.3 V will turn on the
input protection diodes, and recovery from the saturated condi-
tion may take up to several milliseconds.
CDS Mode Operation
Figure 13 shows the equivalent input circuit for the CDS mode
of operation. The CCD signal is connected to the AD9816’s
analog inputs through a coupling capacitor CIN. The CCD
reference level is clamped during the CDSCLK1 pulse, when
the clamp switch closes and connects the externally-generated
3 V bias to the analog input. After the clamp switch opens
(CDSCLK1 low), the CCD data level will be level shifted by
the voltage held across CIN, and the SHA will sample the input
signal when the CDSCLK2 pulse goes low (see Figures 1 and 3
for CDS mode timing). In this sampling technique, the CDS
function is effectively performed across the input capacitor, CIN.
Input Capacitor CIN
The recommended value for CIN is 1200 pF. This value has
been selected to provide the best overall performance when
considering three factors: input attenuation, linearity and signal
droop. The value of CIN may be optimized for a particular ap-
plication if these three factors are understood.
This CDS method has two additional considerations. First, the
CCD signal cannot be dc-coupled into the AD9816, because
the input capacitor is required. Second, the input clamp of the
AD9816 is operating as a pixel clamp, and must be asserted on
every pixel for true CDS operation. If line clamp operation is
desired, CDSCLK1 may be used at the start of each line to set
the proper dc voltage on CIN. Then, during the effective pixels
of each line, CDSCLK1 can be held low while CDSCLK2
samples the data levels of each pixel. Figure 5 shows the timing
for line clamp operation.
1. Attenuation (Gain Error)
The input voltage will be attenuated by the interaction of
C
IN and CSTRAY. CSTRAY is less than 10 pF, which results in
an attenuation of about 0.8% when CIN is 1200 pF. The gain
error will increase accordingly as the value of CIN is decreased.
2. Linearity
The input capacitance of the AD9816 is shown in Figure 8
as CSTRAY. A small portion of this capacitance is junction
capacitance, which will vary nonlinearly as the input voltage
to the AD9816 changes. When the input voltage is attenu-
ated by the combination of CIN and CSTRAY, there will be a
small nonlinear component caused by the input junction
capacitance. The magnitude of the junction capacitance will
cause a 1 LSB (0.024%) nonlinearity over the 3 V input
range when a 1200 pF CIN is used. This nonlinearity will
increase if a smaller CIN is used.
AD9816
C
IN
I
R
VING
11
BIAS
S
CCD SIGNAL
SHA
C
STRAY
BUFFER
CLAMP
SWITCH
3. Droop
+5V
The input bias current of the AD9816 is typically 10 nA and
is constant regardless of the AD9816’s input voltage. The
droop of the voltage across CIN can be calculated with the
following equation:
1.0k⍀
1.5k⍀
3V
16
OFFSET
0.1F
1F
i
dV = BIAS ×(t)
17
18
CDSCLK1
CDSCLK2
CIN
Figure 13. CDS Mode Input Circuit (All Channels Identical)
where t is the time between clamp intervals. Between the
adjacent pixels of a scanned line, this droop will be insignifi-
cant. Between scanned lines, a 1 ms delay will produce a
droop of about 10 mV, which can be easily clamped on the
first pixel of the next line. If the value of CIN is reduced, the
droop will increase accordingly.
Input Signal Range for CDS Mode
An input dc bias level of 3 V allows a maximum 3 V p-p signal
swing from the CCD. Figure 14 shows a typical full-scale input
waveform to the AD9816, illustrating the allowable input range.
With a reference level of 3 V, the AD9816 can tolerate up to
2 V of reset feedthrough above the reference level. The inputs
5V MAX RESET FEEDTHROUGH
3V REFERENCE LEVEL
(SET BY INPUT CLAMP)
MAX PEAK-PEAK SIGNAL
0V MAX DATA LEVEL
–0.3V MAX SATURATED DATA LEVEL
Figure 14. CCD Input Signal Clamped to 3 V
REV. A
–11–
AD9816
Line Clamp
Programmable Gain Amplifiers
The AD9816 has three programmable amplifiers, one for each
channel. The gain is variable from 1 V/V (0 dB) to 5.98 V/V
(15.5 dB) in 256 increments. Figure 16 shows the PGA gain
transfer function. The gain of the PGA can be calculated ac-
cording to the equation:
If a line clamp technique is implemented (see Figure 5 for
timing), the value of CIN should be increased to more than
1200 pF. The main requirement for line clamp is to keep the
signal droop below 1 LSB across a scanned line. For example, if
a CCD with 5400 effective pixels is clocked at 2 MHz, then
t = 2.7 ms. One LSB at 12 bits with a 3 V full scale is 732 µV.
Rearranging the above droop equation:
Gain Code
PGAGain =1+
51.2
i
CMIN
=
BIAS ×t
dV
6
5
4
3
2
1
In this case, CMIN = 37 nF, and a convenient standard value of
0.047 µF will be adequate.
SHA Mode Operation
When the AD9816 is configured for SHA mode operation, the
OFFSET pin functions as an offset adjustment input. Figure
15 shows a simplified diagram of the AD9816’s inputs when SHA
mode is selected. A positive dc voltage may be applied to OFFSET
which will be subtracted from all three input channels in the
input stage of the AD9816. The maximum input voltage to the
analog input pins or the OFFSET pin in SHA mode is 3 V.
0
51
102
153
204
255
The OFFSET feature is provided to allow coarse offset adjust-
ment of the input signal. If the signal is sampled with respect to
ground, any positive offset on the input signal will subtract from
the dynamic range of the ADC. For example, an input signal
that spans from 1.5 V to 2.5 V cannot utilize all of the available
dynamic range, using either the 1.5 V or 3 V span. However, by
applying a dc value of 1.5 V to the OFFSET pin, the input
signal will be level-shifted down to 0 V to 1 V. This would
allow the use of the 3 V span and a PGA gain of three to use
the entire ADC dynamic range.
GAIN REGISTER CODE – Decimal
Figure 16. PGA Gain Transfer Function
The analog outputs of the three PGAs are multiplexed to the input
of the 12-bit ADC. The differential output of the MUX is also
buffered and externally available at Pins 43 and 44 (PGAOUT_C
and PGAOUT_T, respectively). The timing diagrams, Fig-
ures 1 through 4, show the timing relationships between the
analog inputs, CDSCLK2, ADCCLK, and PGAOUT_T and
PGAOUT_C. The CDSCLK2 pulse resets the outputs of all
three PGAs to an internal bias level. The first rising edge of
ADCCLK after the rising edge of CDSCLK2 will switch the
MUX to the red PGA output. The second ADCCLK rising
edge switches the MUX to the green PGA output, and the third
rising edge switches the MUX to the blue PGA output.
If no dc offset adjustment is desired, the OFFSET pin should
be grounded. The input signal will be sampled with respect to
ground.
AD9816
PGA Outputs
VINR
The PGAOUT_T and PGAOUT_C signals represent the differ-
ential input to the ADC, and are complementary. Both signals
will reset to 3.5 V while CDSCLK2 is high. The voltage swing
of each output is equal to one-half of the ADC’s full-scale volt-
age, centered at 3.5 V. Table V shows the relationship between
the analog input voltage, the PGA output voltage and the ADC
input voltage.
SHA
BUFFER
VING
SHA
BUFFER
VINB
Figure 18 shows the PGA output voltages for three different
color pixel amplitudes. In this example, the red pixel has the
largest amplitude, and the blue pixel has the smallest amplitude.
Because the PGAOUT_T and PGAOUT_C outputs are inter-
nally buffered by source followers, they are not an exact repre-
sentation of the differential ADC input signal. PGAOUT_T and
PGAOUT_C should only be used during evaluation; perfor-
mance of the AD9816 is only guaranteed with these two pins
unconnected.
SHA
BUFFER
OFFSET
12k⍀
CDSCLK1
CDSCLK2
Figure 15. SHA Mode Input Circuit
–12–
REV. A
AD9816
PGAOUT_T
PGAOUT_C
Analog-to-Digital Converter
The AD9816 uses a high speed 12-bit ADC core. This CMOS
converter is designed to run at 6 MSPS with good linearity and
noise performance. Figure 19 shows the INL and DNL perfor-
mance of a typical AD9816 device, running at 6 MHz in 3-channel
CDS mode using the timing shown in Figure 1. The following
timing parameters were used: tCRA = 500 ns, tADCLK = 83 ns,
tC1 = 20 ns, tC1C2 = 170 ns, tC1 = 80 ns, tADC2 = 3 ns, tC2AD = 83 ns,
and tC2C1 = 230 ns.
RED
GREEN
BLUE
PGA
PGA
3:1
DIFF
MUX
12-BIT ADC
SELECT
The digital outputs of the AD9816 follow a straight binary
coding scheme. Table VI shows the digital output coding for
the 3 V input span.
2
ADCCLK
MUX
CONTROL
CDSCLK2
PGA
0.2
Figure 17. PGA/MUX Circuit Configuration
0.0
–0.2
–0.4
–0.6
–0.8
–1.2
–1.4
–1.6
MAX INL 0.18
MIN INL –1.46
PIXEL n
BLUE
ANALOG
INPUTS
GREEN
4095
0
400
800
1200 1600 2000 2400 2800 3200 3600
RED
1.5
1.0
MAX DNL 0.31
MIN DNL –0.33
CDSCLK2
ADCCLK
0.5
0.0
–0.5
–1.0
4.25V
3.5V
RED(n)
RESET
RESET
PGAOUT_T
PGAOUT_C
4095
0
400
800
1200 1600 2000 2400 2800 3200 3600
GREEN(n–1)
GREEN(n)
Figure 19. Typical Linearity Performance
2.75V
BLUE(n)
BLUE(n–1)
Table VI. Digital Output Format
Figure 18. PGA Output Voltages (ADC Input Range = 3 V)
Input Voltage1
Digital Outputs
Table V. Voltage Swing of PGA Outputs
3.0 – 1 LSB
3.0 – 2 LSB
1111 1111 1111
1111 1111 1110
Analog
Input
Differential
ADC
Input
0.0 + 1 LSB
0.0
0000 0000 0001
0000 0000 0000
Voltage1
PGAOUT_T
PGAOUT_C
0.002
1.502
3.002
0.003
0.753
1.503
2.75
3.50
4.25
3.125
3.50
3.875
4.25
3.50
2.75
3.875
3.50
3.125
1.5
0.0
+1.5
0.75
0.0
NOTE
1Analog input voltage in CDS mode is the difference between the
CCD’s reference and data levels.
+0.75
NOTES
1Analog input voltage in CDS mode is the difference between the CCD’s refer-
ence and data levels.
23.0 V Input Range.
31.5 V Input Range.
REV. A
–13–
AD9816
APPLICATIONS INFORMATION
CDS Mode Circuit
supply pin should still be decoupled to the same ground plane
as the rest of the AD9816. The loading of the digital outputs
should be minimized, either by using short traces to the digital
ASIC, or by using external digital buffers. All 0.01 µF and
0.1 µF decoupling capacitors should be located as close as pos-
sible to the AD9816 pins. Also, the 1200 pF input capacitors
should be located close the AD9816’s analog input pins.
The recommended circuit configuration for CDS mode opera-
tion is shown in Figure 20. The input coupling capacitor value
of 1200 pF is recommended, but this value may be adjusted to
suit a particular application (see Circuit Descriptions). A single
ground plane is recommended for the AD9816. A separate power
supply may be used for DRVDD, the digital driver supply, but this
V
DD
V
DD
0.1F
0.01F
0.01F
0.1F
1
2
33
32
31
30
29
28
27
26
25
24
23
AVDD
AVSS
CAPT
CAPT
CAPB
CAPB
VREF
CML
DRVSS
DB5
0.1F
DB5
3
DB4
DB3
DB2
DB1
DB4
+
10F
0.1F
0.1F
4
DB3
5
DB2
AD9816
6
DB1
7
DB0 (LSB)
DVSS
SLOAD
SDATA
SCLK
DB0 (LSB)
8
+
9
VINR
0.1F
1.0F
10F
1200pF
1200pF
10
11
AVSS
VING
SLOAD
SDATA
SCLK
RED_IN
GREEN_IN
BLUE_IN
1200pF
NC = NO CONNECT
V
DD
0.01F
0.1F
V
DD
0.1F
0.01F
ADCCLK
CDSCLK2
CDSCLK1
V
DD
1k⍀
1.0F
0.1F
1.5k⍀
Figure 20. Recommended Circuit for CDS Mode
–14–
REV. A
AD9816
SHA Mode Circuit
reference black level of the CIS can be connected to the OFF-
SET pin, to remove the dc offset. Removing the coarse offset of
the CIS signal will allow the dynamic range of the AD9816 to
be maximized.
The circuit configuration for SHA mode is identical to CDS
mode except for two differences: the analog inputs should be
dc-coupled, and the OFFSET pin is tied to ground or a desired
dc voltage (see Circuit Descriptions). In CIS applications, the
V
DD
V
DD
0.01F
0.1F
0.01F
0.1F
1
2
AVDD
AVSS
CAPT
CAPT
CAPB
CAPB
VREF
CML
33
32
31
30
29
28
27
26
25
24
23
DRVSS
DB5
0.1F
DB5
DB4
DB3
DB2
DB1
3
DB4
+
10F
0.1F
0.1F
4
DB3
5
DB2
6
AD9816
DB1
7
DB0 (LSB)
DVSS
SLOAD
SDATA
SCLK
DB0 (LSB)
8
+
9
VINR
0.1F
10F
1.0F
10
11
SLOAD
AVSS
VING
SDATA
SCLK
RED_IN
GREEN_IN
BLUE_IN
NC = NO CONNECT
V
DD
0.01F
0.1F
V
DD
0.1F
0.01F
V
DD
ADCCLK
CDSCLK2
CDSCLK1
R1
R2
OPTIONAL DC OFFSET
1.0F
0.1F
GROUND-REFERENCED SAMPLING
Figure 21. Recommended Circuit for SHA Mode
REV. A
–15–
AD9816
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead MQFP
(S-44)
0.529 (13.45)
0.510 (12.95)
0.096 (2.45)
0.398 (10.1)
MAX
0.390(9.90)
0.041 (1.03)
0.029 (0.73)
44
34
1
33
SEATING
PLANE
0.333 (8.45)
0.327 (8.3)
TOP VIEW
(PINS DOWN)
11
23
0.01 (0.25) MIN
0.009 (0.23)
0.005 (0.13)
12
22
0.018 (0.45)
0.012 (0.30)
0.031 (0.80)
BSC
0.083 (2.1)
0.077 (1.95)
–16–
REV. A
相关型号：
©2020 ICPDF网 联系我们和版权申明