AD9814S [ADI]
14-Bit CCD/CIS Signal Processor; 14位CCD / CIS信号处理器
| 型号： | AD9814S |
| 厂家： | 
ADI |
| 描述： | 14-Bit CCD/CIS Signal Processor |
| 文件： | 总7页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit CCD/CIS
Signal Processor
AD9814S
1.0
Scope
This specification documents the detail requirements for space qualified product manufactured on Analog Devices, Inc.'s QML
certified line per MIL-PRF-38535 Level V except as modified herein.
The manufacturing flow described in the STANDARD SPACE LEVEL PRODUCTS PROGRAM brochure is to be considered
a part of this specification. http://www.analog.com/aerospace.
This data sheet specifically details the space grade version of this product. A more detailed operational description and a
complete data sheet for commercial product grades can be found at www.analog.com/AD9814.
2.0
3.0
Part Number. The complete part number(s) of this specification follow:
Part Number
Description
AD9814-703F
Complete 14-Bit CCD/CIS Signal Processor
Case Outline
Letter
F
Descriptive designator
CDFP3-F28
Case Outline (Lead Finish per MIL-PRF-38535)
28 lead bottom-brazed flatpack
Figure 1 - Functional Block Diagram
ASD0016515
Rev. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license
is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of
their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2010 Analog Devices, Inc. All rights reserved.
AD9814S
Pin Number
Name
CDSCLK1
CDSCLK2
ADCCLK
OEB
Type
DI
Description
1
CDS Reference Level Sampling Clock
CDS Data Level Sampling Clock
A/D Converter Sampling Clock
2
DI
3
DI
4
DI
Output Enable, Active Low
5
DRVDD
DRVSS
D7
P
Digital Output Driver Supply
6
P
Digital Output Driver Ground
7
DO
DO
DO
DO
DO
DO
DO
DO
DI/DO
DI
Data Output MSB. ADC DB13 High Byte, ADC DB5 Low Byte
Data Output. ADC DB12 High Byte, ADC DB4 Low Byte
Data Output. ADC DB11 High Byte, ADC DB3 Low Byte
Data Output. ADC DB10 High Byte, ADC DB2 Low Byte
Data Output. ADC DB9 High Byte, ADC DB1 Low Byte
Data Output. ADC DB8 High Byte, ADC DB0 Low Byte
Data Output. ADC DB7 High Byte, Don’t Care Low Byte
Data Output LSB. ADC DB6 High Byte, Don’t Care Low Byte
Serial Interface Data Input/Output
Serial Interface Clock Input
8
D6
9
D5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D4
D3
D2
D1
D0
SDATA
SCLK
SLOAD
AVDD
AVSS
CAPB
CAPT
VINB
DI
Serial Interface Load Pulse
P
+5 V Analog Supply
P
Analog Ground
AO
AO
AI
ADC Bottom Reference Voltage Decoupling
ADC Top Reference Voltage Decoupling
Analog Input, Blue Channel
CML
AO
AI
Internal Bias Level Decoupling
VING
OFFSET
VINR
AVSS
AVDD
Analog Input, Green Channel
AO
AI
Clamp Bias Level Decoupling
Analog Input, Red Channel
P
Analog Ground
P
+5 V Analog Supply
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
Figure 2 – Terminal Connections and Pin Function Descriptions
ASD0016515 Rev. D | Page 2 of 7
AD9814S
4.0
Absolute Maximum Ratings. (TA = 25°C, unless otherwise noted)
Parameter
With respect to
AVSS
Min
-0.3
-0.3
-0.5
-0.5
-0.3
-0.3
Max
Units
V
VIN, CAPT, CAPB
Digital Inputs
AVDD
AVDD + 0.3
AVDD + 0.3
+6.5
AVSS
V
AVSS
V
DRVDD
DRVSS
DRVSS
DRVSS
+6.5
V
AVSS
+0.3
V
Digital Outputs
Junction Temperature
Storage Temperature
DRVDD + 0.3
+150
V
°C
°C
°C
-65
+150
Lead Temperature
(10 sec)
+300
NOTES:
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional
operation of the device at these or other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect device reliability.
The input limits are defined as maximum tolerable voltage levels into the AD9814. These levels are not intended to be in the linear input range of
the device. Signals beyond the input limits will turn on the overvoltage protection diodes.
5.0
Thermal Characteristics:
Junction-to-
Case
Junction-to-Ambient
(ΘJA)
Package Type
Units
(ΘJC)
Thermal Resistance,
Bottom Brazed (F)
22
60
°C/W Max
ASD0016515 Rev. D | Page 3 of 7
AD9814S
6.0
Table I. Electrical Table:
Table I
Conditions 1/
Unless Otherwise Specified
Parameter
Symbol
RES
Sub
Group
1,2,3
Limit Min
14
Limit Max
Units
Bits
See notes at end of table
RESOLUTION
No Missing Codes
Supply Currents
IAVDD
IDRVDD
PD
1,2,3
1,2,3
1,2,3
1,2
80
10
mA
mA
Power dissipation
450
0.3
0.5
11
mW
Power supply rejection
PSR
AVDD= +5.0V ± 0.25V
%FSR
%FSR
LSB
3
ACCURACY (Entire Signal Path)
Integral Nonlinearity 2/
INL
1,2
-11
3
1
-18
-1
11
LSB
LSB
ACCURACY (Entire Signal Path)
Differential Nonlinearity
1.25
DNL
2
-1
1
LSB
3
-1
1.5
LSB
mV
ACCURACY (Entire Signal Path)
Offset Error
VOS
GAIN
1,2,3
-104
104
ACCURACY (Entire Signal Path)
Gain Error 3/
1,2,3
1,2,3
1,2,3
1,2,3
-5.3
5.7
5.3
5.9
%FSR
PGA Gain Ratio 4/
PGA GAIN
VREF4
VREF2
DIFFERENTIAL VREF
1.9
2.1
V
V
CAPT-CAPB (4V Input Range)
DIFFERENTIAL VREF
0.94
1.06
CAPT-CAPB (2V Input Range)
TABLE I NOTES:
1/
TA = +25 °C, TA Max = +125 °C, TA Min = -55 °C. AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS, FADCCLK = 6 MHz, FCDSCLK1 = FCDSCLK2 = 2
MHz, PGA Gain = 1, Input Range = 4V, unless otherwise noted.
2/
3/
4/
INL is measured using the “fixed endpoint” method, NOT using a “best-fit” calculation.
The Gain Error specification is dominated by the tolerance of the internal differential voltage reference.
The PGA Gain is approximately “linear in dB” and follows the equation: PGA Gain = (5.8 / (1 + 4.8 (63 – G) / 63)) where G is the register
value.
ASD0016515 Rev. D | Page 4 of 7
AD9814S
Figure 3 – 3-Channel CDS Mode Timing Diagram
Figure 4 – 3-Channel SHA Mode Timing Diagram
ASD0016515 Rev. D | Page 5 of 7
AD9814S
6.0
Table II. Electrical Test Requirements:
Table II
Test Requirements
Subgroups (in accordance with
MIL-PRF-38535, Table III)
Interim Electrical Parameters
1
Final Electrical Parameters
Group A Test Requirements
1, 2, 3 1/ 2/
1, 2, 3
1 2/
1
Group C end-point electrical parameters
Group D end-point electrical parameters
Group E end-point electrical parameters
N/A
Notes:
1/ PDA applies to Subgroup 1. Delta’s excluded from PDA.
2/ See Table III for Delta limits.
7.0
Table III. Life Test / Burn-in Delta limits:
Table III
Units
Test Symbol
Delta Limit
IAVDD
VOS
+/-2
mA
+/-13.2
(+/-54)
mV
(LSB)
+/-0.56
(+/-91)
%
(LSB)
GAIN
+INL
-INL
+/-6
+/-5
LSB
LSB
LSB
LSB
+DNL
-DNL
+/-0.5
+/-0.35
8.0
9.0
Life Test / Burn-In Circuit:
8.1
8.2
8.3
HTRB is not applicable for this drawing.
Burn-in is per MIL-STD-883 Method 1015, test condition D.
Steady state life test is per MIL-STD-883 Method 1005, test condition D.
MIL-STD-38535 QMLV exceptions:
9.1
9.2
Full WLA per MIL-STD-883 TM 5007 is not available for this product. SEM Inspection only is available per
MIL-STD-883, TM2018.
This product is manufactured in a MIL-PRF-38535 QMLQ certified wafer fab facility.
ASD0016515 Rev. D | Page 6 of 7
AD9814S
Rev
A
Description of Change
Date
Initiate
Sept 9, 2007
March 7, 2008
April 7, 2008
March 24, 2010
B
C
D
Update header/footer and add to 1.0 Scope description.
Add reference notations to Section 4.0, Table I
Remove post Group C specification limits in Table III such that only Delta limits
are listed. Remove QMLV exception for testing in QMLQ facility. Add Figure 2
pin descriptions. Formatting improvements.
© 2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective
companies.
Printed in the U.S.A.
3/10
ASD0016515 Rev. D | Page 7 of 7
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