AD9501SQ [ADI]
Digitally Programmable Delay Generator; 数字可编程延时发生器
| 型号： | AD9501SQ |
| 厂家： | 
ADI |
| 描述： | Digitally Programmable Delay Generator |
| 文件： | 总12页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Digitally Programmable
Delay Generator
a
AD9501
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Single +5 V Supply
TTL and CMOS Com patible
10 ps Delay Resolution
2.5 ns to 10 s Full-Scale Range
Maxim um Trigger Rate 50 MHz
MIL-STD-883-Com pliant Versions Available
APPLICATIONS
Disk Drive Deskew ing
Data Com m unications
Test Equipm ent
Radar I & Q Matching
single AD9501. An eight-bit digital word selects a time delay
within the full-scale range. When triggered by the rising edge of
an input pulse, the output of the AD9501 will be delayed by an
amount equal to the selected time delay (tD) plus an inherent
propagation delay (tPD).
GENERAL D ESCRIP TIO N
T he AD9501 is a digitally programmable delay generator which
provides programmed time delays of an input pulse. Operating
from a single +5 V supply, the AD9501 is T T L- or CMOS-
compatible, and is capable of providing accurate timing adjust-
ments with resolutions as low as 10 ps. Its accuracy and
programmability make it ideal for use in data deskewing and
pulse delay applications, as well as clock timing adjustments.
T he AD9501 is available for a commercial temperature range of
0°C to +70°C in a 20-pin plastic DIP, 20-pin ceramic DIP, and
a 20-lead plastic leaded chip carrier (PLCC). Devices fully
compliant to MIL-ST D-883 are available in ceramic DIPs.
Refer to the Analog Devices Military Products Databook or current
AD9501/883B data sheet for detailed specifications.
Full-scale delay range is set by the combination of an external
resistor and capacitor, and can range from 2.5 ns to 10 µs for a
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD9501–SPECIFICATIONS
ABSO LUTE MAXIMUM RATINGS1
Operating T emperature Range
Positive Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Digital Input Voltage Range . . . . . . . . . . . . . . . –0.5 V to +VS
T rigger/Reset Input Volt. Range . . . . . . . . . . . . –0.5 V to +VS
Minimum RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ω
Digital Output Current (Sourcing) . . . . . . . . . . . . . . . 10 mA
Digital Output Current (Sinking) . . . . . . . . . . . . . . . . 50 mA
AD9501JN/JP/JQ . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD9501SQ . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Junction T emperature2 . . . . . . . . . . . . . . . . . . . . . . . +175°C
Lead Soldering T emperature (10 sec) . . . . . . . . . . . . +300°C
[+V = +5 V; C = Open; RSET = 3090 Ω (Full-Scale Range =100 ns); Pin 8 grounded; and
S
EXT
ELECTRICAL CHARACTERISTICS
device output connected to Pin 4 RESET input unless otherwise noted]
0؇C to +70؇C
–55؇C to +125؇C
Test
AD 9501JN/JP /JQ
AD 9501SQ
P aram eter
Tem p
Level
Min
Typ
Max
Min
Typ
Max
Units
RESOLUT ION
8
8
Bits
ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Monotonicity
+25°C
+25°C
+25°C
I
I
I
0.5
1
0.5
1
LSB
LSB
Guaranteed
Guaranteed
DIGIT AL INPUT S
Latch Input “1” Voltage
Latch Input “0” Voltage
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Full
Full
Full
Full
Full
Full
+25°C
+25°C
+25°C
+25°C
+25°C
VI
VI
VI
VI
VI
VI
IV
V
2.0
2.0
2.3
2.0
V
V
V
V
µA
µA
pF
ns
ns
ns
ns
0.8
0.8
0.8
60
3
0.8
60
3
Logic “0” Current
Digital Input Capacitance
Data Setup T ime (tS)3
Data Hold T ime (tH)4
Latch Pulse Width (tL)
Reset/T rigger Pulse Width (tR, tT )
5.5
5.5
2.5
2.5
3.5
2
2.5
2.5
3.5
2
V
V
V
DYNAMIC PERFORMANCE
Maximum T rigger Rate5
Minimum Propagation Delay (tPD
Propagation Delay T empco7
Full-Scale Range T empco
+25°C
+25°C
Full
IV
I
V
V
V
I
V
V
V
I
18
22
25
25
36
18
22
25
25
36
MHz
ns
ps/°C
ps/°C
ps
ns
ns
ns
ns
ns
ns
ns
ns
6
)
30
30
Full
Delay Uncertainty
Reset Propagation Delay (tRD
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
53
53
8
)
14.5
4.5
19
7.5
2.3
1.0
30
17.5
14.5
4.5
19
7.5
2.3
1.0
30
17.5
9
Reset-to-T rigger Holdoff (tT HO
T rigger-to-Reset Holdoff (tRHO
)
)
10
Minimum Output Pulse Width11
Output Rise T ime12
3.5
2.0
3.5
2.0
Output Fall T ime12
DAC Settling T ime (tLD
I
V
V
13
)
14
Linear Ramp Settling T ime (tLRS
)
20
20
DIGIT AL OUT PUT
Logic “1” Voltage (Source 1 mA)
Logic “0” Voltage (Sink 4 mA)
Full
Full
VI
VI
2.4
2.4
V
V
0.24
69.5
0.4
0.24
69.5
0.5
POWER SUPPLY15
Positive Supply Current (+5.0 V)
Power Dissipation
Full
Full
VI
VI
83
415
83
415
mA
mW
Power Supply Rejection Ratio16
Full-Scale Range Sensitivity
+25°C
+25°C
I
I
0.7
0.45
2.0
1.7
0.7
0.45
2.0
1.7
ns/V
ns/V
Minimum Prop Delay Sensitivity
–2–
REV. A
AD9501
NOT ES
1Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability
is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2T ypical thermal impedances: 20-lead plastic leaded chip carrier θJA= 73°C/W; θJC= 29°C/W. 20-pin ceramic DIP θJA= 65°C/W; θJC= 20°C/W. 20-pin plastic DIP
θJA= 65°C/W; θJC= 26°C/W.
3Digital data inputs must remain stable for the specified time prior to the positive transition of the LAT CH signal.
4Digital data inputs must remain stable for the specified time after the positive transition of the LAT CH signal.
5Programmed delay (tD) = 0 ns. Maximum self-resetting trigger rate is limited to 6.9 MHz with 100 ns programmed delay. If t D= 0 ns and external RESET signal is
used, maximum trigger rate is 23 MHz.
6Programmed delay (tD ) = 0 ns. In operation, any programmed delays are in addition to the minimum propagation delay (t PD).
7Programmed delay (tD) = 0 ns. [Minimum propagation delay (tPD)].
8Measured from 50% transition point of the RESET signal input to the 50% transition point of the falling edge of the output.
9Minimum time from the falling edge of RESET to the triggering input to insure valid output pulse, using external RESET pulse.
10Minimum time from triggering event to rising edge of RESET to insure valid output event, using external RESET pulse. Extends to 125 ns when programmed delay
is 100 ns.
11When self-resetting with a full-scale programmed delay.
12Measured from +0.4 V to +2.4 V; source = 1 mA; sink = 4 mA.
13Measured from the data input to the time when the AD9501 becomes 8-bit accurate, after a full-scale change in the program delay data word.
14Measured from the RESET input to the time when the AD9501 becomes 8-bit accurate, after a full-scale programmed delay.
15Supply voltage should remain stable within ±5% for normal operation.
16Measured at +VS = +5.0 V ± 5%; specification shown is for worst case.
Specifications subject to change without notice.
EXP LANATIO N O F TEST LEVELS
Test Level
I
–
100% production tested.
II
–
100% production tested at +25°C, and sample tested at specified
temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization testing.
V
– Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100% production
tested at temperature extremes for extended temperature devices;
sample tested at temperature extremes for commercial/industrial
devices.
O RD ERING GUID E
P ackage
D evice
Tem perature
D escription
O ption*
AD9501JN
AD9501JP
AD9501JQ
AD9501SQ
0°C to +70°C
0°C to +70°C
0°C to +70°C
20-Pin Plastic DIP
20-Lead PLCC
20-Pin Ceramic DIP
N-20
P-20A
Q-20
Q-20
–55°C to +125°C 20-Pin Ceramic DIP
*N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.
D IE LAYO UT AND MECH ANICAL INFO RMATIO N
MECH ANICAL INFO RMATIO N
Die Dimensions . . . . . . . . . . . . . . . . . . 89 × 153 × 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic
Bond Wire . . . . . . . . 1.25 mil, Aluminum; Ultrasonic Bonding
or 1 mil, Gold; Gold Ball Bonding
REV. A
–3–
AD9501
AD 9501 P IN D ESCRIP TIO NS
P in No.
Nam e
Function
1
2
+VS
Positive voltage supply; nominally +5 V.
LAT CH
T T L/CMOS register control line. Logic HIGH latches input data D0–D7. Register is
transparent for logic LOW.
3
T RIGGER
T T L/CMOS-compatible input. Rising edge triggers the internal ramp generator, and begins
the delay cycle.
4
5
6
RESET
T T L/CMOS-compatible input. Logic HIGH resets the ramp voltage and OUT PUT .
Output voltage of the internal digital-to-analog converter.
DAC OUT PUT
CEXT
Optional external capacitor connected to +VS; used with RSET and 8.5 pF internal capacitor
to determine full-scale delay range (tDFS).
7
8
RSET
External resistor to ground, used to determine full-scale delay range (tDFS).
OFFSET ADJUST Normally connected to GROUND. Can be used to adjust minimum propagation delay (tPD);
see T heory of Operation text.
9
GROUND
OUT PUT
+VS
Circuit ground return.
10
T T L-compatible delayed output pulse.
Positive voltage supply; nominally +5 V.
11
12-19
D0–D7
T T L/CMOS-compatible inputs, used to set the programmed delay of the AD9501 delayed
output. D0 is LSB and D7 is MSB.
20
GROUND
Circuit ground return.
AD9501 Equivalent Circuits
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9501 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD9501
Figure 1, the AD9501 Internal T iming diagram, illustrates in
detail how the delay is determined. Minimum Delay (tPD) is the
sum of T rigger Circuit delay, Ramp Generator delay, and
Comparator delay.
TH EO RY O F O P ERATIO N
T he AD9501 is a digitally programmable delay device. Its
function is to provide a precise incremental delay between input
and output, proportional to an 8-bit digital word applied to its
delay control port. Incremental delay resolution is 10 ps at the
minimum full-scale range of 2.5 ns. Digital delay data inputs,
latch, trigger and reset are all T T L/CMOS compatible. Output
is T T L-compatible.
T he T rigger Circuit delay and Comparator delay are fixed;
Ramp Generator delay is a variable affected by the rate of
change of the linear ramp and (to a lesser degree) the value of
the offset voltage described below.
Refer to the block diagram of the AD9501.
Maximum Delay is the sum of Minimum Delay (tPD) and Full-
Scale Program Delay (tDFS).
Inside the unit, there are three main subcircuits: a linear ramp
generator, an 8-bit digital-to-analog converter (DAC) and a
voltage comparator. T he rising edge of the input (T RIGGER)
pulse initiates the delay cycle by triggering the ramp generator.
T he voltage comparator monitors the ramp voltage and switches
the delayed output (Pin 10) HIGH when the ramp voltage
crosses the threshold set by the DAC output voltage. T he DAC
threshold voltage is programmed by the user with digital inputs.
Ramp Generator delay is the time required for the ramp to slew
from its reset voltage to the most positive DAC reference
voltage (00H). T he difference in these two voltages is nominally
18 mV (with OFFSET ADJUST open) or 34 mV (OFFSET
ADJUST grounded).
Figure 1. AD9501 Internal Tim ing
REV. A
–5–
AD9501
Offset between the two levels is necessary for three reasons.
First, offset allows the ramp to reset and settle without re-
entering the voltage range of the DAC. Second, the DAC may
overshoot as it switches to its most positive value (00H); this
could lead to false output pulses if there were no offset between
the ramp reset voltage and the upper reference. Overshoot on
the ramp could also lead to false outputs without the offset.
Finally, the ramp is slightly nonlinear for a short interval when it
is first started; the offset shifts the most positive DAC level
below this nonlinear region and maintains ramp linearity for
short programmed delay settings.
directly or connected to ground through a resistor or potentiom-
eter with a value of 10 kΩ or less.
Caution is urged when using resistance in series with Pin 8. T he
possibility of false output pulses, as discussed above, is in-
creased under these circumstances. Using resistance in series
with Pin 8 is recommended only when matching minimum de-
lays between two or more AD9501 devices; it is not recom-
mended if using a single AD9501. Changing the resistance
between Pin 8 and ground from zero to 10 kΩ varies the Ramp
Generator Delay by approximately 35%.
T he Full-Scale Delay Range (tDFS) can be calculated from the
equation:
Pin 8 of the AD9501 is called OFFSET ADJUST (see block
diagram) and allows the user to control the amount of offset
separating the initial ramp voltage and the most positive DAC
reference. T his, in turn, causes the Ramp Generator delay to
vary.
(tDFS ) = RSET ×(CEXT +8.5 pF ) × 3.84
Whenever Full-Scale Delay Range is 326 ns or less, CEXT should
be left open. Additional capacitance and/or larger values of RSET
increase the Linear Ramp Settling T ime, which reduces the
maximum trigger rate. When delays longer than 326 ns are
required, up to 500 pF can be connected from CEXT to +VS.
RSET should be selected in the range from 50 Ω to 10 kΩ. Graph
1 shows typical Full-Scale Delay Ranges for various values of
Figure 2 shows differences in timing which occur if OFFSET
ADJUST Pin 8 is grounded or open. T he variable Ramp
Generator delay is the major component of the three
components which comprise Minimum Delay (tPD) and,
therefore, is affected by the connection to Pin 8.
RSET and CEXT
.
It is preferable to ground Pin 8 because the smaller offset that
results from leaving it open increases the possibility of false out-
put pulses. When grounding the pin, it should be grounded
Figure 2. AD9501 Minim um Delay (tPD) vs. Full-Scale Delay Range (tDFS
)
–6–
REV. A
AD9501
Ramp charging current and DAC full-scale current are slaved
together in the AD9501 to minimize delay drift over tempera-
ture. T o preserve the unit’s low drift performance, both RSET
and CEXT should have low temperature coefficients. Resistors
which are used should be 1% metal film types.
T he minimum delay through the AD9501 corresponds to an
input code of 00H, and FFH gives the full-scale delay. Any
programmed delay can be approximated by:
tD =(DAC code/256) × tDFS
T otal delay through the AD9501 for any given DAC code is
equal to:
T he programmed delay (tD) is set by the DAC inputs, D0–D7.
tTOTAL = tD +tPD
As shown on the block diagram, T T L/CMOS latches are
included to store the digital delay data. Data is latched when
LAT CH is HIGH. When LAT CH is LOW, the latches are
transparent, and the DAC will attempt to follow any changes on
inputs D0–D7.
T he System T iming Diagram, Figure 3, shows the timing
relationship between the input data and the latch. T he DAC
settling time (tLD) is approximately 30 ns. After the digital
(Programmed Delay) data is updated, a minimum 30 ns must
elapse between the time LAT CH goes high and the arrival of a
T RIGGER pulse to assure rated pulse delay accuracy.
When RESET goes HIGH, the ramp timing capacitor (CEXT
+
8.5 pF) is discharged. T he RESET input is level-sensitive, and
overrides the T RIGGER input. T herefore, any trigger pulse
which occurs when RESET is HIGH will not produce an output
pulse. As shown on the system timing diagram, Figure 3, the
next trigger pulse should not occur before the Linear Ramp
Settling T ime (tLRS) interval is completed to assure rated pulse
delay accuracy.
Graph 1. RC Values vs. Full-Scale Delay Range (tDFS
)
Figure 3. AD9501 System Tim ing
REV. A
–7–
AD9501
For most applications, OUT PUT can be tied to RESET . T his
causes the output pulse to be narrow (equal to the Reset
Propagation Delay tRD). Alternatively, an external pulse can be
applied to RESET . T o assure a valid output pulse, however, the
delay between T RIGGER and RESET should be equal to or
greater than the total delay of tPD + tD illustrated in the internal
timing diagram Figure 1.
As shown in that figure, the capacitor voltage discharges very
rapidly and includes a small amount of overshoot and ringing.
Rated timing delay will not be realized unless subsequent trigger
events are delayed until after the linear ramp settles to its reset
voltage value.
T he values for the various delay increments in the specification
table are based on a Full-Scale Delay Range of 100 ns with
OUT PUT tied to RESET (self-resetting operation).
Figure 4. AD9501 Typical Circuit Configuration
When Full-Scale Delay Range is set for intervals shorter than
100 ns, the rate of change of the linear ramp is increased. T his
faster rate means the Maximum T rigger Rate shown in the
specification table is increased because the Ramp Generator
Delay and, consequently, Minimum Propagation Delay tPD
become smaller.
In Figure 4, the AD9501 typical circuit configuration, the
delayed output is tied back to the RESET input. T his will pro-
duce a narrow output pulse whose leading edge is delayed by an
amount proportional to the 8-bit digital word stored in the on-
board latches. For the configuration shown, the output pulse
width will be equal to the Reset Propagation Delay (tRD). If
wider pulses are required, a delay can be inserted between
OUT PUT and RESET . If preferred, an external pulse can be
used as a reset input to control the timing of the falling edge
(and consequently, the width) of the delayed output.
Linear Ramp Settling T ime tLRS also becomes shorter as Full-
Scale Delay Range is decreased. Minimum Delays for various
Full-Scale Delay Range values are shown in Figure 2.
AP P LICATIO NS
T he AD9501 is useful in a wide variety of precision timing
applications because of its ability to delay T T L/ CMOS pulse
edges by increments as small as 10 ps.
Multiple Signal P ath D eskewing
High speed electronic systems with parallel signal paths require
that close delay matching be maintained. If delay mismatch
(time skew) occurs, errors can occur during data transfer. For
these situations, the matching of delays is generally accom-
plished by carefully matching lead lengths.
Figure 5. Multiple Signal Path Deskewing
–8–
REV. A
AD9501
triggered from a common clock signal. T heir outputs go to the
inputs of an RS flip-flop. A digital delay value is applied as an
input to each with AD9501 # 2 typically having a larger value
than AD9501 # 1.
T his delay matching is often difficult when using high speed,
high-pin-count testers because lead length and circuit
impedance can change when the tester setup is changed for
different types of devices. T he skew which might result from
these changes can be compensated by using AD9501 units as
shown in Figure 5.
As shown by the timing portion of the diagram, changing the
delay value from one clock cycle to the next generates a pseudo-
random pulse whose leading and trailing edge delays are con-
trolled relative to Clock In. T he dashed lines illustrate how the
programmed delays of the AD9501 components control both
the timing and width of the generator output.
When deskewing multiple signal paths, a single stimulus pulse is
applied to all inputs of the AD9501s which are used. T he delay
for each signal path is then measured by the tester’s delay
measurement circuit. Using a closed loop technique, all delays
are equalized by changing the digital value held in the register of
each AD9501. Once all delays have been matched to the desired
tolerance, the calibration loop is opened; and the tester is ready
to test the new type of device.
T he frequency (f) and pulse width (tpw) of the pulse generator
can be determined as follows:
f = fCLOCK IN
and:
D igitally P r ogr am m able O scillator
T wo AD9501s can be configured as an stable oscillator, as
shown in Figure 6.
tpw = tTOT 2 – tTOT 1
Figure 6. Digitally Program m able Oscillator
Delay through each side of the oscillator is determined by the
programmed delay (tD) of each AD9501 plus the minimum
propagation delay (tPD) of each. Increasing the digital value
applied to either AD9501 decreases frequency, just as
with TT OT being equal to each AD9501’s minimum propagation
delay (tPD) plus programmed delay (tD). If both AD9501s are
set for the same full-scale delay range, their minimum
propagation delays will be approximately the same, and the
pulse width will be approximately equal to the difference in
programmed delays.
increasing RC decreases frequency in an analog ring oscillator.
Using a pair of AD9501 Delay Generators as shown allows the
user great flexibility because both the frequency and the duty
cycle of the oscillator are easily controlled.
D igital D elay D etector
An unknown digital delay can be measured by applying a
repetitive clock to the circuit shown in Figure 8.
Frequency of the oscillator output can be established with the
equation:
T he pictured delay detector works in a manner similar to a
successive approximation ADC; in this circuit, however, a
D-type flip-flop replaces the ADC’s voltage comparator.
f =1/(2tPD +tD1 +tD2
)
when tD1 and tD2 are the programmed delays of AD9501 # 1 and
AD9502 # 2, respectively.
T o calibrate the circuit, short out the unknown delay and apply
the clock input to both AD9501 units.
P r ogr am m able P ulse Gener ator
In this application, shown in Figure 7, two AD9501 units are
REV. A
–9–
AD9501
Figure 7. Program m able Pulse Delay Generator
output as the zero reference point for measuring the unknown
delay when it is reinserted into the circuit.
AD9501 # 1 should be programmed so its delay is greater than
the zero-set programmed delay of AD9501 # 2. T o accomplish
this, continue to apply clock pulses and increment the digital
data into AD9501 # 1 until the output of the successive approxi-
mation register (SAR) is 02H (00000010) or greater. At this
point, the delay through AD9501 # 1 is slightly longer than the
delay through AD9501 # 2, making it possible to use the SAR
T his calibration procedure compensates for the setup time of
the flip-flop, stray circuit delays and other nonideal characteristics
which are an inherent part of any circuit.
Eight cycles of the clock input are required to determine the
value of the unknown delay.
Figure 8. Digital Delay Detector
–10–
REV. A
AD9501
Analog Settling Tim e Measur em ent
T hreshold voltages V1 and V2 are set for the desired tolerance
around the final value of the DUT output signal. As shown in
the lower portion of the diagram, the output of the detector is
high when the analog output signal of the converter is within the
limits set by V1 and V2.
T his circuit, shown in Figure 9, functions in a manner similar to
the digital delay detector; for this application, too, the clock
must be repetitive. As in the delay detector, AD9501 # 1 is used
to cancel the propagation delay of AD9501 # 2, propagation
delay of the comparators, stray delays, etc. T o accomplish this,
use the calibration procedure described earlier for the digital
delay generator.
T herefore, the settling time can be measured by starting the
delay of AD9501 # 2 at its maximum setting and decrementing
it until the window comparator goes low. T he difference
between the DAC codes applied to AD9501 # 2 and AD9501
# 1 is a measure of the settling time of the D/A converter being
tested.
T he difference between the two circuits is in the detection
method. T he register of the digital delay is replaced by a win-
dow comparator for the analog settling measurement.
Figure 9. Analog Settling Tim e Measurem ent
Layout Consider ations
switching signals. Most socket assemblies add significant
inter-lead capacitance, and should be avoided whenever pos-
sible. If sockets must be used, individual pin sockets such as
AMP part number 6330808-0 (closed knock-out end) or
6-330808-3 (open end) should be used.
Although the inputs and output of the AD9501 are digital, the
delay is determined by analog circuits. T his makes it critical to
use high speed analog circuit layout techniques to achieve rated
performance.
T he ground plane should be on the component side of the
board and extend under the AD9501 to shield it from digital
Power supply decoupling is also critical for high speed design; a
0.1 µF capacitor should be connected as close as possible to
each supply pin.
REV. A
–11–
AD9501
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
Suffixes JQ and SQ
Suffix JN
Suffix JP
–12–
REV. A
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