AD9508PCBZ [ADI]
1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust; 1.65 GHz的时钟扇出缓冲器与输出分频器和延迟调整
| 型号： | AD9508PCBZ |
| 厂家： | 
ADI |
| 描述： | 1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust |
| 文件： | 总40页 (文件大小：838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.65 GHz Clock Fanout Buffer with
Output Dividers and Delay Adjust
Data Sheet
AD9508
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.65 GHz differential clock inputs/outputs
10-bit programmable dividers, 1 to 1024, all integers
Up to 4 differential outputs or 8 CMOS outputs
Pin strapping capability for hardwired programming at
power-up
<115 fs rms broadband random jitter (see Figure 25)
Additive output jitter: 41 fs rms typical (12 kHz to 20 MHz)
Excellent output-to-output isolation
OUT0
AD9508
DIV/Φ
OUT0
CLK
OUT1
DIV/Φ
CLK
OUT1
OUT2
DIV/Φ
OUT2
OUT3
DIV/Φ
SCLK/SCL/SC0
OUT3
CONTROL
SDIO/SDA/S1
INTERFACE
2
Automatic synchronization of all outputs
Single 2.5 V/3.3 V power supply
SDO/S3
SPI/I C/PINS
CS/C2
Internal LDO (low drop-out) voltage regulator for enhanced
power supply immunity
RESET
SYNC
PIN CONTROL
Phase offset select for output-to-output coarse delay adjust
3 programmable output logic levels, LVDS, HSTL, and CMOS
Serial control port (SPI/I2C) or pin-programmable mode
Space-saving 24-lead LFCSP
Figure 1.
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
GENERAL DESCRIPTION
The AD9508 provides clock fanout capability in a design that
emphasizes low jitter to maximize system performance. This
device benefits applications like clocking data converters with
demanding phase noise and low jitter requirements.
Each output has a programmable divider that can be bypassed
or be set to divide by any integer up to 1024. In addition, the
AD9508 supports a coarse output phase adjustment between the
outputs.
There are four independent differential clock outputs, each with
various types of logic levels available. Available logic types
include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS
(250 MHz). In 1.8 V CMOS output mode, the differential output
becomes two CMOS single-ended signals. The CMOS outputs
are 1.8 V logic levels, regardless of the operating supply voltage.
The device can also be pin programmed for various fixed
configurations at power-up without the need for SPI or IꢀC
programming.
The AD9508 is available in a 24-lead LFCSP and operates from
a either a single 2.5 V or 3.3 V supply. The temperature range is
−40°C to +85°C.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9508
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Programming Mode Selection.................................................. 21
Clock Input.................................................................................. 21
Clock Dividers ............................................................................ 23
Phase Delay Control .................................................................. 23
Reset Modes ................................................................................ 23
Power-Down Mode.................................................................... 23
Output Clock Synchronization................................................. 24
Power Supply............................................................................... 24
Thermally Enhanced Package Mounting Guidelines............ 24
Pin Strapping to Program Upon Power-Up................................ 25
Serial Control Port ......................................................................... 26
SPI/I²C Port Selection................................................................ 26
SPI Serial Port Operation.......................................................... 26
I2C Serial Port Operation .......................................................... 29
Register Map ................................................................................... 32
Register Map Bit Descriptions...................................................... 33
Serial Port Configuration (Register 0x00) .............................. 33
Silicon Revision (Register 0x0A to Register 0x0D) ............... 33
Chip Level Functions (Register 0x12 to Register 0x14)........ 33
OUT0 Functions (Register 0x15 to Register 0x1A)............... 34
OUT1 Functions (Register 0x1B to Register 0x20) ............... 35
OUT2 Functions (Register 0x21 to Register 0x26)................ 36
OUT3 Functions (Register 0x27 to Register 0x2C)............... 37
Packaging and Ordering Information ......................................... 38
Outline Dimensions................................................................... 38
Ordering Guide .......................................................................... 38
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Power Supply Current and Temperature Conditions .............. 3
Clock Inputs and Output DC Specifications ............................ 4
Output Driver Timing Characteristics ...................................... 5
Logic Inputs................................................................................... 6
Serial Port Specifications—SPI Mode........................................ 6
Serial Port Specifications—I2C Mode........................................ 7
External Resistor Values For Pin Strapping Mode................... 8
Clock Output Additive Phase Noise .......................................... 8
Clock Output Additive Time Jitter............................................. 9
Absolute Maximum Ratings ..................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Test Circuits..................................................................................... 19
Input/Output Termination Recommendations...................... 19
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 21
Detailed Block Diagram ............................................................ 21
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Changes to Table 9 ............................................................................ 9
Changes to Figure 10...................................................................... 14
Changes to Figure 15...................................................................... 15
Changes to Figure 24 and Figure 26............................................. 16
Changes to Figure 27, Figure 29 to Figure 32............................. 17
Changes to Figure 33...................................................................... 18
1/13—Revision 0: Initial Version
Rev. A | Page 2 of 40
Data Sheet
AD9508
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical values are given for VS = 3.3 V and 2.5 V and TA = 25°C; minimum and maximum values are given over the full VDD = 3.3 V + 5% down
to 2.5 V − 5% and TA = −40°C to +85°C variation; and input slew rate > 1 V/ns, unless otherwise noted.
POWER SUPPLY CURRENT AND TEMPERATURE CONDITIONS
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY VOLTAGE
2.375
2.5
3.465
V
Use supply voltage setting (2.5 V or 3.3 V) and
appropriate current consumption configura-
tion (see Current Consumption parameters in
Table 1) to calculate total power dissipation
CURRENT CONSUMPTION
LVDS Configuration
152
122
182
118
92
168
134
200
131
101
185
134
94
mA
mA
mA
mA
mA
mA
mA
mA
mA
Input clock: 1500 MHz in differential mode, all
LVDS output drivers at 1500 MHz
Input clock: 800 MHz in differential mode, all
LVDS output drivers at 200 MHz
Input clock: 1500 MHz in differential mode, all
HSTL output drivers at 1500 MHz
Input clock: 491.52 MHz in differential mode, all
output drivers at 491.52 MHz
Input clock: 122.88 MHz in differential mode, all
output drivers at 122.88 MHz
Input clock: 1500 MHz in differential mode, all
CMOS output drivers at 250 MHz, 10 pF load
Input clock: 800 MHz in differential mode, all
CMOS outputs drivers at 200 MHz, 10 pF load
Input clock: 100 MHz in differential mode, all
CMOS outputs drivers at 100 MHz, 10 pF load
HSTL Configuration
CMOS Configuration
141
122
85
Full Power-Down
6
10
TEMPERATURE
Ambient Temperature Range, TA
Junction Temperature, TJ
−40
+25
+85
115
°C
°C
Junction temperatures above 115°C can
degrade performance but no damage should
occur, unless the absolute temperature is
exceeded
Rev. A | Page 3 of 40
AD9508
Data Sheet
CLOCK INPUTS AND OUTPUT DC SPECIFICATIONS
Table 2.
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
CLOCK INPUTS
Differential Mode
Input Frequency
Input Sensitivity
0
360
1650
2200
MHz
Differential input
mV p-p As measured with a differential probe; jitter
performance improves with higher slew
rates (greater voltage swing)
Input Common-Mode Voltage
Input Voltage Offset
DC-Coupled Input Common-
Mode Range
VICM
0.95
0.58
1.05
30
1.15
1.67
V
Input pins are internally self biased, which
enables ac coupling
mV
V
VCMR
This is the allowable common-mode voltage
range when dc-coupled
Pulse Width
Low
High
303
303
5.0
ps
ps
kΩ
pF
µA
Input Resistance (Differential)
Input Capacitance
Input Bias Current (Each Pin)
CMOS CLOCK MODE (SINGLE-ENDED)
Input Frequency
Input Voltage
7
2
9
CIN
100
400
250
Full input swing
MHz
High
Low
VIH
VIL
VDD/2 − 0.15
V
V
VDD/2 + 0.15
Input Current
High
Low
IINH
IINL
CIN
1
µA
µA
pF
−142
2
Input Capacitance
LVDS CLOCK OUTPUTS
Termination = 100 Ω differential (OUTx, OUTx)
Output Frequency
Output Voltage Differential
1650
454
MHz
mV
VOD
247
375
VOH − VOL measurement across a differential
pair at the default amplitude setting with
output driver not toggling; see Figure 6 for
variation over frequency
Delta VOD
ΔVOD
50
mV
This is the absolute value of the difference
between VOD when the normal output is high
vs. when the complementary output is high
Offset Voltage
Delta VOS
VOS
ΔVOS
1.125
1.18
1.375
50
V
mV
(VOH + VOL)/2 across a differential pair
This is the absolute value of the difference
between VOS when the normal output is high
vs. when the complementary output is high
Short-Circuit Current
LVDS Duty Cycle
ISA, ISB
13.6
50.1
24
55
61
mA
%
%
Each pin (output shorted to GND)
Up to 750 MHz input
750 MHz to1500 MHz input
1650 MHz input
45
39
%
HSTL CLOCK OUTPUTS
100 Ω across differential pair; default
amplitude setting
Output Frequency
1650
978
971
55
MHz
mV
mV
%
Differential Output Voltage
Common-Mode Output Voltage
HSTL Duty Cycle
VO
VOCM
859
905
45
925
940
VOH − VOL with output driver static
(VOH + VOL)/2 with output driver static
Up to 750 MHz input
40
60
%
%
750 MHz to 1500 MHz input
1650 MHz input
50.9
Rev. A | Page 4 of 40
Data Sheet
AD9508
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
CMOS CLOCK OUTPUTS
Single-ended; termination = open; OUTx
and OUTx in phase
Output Frequency
250
MHz
With 10 pF load per output, see Figure 14
for swing vs. frequency
Output Voltage
@ 1 mA Load
High
Low
@ 10 mA load
High
VOH
VOL
1.7
1.2
V
V
0.1
0.6
VOH
VOL
V
V
Low
@ 10 mA Load (2 × CMOS Mode)
High
Low
CMOS Duty Cycle
VOH
VOL
1.45
45
V
V
%
0.35
55
Up to 250 MHz
OUTPUT DRIVER TIMING CHARACTERISTICS
Table 3.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions/Comments
LVDS OUTPUTS
Termination = 100 Ω differential, 1 × LVDS
20% to 80% measured differentially
Output Rise/Fall Time
Propagation Delay, Clock-to-LVDS Output
Temperature Coefficient
Output Skew1
All LVDS Outputs
On the Same Part
tR, tF
tPD
152
2.01
2.8
177
2.43
ps
ns
ps/°C
1.56
1.59
2.04
48
781
ps
ps
Across Multiple Parts
Assumes same temperature and supply;
takes into account worst-case propaga-
tion delay delta due to worst-case
process variation
HSTL OUTPUTS
Termination = 100 Ω differential, 1 × HSTL
20% to 80% measured differentially
Output Rise/Fall Time
Propagation Delay, Clock-to-HSTL Output
Temperature Coefficient
Output Skew1
All HSTL Outputs
On the Same Part
tR, tF
tPD
118
2.05
2.9
143
2.5
ps
ns
ps/°C
59
825
ps
ps
Across Multiple Parts
Assumes same temperature and supply;
takes into account worst-case propaga-
tion delay delta due to worst-case
process variation
CMOS OUTPUTS
Output Rise/Fall Time
Propagation Delay, Clock-to-CMOS Output
Temperature Coefficient
Output Skew1
tR, tF
tPD
1.18
2.56
3.3
1.45
3.07
ns
ns
ps/°C
20% to 80%; CLOAD = 10 pF
10 pF load
All CMOS Outputs
On the Same Part
Across Multiple Parts
112
965
ps
ps
Assumes same temperature and supply;
takes into account worst-case
propagation delay delta due to worst-
case process variation
Rev. A | Page 5 of 40
AD9508
Data Sheet
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions/Comments
OUTPUT LOGIC SKEW1
CMOS load = 10 pF and LVDS load = 100 Ω
LVDS Output(s) and HSTL Output(s)
77
119
700
622
ps
ps
ps
Outputs on the same device; assumes
worst-case output combination
Outputs on the same device; assumes
worst-case output combination
Outputs on the same device; assumes
worst-case output combination
LVDS Output(s) and CMOS Output(s)
HSTL Output(s) and CMOS Output(s)
497
424
1 Output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
LOGIC INPUTS
Table 4.
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
RESET SYNC
, IN_SEL
LOGIC INPUTS
,
Input Voltage
High
VIH
VIL
1.7
2.0
V
V
V
V
2.5 V supply voltage operation
3.3 V supply voltage operation
2.5 V supply voltage operation
3.3 V supply voltage operation
Low
0.7
0.8
Input Current
Input Capacitance
IINH, IINL
CIN
−300
+100 µA
pF
2
SERIAL PORT SPECIFICATIONS—SPI MODE
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CS
SCLK has a 200 kΩ internal pull-down resistor
Input Voltage
Logic 1
Logic 0
VDD − 0.4
V
V
0.4
Input Current
Logic 1
Logic 0
Input Capacitance
SCLK
−4
−85
2
µA
µA
µA
Input Voltage
Logic 1
Logic 0
VDD − 0.4
V
V
0.4
Input Current
Logic 1
Logic 0
Input Capacitance
SDIO
70
13
2
µA
µA
pF
As Input
Input Voltage
Logic 1
Logic 0
VDD − 0.4
V
V
0.4
Input Current
Logic 1
Logic 0
−1
−1
2
µA
µA
pF
Input Capacitance
Rev. A | Page 6 of 40
Data Sheet
AD9508
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
As Output
Output Voltage
Logic 1
Logic 0
VDD − 0.4
V
V
1 mA load current
1 mA load current
0.4
SDO
Output Voltage
Logic 1
Logic 0
VDD − 0.4
V
V
1 mA load current
1 mA load current
0.4
30
TIMING
SCLK
Clock Rate, 1/tCLK
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup (tS)
CS to SCLK Hold (tC)
CS Minimum Pulse Width High
MHz
ns
ns
ns
ns
4.6
3.5
2.9
0
15
ns
ns
3.4
0
ns
3.4
ns
SERIAL PORT SPECIFICATIONS—I2C MODE
Table 6.
Parameter
Min
Typ
Max
Unit Test Conditions/Comments
SDA, SCL (AS INPUT)
Input Voltage
Logic 1
Logic 0
Input Current
Hysteresis of Schmitt Trigger Inputs
SDA (AS OUTPUT)
Output Logic 0 Voltage
Output Fall Time from VIH (MIN) to VIL (MAX)
TIMING
VDD − 0.4
V
V
µA
0.4
0
−40
150
For VIN = 10% to 90% DVDD3
mV
0.4
250
V
ns
IO = 3 mA
10 pF ≤ Cb ≤ 400 pF
SCL Clock Rate
Bus-Free Time Between a Stop and Start
Condition, tBUF
Repeated Start Condition Setup Time, tSU; STA
Repeated Hold Time Start Condition, tHD; STA
400
0.6
kHz
µs
1.3
0.6
µs
µs
After this period, the first clock pulse is
generated
Stop Condition Setup Time, tSU; STO
Low Period of the SCL Clock, tLOW
High Period of the SCL Clock, tHIGH
Data Setup Time, tSU; DAT
0.6
1.3
0.6
100
0
µs
µs
µs
ns
µs
Data Hold Time, tHD; DAT
0.9
Rev. A | Page 7 of 40
AD9508
Data Sheet
EXTERNAL RESISTOR VALUES FOR PIN STRAPPING MODE
Table 7.
Parameter
Resistor Polarity
Min
Typ
820
1.8
3.9
8.2
820
1.8
3.9
8.2
Max
Unit
Test Conditions/Comments
EXTERNAL RESISTORS
Voltage Level 0
Voltage Level 1
Voltage Level 2
Voltage Level 3
Voltage Level 4
Voltage Level 5
Voltage Level 6
Voltage Level 7
Using 10% tolerance resistor
Pull down to ground
Pull down to ground
Pull down to ground
Pull down to ground
Pull up to VDD
Ω
kΩ
kΩ
kΩ
Ω
Pull up to VDD
Pull up to VDD
Pull up to VDD
kΩ
kΩ
kΩ
CLOCK OUTPUT ADDITIVE PHASE NOISE
Table 8.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLK-TO-HSTL OR LVDS ADDITIVE PHASE NOISE
CLK = 1474.56 MHz, OUTx = 1474.56 MHz
Divide Ratio = 1
Input slew rate > 1 V/ns
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 100 MHz Offset
−88
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−100
−109
−116
−135
−144
−148
−149
CLK-TO-HSTL OR LVDS or CMOS ADDITIVE PHASE NOISE
CLK = 625 MHz, OUTx = 125 MHz
Divide Ratio = 5
Input slew rate > 1 V/ns
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 20 MHz Offset
−114
−125
−133
−141
−159
−162
−163
−163
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
CLK-TO-HSTL OR LVDS ADDITIVE PHASE NOISE
CLK = 491.52 MHz, OUTx = 491.52 MHz
Divide Ratio = 1
Input slew rate > 1 V/ns
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 20 MHz Offset
−100
−111
−120
−127
−146
−153
−153
−153
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 8 of 40
Data Sheet
AD9508
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 9.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz, Outputs = 622.08 MHz
41
70
69
93
144
142
105
209
206
184
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
BW = 12 kHz to 20 MHz
BW = 20 kHz to 80 MHz
BW = 50 kHz to 80 MHz
BW = 12 kHz to 20 MHz
BW = 20 kHz to 80 MHz
BW = 50 kHz to 80 MHz
BW = 12 kHz to 20 MHz
BW = 20 kHz to 80 MHz
BW = 50 kHz to 80 MHz
BW = 12 kHz to 20 MHz
CLK = 622.08 MHz, Outputs = 155.52 MHz
CLK = 125 MHz, Outputs = 125 MHz
CLK = 400 MHz, Outputs = 50 MHz
HSTL OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz, Outputs = 622.08 MHz
41
56
72
70
76
87
158
156
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
BW = 12 kHz to 20 MHz
BW = 100 Hz to 20 MHz
BW = 20 kHz to 80 MHz
BW = 50 kHz to 80 MHz
BW = 12 kHz to 20 MHz
BW = 100 Hz to 20 MHz
BW = 20 kHz to 80 MHz
BW = 50 kHz to 80 MHz
CLK = 622.08 MHz, Outputs = 155.52 MHz
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 100 MHz, Outputs = 100 MHz
91
fs rms
BW = 12 kHz to 20 MHz
Rev. A | Page 9 of 40
AD9508
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Table 10.
Parameter
Rating
Values of θJB are provided for package comparison and PCB
design considerations.
Supply Voltage (VDD)
3.6 V
Maximum Digital Input Voltage
CLK and CLK
−0.5 V to VDD + 0.5 V
−0.5 V to VDD + 0.5 V
−0.5 V to VDD + 0.5 V
−65°C to +150°C
−40°C to +85°C
300°C
THERMAL CHARACTERISTICS
Maximum Digital Output Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Thermal characteristics established using JEDEC51-7 and
JEDEC51-5 2S2P test boards.
Table 11. Thermal Characteristics, 24-Lead LFCSP
150°C
Thermal Characteristic
(JEDEC51-7 and JEDEC51-5 2S2P
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Symbol Test Boards1)
Value2 Unit
θJA
Junction-to-ambient thermal
resistance per JEDEC JESD51-2 (still
air)
Junction-to-ambient thermal
resistance, 1.0 m/sec airflow per
JEDEC JESD51-6 (moving air)
Junction-to-ambient thermal
resistance, 2.5 m/sec airflow per
JEDEC JESD51-6 (moving air)
Junction-to-board thermal
resistance per JEDEC JESD51-8 (still
air)
Junction-to-case thermal resistance
(die-to-heat sink) per MIL-STD-883,
Method 1012.1
Junction-to-top-of-package
characterization parameter per
JEDEC JESD51-2 (still air)
43.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJMA
θJMA
θJB
40
38.5
16.2
7.1
The following equation determines the junction temperature on
the application PCB:
TJ = TCASE + (ΨJT × PD)
where:
θJC
TJ is the junction temperature (°C).
T
CASE is the case temperature (°C) measured by the customer at
the top center of the package.
ΨJT is the value as indicated in Table 11.
PD is the power dissipation.
ΨJT
0.33
1 The exposed pad on the bottom of the package must be soldered to ground
(VSS) to achieve the specified thermal performance.
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order approxi-
mation of TJ by the following equation:
2 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal
performance for actual applications requires careful inspection of the
conditions in the application to determine if they are similar to those
assumed in these calculations.
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
ESD CAUTION
Rev. A | Page 10 of 40
Data Sheet
AD9508
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
18 RESET
OUT3
CS/S2
OUT0 2
17
16 OUT3
3
OUT0
SDO/S3
EXT_CAP0
VDD
AD9508
TOP VIEW
15 PROG_SEL
14 EXT_CAP1
4
5
6
VDD
13
NOTES
1. THE EXPOSED DIE PAD MUST BE CONNECTED
TO GROUND (VSS).
Figure 2. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CS/S2
Chip Select/Pin Programming. Multipurpose pin. This pin is controlled by the PROG_SEL pin. Chip
Select (CS) is an active logic low CMOS input used in the SPI operation mode. When programming a
device via SPI mode, CS must be held low. In systems where more than one AD9508 is present, this pin
enables individual programming of each AD9508. In pin programming mode, this pin becomes S2. In
this mode, S2 is hard wired with a resistor to either VDD or ground. The resistor value and resistor
biasing determine the channel divider value for the outputs on Pin 11 and Pin 12. See the Pin Strapping
to Program on Power-Up section for more details.
2
3
4
OUT0
OUT0
LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output.
SDO/S3
Serial Data Output/Pin Programming. Multipurpose pin. This pin is controlled by the PROG_SEL pin.
SDO is configured as an output to read back the internal register settings in SPI mode operation. In pin
programming mode, this pin becomes S3, which is hard wired with a resistor to either VDD or ground.
The resistor value and resistor biasing determine the channel divider value for the outputs on Pin 16
and Pin 17. See the Pin Strapping to Program on Power-Up section for more details.
5
6
7
8
9
EXT_CAP0
VDD
OUT1
OUT1
S4
Node for External Decoupling Capacitor for LDO. Tie this pin to a 0.47 μF capacitor to ground.
Power Supply (2.5 V or 3.3 V Operation).
LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Pin Programming. Use this pin in pin programming mode only. The PROG_SEL pin determines which
programming mode is used. In pin programming mode, S4 is hardwired with a resistor to either VDD or
ground. The resistor value and resistor biasing determine the output logic levels used for the outputs
on Pin 2, Pin 3, Pin 7, and Pin 8. See the Pin Strapping to Program on Power-Up section for more details.
10
S5
Pin Programming. Use this pin in pin programming mode only. The PROG_SEL pin determines which
programming mode is used. In pin programming mode, S5 is hardwired with a resistor to either VDD or
ground. The resistor value and resistor biasing determine the output logic levels used for the outputs
on Pin 11, Pin 12, Pin 16, and Pin 17. See the Pin Strapping to Program on Power-Up section for more
details.
11
12
13
14
15
OUT2
OUT2
LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Power Supply (2.5 V or 3.3 V Operation).
Node for External Decoupling Capacitor for LDO. Tie this pin to a 0.47 μF capacitor to ground.
Three-State CMOS Input. Pin 15 selects the type of device programming interface to be used (SPI, I2C,
or pin programming).
VDD
EXT_CAP1
PROG_SEL
16
17
OUT3
OUT3
LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Rev. A | Page 11 of 40
AD9508
Data Sheet
Pin No.
Mnemonic
Description
18
RESET
CMOS Input. Device Reset. When this active low pin is asserted, the internal register settings enter their
default state after the RESET is released. Note that RESET also serves as a power-down of the device
while an active low signal is applied to the pin. The RESET pin has an internal 24 kΩ pull-up resistor.
19
SCLK/SCL/S0
Serial Programming Clock/Data Clock/Programming Pin. Multipurpose pin controlled by the PROG_SEL
pin used for serial programming clock (SCLK) in SPI mode or data clock (SCL) for serial programming in
I2C Mode. The PROG_SEL pin determines which programming mode is used. In pin programming
mode, this pin becomes S0. In this mode, S0 is hardwired with a resistor to either VDD or ground. The
resistor value and resistor biasing determine the channel divider values for the outputs on Pin 2 and
Pin 3. See the Pin Strapping to Program on Power-Up section for more details.
20
21
SYNC
CLK
Clock Synchronization. When this pin is active low, the output drivers are held static and then
synchronized on a low-to-high transition of this pin. The SYNC pin has an internal 24 kΩ pull-up
resistor.
Differential Clock Input or Single-Ended CMOS Input. Whether this pin serves as the differential clock
input or the single-ended CMOS input depends on the logic state of the IN_SEL pin.
22
23
CLK
Complementary Differential Clock Input.
IN_SEL
CMOS Input. A logic high configures the CLK and CLK inputs for a differential input signal. A logic low
configures the input for single-ended CMOS applied to the CLK pin. AC-couple the unused CLK to
ground with a 0.1 μF capacitor.
24
SDIO/SDA/S1
Serial Data Input and Output (SPI)/Serial Data (I2C)/Pin Programming. Pin 24 is a multipurpose input
controlled by the PROG_SEL pin used for SPI (SDIO), I2C (SDA), and pin strapping modes (S1). When the
device is in 4-wire SPI mode, data is written via SDIO. In 3-wire mode, both data reads and writes occur
on this pin. There is no internal pull-up/pull-down resistor on this pin. In I2C mode, SDA serves as the
serial data pin. The PROG_SEL pin determines which programming mode is used. In pin programming
mode, this pin becomes S1. In this mode, S1 is hardwired with a resistor to either VDD or ground. The
resistor value and resistor biasing determine the channel divider values for the outputs on Pin 7 and
Pin 8. See the Pin Strapping to Program on Power-Up section for more details.
EP
Exposed Pad. The exposed die pad must be connected to ground (VSS).
Rev. A | Page 12 of 40
Data Sheet
AD9508
TYPICAL PERFORMANCE CHARACTERISTICS
800
700
600
500
400
TIME (250ps/DIV)
100
300
500
700
900
1100
1300
1500
FREQUENCY (MHz)
Figure 6. LVDS Differential Output Swing vs. Frequency
Figure 3. LVDS Differential Output Waveform @ 800 MHz
800
780
760
740
720
700
TIME (1.5ns/DIV)
2.3
2.5
2.7
2.9
3.1
3.3
3.5
POWER SUPPLY (V)
Figure 7. LVDS Differential Output Swing vs. Power Supply Voltage
Figure 4. LVDS Differential Output Waveform @ 156.25 MHz
200
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
ONE OUTPUT (mA)
TWO OUTPUTS (mA)
THREE OUTPUTS (mA)
FOUR OUTPUTS (mA)
150
100
50
0
0
400
800
1200
1600
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (MHz)
INPUT DIFFERENTIAL (V p-p)
Figure 5. Power Supply Current vs. Frequency and Number of Outputs Used,
LVDS
Figure 8. LVDS Propagation Delay vs. Input Differential Voltage
Rev. A | Page 13 of 40
AD9508
Data Sheet
2.6
2.4
2.2
2.0
1.8
1.6
1.4
300
TIME (5ns/DIV)
500
700
900
1100
1300
1500
COMMON-MODE VOLTAGE (mV)
Figure 12. CMOS Output Waveform @ 50 MHz with 10 pF Load
Figure 9. LVDS Propagation Delay vs. Input Common-Mode Voltage
125
60
DIVIDER 1
ONE OUTPUT (mA)
TWO OUTPUTS (mA)
THREE OUTPUTS (mA)
FOUR OUTPUTS (mA)
FIVE OUTPUTS (mA)
DIVIDER 2 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 800MHz)
DIVIDER 3 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 500MHz)
100
55
50
45
40
SIX OUTPUTS (mA)
SEVEN OUTPUTS (mA)
EIGHT OUTPUTS (mA)
75
50
25
25
50
75
100
125
150
175
200
225
250
0
200
400
600
800
1000
1200
1400
1600
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. Power Supply Current vs. Frequency vs. Number of Outputs Used,
CMOS
Figure 10. LVDS Output Duty Cycle vs. Output Frequency
1.9
300Ω LOAD
500Ω LOAD
750Ω LOAD
1kΩ LOAD
1.8
1.7
1.6
1.5
1.4
TIME (1.25ns/DIV)
0
50
100
150
200
250
FREQUENCY (MHz)
Figure 11. CMOS Output Waveform @ 200 MHz with 10 pF Load
Figure 14. CMOS Output Swing vs. Frequency and Resistive Load
Rev. A | Page 14 of 40
Data Sheet
AD9508
2.0
1.8
1.6
1.4
1.2
–40°C
+25°C
+85°C
1.0
0
50
100
150
200
250
TIME (1.5ns/DIV)
FREQUENCY (MHz)
Figure 15. CMOS Output Swing vs. Frequency and Temperature (10 pF Load)
Figure 18. HSTL Differential Output Waveform @ 156.25 MHz
1.9
200
ONE OUTPUT (mA)
TWO OUTPUTS (mA)
THREE OUTPUTS (mA)
FOUR OUTPUTS (mA)
1.7
1.5
1.3
150
100
50
2pF LOAD
5pF LOAD
10pF LOAD
20pF LOAD
1.1
0
0
50
100
150
200
250
0
400
800
FREQUENCY (MHz)
1200
1600
FREQUENCY (MHz)
Figure 16. CMOS Output Swing vs. Frequency and Capacitive Load
(2 pF, 5 pF, 10 pF, 20 pF)
Figure 19. Power Supply Current vs. Frequency and Number of Outputs Used,
HSTL
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
TIME (250ps/DIV)
100
300
500
700
900
1100
1300
1500
FREQUENCY (MHz)
Figure 20. HSTL Differential Output Swing vs. Frequency
Figure 17. HSTL Differential Output Waveform @ 800 MHz
Rev. A | Page 15 of 40
AD9508
Data Sheet
2.0
1.9
1.8
1.7
1.6
60
55
50
45
40
DIVIDER 1
DIVIDER 2 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 800MHz)
DIVIDER 3 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 500MHz)
1.5
2.3
0
200
400
600
800
1000
1200
1400
1600
2.5
2.7
2.9
3.1
3.3
3.5
FREQUENCY (MHz)
POWER SUPPLY (V)
Figure 21. HSTL Differential Output Swing vs. Power Supply Voltage
Figure 24. HSTL Output Duty Cycle vs. Output Frequency
150
140
130
120
110
100
90
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
80
0
2
4
6
8
10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
SLEW RATE (V/ns)
INPUT DIFFERENTIAL (V p-p)
Figure 25. Additive Broadband Jitter vs. Input Slew Rate, LVDS, HSTL
(Calculated from SNR of ADC Method)
Figure 22. HSTL Propagation Delay vs. Input Differential Voltage
–80
2.6
2.4
2.2
2.0
1.8
1.6
1.4
HSTL 155.52MHz
HSTL 311.04MHz
–90
–100
–110
–120
–130
–140
–150
–160
–170
HSTL 622.08MHz
10
100
1k
10k
100k
1M
10M
100M
300
500
700
900
1100
1300
1500
FREQUENCY OFFSET (Hz)
COMMON-MODE VOLTAGE (mV)
Figure 26. Absolute Phase Noise in HSTL Mode with Clock Input @
622.08 MHz and Outputs = 622.08 MHz, 311.04 MHz, 155.52 MHz
Figure 23. HSTL Propagation Delay vs. Input Common-Mode Voltage
Rev. A | Page 16 of 40
Data Sheet
AD9508
–80
–80
–90
LVDS 155.52MHz
LVDS 311.04MHz
LVDS 622.08MHz
MARKER
FREQUENCY AMPLITUDE
–90
1. 10Hz
2. 100Hz
3. 1kHz
4. 10kHz
5. 100.5kHz
6. 1MHz
7. 10MHz
–116.04dBc/Hz
–126.68dBc/Hz
–135.27dBc/Hz
–142.56dBc/Hz
–159.42dBc/Hz
–161.97dBc/Hz
–164.55dBc/Hz
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
1
2
3
4
5
6
7
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
FREQUENCY (Hz)
Figure 27. Absolute Phase Noise in LVDS Mode with Clock Input @
622.08 MHz and Outputs = 622.08 MHz, 311.04 MHz, 155.52 MHz
Figure 30. Additive Phase Noise with Clock Input = 1500 MHz with HSTL
Outputs = 100 MHz
–80
–90
–80
MARKER
FREQUENCY AMPLITUDE
–90
1. 10Hz
2. 100Hz
3. 1kHz
4. 10kHz
5. 100.5kHz
6. 1MHz
7. 10MHz
8. 20MHz
–112.35dBc/Hz
–118.81dBc/Hz
–127.84dBc/Hz
–135.97dBc/Hz
–151.91dBc/Hz
–157.87dBc/Hz
–159.78dBc/Hz
–157.88dBc/Hz
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
1
2
3
4
5
6
8
7
1
1000
100000
10000000
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (MHz)
FREQUENCY (Hz)
Figure 31. Additive Phase Noise with Clock Input = 622.08 MHz with HSTL
Outputs = 155.52 MHz
Figure 28. Absolute Phase Noise of Clock Source @ 622.08 MHz
–80
–80
MARKER
FREQUENCY AMPLITUDE
MARKER
FREQUENCY AMPLITUDE
1
–90
–90
1. 10Hz
2. 100Hz
3. 1kHz
4. 10kHz
5. 100kHz
6. 1MHz
7. 10MHz
8. 100MHz
–89.57dBc/Hz
–100.45dBc/Hz
–109.97dBc/Hz
–116.93dBc/Hz
–135.33dBc/Hz
–144.39dBc/Hz
–148.66dBc/Hz
–149.78dBc/Hz
1. 10Hz
2. 100Hz
3. 1kHz
4. 10kHz
5. 100.5kHz
6. 1MHz
7. 10MHz
8. 20MHz
–100.17dBc/Hz
–109.18dBc/Hz
–117.67dBc/Hz
–124.94dBc/Hz
–143.83dBc/Hz
–151.64dBc/Hz
–153.81dBc/Hz
–152.87dBc/Hz
1
2
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
3
2
4
3
4
5
7
6
5
8
6
7
8
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32. Additive Phase Noise with Clock Input = 622.08 MHz with LVDS
Outputs = 622.08 MHz
Figure 29. Additive Phase Noise with Clock Input = 1474.56 MHz with HSTL
Outputs = 1474.76 MHz
Rev. A | Page 17 of 40
AD9508
Data Sheet
–80
MARKER
FREQUENCY AMPLITUDE
–90
1. 10Hz
2. 100Hz
3. 1kHz
4. 10kHz
5. 100.5kHz
6. 1MHz
7. 10MHz
8. 20MHz
–114.15dBc/Hz
–127.18dBc/Hz
–134.13dBc/Hz
–141.63dBc/Hz
–154.66dBc/Hz
–155.37dBc/Hz
–152.86dBc/Hz
–153.09dBc/Hz
–100
–110
–120
–130
–140
–150
–160
–170
1
2
3
4
7
8
5
6
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 33. Additive Phase Noise with Clock Input = 100 MHz with CMOS
Outputs = 100 MHz
Rev. A | Page 18 of 40
Data Sheet
AD9508
TEST CIRCUITS
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
CLK
0.1µF
0.1µF
DOWNSTREAM
100Ω
AD9508
DEVICE
WITH HIGH
IMPEDANCE
INPUT AND
INTERNAL
DC-BIAS
CLK
100Ω
AD9508
HSTL OR
LVDS
CLK
CLK
100Ω
AD9508
Figure 34. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configurations
Figure 38. AC-Coupled LVDS or HSTL Output Driver (100 Ω Resistor Can Go
on Either Side of Decoupling Capacitors Placed As Close As Possible To The
Destination Receiver)
V
CC
Z
= 50Ω
0
LVDS OR 1.8V HSTL
HIGH-IMPEDANCE
DIFFERENTIAL
RECEIVER
CLK
CLK
SINGLE-ENDED
(NOT COUPLED)
AD9508
HSTL OR
LVDS
100Ω
AD9508
Z
= 50Ω
0
V
CC
CLK
CLK
AD9508
Figure 35. Typical AC-Coupled or DC-Coupled CML Configurations
Figure 39. DC-Coupled LVDS or HSTL Output Driver
V
= 3.3V
S
CLK
AD9508
82Ω
82Ω
Z
= 50Ω
0
0.1µF
0.1µF
CLK
50Ω 50Ω
3.3V
LVPECL
SINGLE-ENDED
(NOT COUPLED)
AD9508
1.8V
V
– 2V
HSTL
CC
Z
= 50Ω
0
127Ω
127Ω
CLK
CLK
AD9508
50Ω 50Ω
V
– 2V
CC
Figure 40. Interfacing the HSTL Driver to a 3.3 V LVPECL Input (This method
incorporates impedance matching and dc biasing for bipolar LVPECL
receivers. If the receiver is self-biased, the termination scheme shown in
Figure 38 is recommended.)
Figure 36. Typical AC-Coupled or DC-Coupled LVPECL Configurations
CLK
AD9508
CLK
Figure 37. Typical 1.8 V CMOS Configurations for Short Trace Lengths
Rev. A | Page 19 of 40
AD9508
Data Sheet
TERMINOLOGY
varies. In a square wave, the time jitter is a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or one
sigma of the Gaussian distribution.
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and an even progression phase with time from 0 degrees to
360 degrees for each cycle. Actual signals, however, display a
certain amount of variation from ideal phase progression over
time. This phenomenon is phase jitter. Although many causes
can contribute to phase jitter, one major cause is random noise,
characterized statistically as being Gaussian (normal) in
distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the SNR and dynamic range of the converter.
A sampling clock with the lowest possible jitter provides the
highest performance from a given converter.
Phase jitter leads to a spreading out of the energy of the sine wave
in the frequency domain, producing a continuous power spec-
trum. This power spectrum is usually reported as a series of
values whose units are dBc/Hz at a given offset in frequency
from the sine wave (carrier). The value is a ratio (expressed in
dB) of the power contained within a 1 Hz bandwidth with respect
to the power at the carrier frequency. For each measurement,
the offset from the carrier frequency is also given.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable only to the device or subsystem being measured.
The residual phase noise system makes use of two devices
operating in perfect quadrature. The correlated noise of any
external components common to both devices (such as clock
sources) is not present. This makes it possible to predict the
degree to which the device is going to affect the total system
phase noise when used in conjunction with the various oscillators
and clock sources, each of which contribute their own phase
noise to the total. In many cases, the phase noise of one element
dominates the system phase noise.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise contained within that offset frequency
interval.
Additive Time Jitter
Additive time jitter refers to the amount of time jitter that is
attributable to the device or subsystem being measured. It is
calculated by integrating the additive phase noise over a specific
range. This makes it possible to predict the degree to which the
device is going to impact the total system time jitter when used
in conjunction with the various oscillators and clock sources,
each of which contribute their own time jitter to the total. In
many cases, the time jitter of the external oscillators and clock
sources dominates the system time jitter.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as with time jitter. When
observing a sine wave, the time of successive zero crossings
Rev. A | Page 20 of 40
Data Sheet
AD9508
THEORY OF OPERATION
DETAILED BLOCK DIAGRAM
VDD
LDO
EXT_CAP0
LVDS/HSTL/CMOS
OUTPUTS
SUB LDO
CLK
CLK
OUT0
OUT0
10-BIT
DIVIDER
11-BIT
∆Φ
OUT1
OUT1
11-BIT
∆Φ
10-BIT
DIVIDER
IN_SEL
2
SPI/I C/PIN_
PROG_SEL
REVISION ID
PROG
OUT2
OUT2
11-BIT
∆Φ
10-BIT
DIVIDER
CS/S2
SCLK/SCL/S0
SPI
INTERFACE
OUT3
OUT3
DIGITAL LOGIC
AND
REGISTERS
SDIO/SDA/S1
SDO/S3
S4
11-BIT
∆Φ
10-BIT
DIVIDER
SUB LDO
LDO
SCL
SDA
EXT_CAP1
VDD
S5
2
I C
INTERFACE
6
COARSE
A/D
PIN PROGRAM
READ CONTROL
SYNC
RESET
Figure 41. Detailed Block Diagram
The AD9508 accepts either a differential input clock applied to
CLK
applied to the CLK pin. The input clock signal is sent to the clock
distribution section, which has programmable dividers and
phase offset adjustment. The clock distribution section operates
at speeds of up to 1650 MHz.
The divider range under SPI or I2C control ranges from 1 to
divide-by-1024 and the phase offset adjustment is equipped with
11 bits of resolution. However, in pin programming mode, the
divider range is limited to a maximum divide-by-16 and there is
no phase offset adjustment available.
PROGRAMMING MODE SELECTION
the CLK and
pins or a single-ended 1.8 V CMOS clock
The AD9508 supports both SPI and IꢀC protocols, and a pin
strapping option to program the device. The active interface
depends on the logic state of the PROG_SEL pin. See Table 13
for programming mode selections. See the Serial Control Port
and Pin Strapping to Program on Power-Up sections for more
detailed information.
Table 13. SPI/I2C/Pin Serial Port Setup
PROG_SEL
SPI/I²C/Pin
Float
SPI
Logic 0
Logic 1
I²C
The outputs can be configured to as many as four LVDS/HSTL
differential outputs or as many as eight 1.8 V CMOS single-
ended outputs. In addition, the output current for the different
outputs is adjustable for output drive strength.
Pin programming control
CLOCK INPUT
The IN_SEL pin controls the desired input clock configuration.
When the IN_SEL pin is set for single-ended operation, the
device expects 1.8 V, 2.5 V, or 3.3 V CMOS-compatible logic
levels on the CLK input pin. Bypass the unused
ground with a 0.1 μF capacitor.
The device can be powered with either a 3.3 V or 2.5 V external
supply; however, the internal supply on the chip runs off an
internal 1.8 V LDO, delivering high performance with minimal
power consumption.
CLK
pin to
When the IN_SEL pin is set for differential input clock mode,
the inputs of the AD9508 are internally self biased. The internal
Rev. A | Page 21 of 40
AD9508
Data Sheet
V
V
DD
DD
inputs have a resistor divider, which sets the common-mode
level. The complementary input is biased about 30 mV lower
than the true input to avoid oscillations in the event that the
input signal ceases. See Figure 42 for the equivalent differential
input circuit.
OUTxA
OUTxB
V
DD
12.5kΩ
13kΩ
16kΩ
Figure 44. CMOS Equivalent Output Circuit
CLK
16.5kΩ
CLK
In LVDS or HSTL modes, there are register settings to control the
output logic type and current drive strength. The LVDS output
current can be set to the nominal 3.5 mA, additional settings
include 0.5, 0.75, 1.0 (default), and 1.25 multiplied by 3.5 mA.
The HSTL output current can be set to 8 mA (nominal) or
16 mA (double amplitude). For pin programming mode, see the
Pin Strapping to Program on Power-Up section for details and
limitations of the device. Under pin programming mode, the
nominal current is the default setting and is nonadjustable.
GND
Figure 42. AD9508 Differential Input Stage
The inputs can be ac-coupled or dc-coupled in differential
mode. See Table 14 for input logic compatibility. The user can
supply a single-ended input with the input in differential mode
by ac or dc coupling to one side of the differential input and
bypassing the other input to ground by a capacitor.
Note that jitter performance degrades with low input slew rate,
as shown in Figure 25. See Figure 34 through Figure 37 for
different input clock termination schemes.
When routing single-ended CMOS signals, avoid driving multiple
input receivers with one output. Series termination at the source
is generally required to provide transmission line matching and/or
to reduce current transients at the driver. The value of the series
resistor is dependent on the board design and timing require-
ments (typically 10 Ω to 100 Ω). CMOS outputs are also limited in
terms of the capacitive load or trace length that they can drive.
Typically, trace lengths less than 3 inches are recommended to
preserve signal rise/fall times and signal integrity.
CLOCK OUTPUTS
Each channel output driver can be configured for either a
differential LVDS/HSTL output or two single-ended CMOS
outputs. When the LVDS/HSTL driver is enabled, the
corresponding CMOS driver is in tristate. When the CMOS
driver is enabled, the corresponding LVDS/HSTL driver is
powered down and tristated. See Figure 43 and Figure 44 for
the equivalent output stages.
60.4Ω
(1.0 INCH)
10Ω
CMOS
AD9508
MICROSTRIP
V
DD
Figure 45. Series Termination of CMOS Output
OUTx
OUTx
Figure 43. LVDS/HSTL Output Simplified Equivalent Circuit
CLK
Table 14. CLK and
Differential Input Logic Compatibility
Supply (V)
Logic
CML
CML
CML
CMOS
CMOS
CMOS
HSTL
Common Mode (V)
Output Swing (V)
AC-Coupled
Yes
Yes
DC-Coupled
Not allowed
Not allowed
Yes
Yes
Yes
Yes
Yes
3.3
2.5
1.8
2.9
2.1
1.4
1.65
1.25
0.9
0.75
1.25
2.0
0.8
0.8
0.8
3.3
2.5
1.8
0.75
0.4
0.8
0.8
0.8
Yes
3.31
F
Not allowed
Not allowed
Not allowed
Yes
Yes
Yes
2.51
1.81
1.5
N/A2
3.3
F
LVDS
Yes
Not allowed
Yes
LVPECL
LVPECL
LVPECL
2.5
1.8
1.2
0.5
Yes
Yes
Yes
1 IN_SEL is set for single-ended CMOS mode.
2 N/A means not applicable.
Rev. A | Page 22 of 40
Data Sheet
AD9508
CLOCK DIVIDERS
RESET MODES
The four independent channel dividers are 10-bit integer
dividers with a divide range of 1 to 1024 in SPI and I2C modes.
The channel divider block contains duty cycle correction that
guarantees 50% duty cycle for both even and odd divide ratios.
In pin programming mode, divide values of 1 to 8 and 16 are
supported.
The AD9508 has a power-on reset (POR) and other ways to
apply a reset condition to the chip.
Power-On Reset
During chip power-up, an internal power-on reset pulse is
issued when VDD reaches ~1.15 V and restores the chip to the
default on-chip setting. It takes ~20 ms for the outputs to begin
toggling after the power-on reset pulse signal is internally
generated.
In SPI or I2C modes, the default power-on state of the AD9508
is configured as a buffer with the dividers set to divide by 1. In
pin programmable mode, the part is configured per the
hardwiring of the S0 to S5 pins.
PHASE DELAY CONTROL
The AD9508 provides a coarse output phase delay adjustment
between outputs but with a wide delay range that is beneficial
for some applications. The minimum delay step is equivalent to
half the period of the input clock rate. This minimum delay step
can be multiplied from 1 to 2047 times the minimum delay step
to cover a wide delay range. The multiplication of the minimum
delay step is provided for each channel output via the appropriate
internal programming register. Phase delay is not supported in
pin programming mode.
RESET
Hardware Reset via the
A hard asynchronous reset is executed by briefly pulling
low. This restores the chip to the on-chip default register settings.
Pin
RESET
RESET
It takes ~20 ms for the outputs to begin toggling after
released.
is
Note that the phase delay adjustment requires the use of the
SYNC
function pin. Phase adjustment and output synchroni-
SYNC
Soft Reset via the Serial Port
zation occurs on the rising edge of the
pin. Therefore, the
SYNC
pin must be pulled low and released to produce the
A soft reset is initiated by setting Bit 2 and Bit 5 in Register 0x000.
Except for Register 0x000, when Bit 5 and Bit 2 are set, the chip
enters a soft reset mode and restores the chip to the on-chip
setting. These bits are self clearing. However, the self clearing
operation does not complete until an additional serial port SCLK
cycle occurs, and the AD9508 is held in reset until that happens.
SYNC
desired phase relationship between outputs. If the
is not
active low prior to a phase delay change, the desired output
phase delay between outputs is not guaranteed to occur;
instead, a random phase delay can occur between outputs.
SYNC
However, a future
pulse corrects to the desired phase
SYNC
relationship, if initiated. During the active low
the outputs are forced to a static state.
period,
POWER-DOWN MODE
Individual Clock Channel Power-Down
Figure 46 shows three independent outputs, each set for DIV = 4
of the input clock rate. By incrementing the phase offset value
in the programming registers from 0 to 2, each output is offset
In SPI or I²C programming mode, the clock distribution
channels can be powered down individually by writing to the
appropriate registers. Powering down a clock channel is similar
to powering down an individual driver, but it saves more power
because additional circuits are also powered down. The register
map details the individual power-down settings for each output
channel. These settings are found in Register 0x0F0, Bit 4; Regis-
ter 0x0F2, Bit 4; Register 0x0F4, Bit 4; and Register 0x0F6, Bit 4.
SYNC
from the initial edge by a multiple of ½ tCLK. Note that the
signal is not shown in this timing diagram.
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
CLOCK INPUT
CLK
DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
START = 0,
PHASE = 0
Note that in all three programming modes, a logic low on the
START = 0,
PHASE = 1
RESET
pin can be used to power down the device.
START = 0,
PHASE = 2
tCLK
Figure 46. Phase Offset—All Dividers Set for DIV = 4, Phase Set from 0 to 2
Rev. A | Page 23 of 40
AD9508
Data Sheet
OUTPUT CLOCK SYNCHRONIZATION
THERMALLY ENHANCED PACKAGE MOUNTING
GUIDELINES
Exposed Metal Paddle
On power up, the default output channel divider value is divide-
by-1 if SPI and I2C programming modes are used. Therefore,
there is no real requirement for synchronization after power up
unless a change in divider value or a phase offset value is
desired. A hard asynchronous output synchronization is
The exposed metal paddle on the AD9508 package is an
electrical connection, as well as a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to ground (VSS). The AD9508 dissipates heat through
its exposed paddle. The PCB acts as a heat sink for the AD9508.
The PCB attachment must provide a good thermal path to a
larger heat dissipation area, such as the ground plane on the
PCB. This requires a grid of vias from the top layer down to the
ground plane. See Figure 47 for an example.
executed by briefly pulling the
pin low. This forces the
SYNC
outputs to be edge aligned regardless of their divide ratio after
the pin is released.
SYNC
If the sync mask bit is set to a Logic 1 in any output channel,
those channels continue working uninterrupted while a sync
operation is being applied to other channels. Outputs are pulled
low while
is low if they are not masked by the sync mask
SYNC
bit. This only applies if outputs are functioning under normal
operation with its logic level set to 11 or toggle mode.
VIAS TO GND PLANE
POWER SUPPLY
The AD9508 is designed to work off a 3.3 V + 5% power supply
down to a 2.5 V − 5% power supply. Best practice recommends
bypassing the power supply on the printed circuit board (PCB)
with adequate capacitance (>10 µF) and bypassing all power pins
with adequate capacitance (0.1 µF) as close to the part as possible.
The layout of the AD9508 evaluation board (AD9508/PCBZ),
available at www.analog.com, provides a good layout example
for this device.
Figure 47. PCB Land Example for Attaching Exposed Paddle
Refer to the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), for more information about mounting devices with
an exposed paddle.
Rev. A | Page 24 of 40
Data Sheet
AD9508
PIN STRAPPING TO PROGRAM ON POWER-UP
The PROG_SEL input when set to Logic 1 places the AD9508 in
pin strapping control mode without the need for SPI or I2C
operations. In this mode, Pin S0 through Pin S5 program the
desired internal divider value and output logic type for each
output or to set the output to a high-Z state.
S0 to S5 pins. The other side of the resistor is then biased to
ground or VDD, depending on the desired settings. The actual
settings are applied after an internal ADC scans each one of the
S0 to S5 pins. An ADC scan is initiated by either the internal
power-on reset when the device is powered up or by toggling
SYNC
reset, the
accepted.
the
pin. If changes are made after the internal power-on
SYNC
The maximum divide value is limited to divide-by-16 and phase
offset delay control is not supported in this mode. LVDS and
HSTL logic types are supported in this mode. However, if HSTL
mode is set and the 100 Ω output termination is removed, the
output swings to 1.8 V CMOS logic levels. In this configura-
tion, the differential outputs of the channel selected become two
single-ended CMOS signals. Those outputs maintain a 180° phase
relationship and share the same channel divider value.
pin must be toggled before any new changes are
Table 15 depicts all the pin strapping selections available for
each output channel divider value and logic type. The resistors
listed in Table 15 must have 10% or better tolerance.
Note that if all outputs use an output divider value of one and
use either HSTL outputs or 1.8 V CMOS output levels, then the
S0 to S5 pins can be grounded to accomplish that particular
configuration instead of using the 820 Ω resistor.
Programming individual outputs and the output logic type is
performed by hardwiring specific resistor values to each of the
Table 15. Selection Table for Pin Strapping Control
ADC Voltage Level (0 Through 7) vs. Resistor Value vs. Divide Value and Logic Type
0 = 820 Ω 1 = 1.8 kΩ 2 = 3.9 kΩ 3 = 8.2 kΩ 4 = 820 Ω 5 = 1.8 kΩ 6 = 3.9 kΩ 7 = 8.2 kΩ
Programming Pulled to Pulled to
Pulled to
GND
Pulled to
GND
Pulled to
VDD
Pulled to
VDD
Pulled to
VDD
Pulled to
VDD
Pins
GND
GND
Description
S0
÷1
÷2
÷3
÷3
÷3
÷3
÷4
÷4
÷4
÷4
÷5
÷5
÷5
÷5
÷6
÷6
÷6
÷6
÷8
÷8
÷8
÷8
÷16
÷16
÷16
÷16
SO is assigned to the
Channel 0 divider ratio only
S1 is assigned to the
Channel 1 divider ratio only
S2 is assigned to the
Channel 2 divider ratio only
S3 is assigned to the
Channel 3 divider ratio only
S1
S2
S3
S4
÷1
÷1
÷1
÷2
÷2
÷2
HSTL/
HSTL
HSTL/
LVDS
HSTL/
high-Z
LVDS/
HSTL
LVDS/
LVDS
LVDS/
high-Z
High-Z/
HSTL
High Z/
high-Z
S4 is assigned to Channel 0
and Channel 1 to select their
output logic types
S5
HSTL/
HSTL
HSTL/
LVDS
HSTL/
high-Z
LVDS/
HSTL
LVDS/
LVDS
LVDS/
high-Z
High-Z/
HSTL
High-Z/
high-Z
S5 is assigned to Channel 2
and Channel 3 to select their
output logic types
Rev. A | Page 25 of 40
AD9508
Data Sheet
SERIAL CONTROL PORT
SPI Mode Operation
The AD9508 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to
many industry-standard microcontrollers and microprocessors.
The serial control port is compatible with most synchronous
transfer formats, including I²C, Motorola SPI, and Intel SSR
protocols. The serial control port allows read/write access to the
AD9508 register map.
The SPI port supports both 3-wire (bidirectional) and 4-wire
(unidirectional) hardware configurations and both MSB first
and LSB first data formats. Both the hardware configuration
and data format features are programmable. By default, the
AD9508 uses the bidirectional MSB first mode. The reason that
bidirectional is the default mode is so that the user can continue
to write to the device (if it is wired for unidirectional operation)
to switch to unidirectional mode.
In SPI mode, single- or multiple-byte transfers are supported.
The SPI port configuration is programmable via Register 0x00.
This register is integrated into the SPI control logic rather than
in the register map and it is distinct from the I2C Register 0x00.
CS
Assertion (active low) of the
operation to the AD9508 SPI port. For data transfers of three
bytes or fewer (excluding the instruction word), the device
pin initiates a write or read
SPI/I²C PORT SELECTION
CS
CS
supports the
be temporarily deasserted on any byte boundary, allowing time
CS
stalled high mode. In this mode, the
pin can
The AD9508 has two serial interfaces, SPI and I²C. Users can
select either SPI or I²C depending on the state of the PROG_SEL
pin. In I²C operation, four different I²C slave address (seven bits
wide) settings are available, see Table 16. The five MSBs of the
slave address are hardware coded as 11011 and Pin S4 and Pin
S5 program the two LSBs.
for the system controller to process the next byte. However,
can be deasserted on byte boundaries only; this applies to both
the instruction and data portions of the transfer.
During stall high periods, the serial control port state machine
enters a wait state until all data is sent. If the system controller
decides to abort a transfer midstream, the state machine must be
Table 16. Serial Port Mode Selection
S4
S5
Address
CS
reset either by completing the transfer or by asserting the
pin for at least one complete SCLK cycle (but less than eight
CS
Low
Low
High
High
Low
High
Low
High
I²C, 1101100
I²C, 1101101
I²C, 1101110
I²C, 1101111
SCLK cycles). Deasserting the
pin on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 17), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented. must be deasserted
at the end of the last byte that is transferred, thereby ending the
stream mode.
SPI SERIAL PORT OPERATION
Pin Descriptions
CS
The SCLK (serial clock) pin serves as the serial shift clock. This
pin is an input. SCLK synchronizes serial control port read and
write operations. The rising edge SCLK registers write data bits,
and the falling edge registers read data bits. The SCLK pin
supports a maximum clock rate of 40 MHz.
Table 17. Byte Transfer Count
W1
W0
Bytes to Transfer
0
0
1
2
0
1
The SDIO (serial data input/output) pin is a dual-purpose pin
and acts either as an input only (unidirectional mode) or as both
an input and an output (bidirectional mode). The AD9508
default SPI mode is bidirectional.
1
1
0
1
3
Streaming mode
Communication Cycle—Instruction Plus Data
The SPI protocol consists of a two part communication cycle.
The first part is a 16-bit instruction word that is coincident with
the first 16 SCLK rising edges and a payload. The instruction
word provides the AD9508 serial control port with information
The SDO (serial data output) pin is useful only in unidirectional
I/O mode. It serves as the data output pin for read operations.
CS
The
and write operations. This pin is internally connected to a 30 kΩ
CS
(chip select) pin is an active low control that gates read
W
regarding the payload. The instruction word includes the R/
pull-up resistor. When
a high impedance state.
is high, the SDO and SDIO pins enter
bit that indicates the direction of the payload transfer; that is, a
read or write operation. The instruction word also indicates the
number of bytes in the payload and the starting register address
of the first payload byte.
Rev. A | Page 26 of 40
Data Sheet
AD9508
Write
SPI MSB First and LSB First Transfers
When the instruction word indicates a write operation, the payload
is written into the serial control port buffer of the AD9508. Data
bits are registered on the rising edge of SCLK. The length of the
transfer (one, two, or three bytes or streaming mode) depends
on the W0 and W1 bits in the instruction byte. When not
The AD9508 instruction word and payload can be MSB first or
LSB first; the default is MSB first. The LSB first mode can be set by
writing a 1 to Register 0x00, Bit 6. Immediately after the LSB first
bit is set, subsequent serial control port operations are LSB first.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant payload byte. Subsequent
data bytes must follow, in order, from high address to low address.
In MSB first mode, the serial control port internal address genera-
tor decrements for each data byte of the multibyte transfer cycle.
CS
streaming,
bits to stall the bus (except after the last byte, where it ends the
CS
can be deasserted after each sequence of eight
cycle). When the bus is stalled, the serial transfer resumes when
CS
is asserted. Deasserting the
pin on a nonbyte boundary resets
the serial control port. Reserved or blank registers are not skipped
automatically during a write sequence. Therefore, the user must
know what bit pattern to write to the reserved registers to preserve
proper operation of the device. Generally, it does not matter what
data is written to blank registers, but it is customary to write 0s.
When Register 0x00, Bit 6 = 1 (LSB first), the instruction and
data bytes must be written from LSB to MSB. Multibyte data
transfers in LSB first format start with an instruction byte that
includes the register address of the least significant payload byte,
followed by multiple data bytes. The serial control port internal
byte address generator increments for each byte of the multibyte
transfer cycle.
Most of the serial port registers are buffered. This means that
data written into buffered registers do not take effect until the
user issues an I/O update. An I/O update operation is executed
by writing a Logic 1 to Register 0x0005, Bit 0 (which is an auto-
clearing bit) or by programming a multifunction pin to perform
the I/O update function and applying an external signal to that
pin. The user can change as many register bits as needed before
executing an I/O update. The I/O update operation transfers the
buffer register contents to their active register counterparts.
For multibyte MSB first (default) I/O operations, the serial control
port register address decrements from the specified starting address
toward Address 0x00. For multibyte LSB first I/O operations, the
serial control port register address increments from the starting
address toward Address 0x2C. Reserved addresses are not skipped
during multibyte I/O operations; therefore, the user writes the
default value to a reserved register and writes 0s to unmapped
registers. Note that it is more efficient to issue a new write
command than to write the default value to more than two
consecutive reserved (or unmapped) registers.
Read
The AD9508 supports the long instruction mode only. If the
instruction word indicates a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in
the instruction word. N is the number of data bytes read and
depends on the W0 and W1 bits of the instruction word. The
readback data is valid on the falling edge of SCLK. Blank registers
are not skipped during readback.
Table 18. Streaming Mode (No Addresses Skipped)
Write Mode Address Direction Stop Sequence
LSB First
MSB First
Increment
Decrement
0x00 … 0x2C
0x2C … 0x00
A readback operation takes data from either the serial control
port buffer registers or the active registers.
SPI Instruction Word (16 Bits)
W
The MSB of the 16-bit instruction word is R/ , which indicates
whether the instruction is a read or a write. The next two bits, W1
and W0, indicate the number of bytes in the transfer. The final 13
bits are the register address (A12 to A0), which indicates the
starting register address of the read/write operation (see Table 19).
Table 19. Serial Control Port, 16-Bit Instruction Word, MSB First Bit Map
MSB
LSB
I0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
A4
I3
I2
I1
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A3
A2
A1
A0
CS
SCLK DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA
Figure 48. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data
Rev. A | Page 27 of 40
AD9508
Data Sheet
CS
SCLK
DON'T CARE
DON'T CARE
SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDO DON'T CARE
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
REGISTER (N – 3) DATA
DON'T
CARE
Figure 49. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data
tDS
tHIGH
tS
tC
tCLK
tDH
tLOW
CS
SCLK
SDIO
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
Figure 50. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CS
SCLK
tDV
SDIO
SDO
DATA BIT N
DATA BIT N – 1
Figure 51. Timing Diagram for Serial Control Port Register Read
CS
SCLK DON'T CARE
DON'T CARE
DON'T CARE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA
DON'T CARE
SDIO
Figure 52. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data
tS
tC
CS
tCLK
tHIGH
tLOW
tDS
SCLK
SDIO
tDH
BIT N
BIT N + 1
Figure 53. Serial Control Port Timing—Write
Rev. A | Page 28 of 40
Data Sheet
AD9508
Table 20. Serial Control Port Timing
Parameter
Description
tDS
tDH
tCLK
tS
Setup time between data and the rising edge of SCLK
Hold time between data and the rising edge of SCLK
Period of the clock
Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle)
Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 51)
tC
tHIGH
tLOW
tDV
I2C SERIAL PORT OPERATION
The transfer of data is shown in Figure 54. One clock pulse is
The I2C interface has the advantage of requiring only two control
pins and is a de facto standard throughout the I2C industry.
However, its disadvantage is the programming speed, which is
400 kbps maximum. The AD9508 IꢀC port design is based on
the IꢀC fast mode standard; therefore, it supports both the 100 kHz
standard mode and 400 kHz fast mode. Fast mode imposes a glitch
tolerance requirement on the control signals; that is, the input
receivers ignore pulses of less than 50 ns duration.
generated for each data bit transferred. The data on the SDA
line must be stable during the high period of the clock. The
high or low state of the data line can change only when the
clock signal on the SCL line is low.
SDA
SCL
The AD9508 IꢀC port consists of a serial data line (SDA) and
a serial clock line (SCL). In an IꢀC bus system, the AD9508 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9508.
The AD9508 uses direct 16-bit memory addressing rather than
traditional 8-bit memory addressing.
DATA LINE
STABLE;
CHANGE
OF DATA
ALLOWED
DATA VALID
Figure 54. Valid Bit Transfer
Start/stop functionality is shown in Figure 55. The start condition
is characterized by a high-to-low transition on the SDA line while
SCL is high. The start condition is always generated by the master
to initialize a data transfer. The stop condition is characterized
by a low-to-high transition on the SDA line while SCL is high.
The stop condition is always generated by the master to terminate
a data transfer. Every byte on the SDA line must be eight bits long.
Each byte must be followed by an acknowledge bit; bytes are sent
MSB first.
The AD9508 allows up to four unique slave devices to occupy
the I2C bus. These slave devices are accessed via a 7-bit slave
address that is transmitted as part of an I2C packet. Only the
device that has a matching slave address responds to subsequent
I2C commands. Table 16 lists the supported device slave
addresses.
I2C Bus Characteristics
Table 21 provides a summary of the various I2C abbreviations
used in the protocol.
The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has been received. The acknowledge bit is communicated
by pulling the SDA line low during the ninth clock pulse after
each 8-bit data byte (see Figure 56).
Table 21. I2C Bus Abbreviation Definitions
Abbreviation
Definition
S
Start
Sr
P
Repeated start
Stop
The no acknowledge bit (NACK) is the ninth bit attached to any
8-bit data byte. The receiving device (receiver) always generates
the no acknowledge bit to inform the transmitter that the byte
has not been received. The no acknowledge bit is communi-
cated by leaving the SDA line high during the ninth clock pulse
after each 8-bit data byte.
ACK
NACK
W
Acknowledge
No acknowledge
Write
R
Read
Rev. A | Page 29 of 40
AD9508
Data Sheet
SDA
SCL
S
P
START CONDITION
STOP CONDITION
Figure 55. Start and Stop Conditions
MSB
SDA
SCL
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
3 TO 7
8
9
3 TO 7
8
9
10
P
1
2
1
2
S
Figure 56. Acknowledge Bit
Data Transfer Process
bytes immediately after the slave address byte serve as the inter-
nal memory (control registers) address bytes, with the high
address byte first. This addressing scheme gives a memory
address of up to ꢀ16 − 1 = 65,535. e data bytes aꢁer these
two memory address bytes are register data that are written
to or read from the control registers. In read mode, the data
bytes after the slave address byte are register data that are
written to or read from the control registers.
The master initiates a data transfer by asserting a start condition,
which indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/ bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 =
write, 1 = read).
W
When all data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts a
stop condition to end data transfer during the 10th clock pulse
following the acknowledge bit for the last data byte from the
slave device (receiver). In read mode, the master device (receiver)
receives the last data byte from the slave device (transmitter)
but does not pull SDA low during the ninth clock pulse. This
condition is known as a no acknowledge bit. By receiving the no
acknowledge bit, the slave device knows that the data transfer is
finished and enters idle mode. The master then takes the data
line low during the low period before the 10th clock pulse and
high during the 10th clock pulse to assert a stop condition.
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
for data to be read from or written to it. If the R/ bit is 0, the
master (transmitter) writes to the slave device (receiver). If the
W
W
R/ bit is 1, the master (receiver) reads from the slave device
(transmitter). The format for these commands is described in
the Data Transfer Format section.
Data is then sent over the serial bus in the format of nine clock
pulses: one data byte (eight bits) from either master (write mode)
or slave (read mode) followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted
per transfer is unrestricted. In write mode, the first two data
A start condition can be used in place of a stop condition.
Furthermore, a start or stop condition can occur at any time,
and partially transferred bytes are discarded.
MSB
SDA
SCL
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
3 TO 7
8
9
3 TO 7
8
9
10
P
1
2
1
2
S
Figure 57. Data Transfer Process (Master Write Mode, Two-Byte Transfer)
Rev. A | Page 30 of 40
Data Sheet
AD9508
SDA
ACK FROM
MASTER RECEIVER
NACK FROM
MASTER RECEIVER
SCL
S
3 TO 7
8
9
3 TO 7
8
9
10
P
1
2
1
2
Figure 58. Data Transfer Process (Master Read Mode, Two-Byte Transfer)
Data Transfer Format
Write byte format: The write byte protocol writes a register address to the RAM, starting from the specified RAM address.
S
Slave
Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
Send byte format: The send byte protocol sets up the register address for subsequent reads.
Slave Address RAM Address High Byte RAM Address Low Byte
S
W
A
A
A
P
Receive byte format: The receive byte protocol reads the data byte(s) from RAM, starting from the current address.
Slave Address RAM Data 0 RAM Data 1 RAM Data 2
S
R
A
A
A
A
P
Read byte format: This is the combined format of the send byte and the receive byte.
S
Slave
Address
W
A
RAM
Address
High Byte
A
RAM
Address
Low Byte
A
Sr Slave
Address
R
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
I²C Serial Port Timing
SDA
tLOW
tR
tSU; DAT
tBUF
tHD; STA
tR
tF
tSP
tF
SCL
tSU; STA
tSU; STO
tHD; STA
tHIGH
tHD; DAT
S
Sr
S
P
Figure 59. I²C Serial Port Timing
Table 22. IꢀC Timing Definitions
Parameter
Description
fSCL
Serial clock
tBUF
Bus free time between stop and start conditions
Repeated hold time start condition
Repeated start condition setup time
Stop condition setup time
Data hold time
Date setup time
tHD; STA
tSU; STA
tSU; STO
tHD; DAT
tSU; DAT
tLOW
SCL clock low period
tHIGH
SCL clock high period
tR
tF
Minimum/maximum receive SCL and SDA rise time
Minimum/maximum receive SCL and SDA fall time
tSP
Pulse width of voltage spikes that must be suppressed by the input filter
Rev. A | Page 31 of 40
AD9508
Data Sheet
REGISTER MAP
Register addresses that are not listed in Table 23 are unused, and writing to those registers has no effect. The user should write the default
value to sections of registers marked reserved.
The abbreviation, R, in the optional (Opt) column in Table 23 means read only and NS means that the value does not change during a soft
reset. Note that the default column is represented by Def.
Table 23. Register Map
Reg
Addr
(Hex)
Opt
Name
D7
D6
D5
D4
D3
Reserved
D2
D1
D0
Def
Serial Control Port Configuration and Part Identification
0x00
NS
SPI control
SDO enable
LSB first/
increment
address
Soft reset
Soft reset
LSB first/
increment
address
SDO enable
00
0x00
0x0A
0x0B
0x0C
0x0D
NS
I²C control
Silicon rev
Reserved
Part ID
Reserved
Soft reset
Reserved
Soft reset
Reserved
00
00
00
05
00
R, NS
R, NS
R, NS
R,NS
Silicon Revision[7:0]
Reserved
Clock Part Family ID[7:0]
Clock Part Family ID[15:8]
Part ID
Chip Level Functions
0x12
0x13
Reserved
Reserved
Sleep
02
00
Sleep
Reserved
Reserved
0x14
NS
SYNC_BAR
Reserved
SYNC_BAR
01
OUT0 Functions
0x15
OUT0
Divide
Ratio[9:0]
OUT0 Divide Ratio[7:0]
00
00
0x16
Reserved
OUT0 Divide Ratio[9:8]
0x17
OUT0
Phase[9:0]
OUT0 Phase[7:0]
00
00
14
00
0x18
Reserved
OUT0 Driver Phase[1:0]
CMOS_0P_PHASE[1:0] EN_CMOS_0N
OUT0 Phase[10:8]
0x19
OUT0 Driver PD_0
SYNCMASK0
OUT0 Mode[2:0]
CMOS_0N_PHASE[1:0]
Reserved
Reserved
0x1A
OUT0 CMOS
EN_CMOS_0P
OUT1 Functions
0x1B
OUT1
Divide
Ratio[9:0]
OUT1 Divide Ratio[7:0]
Reserved
00
00
0x1C
OUT1 Divide Ratio[9:8]
0x1D
OUT1
Phase[9:0]
OUT1 Phase[7:0]
00
00
14
00
0x1E
Reserved
OUT1 Driver Phase[1:0]
CMOS_1P_PHASE[1:0] EN_CMOS_1N
OUT1 Phase[10:8]
OUT1 Mode[2:0]
CMOS_1N_PHASE[1:0]
0x1F
OUT1 Driver PD_1
SYNCMASK1
Reserved
Reserved
0x20
OUT1 CMOS
EN_CMOS_1P
OUT2 Functions
0x21
OUT2
Divide
Ratio[9:0]
OUT2 Divide Ratio[7:0]
Reserved
00
00
0x22
OUT2 Divide Ratio[9:8]
0x23
OUT2
Phase[9:0]
OUT2 Phase [7:0]
00
00
14
00
0x24
Reserved
OUT2 Driver Phase[1:0]
CMOS_2P_PHASE[1:0] EN_CMOS_2N
OUT2 Phase[10:8]
0x25
OUT2 Driver PD_2
SYNCMASK2
OUT2 Mode[2:0]
CMOS_2N_PHASE[1:0]
Reserved
Reserved
0x26
OUT2 CMOS EN_CMOS_2P
OUT3 Functions
0x27
OUT3
Divide
Ratio[9:0]
OUT3 Divide Ratio[7:0]
Reserved
00
00
0x28
OUT3 Divide Ratio[9:8]
0x29
0x2A
0x2B
0x2C
OUT3
Phase[9:0]
OUT3 Phase[7:0]
00
00
14
00
Reserved
OUT3 Driver Phase[1:0]
CMOS_3P_PHASE[1:0] EN_CMOS_3N
OUT3 Phase[10:8]
OUT3 Mode[2:0]
CMOS_3N_PHASE[1:0]
OUT3 Driver PD_3
SYNCMASK3
Reserved
Reserved
OUT3 CMOS EN_CMOS_3P
Rev. A | Page 32 of 40
Data Sheet
AD9508
REGISTER MAP BIT DESCRIPTIONS
SERIAL PORT CONFIGURATION (REGISTER 0x00)
Table 24. Serial Configuration
Address
Bits
Bit Name
Description
0x00
7
SDO enable
Enables SPI port SDO pin. This bit does nothing in I²C mode.
1 = 4-wire (SDO pin enabled).
0 = 3-wire (default).
6
LSB first/increment address Bit order for the SPI port. This bit is nonfunctional in I²C mode.
1 = LSB and byte first. Register addresses are automatically incremented in multibyte
transfers.
0 = MSB and byte first (default). Register addresses are automatically decremented in
multibyte transfers.
5
Soft reset
Reserved
Soft reset
Device reset.
[4:3]
Reserved.
2
1
0
Same function as Bit 5 of this register, set Bit 2 and Bit 5 to the same value.
LSB first/increment address Same function as Bit 6 of this register, set Bit 1 and Bit 6 to the same value.
SDO enable Same function as Bit 7 of this register, set Bit 7 and Bit 0 to the same value.
SILICON REVISION (REGISTER 0x0A TO REGISTER 0x0D)
Table 25. Silicon Revision
Address
Bits
[7:0]
[7:0]
[7:0]
Bit Name
Description
0x0A
Silicon Revision[7:0]
Reserved
A read-only register. Identifies the revision level of the AD9508.
0x00 = default.
0x0B
0x0C
Clock Part Family ID[7:0]
A read-only register. This register, together with Register 0x000D, uniquely identifies an
AD9508. No other device in the Analog Devices, Inc., AD95xx family has a value of 0x0005 in
these two registers.
0x05 = default.
0x0D
[7:0]
Clock Part Family ID[15:8]
This register is a continuation of Register 0x000C.
0x00 = default.
CHIP LEVEL FUNCTIONS (REGISTER 0x12 TO REGISTER 0x14)
Table 26. Sleep and Synchronization
Address
Bits
[7:0]
[7:5]
4
Bit Name
Reserved
Reserved
Sleep
Description
0x12
0x00000010 = default
0x13
0x000 = default
0 = disables sleep mode (default)
1 = enables sleep mode
[3:0]
[7:1]
0
Reserved
Reserved
SYNC_BAR
0x0000 = default
0x14
0x0000000 = default
0 = enables a software output synchronization routine
1 = output synchronization via software disabled (default)
Rev. A | Page 33 of 40
AD9508
Data Sheet
OUT0 FUNCTIONS (REGISTER 0x15 TO REGISTER 0x1A)
Table 27. Divide Ratio and Phase
Address
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bit Name
Description
0x15
OUT0 Divide Ratio[7:0]
Reserved
Channel 0 divide ratio, Bits[7:0]
0x00 = default
0x16
OUT0 Divide Ratio[9:8]
OUT0 Phase[7:0]
Reserved
Channel 0 divide ratio, Bits[9:8]
Channel 0 divider phase, Bits[7:0]
0x00 = default
0x17
0x18
OUT0 Phase[10:8]
Channel 0 divider phase, Bits[9:8]
Table 28. Output Driver, Power Down, and Sync
Address
Bits
Bit Name
Description
0x19
7
PD_0
Channel 0 power down
6
SYNCMASK0
Setting this bit masks Channel 0 from the output sync function
0 = Channel 0 is synchronized during output sync (default)
1 = Channel 0 is excluded from an output sync
These bits determine the phase of the OUT0 driver
00 = force high
[5:4]
[3:1]
OUT0 Driver Phase[1:0]
OUT0 Mode[2:0]
01 = noninverting (default)
10 = inverting
11 = force low
These bits determine the OUT0 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0
7
Reserved
0b = default
0x1A
EN_CMOS_0P
Setting this bit enables the OUT0P CMOS driver
0 = disables the OUT0P CMOS driver (default)
1 = enables the OUT0P CMOS driver
These bits determine the phase of the OUT0P CMOS driver
00 = force high (default)
[6:5]
CMOS_0P_PHASE[1:0]
01 = noninverting
10 = inverting
11 = force low
4
EN_CMOS_0N
Setting this bit enables the OUT0N CMOS driver
0 = disables the OUT0N CMOS driver (default)
1 = enables the OUT0N CMOS driver
These bits determine the phase of the OUT0N CMOS driver
00 = force high (default)
[3:2]
CMOS_0N_PHASE[1:0]
01 = noninverting
10 = inverting
11 = force low
[1:0]
Reserved
00b = default
Rev. A | Page 34 of 40
Data Sheet
AD9508
OUT1 FUNCTIONS (REGISTER 0x1B TO REGISTER 0x20)
Table 29. Divide Ratio and Phase
Address
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bit Name
Description
0x1B
OUT1 Divide Ratio[7:0]
Reserved
Channel 1 divide ratio, Bits[7:0]
0x00 = default
0x1C
OUT1 Divide Ratio[9:8]
OUT1 Phase[7:0]
Reserved
Channel 1 divide ratio, Bits[9:8]
Channel 1 divider phase, Bits[7:0]
0x00 = default
0x1D
0x1E
OUT1 Phase[10:8]
Channel 1 divider phase, Bits[9:8]
Table 30. Output Driver, Power Down, and Sync
Address
Bits
Bit Name
Description
0x1F
7
PD_1
Channel 1 power-down
6
SYNCMASK1
Setting this bit masks Channel 1 from the output sync function
0 = Channel 1 is synchronized during output sync (default)
1 = Channel 1 is excluded from an output sync
These bits determine the phase of the OUT1 driver
00 = force high
[5:4]
[3:1]
OUT1 Driver Phase[1:0]
OUT1 Mode[2:0]
01 = noninverting (default)
10 = inverting
11 = force low
These bits determine the OUT1 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0
7
Reserved
0b = default
0x20
EN_CMOS_1P
Setting this bit enables the OUT1P CMOS driver
0 = disables the OUT1P CMOS driver (default)
1 = enables the OUT1P CMOS driver
These bits determine the phase of the OUT1P CMOS driver
00 = force high (default)
[6:5]
CMOS_1P_PHASE[1:0]
01 = noninverting
10 = inverting
11 = force low
[4]
EN_CMOS_1N
Setting this bit enables the OUT1N CMOS driver
0 = disables the OUT1N CMOS driver (default)
1 = enables the OUT1N CMOS driver
These bits determine the phase of the OUT1N CMOS driver
00 = force high (default)
[3:2]
CMOS_1N_PHASE[1:0]
01 = noninverting
10 = inverting
11 = force low
[1:0]
Reserved
00b = default
Rev. A | Page 35 of 40
AD9508
Data Sheet
OUT2 FUNCTIONS (REGISTER 0x21 TO REGISTER 0x26)
Table 31. Divide Ratio and Phase
Address
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bit Name
Description
0x21
OUT2 Divide Ratio[7:0]
Reserved
Channel 2 divide ratio, Bits[7:0]
0x00 = default
0x22
OUT2 Divide Ratio[9:8]
OUT2 Phase[7:0]
Reserved
Channel 2 divide ratio, Bits[9:8]
Channel 2 divider phase, Bits[7:0]
0x00 = default
0x23
0x24
OUT2 Phase[10:8]
Channel 2 divider phase, Bits[9:8]
Table 32. Output Driver, Power Down, and Sync
Address
Bits
Bit Name
Description
0x25
7
PD_2
Channel 2 power-down
6
SYNCMASK2
Setting this bit masks OUT2 from the output sync function
0 = Channel 2 is synchronized during output sync (default)
1 = Channel 2 is excluded from an output sync
These bits determine the phase of the OUT2 driver
00 = force high
[5:4]
[3:1]
OUT2 Driver Phase[1:0]
OUT2 Mode[2:0]
01 = noninverting (default)
10 = inverting
11 = force low
These bits determine the OUT2 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0
7
Reserved
0b = default
0x26
EN_CMOS_2P
Setting this bit enables the OUT2P CMOS driver
0 = disables the OUT2P CMOS driver (default)
1 = enables OUT2P CMOS driver
These bits determine the phase of the OUT2P CMOS driver
00 = force high (default)
[6:5]
CMOS_2P_PHASE[1:0]
01 = noninverting
10 = inverting
11 = force low
4
EN_CMOS_2N
Setting this bit enables the OUT2N CMOS driver
0 = disables the OUT2N CMOS driver (default)
1 = enables OUT2N CMOS driver
These bits determine the phase of the OUT2N CMOS driver
00 = force high (default)
[3:2]
CMOS_2N_PHASE[1:0]
01 = noninverting
10 = inverting
11 = force low
[1:0]
Reserved
00b = default
Rev. A | Page 36 of 40
Data Sheet
AD9508
OUT3 FUNCTIONS (REGISTER 0x27 TO REGISTER 0x2C)
Table 33. Divide Ratio and Phase
Address
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bit Name
Description
0x27
OUT3 Divide Ratio[7:0]
Reserved
Channel 3 divide ratio, Bits[7:0]
0x00 = default
0x28
OUT3 Divide Ratio[9:8]
OUT3 Phase[7:0]
Reserved
Channel 3 divide ratio, Bits[9:8]
Channel 3 divider phase, Bits[7:0]
0x00 = default
0x29
0x2A
OUT3 Phase[10:8]
Channel 3 divider phase, Bits[9:8]
Table 34. Output Driver, Power Down, and Sync
Address
Bits
Bit Name
Description
0x2B
7
PD_3
Channel 3 power-down
6
SYNCMASK3
Setting this bit masks OUT3 from the output sync function
0 = Channel 3 is synchronized during output sync (default)
1 = Channel 3 is excluded from an output sync
These bits determine the phase of the OUT3 driver
00 = force high
[5:4]
[3:1]
OUT3 Driver Phase[1:0]
OUT3 Mode[2:0]
01 = noninverting
10 = inverting
11 = force low
These bits determine the OUT3 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0
7
Reserved
0b = default
0x2C
EN_CMOS_3P
Setting this bit enables the OUT3P CMOS driver
0 = disables the OUT3P CMOS driver (default)
1 = enables OUT3P CMOS driver
These bits determine the phase of the OUT3P CMOS driver
00 = force high (default)
[6:5]
CMOS_3P_PHASE[1:0]
01 = noninverting
10 = inverting
11 = force low
4
EN_CMOS_3N
Setting this bit enables the OUT3N CMOS driver
0 = disables the OUT3N CMOS driver (default)
1 = enables OUT3N CMOS driver
These bits determine the phase of the OUT3N CMOS driver
00 = force high (default)
[3:2]
CMOS_3N_PHASE[1:0]
01 = noninverting
10 = inverting
11 = force low
[1:0]
Reserved
00b = default
Rev. A | Page 37 of 40
AD9508
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
PIN 1
INDICATOR
INDICATOR
24
19
0.50
BSC
1
6
18
EXPOSED
PAD
2.65
2.50 SQ
2.45
13
12
7
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 60. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9508BCPZ
AD9508BCPZ-REEL7
AD9508/PCBZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-24-7
CP-24-7
24-Lead Lead Frame Chip Scale Package (LFCSP_WQ)
24-Lead Lead Frame Chip Scale Package (LFCSP_WQ)
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. A | Page 38 of 40
Data Sheet
NOTES
AD9508
Rev. A | Page 39 of 40
AD9508
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11161-0-4/13(A)
www.analog.com/AD9508
Rev. A | Page 40 of 40
相关型号：
AD9511BCPZ-REEL7
9511 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48, 7 X 7 MM, LEAD FREE, MO-220VKKD-2, LFCSP-48
ROCHESTER
©2020 ICPDF网 联系我们和版权申明