AD9261BCPZRL7-10 [ADI]
16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC;
| 型号： | AD9261BCPZRL7-10 |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC 转换器 |
| 文件： | 总29页 (文件大小：610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 10 MHz Bandwidth, 30 MSPS to
160 MSPS Continuous Time Sigma-Delta ADC
AD9261
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
SNR: 83 dB (85 dBFS) to 10 MHz input
SFDR: 87 dBc to 10 MHz input
Noise figure: 15 dB
OR
VIN+
VIN–
D15
SAMPLE
RATE
CONVERTER
LOW-PASS
Σ-Δ
CMOS
BUFFER
DECIMATION
FILTER
MODULATOR
Input impedance: 1 kΩ
D0
Power: 340 mW
PLL_
LOCKED
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Selectable bandwidth
PHASE
LOCKED
LOOP
CLK+
CLK–
AD9261
VREF
CFILT
2.5 MHz/5 MHz/10 MHz
SERIAL
INTERFACE
DCO
Output data rate: 30 MSPS to 160 MSPS
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier
On-chip voltage reference
AGND
SDIO SCLK CSB DGND
Figure 1.
Offset binary, Gray code, or twos complement data format
Serial control interface (SPI)
APPLICATIONS
Data acquisition
Automated test equipment
Instrumentation
Medical imaging
GENERAL DESCRIPTION
The AD9261 is a single 16-bit analog-to-digital converter
(ADC) based on a continuous time (CT) sigma-delta (Σ-Δ)
architecture that achieves 87 dBc of dynamic range over a 10 MHz
input bandwidth. The integrated features and characteristics
unique to the continuous time Σ-Δ architecture significantly
simplify its use and minimize the need for external components.
The digital output data is presented in offset binary, Gray code,
or twos complement format. A data clock output (DCO) is
provided to ensure proper timing with the receiving logic.
The AD9261 operates on a 1.8 V analog supply and a 1.8 V
to 3.3 V digital supply, consuming 340 mW. The AD9261 is
available in a 48-lead LFCSP and is specified over the industrial
temperature range (−40°C to +85°C).
The AD9261 has a resistive input impedance that relaxes the
requirements of the driver amplifier. In addition, a 32× oversam-
pled fifth-order continuous time loop filter significantly attenuates
out-of-band signals and aliases, reducing the need for external
filters at the input.
PRODUCT HIGHLIGHTS
1. Continuous time Σ-Δ architecture efficiently achieves high
dynamic range and wide bandwidth.
2. Passive input structure reduces or eliminates the require-
ments for a driver amplifier.
3. An oversampling ratio of 32× and high order loop filter
provide excellent alias rejection reducing or eliminating the
need for antialiasing filters.
4. An integrated decimation filter, sample rate converter, PLL
clock multiplier, and voltage reference provide ease of use.
5. This part operates from a single 1.8 V analog power supply
and 1.8 V to 3.3 V output supply.
An external clock input or the integrated integer-N PLL provides
the 640 MHz internal clock needed for the oversampled conti-
nuous time Σ-Δ modulator. On-chip decimation filters and sample
rate converters reduce the modulator data rate from 640 MSPS to a
user-defined output data rate from 30 MSPS to 160 MSPS,
enabling a more efficient and direct interface.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
AD9261* PRODUCT PAGE QUICK LINKS
Last Content Update: 09/27/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
EVALUATION KITS
• AD9261 Evaluation Board
• Understanding Continuous-Time, Discrete-Time Sigma-
Delta ADCs And Nyquist ADCs
DESIGN RESOURCES
• AD9261 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-283: Sigma-Delta ADCs and DACs
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
DISCUSSIONS
View all AD9261 EngineerZone Discussions.
• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
SAMPLE AND BUY
• AN-835: Understanding High Speed ADC Testing and
Evaluation
Visit the product page to see pricing options.
• AN-878: High Speed ADC SPI Control Software
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
Data Sheet
• AD9261: 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS
Continuous Time Sigma-Delta ADC Preliminary Data
Sheet
DOCUMENT FEEDBACK
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AD9261
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................9
Equivalent Circuits......................................................................... 13
Theory of Operation ...................................................................... 14
Analog Input Considerations ................................................... 14
Clock Input Considerations...................................................... 16
Power Dissipation and Standby Mode .................................... 18
Digital Engine............................................................................. 19
Digital Outputs ........................................................................... 21
Timing ......................................................................................... 21
Serial Port Interface (SPI).............................................................. 23
Configuration Using the SPI..................................................... 23
Hardware Interface..................................................................... 24
Memory Map .................................................................................. 25
Memory Map Definitions ......................................................... 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Decimation Filtering Characteristics............................ 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD9261
SPECIFICATIONS
DC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN1 = −2.0 dBFS,
unless otherwise noted.
Table 1.
Parameter
Temp
Min
Typ
Max
Unit
Bits
RESOLUTION
Full
16
ANALOG INPUT BANDWIDTH
ACCURACY
10
MHz
No Missing Codes
Offset Error
Gain Error
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Full
Full
Full
Full
Guaranteed
0.02
0.ꢁ
0.1ꢀ
3.0
% FSR
% FSR
LSB
1.ꢀ
Full
Full
1.ꢀ
ꢀ0
ppm/°C
ppm/°C
mV
Gain Error
INTERNAL VOLTAGE REFERENCE
ANALOG INPUT
Input Span, VREF = 0.ꢀ V
Common-Mode Voltage
Input Resistance
POWER SUPPLIES
Supply Voltage
AVDD
490
1.ꢁ
ꢀ00
ꢀ10
1.9
Full
Full
Full
2
1.8
1
V p-p diff
V
kΩ
Full
Full
Full
Full
1.ꢁ
1.ꢁ
1.ꢁ
1.ꢁ
1.8
1.8
1.8
1.8
1.9
1.9
1.9
3.6
V
V
V
V
CVDD
DVDD
DRVDD
Supply Current
2
IAVDD
Full
Full
Full
Full
Full
Full
ꢁ4
ꢀꢁ
8.0
100
ꢀ.ꢀ
10
83
mA
mA
mA
mA
mA
mA
ICVDD2 PLL Enabled
ICVDD2 PLL Disabled
6ꢀ4
8.8
108
ꢀ.8
2
IDVDD
IDRVDD2 (1.8 V)
IDRVDD2 (3.3 V)
POWER CONSUMPTION
Sine Wave Input2 PLL Disabled
Sine Wave Input2 PLL Enabled
Power-Down Power
Standby Power2
Full
Full
Full
Full
Full
340
42ꢀ
20
ꢁ
3ꢁ0
46ꢀ
mW
mW
mW
mW
mW
Sleep Power
3
4
1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted.
2 Measured with a low input frequency, full-scale sine wave.
Rev. 0 | Page 3 of 28
AD9261
AC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 2.
Parameter1
Temp
Min
Typ
Max
Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 4.2 MHz
Full
2ꢀ°C
2ꢀ°C
81
83
83
83
dB
dB
dB
fIN = 8.4 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 4.2 MHz
2ꢀ°C
2ꢀ°C
2ꢀ°C
13.ꢀ
13.ꢀ
13.ꢀ
Bits
Bits
Bits
fIN = 8.4 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 4.2 MHz
Full
2ꢀ°C
2ꢀ°C
8ꢁ
8ꢁ
<120
80
dBc
dBc
dBc
fIN = 8.4 MHz
NOISE SPECTRAL DENSITY (NSD)
AIN= −2 dBFS
AIN = −40 dBFS
Full
Full
−1ꢀꢀ
−1ꢀ6
1ꢀ
−1ꢀ3
−1ꢀ4.ꢀ
dB/Hz
dB/Hz
dB
NOISE FIGURE2
2ꢀ°C
TWO-TONE SFDR
fIN1 = 2.1 MHz at −8 dBFS, fIN2 = 2.4 MHz at −8 dBFS
fIN1 = 3.6 MHz at −8 dBFS, fIN2 = 4.2 MHz at −8 dBFS
fIN1 = ꢁ.2 MHz at −8 dBFS, fIN2 = 8.4 MHz at −8 dBFS
ANALOG INPUT BANDWIDTH
APERTURE JITTER
2ꢀ°C
2ꢀ°C
2ꢀ°C
2ꢀ°C
2ꢀ°C
93
92.ꢀ
92.ꢀ
dBc
dBc
dBc
10
1
MHz
ps rms
1 See the AN-83ꢀ Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Noise figure with respect to ꢀ0 Ω. AD9261 internal impedance is 1000 Ω differential. See the AN-83ꢀ Application Note for a definition.
DIGITAL DECIMATION FILTERING CHARACTERISTICS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted.
Table 3.
2.5 MHz BW
Typ
5 MHZ BW
Typ
10 MHz BW
Typ
Parameter1
Min
Max
Min
Max
Min
Max
Unit
MHz
dB
MHz
dB
Pass-Band Transition
Pass-Band Ripple
Stop Band
2.ꢀ
3.ꢁꢀ
ꢀ
6.ꢀ
10
13
<0.1
3.ꢁꢀ MHz − fS/2
>8ꢀ
<0.1
6.ꢀ MHz − fS/2
>8ꢀ
<0.1
13 MHz − fS/2
>8ꢀ
Stop Band Attenuation
1 See the AN-83ꢀ Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. 0 | Page 4 of 28
AD9261
DIGITAL SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 4.
Parameter1
Temp
Min
Typ
Max
Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
CMOS/LVPECL
2
Full
Full
Full
Full
Full
Full
0.4
0.3
−60
−60
0.8
V p-p
V
μA
μA
kΩ
pF
0.4ꢀ0
0.ꢀ
+60
+60
20
1
LOGIC INPUTS (SCLK)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Full
Full
Full
Full
Full
Full
1.2
0
−ꢀ0
−10
DRVDD + 0.3
0.8
−ꢁꢀ
+10
V
V
μA
μA
kΩ
pF
30
2
LOGIC INPUTS (SDIO, CSB, RESET)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Full
Full
Full
Full
Full
Full
1.2
0
−10
+40
DRVDD + 0.3
0.8
+10
V
V
μA
μA
kΩ
pF
+13ꢀ
Input Resistance
Input Capacitance
26
ꢀ
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage (VOH, IOH = ꢀ0 μA)
High Level Output Voltage (VOH, IOH = 0.ꢀ mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = ꢀ0 μA)
DRVDD = 1.8 V
Full
Full
Full
Full
3.29
3.2ꢀ
V
V
V
V
0.2
0.0ꢀ
High Level Output Voltage (VOH, IOH = ꢀ0 μA)
High Level Output Voltage (VOH, IOH = 0.ꢀ mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = ꢀ0 μA)
Full
Full
Full
Full
1.ꢁ9
1.ꢁꢀ
V
V
V
V
0.2
0.0ꢀ
1 See the AN-83ꢀ Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. 0 | Page ꢀ of 28
AD9261
SWITCHING SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 5.
Parameter1
Temp
Min
Typ
Max
Unit
CLOCK INPUT (USING CLOCK MULTIPLIER)
Conversion Rate
Full
Full
Full
30
160
33
60
MSPS
ns
%
CLK Period
CLK Duty Cycle
6.2ꢀ
40
ꢀ0
CLOCK INPUT (DIRECT CLOCKING)
Conversion Rate
CLK Period
Full
Full
Full
608
1.49
40
640
1.ꢀ62ꢀ
ꢀ0
6ꢁ2
1.64
60
MSPS
ns
%
CLK Duty Cycle
DATA OUTPUT PARAMETERS
Output Data Rate
Full
Full
Full
Full
Full
Full
Full
Full
20
3
168
MSPS
ns
Cycles
2
DCO to Data Skew (tSKEW
Sample Latency
WAKE-UP TIME3
Power Down Power
Standby Power
)
960
3
9
1ꢀ
960
ꢂs
ꢂs
ꢂs
Sleep Power
OUT-OF-RANGE RECOVERY TIME
SERIAL PORT INTERFACE4
SCLK Period
Cycles
Full
Full
Full
Full
Full
Full
Full
40
16
16
ꢀ
ns
ns
ns
ns
ns
ns
ns
SCLK Pulse Width High Time (tSHIGH
)
SCLK Pulse Width Low Time (tSLOW
SDIO to SCLK Setup Time (tSDS
SDIO to SCLK Hold Time (tSDH
CSB to SCLK Setup Time (tSS)
CSB to SCLK Hold Time (tSH)
)
)
)
2
ꢀ
2
1 See the AN-83 ꢀ Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Data skew is measured from DCO ꢀ0% transition to data (D0 to D1ꢀ) ꢀ0% transition, with ꢀ pF load.
3 Wake-up time is dependent on the value of the decoupling capacitors. Values are shown with 10 μF capacitor on VREF and CFILT.
4 See Figure ꢀ0 and the Serial Port Interface (SPI) section.
Timing Diagram
DCO
tSKEW
D0 TO D15
Figure 2. Timing Diagram
Rev. 0 | Page 6 of 28
AD9261
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints, maximizing the
thermal capability of the package.
Parameter
Rating
Electrical
AVDD to AGND
DVDD to DGND
DRVDD to DGND
AGND to DGND
AVDD to DRVDD
CVDD to CGND
CGND to DGND
D0 to D1ꢀ to DGND
DCO to DGND
OR to DGND
PDWN to GND
PLLMULTx to DGND
SDIO to DGND
CSB to AGND
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +0.3 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +2.ꢀ V
−0.3 V to +2.0 V
Table 7. Thermal Resistance
Package Type
θJA
θJB
θJC
Unit
48-Lead LFCSP (CP-48-1)
2ꢁ.ꢁ
11.8
1.1
°C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA.
ESD CAUTION
SCLK to AGND
VIN+, VIN− to AGND
CLK+, CLK− to CGND
Environmental
Storage Temperature Range
Operating Temperature Range
−6ꢀ°C to +12ꢀ°C
−40°C to +8ꢀ°C
Lead Temperature (Soldering, 10 Sec) 300°C
Junction Temperature 1ꢀ0°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page ꢁ of 28
AD9261
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK–
CVDD
1
2
3
4
5
6
7
8
9
36 PLLMULT0/SCLK
35 PLLMULT1/SDIO
34 PLLMULT2
PIN 1
INDICATOR
PDWN
33 PLLMULT3
DVDD
DGND
32 PLLMULT4
AD9261
DRVDD
PLL_LOCKED
DCO
DVDD
31
30 DGND
29 DRVDD
28 OR
TOP VIEW
(Not to Scale)
D0
D1 10
D2 11
D3 12
27 D15
26 D14
25 D13
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR
THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB
INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING
THE THERMAL CAPACITY OF THE PACKAGE.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLK−
Clock Input (−).
2
CVDD
Clock Supply (1.8 V).
3
PDWN
DVDD
External Power-Down Pin.
Digital Supply (1.8 V).
4, 19, 31
ꢀ, 18, 30
DGND
Digital Ground.
6, 1ꢁ, 29
ꢁ
8
DRVDD
PLL_LOCKED
DCO
Digital Output Driver Supply (1.8 V to 3.3 V).
PLL Lock Indicator.
Data Clock Output.
9 to 16, 20 to 2ꢁ
28
D0 to D1ꢀ
OR
Data Output Bits. D0 is the LSB and D1ꢀ is the MSB.
Overrange Indicator.
32, 33, 34
PLLMULT4, PLLMULT3, PLLMULT2 PLL Mode Selection Pins.
3ꢀ
36
3ꢁ
38, 46
39, 42, 4ꢀ
40
41
43
PLLMULT1/SDIO
PLLMULT0/SCLK
CSB
AGND
AVDD
VREF
CFILT
VIN+
PLL Mode Selection Pin/Serial Port Interface Data Input/Output.
PLL Mode Selection Pin/Serial Port Interface Clock.
Serial Port Interface Chip Select. Active low.
Analog Ground.
Analog Supply (1.8 V).
Voltage Reference Input/Output.
Noise Limiting Filter Capacitor.
Analog Input (+).
44
VIN–
Analog Input (−).
4ꢁ
CGND
Clock Ground.
48
CLK+
Clock Input (+).
49
EPAD
Analog Ground. Pin 49 is the exposed thermal pad on the bottom of the package.
Rev. 0 | Page 8 of 28
AD9261
TYPICAL PERFORMANCE CHARACTERISTICS
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS,
TA = 25°C, unless otherwise noted.
0
0
BANDWIDTH: 2.5MHz
DATA RATE: 40MSPS
BANDWIDTH: 2.5MHz
DATA RATE: 40MSPS
–20
–20
f
f
: 2.1MHz AT –8dBFS
: 2.5MHz AT –8dBFS
f
: 600kHz AT –2dBFS
IN1
IN2
IN
SNR: 88.8dB
SFDR: 90dBc
–40
–40
SFDR: 90.6dBc
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.5 MHz, and BW = 2.5 MHz
Figure 4. Single-Tone FFT with fIN = 600 kHz and BW = 2.5 MHz
0
0
BANDWIDTH: 5MHz
DATA RATE: 40MSPS
BANDWIDTH: 5MHz
DATA RATE: 40MSPS
–20
–20
f
f
: 2.1MHz AT –8dBFS
: 2.4MHz AT –8dBFS
f
: 1.2MHz AT –2dBFS
IN1
IN2
IN
SNR: 86dB
SFDR: 90.3dBc
–40
–60
–40
–60
SFDR: 91.9dBc
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. Single-Tone FFT with fIN = 1.2 MHz and BW = 5 MHz
Figure 7. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz and BW = 5 MHz
Rev. 0 | Page 9 of 28
AD9261
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS,
10 MHz bandwidth, output data rate 40 MSPS, TA = 25°C, unless otherwise noted.
0
0
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
–20
–20
f
: 2.4MHz AT –2dBFS
f
f
: 2.1MHz AT –8dBFS
: 2.4MHz AT –8dBFS
IN
IN1
IN2
SNR: 83.2dB
SFDR: 92.6dBc
–40
–40
SFDR: 91.2dBc
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. Single-Tone FFT with fIN = 2.4 MHz
Figure 11. Two-Tone FFT with fIN1 = 2.1 MHz and fIN2 = 2.4 MHz
0
–20
0
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
–20
f
f
: 3.6MHz AT –8dBFS
: 4.2MHz AT –8dBFS
f
: 4.2MHz AT –2dBFS
IN1
IN2
IN
SNR: 83.1dB
SFDR: 91.5dBc
–40
–40
–60
SFDR: 92.2dBc
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Single-Tone FFT with fIN = 4.2 MHz
Figure 12. Two-Tone FFT with fIN1 = 3.6 MHz and fIN2 = 4.2 MHz
0
–20
0
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
BANDWIDTH: 10MHz
DATA RATE: 40MSPS
–20
f
: 8.4MHz AT –2dBFS
f
f
: 7.2MHz AT –8dBFS
: 8.4MHz AT –8dBFS
IN
IN1
IN2
SNR: 83dB
SFDR: 105.7dBc
–40
–40
–60
SFDR: 93dBc
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Single-Tone FFT with fIN = 8.4 MHz
Figure 13. Two-Tone FFT with fIN1 = 7.2 MHz and fIN2 = 8.4 MHz
Rev. 0 | Page 10 of 28
AD9261
110
105
100
95
120
100
80
SFDR (dBFS)
SNR (dBFS)
60
SFDR (dBc)
SNR (dB)
SFDR (dB)
90
40
SNR (dB)
85
80
20
0
0
1
2
3
4
5
6
7
8
9
10
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 14. Single-Tone SNR and SFDR vs. Input Amplitude with fIN = 2.4 MHz
Figure 17. SNR/SFDR vs. Input Frequency
–40
92
91
1.9V
–50
–60
SFDR
90
89
1.8V
1.7V
SFDR (dBc)
–70
88
87
86
85
84
83
82
81
–80
–90
SNR
–100
1.9V
1.8V
SFDR (dB)
–110
1.7V
–120
–60
–50
–40
–30
–20
–10
–60
–40
–20
0
20
40
60
80
100
INPUT AMPLITUDE (dBFS)
TEMPERATURE (°C)
Figure 18. SFDR/SNR vs. Temperature with fIN = 2.4 MHz
Figure 15. Two-Tone SFDR/IMD3 vs. Input Amplitude
with fIN1 = 2.1 MHz and fIN2 = 2.4 MHz
94
92
84.0
SFDR (dBc)
83.8
83.6
83.4
83.2
83.0
82.8
82.6
82.4
82.2
82.0
90
88
86
84
82
80
SNR (dBc)
20
40
60
80
100
120
140
160
1.700 1.725 1.750 1.775 1.800 1.825 1.850 1.875 1.900
OUTPUT DATA RATE (MSPS)
COMMON-MODE VOLTAGE (V)
Figure 16: SNR/SFDR vs. Output Data Rate with fIN = 2.4 MHz
Figure 19. SNR vs. Input Common Mode Voltage with fIN = 2.4 MHz
Rev. 0 | Page 11 of 28
AD9261
1.0
0.5
84
83
82
81
2.4MHz
8.4MHz
0
–0.5
–1.0
–1.5
–2.0
80
79
78
77
0
8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
OUTPUT CODE
1
8
9
10 12 14 15 16 17 18 20 21 24 25 28 30 32 34 42
PLL DIVIDE RATIO
Figure 21. INL with fIN = 2.4 MHz
Figure 20. Single-Tone SNR vs. PLL Divide Ratio
Rev. 0 | Page 12 of 28
AD9261
EQUIVALENT CIRCUITS
AVDD
26kΩ
1kΩ
CSB
500Ω
2V p-p DIFFERENTIAL
1.8V CM
500Ω
Figure 22. Equivalent Analog Input Circuit
Figure 26. Equivalent CSB Input Circuit
CVDD
DRVDD
CLK+
CLK–
10kΩ
90kΩ
10kΩ
30kΩ
CVDD
DRGND
Figure 27. Equivalent Digital Output Circuit
Figure 23. Equivalent Clock Input Circuit
DRVDD
2.85kΩ
8.5kΩ
10kΩ
0.5V
1kΩ
SDIO
3.5kΩ
10µF
TO CURRENT
GENERATOR
Figure 28. Equivalent VREF Circuit
Figure 24. Equivalent SDIO Input Circuit
1kΩ
SCLK
30kΩ
Figure 25. Equivalent SCLK Input Circuit
Rev. 0 | Page 13 of 28
AD9261
THEORY OF OPERATION
DIGITAL FILTER CUTOFF FREQUENCY
The AD9261 uses a continuous time Σ-Δ modulator to convert
the analog input to a digital word. The digital word is processed
by the decimation filter and rate-adjusted by the sample rate
converter (see Figure 29). The modulator consists of a continuous
fMOD/32
fMOD/16
time loop filter preceding a quantizer that samples at fMOD
=
BAND OF INTEREST
640 MSPS. This produces an oversampling ratio (OSR) of 32 for
a 10 MHz input bandwidth. The output of the quantizer is fed
back to a DAC that ideally cancels the input signal. The incom-
plete input cancellation residue is filtered by the loop filter and
is used to form the next quantizer sample.
Figure 32. Digital Filter Cutoff Frequency
MODULATOR
fOUT/2
BAND OF INTEREST
fOUT
fMOD/16
DECIMATION SAMPLE RATE
FILTER
CONVERTER
LOOP FILTER
H(f)
QUANTIZER
ADC
Figure 33. Sample Rate Converter
+
SRC
–
ANALOG INPUT CONSIDERATIONS
The continuous time modulator removes the need for an anti-
alias filter at the input to the AD9261. A discrete time converter
aliases signals around the sample clock frequency and its multiples
to the band of interest (see Figure 34). Therefore, an external
antialias filter is needed to reject these signals.
Figure 29. Σ-Δ Modulator Overview
The quantizer produces a nine-level digital word. The quantization
noise is spread uniformly over the Nyquist band (see Figure 30),
but the feedback loop causes the quantization noise present in
the nine-level output to have a nonuniform spectral shape. This
noise-shaping technique (see Figure 31) pushes the in-band
noise out of band; therefore, the amount of quantization noise
in the frequency band of interest is minimal.
DESIRED
INPUT
UNDESIRED
SIGNAL
fS
fS/2
ADC
Figure 34. Discrete Time Converter
The digital decimation filter that follows the modulator removes
the large out-of-band quantization noise (see Figure 32), while
also reducing the data rate from fMOD to fMOD/16. If the internal
PLL is enabled, the sample rate converter generates samples at
the same frequency as the input clock frequency. If the internal
PLL is disabled, the sample rate converter can be programmed
to give an output frequency that is a divide ratio of the modulator
clock. The sample rate converter is designed to attenuate images
outside the band of interest (see Figure 33).
In contrast, the continuous time Σ-Δ modulator used within the
AD9261 has inherent antialiasing. The antialiasing property
results from sampling occurring at the output of the loop filter
(see Figure 35), and thus aliasing occurs at the same point in the
loop as quantization noise is injected; aliases are shaped by the
same mechanism as quantization noise. The quantization noise
transfer function, NTF(f), has zeros in the band of interest and in
all alias bands because NTF(f) is a discrete time transfer function,
whereas the loop filter transfer function, LF(f), is a continuous
time transfer function, which introduces poles only in the band
of interest. The signal transfer function, being the product of
NTF(f) and LF(f), only has zeros in alias bands and therefore
suppresses all aliases.
QUANTIZATION NOISE
fMOD/2
BAND OF INTEREST
LF(f)
Figure 30. Quantization Noise
LOOP FILTER
INPUT
LF(f)
QUANTIZATION
fMOD
NOISE
fMOD
NOISE SHAPING
OUTPUT
H(z)
fMOD/2
NTF(f)
BAND OF INTEREST
Figure 31. Noise Shaping
f
fMOD
Figure 35. Continuous Time Converter
Rev. 0 | Page 14 of 28
AD9261
Input Common Mode
2V p-p
VIN+
VIN–
50Ω
1:1
The analog inputs of the AD9261 are not internally dc biased. In
ac-coupled applications, the user must provide this bias externally.
Setting the device such that VCM = AVDD is recommended for
optimum performance. The analog inputs are 500 Ω resistors,
and the internal reference loop aims to develop 0.5 V across
each input resistor (see Figure 36). With 0 V differential input,
the driver sources 1 mA into each analog input.
R
T
V
AD9261
S
50Ω
SIGNAL
SOURCE
AVDD
0.1µF
Figure 38. Differential Transformer Configuration
Voltage Reference
AVDD – 0.5V
A stable and accurate 0.5 V voltage reference is built into the
AD9261. The reference voltage should be decoupled to minimize
the noise bandwidth using a 10 μF capacitor. The reference is
used to generate a bias current into a matched resistor such that,
when used to bias the current in the feedback DAC, a voltage
of AVDD − 0.5 V is developed at the internal side of the input
resistors (see Figure 39). The current bias circuit should also be
decoupled on the CFILT pin with a 10 μF capacitor. For this
reason, the VREF voltage should always be 0.5 V.
500Ω
VIN+
V
V
= AVDD
p-p = 2V
TO LOOP FILTER
STAGE 2
CM
IN
VIN–
500Ω
DAC
FROM QUANTIZER
Figure 36. Input Common Mode
Differential Input Configurations
AVDD – 0.5V
The AD9261 can also be configured for differential inputs. The
ADA4937-1 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the ADA4937-1 is easily set by connecting AVDD to
the VOCM pin of the ADA4937-1 (see Figure 37). The noise and
linearity of the ADA4937-1 needs important consideration because
the system performance may be limited by the ADA4937-1.
V
V
= AVDD
p-p = 2V
CM
500Ω
500Ω
IN
VIN+
VIN–
0.5V
TO LOOP
FILTER
STAGE 2
VREF
10kΩ
AVDD
500Ω
REF
10µF
AVDD – 0.5V
+5V
+1.8V
0.1µF
CFILT
0.1µF
10µF
VIN–
200Ω
AVDD
8
Figure 39. Voltage Reference Loop
2V p-p
50Ω
200Ω
2
9
3
11
V
Internal Reference Connection
OCM
ADA4937-1
AD9261
V
R
T
60.4Ω
S
To minimize thermal noise, the internal reference on the AD9261
is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor,
which, when externally decoupled with a 10 μF capacitor, limits
the noise (see Figure 40). The unbuffered reference should not
be used to drive any external circuitry. The internal reference is
used by default.
10
15
SIGNAL
SOURCE
200Ω
VIN+
0.1µF
49.9Ω
0.1µF
60.4Ω
–5V
Figure 37. Differential Input Configuration Using the ADA4937-1
For frequencies offset from dc, where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 38. The center
tap of the secondary winding of the transformer is connected to
AVDD to bias the analog input.
2.85kΩ
8.5kΩ
10kΩ
0.5V
3.5kΩ
10µF
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a couple of megahertz (MHz), and excessive signal power
can cause core saturation, which leads to distortion.
TO CURRENT
GENERATOR
Figure 40. Internal Reference Configuration
Rev. 0 | Page 1ꢀ of 28
AD9261
External Reference Operation
In either case, using the on-chip clock multiplier to generate the
Σ-Δ modulator clock rate or directly sourcing the clock, any
deviation from 640 MHz results in a change in input bandwidth.
The input range of the clock is limited to 640 MHz 5%.
If an external reference is desired, the internal reference can be
disabled by setting Register 0x18[6] high. Figure 41 shows an
application using the ADR130B as a stable external reference.
0.5V
Direct Clocking
ADR130B
AVDD
10kΩ
0.1µF
10µF
The default configuration of the AD9261 is for direct clocking
where the PLL is bypassed. Figure 42 shows one preferred method
for clocking the AD9261. A low jitter clock source is converted
from a single-ended signal to a differential signal using an RF
transformer. The back-to-back Schottky diodes across the
secondary side of the transformer limits clock excursions into the
AD9261 to approximately 0.8 V p-p differential. This helps
prevent the large voltage swings of the clock from feeding
through to other portions of the AD9261 while preserving the
fast rise and fall times of the signal, which are critical to
achieving low jitter.
TO CURRENT
GENERATOR
Figure 41. External Reference Configuration
CLOCK INPUT CONSIDERATIONS
The AD9261 offers two modes of sourcing the ADC sample
clock (CLK+ and CLK−). The first mode uses an on-chip clock
multiplier that accepts a reference clock operating at the lower
input frequency. The on-chip phase-locked loop (PLL) then
multiplies the reference clock up to a higher frequency, which is
then used to generate all the internal clocks required by the ADC
®
MINI-CIRCUITS
TC1-1-13M+, 1:1
The clock multiplier provides a high quality clock that meets
the performance requirements of most applications. Using the
on-chip clock multiplier removes the burden of generating and
distributing the high speed clock.
0.1µF
0.1µF
0.1µF
XFMR
CLK+
CLK–
CLOCK
INPUT
ADC
AD9261
50Ω
SCHOTTKY
DIODES:
HSM2812
The second mode bypasses the clock multiplier circuitry and
allows the clock to be directly sourced. This mode enables the
user to source a very high quality clock directly to the Σ-Δ
modulator. Sourcing the ADC clock directly may be necessary
in demanding applications that require the lowest possible ADC
output noise. Refer to Figure 20, which shows the degradation
in SNR performance for the various PLL settings.
0.1µF
Figure 42. Transformer-Coupled Differential Clock
If a differential clock is not available, the AD9261 can be driven
by a single-ended signal into the CLK+ terminal with the CLK−
terminal ac-coupled to ground. Figure 43 shows the circuit
configuration.
In either case, when using the on-chip clock multiplier or
sourcing the high speed clock directly, it is necessary that the
clock source have low jitter to maximize the ADC noise
performance. High speed, high resolution ADCs are sensitive to
the quality of the clock input. As jitter increases, the SNR
performance of the AD9261 degrades from that specified in
Table 2. The jitter inherent to the part due to the PLL root sum
squares with any external clock jitter, thereby degrading
performance. To prevent jitter from dominating the performance
of the AD9261, the input clock source should be no greater than
1 ps rms of jitter.
0.1µF
CLK+
CLK–
CLOCK
INPUT
ADC
AD9261
50Ω
SCHOTTKY
DIODES:
HSM2812
0.1µF
Figure 43. Single-Ended Clock
Another option is to ac couple a differential LVPECL signal to
the sample clock input pins, as shown in Figure 44. The AD951x
family of clock drivers is recommended because it offers excellent
jitter performance.
The CLK inputs are self-biased to 450 mV (see Figure 23); if
dc-coupled, it is important to maintain the specified 450 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p single-ended about the 450 mV
common-mode voltage. The recommended clock inputs are
CMOS or LVPECL.
0.1µF
0.1µF
CLK+
CLK–
CLOCK
INPUT
CLK
ADC
AD951x
LVPECL
DRIVER
AD9261
100Ω
CLOCK
INPUT
CLK
The specified clock rate of the Σ-Δ modulator, fMOD, is 640 MHz.
The clock rate possesses a direct relationship with the available
input bandwidth of the ADC.
0.1µF
0.1µF
240Ω
240Ω
1
1
50Ω
50Ω
Bandwidth = fMOD ÷ 64
1
50Ω RESISTORS ARE OPTIONAL.
Figure 44. Differential LVPECL Sample Clock
Rev. 0 | Page 16 of 28
AD9261
Table 10. Internal PLL Multiplication Factors
Internal PLL Clock Distribution
0x0A[5:0]
PLLMULT (N) 0x0A[5:0]
PLLMULT (N)
The alternative clocking option available on the AD9261 is to apply
a low frequency reference clock and use the on-chip clock multip-
lier to generate the high frequency fMOD rate. The internal clock
architecture is shown in Figure 45.
1
2
3
4
ꢀ
6
ꢁ
8
8
33
34
3ꢀ
36
3ꢁ
38
39
40
41
42
43
44
4ꢀ
46
4ꢁ
48
49
ꢀ0
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ꢀꢀ
ꢀ6
ꢀꢁ
ꢀ8
ꢀ9
60
61
62
63
64
32
34
34
34
34
34
34
34
34
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
8
8
8
8
8
8
8
9
CLK+/CLK–
PHASE
DETECTOR
LOOP
FILTER
1.28GHz
VCO
PLL
÷2
DIVIDER
÷N
9
10
11
12
13
14
1ꢀ
16
1ꢁ
18
19
20
21
22
23
24
2ꢀ
26
2ꢁ
28
29
30
31
32
10
10
12
12
14
1ꢀ
16
1ꢁ
18
18
20
21
21
21
24
2ꢀ
2ꢀ
2ꢀ
28
28
30
30
32
PLL MULT
0x0A[5:0]
MODULATOR
CLOCK
640MSPS
PLLENABLE
0x09[2]
Figure 45. Internal Clock Architecture
The clock multiplication circuit operates such that the VCO
outputs a frequency, fVCO, equal to the reference clock input
multiplied by N
f
VCO = (CLK ) × (N)
where N is the PLL multiplication (PLLMULT) factor.
The Σ-Δ modulator clock frequency, fMOD, is equal to
f
MOD = fVCO ÷ 2
The reference clock, CLK , is limited to 30 MHz to 160 MHz
when configured to use the on-chip clock multiplier. Given the
input range of the reference clock and the available multiplication
factors, the fVCO is approximately 1280 MHz. This results in the
desired fMOD rate of 640 MHz with a 50% duty cycle.
Before the PLL enable (PLLENABLE) register bit is set, the PLL
multiplication factor should be programmed into Register
0x0A[5:0]. After setting the PLLENABLE bit, the PLL locks and
reports a locked state in Register 0x0A[7]. If the PLL multiplica-
tion factor is changed, the PLL enable bit should be reset and set
again. Some common clock multiplication factors are shown in
Table 11.
External PLL Control
At power-up, the serial interface is disabled until the first serial
port access. If the serial interface is disabled, the PLLMULTx
pins control the PLL multiplication factor. The five PLLMULTx
pins (Pin 32 to Pin 36) offer all the available multiplication
factors. If all PLLMULTx pins are tied high, the PLL is disabled
and the AD9261 assumes the high frequency modulator clock
rate that is applied to the CLK pins. Table 12 shows the relation-
ship between PLLMULTx pins and the PLL multiplication factor.
The recommended sequence for enabling and programming the
on-chip clock multiplier is summarized in Table 9.
Table 9. Sequence for Enabling and Programming the PLL
Step
Procedure
1
2
Apply a reference clock to the CLK pins.
Program the PLL multiplication factor in
Register 0x0A[ꢀ:0]. See Table 10.
3
4
ꢀ
6
Enable the PLL; Register 0x09 = 04 (decimal).
Enable the PLL autoband select.
Initiate an SRC reset; Register 0x101[ꢀ:0] = 0.
Set SRC to the desired value via Register 0x101[ꢀ:0].
Rev. 0 | Page 1ꢁ of 28
AD9261
Jitter Considerations
PLL Autoband Select
The aperture jitter requirements for continuous time Σ-Δ conver-
ters may be more forgiving than Nyquist rate converters. The
continuous time Σ-Δ architecture is an oversampled system,
and to accurately represent the analog input signal to the ADC,
a large number of output samples must be averaged together. As a
result, the jitter contribution from each sample is root sum
squared, resulting in a more subtle impact on noise perfor-
mance as compared to Nyquist converters where aperture jitter
has a direct impact on each sampled output.
The PLL VCO has a wide operating range that is covered by
overlapping frequency bands. For any desired VCO output
frequency, there are multiple valid PLL band select values. The
AD9261 possesses an automatic PLL band select feature on chip
that determines the optimal PLL band setting. This feature can be
enabled by writing to Register 0x0A[6] and is the recommended
configuration with the PLL clocking option. Follow the sequence
shown in Table 9 for enabling the autoband select and configur-
ing the PLL.
In the block diagram of the continuous time Σ-Δ modulator
(see Figure 29), the two building blocks most susceptible to
jitter are the quantizer and the DAC. The error introduced
through the sampling process or quantizer is reduced by the
loop gain and shaped in the same way as the quantization noise
and, therefore, its effect can be neglected. On the contrary, the
jitter error associated to the DAC directly adds to the input
signal, thus increasing the in-band noise power and degrading
the modulator performance. The SNR degradation due to jitter
can be represented by the following equation:
When the device is taken out of sleep or standby mode, Register
0x0A[6] must be toggled to reinitiate the autoband detect.
Table 11. Common Modulator Clock Multiplication Factors
CLK
0x0A[5:0]
fMOD
BW
(MHz)
(PLLMULT)
fVCO (MHz) (MHz)
(MHz)
42
32
2ꢀ
21
1ꢁ
1ꢁ
16
1ꢀ
14
10
10
8
1290.24
12ꢀ8.29
1300.00
1290.24
130ꢀ.60
1326.00
12ꢀ8.29
1344.00
1290.24
1228.80
1344.00
1228.80
12ꢀ8.29
64ꢀ.12
629.1ꢀ
6ꢀ0.00
64ꢀ.12
6ꢀ2.80
663.00
629.1ꢀ
6ꢁ2.00
64ꢀ.12
614.40
6ꢁ2.00
614.40
629.1ꢀ
10.08
9.83
30.ꢁ2
39.3216
ꢀ2.00
61.44
ꢁ6.80
ꢁ8.00
ꢁ8.6432
89.60
10.16
10.08
10.20
10.36
9.83
SNR = −20 log (2πfanalogtjitter_rms) dB
where fanalog is the analog input frequency and tjitter_rms is the jitter.
10.ꢀ0
10.08
9.60
The SNR performance of the AD9261 remains constant within
the input bandwidth of the converter, from dc to 10 MHz.
Therefore, the minimal jitter specification is determined at the
highest input frequency. From the calculation, the aperture
jitter of the input clock must be no greater than 1 ps to achieve
optimal SNR performance.
92.16
122.88
134.40
1ꢀ3.60
1ꢀꢁ.2864
10.ꢀ0
9.60
8
9.83
POWER DISSIPATION AND STANDBY MODE
Table 12. External PLLMULTx Pins and PLL Multiplication
Factor
The AD9261 power consumption can be further reduced by
configuring the chip in channel power-down, standby, or sleep
mode. The low power modes turn off internal blocks of the chip
including the reference. As a result, the wake-up time is depen-
dent on the amount of circuitry that is turned off. Fewer internal
circuits that are powered down result in proportionally shorter
wake-up time. The different low power modes are shown in
Table 13. In the standby mode, all clock related activity and the
output channels are disabled. Only the references and CMOS
outputs remain powered up to ensure a short recovery and link
integrity. During sleep mode, all internal circuits are powered
down, putting the device into its lowest power mode, and the
CMOS outputs are disabled.
PLLMULTx[4:0] Pins
PLL Multiplication Factors (N)
0
8
1
9
2
10
3
12
4
14
ꢀ
1ꢀ
6
16
ꢁ
1ꢁ
8
18
9
20
10
21
11
24
If the serial port interface is not available, the AD9261 can be
configured in power-down mode by connecting Pin 3 (PDWN)
to AVDD.
12
2ꢀ
13
28
14
30
1ꢀ
32
16
34
1ꢁ to 30
31
42
Direct clocking
Rev. 0 | Page 18 of 28
AD9261
Table 13. Low Power Modes
Table 14. DEC4 Filter Coefficients
Mode
0x08[1:0] Analog Circuitry
Clock Ref
Coefficient
Number
Coefficient
Coefficient Number
Normal
Power-Down
Standby
Sleep
0x0
0x1
0x2
0x3
On
Off
Off
Off
On
On
Off
Off
On
On
On
Off
Coefficient
1121
0
−2ꢁ96
0
10,184
16,384
C0, C22
C1, C21
C2, C20
C3, C19
C4, C18
Cꢀ, C1ꢁ
−21
0
122
0
−418
0
C6, C16
Cꢁ, C1ꢀ
C8, C14
C9, C13
C10, C12
C11
DIGITAL ENGINE
Bandwidth Selection
The digital engine (see Figure 46) selects the decimation signal
bandwidth by cascading third-order sinc (sinc3) decimate-by-2
filters. For a 10 MHz signal band, no filters are cascaded; for a
5 MHz signal band, a single filter is used; and for a 2.5 MHz
signal band, the 5 MHz filter is cascaded with a second filter.
Depending on the signal bandwidth, this drops the data rate
into the fixed decimation filter. As a result, lower signal bandwidth
options result in lower power. Bandwidth selection is determined
by setting Register 0x0F[6:5].
Table 15. LPF/EQZ Filter Coefficients
Coefficient
Number
Coefficient
Coefficient
1ꢁ
Number
C16, C46
C1ꢁ, C4ꢀ
C18, C44
C19, C43
C20, C42
C21, C41
C22, C40
C23, C39
C24, C38
C2ꢀ, C3ꢁ
C26, C36
C2ꢁ, C3ꢀ
C28, C34
C29, C33
C30, C32
C31
Coefficient
694
−ꢁ44
−6ꢁꢁ
12ꢁ1
4ꢀ0
−1909
103
C0, C62
C1, C61
C2, C60
C3, Cꢀ9
C4, Cꢀ8
Cꢀ, Cꢀꢁ
C6, Cꢀ6
Cꢁ, Cꢀꢀ
C8, Cꢀ4
C9, Cꢀ3
C10, Cꢀ2
C11, Cꢀ1
C12, Cꢀ0
C13, C49
C14, C48
C1ꢀ, C4ꢁ
31
−1ꢀ
−ꢀ2
36
ꢁ8
Decimation Filters
−84
−98
1ꢁ0
9ꢁ
−291
−42
441
−98
−ꢀ92
3ꢀ3
A fixed frequency low-pass filter is used to define the signal
band. This filter incorporates magnitude equalization for the
droop of the preceding sinc decimation filters and the sinc
filters of the sample rate converter. Table 14 and Table 15 detail
the coefficients for the DEC4 and LPF/EQZ filters. The preceding
sinc decimation filters are a standard sinc filter implementation.
2612
−114ꢁ
−3326
3022
40ꢀ1
−68ꢁ0
−ꢀ30ꢀ
21,141
38,9ꢀ6
BANDWIDTH SELECTION
DECIMATION FILTERS
10MHz
5MHz
10MHz
5MHz
DEC1
4
DEC2
4
DEC3
DEC4
HB
LPF/EQZ
FIR
DEC01
4
3
6
SINC
2
2
SINC
2
SINC
2
SINC
2
4
2
Σ-Δ
OUTPUT
2.5MHz
2.5MHz
DEC02
3
INT1
HB
INT2
HB
INT3
5
INT4
SINC
10MHz
5MHz
16
DATA
5
SINC
8
2
2
2
SINC
2.5MHz
OUTPUT
SAMPLE RATE CONVERTER
NCO
Figure 46. Digital Engine
Rev. 0 | Page 19 of 28
AD9261
Sample Rate Converter
Table 18. SRC Conversion Factors
The sample rate converter (SRC) allows the flexibility of a user-
defined output sample rate, enabling a more efficient and direct
interface to the digital receiver blocks.
0x101[5:0]
KOUT
0x101[5:0]
KOUT
11
0x101[5:0]
KOUT
22
0
SRC reset
22
23
24
2ꢀ
26
2ꢁ
28
29
30
31
32
33
34
3ꢀ
36
3ꢁ
38
39
40
41
42
43
44
4ꢀ
46
4ꢁ
48
49
ꢀ0
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ꢀꢀ
ꢀ6
ꢀꢁ
ꢀ8
ꢀ9
60
61
62
63
1
4
11.ꢀ
12
22.ꢀ
23
2
4
The sample rate converter performs an interpolation and
resampling procedure to provide an output data rate of
20 MSPS to 168 MSPS. Table 16 and Table 17 detail the coeffi-
cients for the INT1 and INT2 filters. The sinc filters are a
standard implementation.
3
4
12.ꢀ
13
23.ꢀ
24
4
4
ꢀ
4
13.ꢀ
14
24.ꢀ
2ꢀ
6
4
ꢁ
4
14.ꢀ
1ꢀ
2ꢀ.ꢀ
26
8
4
Table 16. INT1 Filter Coefficients
9
4.ꢀ
ꢀ
1ꢀ.ꢀ
16
26.ꢀ
2ꢁ
Coefficient
Number
Coefficient
Coefficient Number
10
11
12
13
14
1ꢀ
16
1ꢁ
18
19
20
21
Coefficient
ꢀ.ꢀ
6
16.ꢀ
1ꢁ
2ꢁ.ꢀ
28
C0, C26
C1, C2ꢀ
C2, C24
C3, C23
C4, C22
Cꢀ, C21
C6, C20
1ꢀ
Cꢁ, C19
C8, C18
C9, C1ꢁ
C10, C16
C11, C1ꢀ
C12, C14
C13
0
6.ꢀ
ꢁ
1ꢁ.ꢀ
18
28.ꢀ
29
0
−9ꢁ
0
24ꢀ0
0
ꢁ.ꢀ
8
18.ꢀ
19
29.ꢀ
30
−ꢀꢁ61
0
361
0
8.ꢀ
9
19.ꢀ
20
30.ꢀ
31
20433
32ꢁ68
−101ꢁ
9.ꢀ
10
10.ꢀ
20.ꢀ
21
31.ꢀ
21.ꢀ
Table 17. INT2 Filter Coefficients
Cascaded Filter Responses
The cascaded filter responses for the three signal bandwidth
settings are for a 160 MSPS output data rate, as shown in Figure 47,
Figure 48, and Figure 49.
Coefficient
Number
Coefficient
Coefficient Number
Coefficient
−1032
0
4928
8192
C0, C14
C1, C13
C2, C12
C3, C11
−2ꢁ
0
C4, C10
Cꢀ, C9
C6, C8
Cꢁ
22ꢁ
0
0
0.08
–20
0.04
The relationship between the output sample rate and the Σ-Δ
modulator clock rate is expressed as follows:
–40
0
–60
–0.04
f
OUT = fMOD ÷ KOUT
–0.08
–80
Table 18 shows the available KOUT conversion factors.
0
2
4
6
8
10
FREQUENCY (MHz)
–100
–120
–140
–160
If the main clocking source of the AD9261 is provided by the
PLL, it is important that once the PLL has been programmed
and locked, to initiate an SRC reset before programming the
desired KOUT factor. This is done by first writing 0x101[5:0] = 0
and then rewriting to the same register with the appropriate
0
10
20
30
40
50
60
70
80
K
OUT value. In addition, if the AD9261 loses its clock source and
FREQUENCY (MHz)
then later regains it, an SRC reset should be initiated.
Figure 47. 10 MHz Signal Bandwidth, 160 MSPS
Rev. 0 | Page 20 of 28
AD9261
0
–20
an overrange condition typically extends well beyond one clock
cycle—that is, it does not toggle at the DCO rate—data can
usually be successfully detected on the rising edge of DCO or
monitored asynchronously.
0.08
0.04
0
–40
–60
–0.04
–0.08
The AD9261 has two trip points that can trigger an overrange
condition: analog and digital. The analog trip point is located
in the modulator, and the second trip point is in the digital
engine. In normal operation, it is possible for the analog trip
point to toggle the OR pin for a number of clock cycles as the
analog input approaches full scale. Because the OR pin is a pulse-
width modulated (PWM) signal, as the analog input increases
in amplitude, the duration of overrange pin toggling increases.
Eventually, when the OR pin is high for an extended period of
time, the ADC is overloaded, and there is little correspondence
between analog input and digital output.
–80
0
1
2
3
4
5
FREQUENCY (MHz)
–100
–120
–140
–160
0
10
20
30
40
50
60
70
80
FREQUENCY (MHz)
Figure 48. 5 MHz Signal Bandwidth, 160 MSPS
0
–20
0.08
0.04
0
The second trip point is in the digital block. If the input signal
is large enough to cause the data bits to clip to the maximum
full-scale level, an overrange condition occurs. The overrange
trip point can be adjusted by specifying a threshold level.
–40
–60
–0.04
–0.08
–80
Table 19 shows the corresponding threshold level in dBFS vs.
register setting. If the input signal crosses this level, the OR pin
is set. In the case where 0x111[5:0] is set to all 0s, the threshold
level is set to the maximum code of 32,76710. This feature
provides a means of reporting the instantaneous amplitude as it
crosses a user-provided threshold. This gives the user a sense
for the signal level without needing to perform a full power
measurement.
0.5
1.5
2.5
FREQUENCY (MHz)
–100
–120
–140
–160
0
10
20
30
40
50
60
70
80
FREQUENCY (MHz)
Figure 49. 2.5 MHz Signal Bandwidth, 160 MSPS
The user has the ability to select how the overrange conditions
are reported, and this is controlled through Register 0x111 via
AUTORST, OR_IND, and ORTHRESH (see Table 20). By
enabling the AUTORST bit, Register 0x111[7], if an overrange
occurs, the ADC automatically resets itself. The OR pin remains
high until the automatic reset has completed. If an analog trip
occurs, the modulator resets itself after 16 consecutive clock
cycles of overrange.
DIGITAL OUTPUTS
Digital Output Format
The AD9261 offers a variety of digital output formats for ease of
system integration. The digital output consists of 16 data bits and
an output clock signal (DCO) for data latching. The data bits can
be configured for offset binary, twos complement, or Gray code
by writing to Register 0x14[1:0]. In addition, the voltage swing of
the digital outputs can be configured to 3.3 V TTL levels or a
reduced voltage swing of 1.8 V by accessing Register 0x14[7].
When 3.3 V voltage levels are desirable, the DRVDD power
supply must be set to 3.3 V.
If the AD9261 is used in a system that incorporates automatic
gain control (AGC), the OR signal can be used to indicate that
the signal amplitude should be reduced. This may be particularly
effective for use in maximizing the signal dynamic range if the
signal includes high occurrence components that occasionally
exceed full scale by a small amount.
Overrange (OR) Condition
The OR pin serves as an indicator for an overrange condition. The
OR pin is triggered by in-band signals that exceed the full-scale
range of the ADC. In addition, the AD9261 possesses out-of-
band gain above 10 MHz; therefore, a large out-of-band signal
may trip an overrange condition.
TIMING
The AD9261 provides a data clock out (DCO) pin to assist
in capturing the data in an external register. The data outputs
are valid on the rising edge of DCO, unless changed by setting
Register 0x16[7]. See Figure 2 for a graphical timing description.
The OR pin is a synchronous output that is updated at the out-
put data rate. Ideally, OR should be latched on the falling edge of
DCO to ensure proper setup-and-hold time. However, because
Rev. 0 | Page 21 of 28
AD9261
Table 19. OR Threshold Levels
0x111[5:0]
Threshold (dBFS)
0x111[5:0]
16
Threshold (dBFS)
−9.28
0x111[5:0]
2B
Threshold (dBFS)
−3.4ꢀ
1
−36.12
−30.10
−26.ꢀ8
−24.08
−22.14
−20.ꢀ6
−19.22
−18.06
−1ꢁ.04
−16.12
−1ꢀ.29
−14.ꢀ4
−13.84
−13.20
−12.60
−12.04
−11.ꢀ1
−11.02
−10.ꢀ6
−10.10
−9.68
2
3
4
ꢀ
6
ꢁ
8
9
A
B
C
D
E
1ꢁ
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
2ꢀ
26
2ꢁ
28
−8.89
−8.ꢀ2
−8.16
−ꢁ.82
−ꢁ.ꢀ0
−ꢁ.18
−6.88
−6.ꢀ8
−6.30
−6.02
−ꢀ.ꢁꢀ
−ꢀ.49
−ꢀ.24
−ꢀ.00
−4.ꢁ6
−4.ꢀ3
2C
2D
2E
2F
30
31
32
33
34
3ꢀ
36
3ꢁ
38
39
3A
3B
3C
3D
3E
−3.2ꢀ
−3.06
−2.8ꢁ
−2.68
−2.ꢀ0
−2.32
−2.14
−1.9ꢁ
−1.80
−1.64
−1.48
−1.32
−1.16
−1.00
−0.86
−0.ꢁ1
F
10
11
12
13
14
1ꢀ
−4.30
−4.08
−3.8ꢁ
−3.66
−0.ꢀ6
−0.42
−0.28
−0.14
29
2A
3F
Table 20. OR Conditions
OR Conditions
AUTORST OR_IND ORTHRESH[5:0] ORTHRESH[4:0] Description
Normal, Reset Off
0
0
0
0
0
00000
Digital trip: if 16-bit output > 32,ꢁ6ꢁ, OR = 1, else OR = 0
Digital Threshold,
Reset Off
>0
Digital threshold: If 16-bit output > ORTHRESH, OR = 1,
else OR = 0
Full Overrange,
Reset Off
0
1
0
X1
If analog trip or digital trip, OR = 1, else OR = 0
Data Valid, No Reset
Normal, Reset On
0
1
1
1
0
0
1
0
X1
If analog trip or digital trip or calibration, OR = 0, else OR = 1
Digital trip: if 16-bit output > 32,ꢁ6ꢁ, OR = 1, else OR = 0
00000
Digital Threshold,
Reset On
>0
Digital threshold: if 16-bit output > ORTHRESH, OR = 1,
else OR = 0
Full Overrange,
Reset On
1
1
1
1
0
1
X1
X1
If analog trip or digital trip, OR = 1, else OR = 0
Data Valid,
Reset On
If analog trip or digital trip or calibration, OR = 0 else OR = 1
1 X = don’t care.
Rev. 0 | Page 22 of 28
AD9261
SERIAL PORT INTERFACE (SPI)
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit words.
The first bit of each individual byte of serial data indicates whether
a read or write command is issued. This allows the serial data
input/output (SDIO) pin to change direction from an input to
an output.
The AD9261 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. This provides
the user added flexibility and customization depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that are further divided into fields, as documented in
the Memory Map section. For detailed operational information,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as to read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
CONFIGURATION USING THE SPI
As summarized in Table 21, three pins define the SPI of this ADC.
The SCLK pin synchronizes the read and write data presented
to the ADC. The SDIO pin allows data to be sent and read from
the internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
Data can be sent in MSB-first or in LSB-first mode. MSB first is
the default setting on power-up and can be changed via the
configuration register. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Table 21. Serial Port Interface Pins
Pin Name
SCLK
Description
Table 22. SPI Timing Diagram Specifications
Parameter Description
SCLK (serial clock) is the serial shift clock. SCLK
synchronizes serial interface reads and writes.
SDIO (serial data input/output) is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select bar) is an active low control that
gates the read and write cycles.
tSDS
tSDH
tSCLK
tSS
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SDIO
CSB
tSH
The falling edge of CSB in conjunction with the rising edge of
SCLK determines the start of the framing. Figure 50 and Table 22
provide an example of the serial timing and its definitions.
tSHIGH
Minimum period that SCLK should be in a logic
high state
Minimum period that SCLK should be in a logic
low state
tSLOW
Other modes involving CSB are available. CSB can be held low
indefinitely to permanently enable the device (this is called
streaming). CSB can stall high between bytes to allow for addi-
tional external timing. When CSB is tied high, SPI functions are
placed in a high impedance mode.
tSDS
tSHIGH
tSCLK
tSH
tSS
tSDH
tSLOW
CSB
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 50. Serial Port Interface Timing Diagram
Rev. 0 | Page 23 of 28
AD9261
HARDWARE INTERFACE
The pins described in Table 21 comprise the physical interface
between the programming device of the user and the serial port
of the AD9261. The SCLK and CSB pins function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
such method is described in detail in the AN-812 Application
Note, MicroController-Based Serial Port Interface (SPI) Boot
Circuit.
When the SPI interface is not used, some pins serve a dual
function. When strapped to AVDD or ground during device
power-on, the pins are associated with a specific function.
The SPI interface is flexible enough to be controlled by either
PROM or PIC microcontrollers. This provides the user with the
ability to use an alternate method to program the ADC. One
Rev. 0 | Page 24 of 28
AD9261
MEMORY MAP
Table 23. Memory Map
Register Name
SPI Port Config
Chip ID
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00
0x01
0x02
0x08
0x09
0x0A
0x0F
0x14
0x1ꢀ
0x16
0x18
0x101
0x111
0
LSBFIRST
SOFTRESET
1
1
SOFTRESET
LSBFIRST
0
CHIPID[ꢁ:0]
CHILDID[2:0]
Chip Grade
Power Modes
PLLENABLE
PLL
PWRDWN[1:0]
PLLENABLE
PLLLOCKED
DRVSTD
PLLAUTO
PLLMULT[ꢀ:0]
Analog Input
Output Modes
Output Adjust
Output Clock
Reference
BW[1:0]
Interleave
OUTENB
OUTINV
Format[1:0]
DRVSTR33[1:0]
DRVSTR18[1:0]
DCOINV
EXTREF
OR_IND
Output Data
Overrange
KOUT[ꢀ:0]
AUTORST
ORTHRESH[ꢀ:0]
MEMORY MAP DEFINITIONS
Table 24. Memory Map Definitions
Register
Address
Bit(s)
Mnemonic
Default
Description
SPI Port Config
0x00
6, 1
LSBFIRST
0
0: serial interface uses MSB first format
1: serial interface uses LSB first format
ꢀ, 2
SOFTRESET
CHIPID
0
1: default all serial registers except 0x00, 0x09, and 0x0A
0x26: AD9261
Chip ID
0x01
0x02
0x08
[ꢁ:0]
[ꢀ:4]
[1:0]
0x26
Chip Grade
Power Modes
CHILDID
PWRDWN
0
0
0x00: 10 MHz bandwidth
0x0: normal operation
0x1: power-down (local)
0x2: standby (everything except reference circuits)
0x3: sleep
PLLENABLE
PLL
0x09
0x0A
2
ꢁ
PLLENABLE
PLLLOCKED
0
0
1: enable PLL
0: PLL is not locked
1: PLL is locked
6
[ꢀ:0]
[6:ꢀ]
PLLAUTO
PLLMULT
BW
0
0
0
1: PLL autoband enabled
See Table 10
Analog Input
0x0F
0x14
0x0: 10 MHz
0x1: ꢀ MHz
0x2: 2.ꢀ MHz
0x3: 10 MHz
Output Modes
ꢁ
DRVSTD
0
0: 3.3 V
1: 1.8 V
ꢀ
4
2
[1:0]
Interleave
OUTENB
OUTINV
Format
0
0
0
0
1: interleave both channels onto D[1ꢀ:0]
1: data outputs tristated
1: data outputs bitwise inverted
0: offset binary
1: twos complement
2: Gray code
3: offset binary
Rev. 0 | Page 2ꢀ of 28
AD9261
Register
Address
Bit(s)
Mnemonic
Default
Description
Output Adjust
0x1ꢀ
[3:2]
DRVSTR33
0
Typical output sink current to DGND
0: 33 mA
1: 63 mA
2: 93 mA
3: 120 mA
[1:0]
DRVSTR18
2
Typical output sink current to DGND
0: 10 mA
1: 20 mA
2: 30 mA
3: 39 mA
Output Clock
Reference
0x16
ꢁ
DCOINV
EXTREF
KOUT
0
0
0
0
0
0
1: invert DCO
0x18
6
1: use external reference
Output data rate, see Table 18
1: enable loop filter reset indicator on OR pin
See Table 20
Output Data
Overrange
0x101
0x111
[ꢀ:0]
ꢁ
6
AUTORST
OR_IND
ORTHRESH
[ꢀ:0]
See Table 19
Rev. 0 | Page 26 of 28
AD9261
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
SECTION OF THIS DATA SHEET.
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 51. 48-Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad (CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +8ꢀ°C
−40°C to +8ꢀ°C
Package Description
Package Option
AD9261BCPZ-10
AD9261BCPZRLꢁ-10
AD9261-10EBZ
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
CP-48-1
CP-48-1
1 Z = RoHS Compliant Part.
Rev. 0 | Page 2ꢁ of 28
AD9261
NOTES
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D07803-0-4/10(0)
Rev. 0 | Page 28 of 28
相关型号：
AD9262BCPZ
2-CH 16-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, QCC64, 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
ROCHESTER
AD9262BCPZ
16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC
ADI
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