AD9259-50EB1 [ADI]
High Speed ADC USB FIFO Evaluation Kit; 高速ADC的USB FIFO评估套件型号: | AD9259-50EB1 |
厂家: | ADI |
描述: | High Speed ADC USB FIFO Evaluation Kit |
文件: | 总28页 (文件大小:902K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
High Speed ADC USB FIFO Evaluation Kit
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Buffer memory board for capturing digital data
used with high speed ADC evaluation boards
to simplify evaluation
STANDARD
USB 2.0
32 kB FIFO depth at 133 MSPS (upgradable)
Measures performance with ADC Analyzer™
Real-time FFT and time domain analysis
Analyzes SNR, SINAD, SFDR, and harmonics
Simple USB port interface (2.0)
HSC-ADC-EVALB-SC
OR
HSC-ADC-EVALB-DC
SINGLE OR DUAL
HIGH-SPEED ADC
EVALUATION BOARD
Supporting ADCs with serial port interfaces (SPI®)
On-board regulator circuit, no power supply required
6 V, 2 A switching power supply included
CHB FIFO,
32K,
PS
PS
REG
n
Compatible with Windows® 98 (2nd ed.), Windows 2000,
Windows Me, and Windows XP
133MHz
FILTERED
ANALOG
INPUT
+3.0V
REG
TIMING
CIRCUIT
ADC
USB
CTLR
EQUIPMENT NEEDED
Analog signal source and antialiasing filter
Low jitter clock source
CHA FIFO,
32K,
133MHz
n
CLOCK
CIRCUIT
SPI
SPI
High speed ADC evaluation board and ADC data sheet
CLOCK INPUT
PC running Windows 98 (2nd ed.), Windows 2000,
Windows Me, or Windows XP
Latest version of ADC Analyzer
120-PIN CONNECTOR
Figure 1.
USB 2.0 port recommended (USB 1.1-compatible)
PRODUCT HIGHLIGHTS
1. Easy to Set Up. Connect the included power supply and
signal sources to the two evaluation boards. Then connect
to the PC and evaluate the performance instantly.
PRODUCT DESCRIPTION
The high speed ADC FIFO evaluation kit includes the latest
version of ADC Analyzer and a buffer memory board to capture
blocks of digital data from the Analog Devices high speed
analog-to-digital converter (ADC) evaluation boards. The FIFO
board is connected to the PC through a USB port and is used
with ADC Analyzer to quickly evaluate the performance of high
speed ADCs. Users can view an FFT for a specific analog input
and encode rate to analyze SNR, SINAD, SFDR, and harmonic
information.
2. ADIsimADC™. ADC Analyzer supports virtual ADC
evaluation using ADI proprietary behavioral modeling
technology. This allows rapid comparison between multiple
ADCs, with or without hardware evaluation boards. For more
information, see AN-737 at www.analog.com/ADIsimADC.
3. USB Port Connection to PC. PC interface is a USB 2.0
connection (1.1-compatible) to the PC. A USB cable is
provided in the kit.
The evaluation kit is easy to set up. Additional equipment needed
includes an Analog Devices high speed ADC evaluation board,
a signal source, and a clock source. Once the kit is connected
and powered, the evaluation is enabled instantly on the PC.
4. 32 kB FIFO. The FIFO stores data from the ADC for processing.
A pin-compatible FIFO family is used for easy upgrading.
5. Up to 133 MSPS Encode Rate on Each Channel. Single-
channel ADCs with encode rates up to 133 MSPS can be used
with the FIFO board. Multichannel and demultiplexed output
ADCs can also be used with the FIFO board with clock rates
up to 266 MSPS.
Two versions of the FIFO are available. The HSC-ADC-EVALB-
DC is used with multichannel ADCs and converters with demulti-
plexed digital outputs. The HSC-ADC-EVALB-SC evaluation
board is used with single-channel ADCs. See Table 1 to choose
the FIFO appropriate for your high speed ADC evaluation
board.
6. Supports ADC with Serial Port Interface or SPI. Some ADCs
include a feature set that can be changed via the SPI. The FIFO
supports these SPI-driven features through the existing USB
connection to the computer without additional cabling needed.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
TABLE OF CONTENTS
Features .............................................................................................. 1
Equipment Needed........................................................................... 1
Product Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
FIFO Evaluation Board Easy Start.................................................. 3
Requirements ................................................................................ 3
Easy Start Steps ............................................................................. 3
Virtual Evaluation Board Easy Start With ADIsimADC ............ 4
Requirements ................................................................................ 4
Easy Start Steps ............................................................................. 4
FIFO 4.1 Data Capture Board Features ......................................... 5
FIFO 4.1 Supported ADC Evaluation Boards .......................... 6
Theory of Operation ........................................................................ 9
Clocking Description................................................................... 9
SPI Description............................................................................. 9
Clocking with Interleaved Data................................................ 10
Connecting to the HSC-ADC-FPGA-4/-8 ............................. 10
Connecting to the DEMUX BRD ............................................ 10
Upgrading FIFO Memory ......................................................... 10
Jumpers ............................................................................................ 11
Default Settings........................................................................... 11
Evaluation Board ............................................................................ 13
Power Supplies............................................................................ 13
Connection and Setup ............................................................... 13
FIFO Schematics and PCB Layout............................................... 14
Schematics................................................................................... 14
PCB Layout ................................................................................. 21
Bill of Materials............................................................................... 23
Ordering Information.................................................................... 25
Ordering Guide .......................................................................... 25
ESD Caution................................................................................ 25
REVISION HISTORY
2/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
FIFO EVALUATION BOARD EASY START
6. Once the cable is connected to both the computer and the
FIFO board, and power is supplied, the USB drivers start
to install. To complete the total installation of the FIFO
drivers, you need to complete the new hardware sequence
two times. The first Found New Hardware Wizard opens
with the text message This wizard helps you install
software for…Pre-FIFO 4.1. Click the recommended
install, and go to the next screen. A hardware installation
warning window should then be displayed. Click Continue
Anyway. The next window that opens should finish the Pre-
FIFO 4.1 installation. Click Finish. Your computer should
go through a second Found New Hardware Wizard, and
the text message, This wizard helps you install software
for…Analog Devices FIFO 4.1, should be displayed.
Continue as you did in the previous installation and click
Continue Anyway. Then click Finish on the next two
windows. This completes the installation.
REQUIREMENTS
•
•
•
•
•
FIFO evaluation board, ADC Analyzer, and USB cable
High speed ADC evaluation board and ADC data sheet
Power supply for ADC evaluation board
Analog signal source and appropriate filtering
Low jitter clock source applicable for specific ADC
evaluation, typically <1 ps rms
•
•
PC running Windows 98 (2nd ed.), Windows 2000,
Windows Me, or Windows XP
PC with a USB 2.0 port recommended (USB 1.1-
compatible)
EASY START STEPS
Note: You need administrative rights for the Windows
operating systems during the entire easy start procedure.
It is recommended to complete every step before reverting
to a normal user mode.
7. (Optional) Verify in the device manager that Analog
Devices, FIFO4.1 is listed under the USB hardware.
1. Install ADC Analyzer from the CD provided in the FIFO
evaluation kit or download the latest version on the Web.
For the latest updates to the software, check the Analog
Devices website at www.analog.com/hsc-FIFO.
8. Apply power to the evaluation board and check the voltage
levels at the board level.
9. Connect the appropriate analog input (which should be
filtered with a band-pass filter) and low jitter clock signal.
Make sure the evaluation boards are powered on before
connecting the analog input and clock.
2. Connect the FIFO evaluation board to the ADC evaluation
board. If an adapter is required, insert the adapter between
the ADC evaluation board and the FIFO board. If using
the HSC-ADC-EVALB-SC model, connect the evaluation
board to the bottom two rows of the 120-pin connector,
closest to the installed IDT FIFO chip. If using an ADC
with a SPI interface, remove the two 4-pin corner keys so
that the third row can be connected.
10. Start ADC Analyzer.
11. Choose an existing configuration file for the ADC
evaluation board or create one.
12. Click Time Data in ADC Analyzer (left-most button under
the menus). A reconstruction of the analog input is
3. Connect the provided USB cable to the FIFO evaluation
board and to an available USB port on the computer.
displayed. If the expected signal does not appear, or if there
is only a flat red line, refer to the ADC Analyzer data sheet
at www.analog.com/hsc-FIFO for more information.
4. Refer to Table 5 for any jumper changes. Most evaluation
boards can be used with the default settings.
5. After verification, connect the appropriate power supplies
to the ADC evaluation boards. The FIFO evaluation board
is supplied with a wall mount switching power supply that
provides a 6 V, 2 A maximum output. Connect the supply
end to the rated 100 ac to 240 ac wall outlet at 47 Hz to
63 Hz. The other end is a 2.1 mm inner diameter jack that
connects to the PCB at J301. Refer to the instructions
included in the ADC data sheet for more information
about the ADC evaluation board’s power supply and other
requirements.
Rev. 0 | Page 3 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
VIRTUAL EVALUATION BOARD EASY START WITH ADIsimADC
5. In the ADC Modeling dialog box, click the Device tab and
REQUIREMENTS
then click the … (Browse) button, adjacent to the dialog
box. This opens a file browser and displays all of the
models found in the default directory: c:\program
files\adc_analyzer\models. If no model files are found,
follow the on-screen directions or see Step 1 to install
available models. If you have saved the models somewhere
other than the default location, use the browser to navigate
to that location and select the file of interest.
Requirements include
•
Completed installation of ADC Analyzer, Version 4.5.17 or
later.
•
ADIsimADC product model files for the desired converter.
Models are not installed with the software, but they can be
downloaded from the ADIsimADC Virtual Evaluation
Board website at no charge.
No hardware is required. However, if you wish to compare
results of a real evaluation board and the model, you can switch
easily between the two, as outlined in the following Easy Start
Steps section.
6. From the menu, click Config > FFT. In the FFT
Configuration dialog box, ensure that the Encode
Frequency is set for a valid rate for the simulated device
under test. If set too low or too high, the model does not run.
EASY START STEPS
7. Once a model has been selected, information about the
model displays on the Device tab of the ADC Modeling
dialog box. After ensuring that you have selected the right
model, click the Input tab. This lets you configure the
input to the model. Click either Sine Wave or Two Tone
for the input signal.
1. To get ADC model files, go to www.analog.com/ADIsimADC
for the product of interest. Download the product of
interest to a local drive. The default location is c:\program
files\adc_analyzer\models.
2. Start ADC Analyzer (see the ADC Analyzer User Manual).
8. Click Time Data (left-most button under the pull-down
menus). A reconstruction of the analog input is displayed.
The model can now be used just as a standard evaluation
board would be.
3. From the menu, click Config > Buffer > Model as the
buffer memory. In effect, the model functions in place of
the ADC and data capture hardware.
4. After selecting the model, click the Model button (located
next to the Stop button) to select and configure which
converter is to be modeled. A dialog box appears in the
workspace, where you can select and configure the
behavior of the model.
9. The model supports additional features not found when
testing a standard evaluation board. When using the
modeling capabilities, it is possible to sweep either the
analog amplitude or the analog frequency. For more
information consult the ADC Analyzer User Manual at
www.analog.com/hsc-FIFO.
Rev. 0 | Page 4 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
FIFO 4.1 DATA CAPTURE BOARD FEATURES
6V SWITCHING
POWER SUPPLY
CONNECTION
IDT72V283 32k⋅
16-BIT 133MHz FIFO
TIMING ADJUSTMENT
JUMPERS
ON BOARD +3.3V
REGULATOR
120-CONNECTOR
(PARALLEL CMOS
INPUTS)
OPTIONAL POWER
CONNECTION
IDT72V283 32k⋅
16-BIT 133MHz FIFO
USB CONNECTION
TO COMPUTER
OPEN SOLDER MASK
ON ALL DATA AND
CLOCK LINES FOR
EASY PROBING
OPTIONAL SERIAL
PORT INTERFACE
CONNECTOR
RESET SWITCH
WHEN ENCODE RATE
IS INTERRUPTED
µCONTROLLER CRYSTAL
CLOCK = 24MHz,
OFF DURING
DATA CAPTURE
Figure 2. FIFO Components (Top View)
Rev. 0 | Page 5 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
120-CONNECTOR
(PARALLEL CMOS
INPUTS)
TIMING ADJUSTMENT
JUMPERS
EPROM TO LOAD
USB FIRMWARE
DRIVER CIRCUIT FOR
SERIAL PORT INTERFACE
(SPI) LINES
CYPRESS Fx2 HIGH SPEED
USB 2.0 µCONTROLLER
OPTIONAL SERIAL
PORT INTERFACE
(SPI) CONNECTOR
Figure 3. FIFO Components (Bottom View)
FIFO 4.1 SUPPORTED ADC EVALUATION BOARDS
The evaluation boards in Table 1 can be used with the high speed ADC FIFO evaluation kit. Some evaluation boards require an adapter between
the ADC evaluation board connector and the FIFO connector. If an adapter is needed, send an email to highspeed.converters@analog.com with
the part number of the adapter and a mailing address.
Table 1. HSC-ADC-EVALB-DC- and HSC-ADC-EVALB-SC-Compatible Evaluation Boards1
Evaluation Board Model
AD6644ST/PCB
Description of ADC
14-bit, 65 MSPS ADC
14-bit, 80 MSPS ADC
14-bit, 105 MSPS ADC
10-bit, 60 MSPS ADC
10-bit, 20 MSPS ADC
10-bit, 20 MSPS ADC
Dual 10-bit, 20 MSPS ADC1
10-bit, 40 MSPS ADC
Octal 10-bit, 65 MSPS ADC
10-bit, 65 MSPS ADC
10-bit, 80 MSPS ADC
10-bit, 105 MSPS ADC
10-bit, 65 MSPS ADC
10-bit, 80 MSPS ADC
10-bit, 105 MSPS ADC
Dual 10-bit, 80 MSPS ADC
Dual 10-bit, 105 MSPS ADC
FIFO Board Version
Comments
SC
SC
SC
SC
SC
SC
SC
SC
DC
SC
SC
SC
SC
SC
SC
DC
DC
AD6645-80/PCB
AD6645-105/PCB
AD9051/PCB
AD9200SSOP-EVAL
AD9200TQFP-EVAL
AD9201-EVAL
Requires AD9051FFA
Requires AD922xFFA
Requires AD922xFFA
Requires AD922xFFA
Requires AD922xFFA
Requires HSC-ADC-FPGA-8
AD9203-EB
AD9212-65EB1
AD9215BCP-65EB
AD9215BCP-80EB
AD9215BCP-105EB
AD9215BRU-65EB
AD9215BRU-80EB
AD9215BRU-105EB
AD9216-80PCB
AD9216-105PCB
Rev. 0 | Page 6 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
Evaluation Board Model
AD9218-105PCB
AD9218-65PCB
AD9219-65EB1
AD9220-EB
Description of ADC
FIFO Board Version
Comments
10-bit, 105 MSPS ADC
10-bit, 65 MSPS ADC
Quad 10-bit, 65 MSPS ADC
12-bit, 10 MSPS ADC
Octal 12-bit, 65 MSPS ADC
12-bit, 65 MSPS ADC
12-bit, 65 MSPS ADC
Quad 12-bit, 65 MSPS ADC
Quad 12-bit, 65 MSPS ADC
12-bit, 80MSPS ADC
12-bit, 105MSPS ADC
12-bit, 125MSPS ADC
12-bit, 150MSPS ADC
12-bit, 20 MSPS ADC
12-bit, 40 MSPS ADC
12-bit, 65 MSPS ADC
12-bit, 20 MSPS ADC
12-bit, 40 MSPS ADC
12-bit, 65 MSPS ADC
12-bit, 80 MSPS ADC
12-bit, 80 MSPS ADC
12-bit, 20 MSPS ADC
12-bit, 40 MSPS ADC
12-bit, 65 MSPS ADC
Dual 12-bit, 20 MSPS ADC
Dual 12-bit, 40 MSPS ADC
Dual 12-bit, 65 MSPS ADC
Dual 12-bit, 20 MSPS ADC
Dual 12-bit, 40 MSPS ADC
Dual 12-bit, 65 MSPS ADC
14-bit, 40 MSPS ADC
14-bit, 1.25 MSPS ADC
14-bit, 3 MSPS ADC
14-bit, 40 MSPS ADC
14-bit, 65 MSPS ADC
14-bit, 20 MSPS ADC
14-bit, 40 MSPS ADC
14-bit, 65 MSPS ADC
14-bit, 80 MSPS ADC
14-bit, 80 MSPS ADC
14-bit, 105 MSPS ADC
14-bit, 125 MSPS ADC
Dual 14-bit, 65 MSPS ADC
Dual 14-bit, 20 MSPS ADC
Dual 14-bit, 40 MSPS ADC
Dual 14-bit, 65 MSPS ADC
Quad 14-bit, 50 MSPS ADC
16-bit, 2.5 MSPS ADC
8-bit, 32 MSPS ADC
DC
DC
DC
SC
DC
SC
SC
DC
DC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
Requires HSC-ADC-FPGA-4/-8
Requires AD922xFFA
Requires HSC-ADC-FPGA-8
Requires AD922xFFA
Requires AD922xFFA
Requires HSC-ADC-FPGA-4/-8
Requires HSC-ADC-FPGA-4/-8
AD9222-65EB1
AD9226-EB
AD9226QFP-EB
AD9228-65EB1
AD9229-65EB1
AD9233-80EB
AD9233-105EB
AD9233-125EB
AD9234-EB
AD9235BCP-20EB
AD9235BCP-40EB
AD9235BCP-65EB
AD9235-20PCB
AD9235-40PCB
AD9235-65PCB
AD9236BRU-80EB
AD9236BCP-80EB
AD9237BCP-20EB
AD9237BCP-40EB
AD9237BCP-65EB
AD9238BST-20PCB
AD9238BST-40PCB
AD9238BST-65PCB
AD9238BCP-20EB
AD9238BCP-40EB
AD9238BCP-65EB
AD9240-EB
SC
SC
DC
DC
DC
DC
DC
DC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
DC
DC
DC
DC
DC
SC
SC
SC
SC
DC
DC
DC
Requires AD922xFFA
Requires AD922xFFA
Requires AD922xFFA
AD9241-EB
AD9243-EB
AD9244-40PCB
AD9244-65PCB
AD9245BCP-20EB
AD9245BCP-40EB
AD9245BCP-65EB
AD9245BCP-80EB
AD9246-80EB
AD9246-105EB
AD9246-125EB
AD9248BST-65EB
AD9248BCP-20EB
AD9248BCP-40EB
AD9248BCP-65EB
AD9259-50EB1
AD9260-EB
Requires HSC-ADC-FPGA-4/-8
Requires AD922xFFA
Requires AD922xFFA
Requires AD922xFFA
Requires AD9283FFA
Requires HSC-ADC-FPGA-4/-8
Requires HSC-ADC-FPGA-9289
Requires DEMUX BRD
AD9280-EB
AD9281-EB
AD9283/PCB
AD9287-100EB1
AD9289-65EB1
AD9411/PCB
Dual 8-bit, 28 MSPS ADC
8-bit, 100 MSPS ADC
Quad 8-bit, 100 MSPS ADC
Quad 8-bit, 65 MSPS ADC
10-bit, 200 MSPS ADC
Rev. 0 | Page 7 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
Evaluation Board Model
AD9430-CMOS/PCB
AD9430-LVDS/PCB2
AD9432/PCB
Description of ADC
FIFO Board Version
Comments
12-bit, 210 MSPS ADC
12-bit, 210 MSPS ADC
12-bit, 105 MSPS ADC
12-bit, 125 MSPS ADC
14 bit, 80 MSPS ADC
DC
DC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
SC
DC
DC
DC
DC
DC
DC
DC
SC
SC
DC
DC
Requires DEMUX BRD
AD9433/PCB
AD9444-CMOS/PCB
AD9444-LVDS/PCB
AD9445-IF-LVDS/PCB
AD9445-BB-LVDS/PCB
AD9446-80LVDS/PCB
AD9446-100LVDS/PCB
AD9460-80EB-IF
AD9460-80EB-BB
AD9460-105EB-IF
AD9460-105EB-BB
AD9461-130EB-IF
AD9461-130EB-BB
AD9480-LVDS/PCB2
AD9481-PCB
AD10200/PCB
AD10201/PCB
AD10226/PCB
AD10265/PCB
AD10465/PCB
AD10677/PCB
AD10678/PCB
AD15252/PCB
14 bit, 80 MSPS ADC
14-bit, 125 MSPS ADC
14-bit, 125 MSPS ADC
16-bit, 80 MSPS ADC
16-bit, 100 MSPS ADC
16-bit, 80 MSPS ADC
16-bit, 80 MSPS ADC
16-bit, 105 MSPS ADC
16-bit, 105 MSPS ADC
16-bit, 130 MSPS ADC
16-bit, 130 MSPS ADC
8-bit, 250 MSPS ADC
8-bit, 250 MSPS ADC
Dual 12-bit, 105 MSPS ADC
Dual 12-bit, 105 MSPS ADC
Dual 12-bit, 125 MSPS ADC
Dual 12-bit, 65 MSPS ADC
Dual 14-bit, 65 MSPS ADC
16-bit, 65 MSPS ADC
16-bit, 80 MSPS ADC
12-bit, Dual 65 MSPS ADC
12-bit, Quad 65 MSPS ADC
Requires DEMUX BRD
Requires GS09066
Requires GS09066
Requires GS09066
Requires GS09066
Requires GS09066
Requires GS09066
Requires GS09066
AD15452/PCB
Requires HSC-ADC-FPGA-4/-8
1 The high speed ADC FIFO evaluation kit can be used to evaluate two channels at a time.
2 If a DEMUX BRD is needed, send an email to highspeed.converters@analog.com.
Rev. 0 | Page 8 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
THEORY OF OPERATION
The FIFO evaluation board can be divided into several circuits,
each of which plays an important part in acquiring digital data
from the ADC and allows the PC to upload and process that
data. The evaluation kit is based around the IDT72V283 FIFO
chip from Integrated Device Technology, Inc (IDT). The system
can acquire digital data at speeds up to 133 MSPS and data
record lengths up to 32 kB using the HSC-ADC-EVALB-SC
FIFO evaluation kit. The HSC-ADC-EVALB-DC, which has
two FIFO chips, is available to evaluate multichannel ADCs or
demultiplexed data from ADCs sampling faster than 133 MSPS.
A USB 2.0 microcontroller communicating with ADC Analyzer
allows for easy interfacing to newer computers using the USB 2.0
(USB 1.1-compatible) interface.
The clock signals are ac-coupled by 0.1 μF capacitors.
Potentiometer R312 and Potentiometer R315 allow for fine
tuning the threshold of the LVDS gates. In applications where
fine-tuning the threshold is critical, these potentiometers can be
replaced with a higher resistance value to increase the
adjustment range. Resistors R301, R302, R303, R304, R311,
R313, R314, and R316 set the static input to each of the
differential gates to a dc voltage of approximately 1.5 V.
At assembly, Solder Jumper J310 to Solder Jumper J313 are set
to bypass the potentiometer. For fine adjustment using the pot,
the solder jumpers must be removed, and R312 and R315 must
be populated.
U302, an XOR gate array, is included in the design to let users
add gate delays to the FIFO memory chip clock paths. They are
not required under normal conditions and are bypassed at
assembly by Jumper J314 and Jumper J315. Jumper J306 and
Jumper J307 allow the clock signals to be inverted through an
XOR gate. In the default setting, the clocks are not inverted by
the XOR gate.
The process of filling the FIFO chip or chips and reading the
data back requires several steps. First, ADC Analyzer initiates
the FIFO chip fill process. The FIFO chips are reset, using a
master reset signal (MRS). The USB microcontroller is then
suspended, which turns off the USB oscillator and ensures that
it does not add noise to the ADC input. After the FIFO chips
completely fill, the full flags from the FIFO chips send a signal
to the USB microcontroller to wake up the microcontroller
from suspend. ADC Analyzer waits for approximately 30 ms
and then begins the readback process.
The clock paths described above determine the WRT_CLK1 and
WRT_CLK2 signals at each FIFO memory chip (U101 and
U201). The timing options above should let you choose a clock
signal that meets the setup and hold time requirements to
capture valid data.
During the readback process, the acquisition of data from
FIFO 1 (U201) or FIFO 2 (U101) is controlled via Signal OEA
and Signal OEB. Because the data outputs of both FIFO chips
drive the same 16-bit data bus, the USB microcontroller
controls the OEA and OEB signals to read data from the correct
FIFO chip. From an application standpoint, ADC Analyzer
sends commands to the USB microcontroller to initiate a read
from the correct FIFO chip, or from both FIFO chips in dual or
demultiplexed mode.
A clock generator can be applied directly to S1 and/or S3. This
clock generator should be the same unit that provides the clock
for the ADC. These clock paths are ac-coupled, so that a sine
wave generator can be used. DC bias can be adjusted by
R301/R302 and R303/R304.
The DS90LV048A differential line receiver is used to square the
clock signal levels applied externally to the FIFO evaluation
board. The output of this clock receiver can either directly drive
the write clock of the IDT72V283 FIFO(s), or first pass through
the XOR gate timing circuitry described above.
CLOCKING DESCRIPTION
Each channel of the buffer memory requires a clock signal to
capture data. These clock signals are normally provided by the
ADC evaluation board and are passed along with the data
through Connector J104 (Pin 37 for both Channel A and
Channel B). If only a single clock is passed for both channels,
they can be connected together by Jumper J303.
SPI DESCRIPTION
The Cypress IC (U502) supports the HSC SPI standard to allow
programming of ADCs that have SPI-accessible register maps.
U102 is a buffer that drives the 4-wire SPI (SCLK, SDI, SDO,
CSB1) through the 120-pin connector (J104) on the third or top
row. J502 is an auxiliary SPI connector to monitor the SPI
signals connected directly to the Cypress IC. For more
information on this and other functions, consult the user
manual titled Interfacing to High Speed ADCs via SPI at
www.analog.com/hsc-FIFO.
Jumpers J304 and J305 at the output of the LVDS receiver allow
the output clock to be inverted by the LVDS receiver. By default,
the clock outputs are inverted by the LVDS receiver.
The single-ended clock signal from each data channel is
buffered and converted to a differential CMOS signal by two
gates of a low voltage differential signal (LVDS) receiver, U301.
This allows the clock source for each channel to be CMOS,
TTL, or ECL.
1 Note that CSB1 is the default CSB line used.
Rev. 0 | Page 9 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
The SPI interface designed on the Cypress IC can communicate
with up to five different SPI-enabled devices. The CLK and data
lines are common to all SPI devices. The correct device is
chosen to communicate by using one of the five active low chip
select pins. This functionality is controlled by selecting a SPI
channel in the software.
CONNECTING TO THE DEMUX BRD
ADCs that have parallel LVDS outputs require another board
that is connected between the ADC evaluation board and the
FIFO data capture card. This board converts parallel LVDS to
parallel CMOS, using both channels of the FIFO data capture
card. For more detailed information on this board, send an
email to highspeed.converters@analog.com
CLOCKING WITH INTERLEAVED DATA
ADCs with very high data rates can exceed the capability of a
single buffer memory channel (~133 MSPS). These converters
often demultiplex the data into two channels to reduce the rate
required to capture the data. In these applications, ADC Analyzer
must interleave the data from both channels to process it as a
single channel. The user can configure the software to process
the first sample from Channel A, the second from Channel B,
and so on, or vice versa. The synchronization circuit included in
the buffer memory forces a small delay between the write enable
signals (WENA and WENB) to the FIFO memory chips (Pin 1,
U101, and U201), ensuring that the data is captured in one
FIFO before the other. Jumper J401 and Jumper J402 determine
which FIFO receives WENA and which FIFO receives WENB.
UPGRADING FIFO MEMORY
The FIFO evaluation board includes one or two 32 kB FIFOs
that are capable of 133 MHz clock signals, depending on the
model number. Pin-compatible FIFO upgrades are available
from IDT. See Table 2 for the IDT part number matrix.
Table 2. IDT Part Number Matrix
Part Number
FIFO Depth
FIFO Speed
133 MHz
133 MHz
133 MHz
133 MHz
166 MHz
166 MHz
166 MHz
166 MHz
IDT72V283-L7-5PF (Default ) 32 kB
IDT72V293-L7-5PF
IDT72V2103-L7-5PF
IDT72V2113-L7-5PF
IDT72V283-L6PF
IDT72V293-L6PF
IDT72V2103-L6PF
IDT72V2113-L6PF
64 kB
132 kB
256 kB
32 kB
64 kB
132 kB
256 kB
CONNECTING TO THE HSC-ADC-FPGA-4/-8
ADCs that have serial LVDS outputs require another board that
is connected between the ADC evaluation board and the FIFO
data capture card. This board converts the serial data into
parallel CMOS so that the FIFO data capture card can accept
the data. For more detailed information on this board, refer to
the HSC-ADC-FPGA datasheet at www.analog.com/hsc-FIFO.
For more information, visit www.idt.com.
Rev. 0 | Page 10 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
JUMPERS
Use the legends in Table 3 and Table 4 to configure the jumpers. On the FIFO evaluation board, Channel A is associated with the bottom
IDT FIFO chip, and Channel B is associated with the top IDT FIFO chip (closest to the Analog Devices logo).
Table 3. Jumper Legend
Position
Description
In
Jumper in place (2-pin header).
Out
Jumper removed (2-pin header).
Position 1 or Position 3
Denotes the position of a 3-pin header. Position 1 is marked on the board.
Table 4. Solder Jumper Legend
Position
Description
In
Out
Solder pads should be connected with 0 Ω resistor.
Solder pads should not be connected with 0 Ω resistor.
DEFAULT SETTINGS
Table 5 lists the default settings for each model of the FIFO evaluation kit. The single channel (SC) model is configured to work with a
single channel ADC using the bottom FIFO, U201. The dual channel (DC) model is configured to work with demultiplexed ADCs (such
as the AD9430). Dual channel ADC settings are shown in a separate column, as are settings for the opposite (top) FIFO, U101 for a single
channel ADC. To align the timing properly, some evaluation boards require modifications to these settings. Refer to the Clocking
Description section in the Theory of Operation section for more information.
Another useful way to configure the jumper settings easily for various configurations is to consult ADC Analyzer under Help > About
HSC_ADC_EVALB, and click Set Up Default Jumper Wizard. Then click the configuration setting that applies to the application of
interest. A picture of the FIFO board is displayed for that application with a visual of the correct jumper settings already in place.
Table 5. Jumper Configurations
Single Channel
Settings, Default Demultiplexed Dual-Channel
Jumper # (Bottom)
Single-Channel
Settings (Top)1
Settings
Settings
Description
J303
J304
In
In
Out
In
Out
In
In
In
Position 2 to Position 4, ties write clocks together
Position 1 to Position 2, POS3: invert clock out of
DS90 (U301)
J305
J306
J307
In
In
In
In
Position 2 to Position 3, POS3: invert clock out of
DS90 (U301)
No invert to encode clock from XOR (U302),
0 Ω resistor
No invert to encode clock from XOR (U302),
0 Ω resistor
All solder jumpers are shorted with 0 Ω resistors
(bypass level shifting to input of DS90)
Out
Out
In
Out
Out
In
Out
Out
In
Out
Out
In
J310 to
J313
J314
In
In
In
In
Position 1 to Position 2, one XOR gate timing
delay for top FIFO (U101)
J315
In
In
In
In
Position 1 to Position 2, one XOR gate timing
delay for bottom FIFO (U201)
J316
J401
In
In
In
In
In
In
In
In
Power connected using switching power supply
Controls if top FIFO (U101) gets write enable
before or after bottom FIFO, 0 Ω resistor
J402
J403
J404
J405
Out
Out
In
Out
Out
In
Out
Out
In
Out
Out
In
Controls if top FIFO (U101) gets write enable
before or after bottom FIFO, 0 Ω resistor
Controls if bottom FIFO (U201) gets a write
enable before or after the top FIFO, 0 Ω resistor
Controls if bottom FIFO (U201) gets a write
enable before or after the top FIFO, 0 Ω resistor
When in, WRT_CLK1 is used to create write enable
signal for FIFOs, 0 Ω resistor (significant only for
interleave mode)
Out
In
Out
Out
Rev. 0 | Page 11 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
Single Channel
Settings, Default Demultiplexed Dual-Channel
Jumper # (Bottom)
Single-Channel
Settings (Top)1
Settings
Settings
Description
J406
In
In
In
In
WRT_CLK2 is used to create write enable signal
for FIFOs, 0 Ω resistor (significant only for
interleave mode)
J503
In
In
In
In
Connect enable empty flag of top FIFO (U101)
to USB MCU, 0 Ω resistor
J504
J505
Out
In
Out
In
Out
In
Out
In
N/A
Connect enable full flag of top FIFO (U101)
to USB MCU, 0 Ω resistor
J506
J602
J603
Out
Out
In
Out
Out
In
Out
Out
In
Out
Out
In
N/A
N/A
N/A
1 Some jumpers can be a 0 Ω resistor instead of a physical jumper. This is shown in Table 5 in the jumper description column.
Rev. 0 | Page 12 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
EVALUATION BOARD
The FIFO provides all of the support circuitry required to
accept two channels of an ADC’s digital parallel CMOS outputs.
Each of the various functions and configurations can be selected by
proper connection of various jumpers (see Table 5). When
using this in conjunction with an ADC evaluation board, it is
critical that the signal sources used for the analog input and
clock have very low phase noise (<1 ps rms jitter) to realize the
ultimate performance of the converter. Proper filtering of the
analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is also necessary to achieve the
specified noise performance.
When operating the evaluation board in a non-default
condition, J316 can be removed to disconnect the switching
power supply. This enables the user to bias the board
independently. Use P302 to connect an independent supply to
the board. A 3.3 V supply is needed with at least a 1 A current
capability.
CONNECTION AND SETUP
The FIFO board has a 120-pin (40-pin, triple row) connector
that accepts two 16-bit channels of parallel CMOS inputs (see
Figure 6). For those ADC evaluation boards that have only an
80-pin (40-pin, double row) connector, it is pertinent for the
lower two rows of the FIFO’s triple row connector to be connected
in order for the data to pass to either FIFO channel correctly.
The top or third row is used to pass SPI signals across to the
adjacent ADC evaluation board that supports this feature.
See Figure 5 to Figure 15 for complete schematics and layout plots.
POWER SUPPLIES
The FIFO board is supplied with a wall mount switching power
supply that provides a 6 V, 2 A maximum output. Connect the
supply to the rated 100 ac to 240 ac wall outlet at 47 Hz to 63 Hz.
The other end is a 2.1 mm inner diameter jack that connects to
the PCB at J301. On the PC board, the 6 V supply is then fused
and conditioned before connecting to the low dropout 3.3 V
linear regulator that supplies the proper bias to the entire board.
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
3.3V
–
+
6V DC
2A MAX
SWITCHING
POWER
SUPPLY
CHB
PARALLEL
CMOS
OUTPUTS
PC
RUNNING
ADC
HSC-ADC-EVALB-DC
FIFO DATA
EVALUATION
BOARD
CAPTURE
BOARD
ROHDE & SCHWARZ,
SMHU,
ANALYZER
BAND-PASS
FILTER
XFMR
INPUT
2V p-p SIGNAL
SYNTHESIZER
CHB
PARALLEL
CMOS
USB
CONNECTION
ROHDE & SCHWARZ,
SMHU,
OUTPUTS
CLK
2V p-p SIGNAL
SYNTHESIZER
SPI
SPI
SPI
Figure 4. Example Setup Using Quad ADC Evaluation Board and FIFO Data Capture Board
Rev. 0 | Page 13 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
FIFO SCHEMATICS AND PCB LAYOUT
SCHEMATICS
ALLOW Fx2 TO CONTROL FIFO’S OUTPUT WIDTH
PC2: TRISTATED, NORMAL 16-BIT DATA PATH
PC2: DRIVEN HIGH, 9-BIT OUTPUT ALLOWS
READING 18 BITS IN TWO READS.
PC2
R101
R102
0Ω
10kΩ
E101
VCC
WEN1
1
2
3
4
5
6
7
8
9
60
E102
WEN
SEN
DNC
VCC
DNC
IW
RT
59
OE1
OE
58
VCC
57
Q17
Q16
Q17
56
Q16
55
GND
54
VCC
GND
D17
VCC
D16
D15
D14
D13
GND
D12
D11
D10
D9
GND
D1_17
53
Q15
Q14
Q15
R108
DNP
52
Q14
D1_16
D1_15
D1_14
D1_13
IDT72V283
TQFP80
TOP FIFO
CHANNEL B
10
51
WRT_CLK1
VCC
R109
DNP
11
12
13
14
15
16
17
18
19
20
50
Q13
Q12
Q13
49
Q12
48
GND
47
Q11
Q10
Q11
D1_12
D1_11
D1_10
D1_9
46
GND
45
Q10
44
VCC
43
Q9
Q8
Q7
Q9
D1_8
42
D8
Q8
41
VCC
Q7
U101
VCC
C101
0.1µF
C102
0.1µF
C103
0.1µF
C104
0.1µF
C105
0.1µF
C106
0.1µF
C107
0.1µF
C108
0.1µF
C109
0.1µF
Figure 5. PCB Schematic
Rev. 0 | Page 14 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
CMOS INPUTS
TEST POINTS
DUT_CLK1
TEST POINTS
PLACEMENT OF HEADER KEY HERE
J104
J104
J104
D1_17
D1_16
C1
A1
B1
D1_17
D1_16
C2
A2
B2
CLKB
C3
A3
B3
D1_15
C4
A4
B4
D1_15
D1_14
D1_13
D1_12
D1_11
D1_10
D1_9
MSB
D1_14
D1_13
D1_12
D1_11
D1_10
D1_9
D1_8
D1_7
D1_6
D1_5
D1_4
D1_3
D1_2
D1_1
D1_0
C5
A5
B5
C6
A6
B6
C7
A7
B7
C8
A8
B8
C9
A9
B9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
D1_8
D1_7
D1_6
D1_5
D1_4
D1_3
D1_2
D1_1
D1_0
CHB
LSB
CTRL_A
D2_17
CTRL_B
CTRL_B
CTRL_A
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
D2_17
D2_16
D2_16
DUT_CLK2
CLKA
MSB
D2_15
D2_14
D2_13
D2_12
D2_11
D2_10
D2_9
D2_15
D2_14
D2_13
D2_12
D2_11
D2_10
D2_9
ALL SPI LABELS ARE WITH
RESPECT TO THE DUT.
VCC
20
19
1
2
VCC
OE2
OE
A0
18
16
1
Y0
15
14
13
2
3
4
17
16
15
3
4
5
Y1
Y2
Y3
A1
A2
A3
CSB1
CSB2
CHA
D2_8
U102
D2_8
74VHC541MTC
D2_7
SDI
D2_7
D2_6
14
13
12
11
6
7
8
9
12
11
10
5
6
7
Y4
Y5
Y6
Y7
A4
A5
A6
A7
D2_6
SCLK
CSB3
CSB4
D2_5
D2_5
D2_4
D2_4
22
D2_3
9
8
SDO
D2_3
GND
10
D2_2
R103
10kΩ
RZ101
R104
10kΩ
D2_2
D2_1
D2_1
D2_0
D2_0
LSB
CTRL_D
CTRL_C
CTRL_D
CTRL_C
PLACEMENT OF HEADER KEY HERE
Figure 6. Schematic (Continued)
Rev. 0 | Page 15 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
PC3
R201
R202
0Ω
10kΩ
E201
VCC
WEN2
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
E202
WEN
SEN
DNC
VCC
DNC
IW
RT
OE
OE2
3
VCC
Q17
Q16
GND
GND
Q15
Q14
VCC
Q13
Q12
GND
Q11
GND
Q10
VCC
Q9
4
Q17
Q16
5
6
7
GND
D17
VCC
D16
D15
D14
D13
GND
D12
D11
D10
D9
D2_17
8
Q15
Q14
9
D2_16
D2_15
D2_14
D2_13
IDT72V283
TQFP80
BOTTOM FIFO
CHANNEL A
10
11
12
13
14
15
16
17
18
19
20
Q13
Q12
Q11
Q10
D2_12
D2_11
D2_10
D2_9
Q9
Q8
Q7
D2_8
D8
Q8
VCC
Q7
U201
VCC
R203
DNP
WRT_CLK2
R204
DNP
VCC
C201
0.1µF
C202
0.1µF
C203
0.1µF
C204
0.1µF
C205
0.1µF
C206
0.1µF
C207
0.1µF
C208
0.1µF
Figure 7. Schematic (Continued)
Rev. 0 | Page 16 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
1
2
1
2
E D I S P O T O N
S D A P N E E W T E B P E M R U S J E A C P L
Figure 8. Schematic (Continued)
Rev. 0 | Page 17 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
Figure 9. Schematic (Continued)
Rev. 0 | Page 18 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
D 7
8 8
D 6
8 7
D 5
8 6
0 D F / 0 P B
1 D F / 1 P B
2 D F / 2 P B
3 D F / 3 P B
4 D F / 4 P B
5 D F / 5 P B
6 D F / 6 P B
7 D F / 7 P B
8 D F / 0 P D
9 D F / 1 P D
0 1 F / D P D 2
1 1 D F / 3 P D
2 1 F / D P D 4
3 1 F / D P D 5
4 1 F / D P D 6
5 1 F / D P D 7
1 D R X
D 4
6 3
Q 0 4 4
Q 1 4 5
Q 2 4 6
Q 3 4 7
Q 4 5 4
Q 5 5 5
Q 6 5 6
Q 7 5 7
Q 8 2 1 0
Q 9 3 1 0
Q 1 4 1 0
Q 1 5 1 0
Q 1 1 1 2
Q 1 2 1 2
Q 1 3 1 2
Q 1 4 1 2
5 3
D 3
6 2
D 2
6 1
D 1
6 0
D 0
5 9
T 0
2 9
T 1
3 0
T 2
3 1
5 L C T
9 8
6 7
6 6
7 1
7 0
6 9
M
N 2 R E
N 2 R E
Ω 9
Ω 9
Ω 9
Ω 9
5 1 R 5 2 4 .
4 L C T
3 L C T
5 1 R 4 2 4 .
T X N E R E
5 1 R 3 2 4 .
0
1
2
3
4
5
C G A F * L / L T 2 C
B G A F * L / L T 1 C
N 1 R E
5 1 R 2 2 4 .
S N W E
Ω 9 . 2 4 1 1 5 R
A
A L G F * 0 L C T
S
5 1 R 0 2 4 .
M R
Ω 9
E D V R
R E S E
3 3
Ω
1 0 k 5 0 R 9
1 0 k 5 0 R 8
B K P T
3 4
E A
3 5
Ω
1
T X D
L
S C
3 6
5 2
0 D R X
A
S D
3 7
5 1
0
T X D
O E
3 8
5 0
P U E K A * W
T E R E S
N
P S E 3 9
1
1 0
9 9
B S U F F _
R D
4 0
W R 4 1
D V C C
2
C S
4 2
C C A V
1 0
D
G N
3
N D A G
1 3
Figure 10. Schematic (Continued)
Rev. 0 | Page 19 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
VCC
CONNECTIONS FOR 2M WORD EXTERNAL MEMORY
EXTERNAL MEMORY OVERRIDES ON BOARD MEMORIES WHEN PLUGGED IN. ONLY A SIDE DATA.
C601
0.1µF
DNP
J601
1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U601
D1_8
D1_9
DC8
RENEXT
QL0
1
2
20 VCC
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
OUT_EN VCC
DC9
19
18
17
16
15
14
13
12
11
1
16 Q0
15 Q1
14 Q2
13 Q3
12 Q4
11 Q5
10 Q6
DC0
DC3
2
D0
D1
D2
D3
D4
D5
D6
D7
GND
Q0
Q1
D1_10
D1_11
D1_12
D1_13
D1_14
D1_15
DC10
DC11
DC12
DC13
DC14
DC15
QL1
3
2
3
4
5
6
7
8
3
QL2
4
DC2
4
Q2
QL3
5
DC6
5
Q3
QL4
6
DC8
6
Q4
QL5
7
DC7
7
Q5
QL6
8
DC11
DC10
DC13
8
Q6
RZ601
QL7
9
9
Q7
9
Q7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
10
D1_0
D1_1
D1_2
D1_3
D1_4
D1_5
D1_6
D1_7
DC0
DC1
DC2
DC3
DC4
DC5
DC6
DC7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
DC14
DC15
CLOCK
RZ605
74LCX574
DC4
DC5
J602
DNP
J603
DC16
DC1
REN2M
RCLK
DC9
J603: ALLOWS 2 MEG BUFFER TO READ BACK DATA
ON EACH RCLK EDGE.
J602: ALLOWS 2 MEG BUFFER TO READ BACK 1 DATA
ON EVERY 3RD RCLK EDGE. J602 IS FOR
DC17
DC12
RZ602
BACKWARD COMPATABILITY IF NEEDED.
R603
0Ω
D1_16
D1_17
DC16
DC17
R604
0Ω
REN1
RCLK
EF1_BHB
FF1_BHB
MRS
WEN1
WRT_CLK1
QL0
QL1
QL2
QL3
QL4
QL5
QL6
QL7
Figure 11. Schematic (Continued)
Rev. 0 | Page 20 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
PCB LAYOUT
Figure 12. Layer 1—Primary Side
Figure 13. Layer 2—Ground Plane
Rev. 0 | Page 21 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
Figure 14. Layer 3—Power Plane
Figure 15. Layer 4—Secondary Side
Rev. 0 | Page 22 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
BILL OF MATERIALS
Table 6. HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC Bill of Materials
Item Qty Reference Designation
Device
Package
Description
Manufacturer
Mfg Part Number
1
42
C101 to C109, C201 to C208,
C302, C303, C305, C306, C308,
C310, C311, C402 to C405,
C503, C506 to C517, C601
Capacitor
402
Ceramic, 0.1 μF, 16 V,
X5R, 10%
Panasonic
ECJ-0EB1C014K
2
3
2
1
1
2
1
1
2
1
1
1
1
1
C301, C307, C309
C312, C313
C501
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Diode
6032-28
603
Tantalum, 10 μF, 16 V, Kemet
10%
T491C106K016AS
ECJ-1VB1A105K
ECS-T1CY105R
ECJ-2FB1E225K
ECJ-0EC1H120J
S2A
3
Ceramic, 1 μF, 10 V,
X5R, 10%
Panasonic
4
3216-18
805
Tantalum, 1 μF, 16 V,
20%
Ceramic, 2.2 μF, 25 V,
X5R 10%
Ceramic, 12 pF,
NPO, 50 V, 5%
Panasonic
Panasonic
Panasonic
5
C502
6
C504, C505
CR301
402
7
DO-214AA
DO-214AB
603
Schottky diode,
50 V, 2 A, SMC
Micro Commercial
Group
8
CR302
Diode
Schottky diode,
30 V, 3 A, SMC
Micro Commercial
Group
SK33MSCT
9
CR303, CR501
CR502
LED
Green, 4 V 5 m,
candela
Switching, 75 V,
150 mA
6.0 V, 2.2 A trip current
resettable fuse
120-pin, female,
Panasonic
Diodes, Inc.
Tyco, Raychem
AMP
LNJ314G8TRA
1N4148W-7
10
11
12
13
14
Diode
SOD-123
1210
F301
Fuse
NANOSMDC110F-2
650874
J104
Connector
PC mount, right angle
J301
Connector 0.08”, PCMT
Connector 4-pin
RAPC722, power
supply connector
Male, straight,
100 mil
Switchcraft
SAMTEC
SC1153
J303
TSW-1-10-08-GD
15
16
4
8
J304, J305, J314, J315
J310 to J313, J401, J404, J406,
J603
Connector 3-pin
Connector 603
Male, straight, 100 mil
2-pin solder jumper,
0 Ω, 1/10 W, 5%
SAMTEC
Panasonic
TWS-103-08-G-S
ERJ-3GEY0R00V
17
18
1
1
J316
J501
Connector 2-pin
Connector 4-pin
Male, straight, 100 mil
USB, PC mount, right
angle, Type B, female
SAMTEC
AMP
TSW-1002-08-G-S
787780-1
19
1
L501
Ferrite
Bead
805
500 mA, 600 Ω @
100 MHz
Steward
HZ0805E601R-00
20
21
5
8
R101, R201, R524, R603, R604
R102 to R04, R202, R508, R509,
R518, R4519
Resistor
Resistor
402
402
0 Ω, 1/16 W, 5%
10 kΩ, 1/16 W, 1%
Panasonic
Panasonic
ERJ-2GE0R00X
ERJ-2RKF1002X
22
10
R301 to R304, R311, R313,
R314, R316, R521, R522
Resistor
402
332 Ω, 1/16 W, 1%
Panasonic
ERJ-2RKF3320X
23
24
25
26
2
2
1
8
R309, R310
R317, R503
R401
R404, R405, R407, R408, R410,
R411, R413, R414
Resistor
Resistor
Resistor
Resistor
402
402
402
402
1 kΩ, 1/16 W, 1%
499 Ω, 1/16 W, 1%
20 kΩ, 1/16 W, 1%
49.9 Ω, 1/16 W, 1%
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-2RKF1002X
ERJ-2RKF1001X
ERJ-2RKF4990X
ERJ-2RKF2002X
27
28
29
4
1
13
R406, R409, R412, R415
R502
R504, R506, R507, R510 to R515,
R520, R525, R526
Resistor
Resistor
Resistor
402
402
402
40.2 Ω, 1/16 W, 1%
100 kΩ, 1/16 W, 1%
24.9 Ω, 1/16 W, 1%
Panasonic
Panasonic
Panasonic
ERJ-2RKF40R2X
ERJ-2RKF1003X
ERJ-2RKF24R9X
30
31
3
1
R516, R517, R523
RZ101
Resistor
Resistor
402
2 kΩ, 1/16 W, 1%
Resistor array, 22 Ω,
1/4 W, 5%
Panasonic
Panasonic
ERJ-2RKF2001X
EXB-2HV220JX
32
1
S501
Switch
Momentary (normally Panasonic
open), 100 GE, 5 mm,
SPST
EVQ-PLDA15
Rev. 0 | Page 23 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
Item Qty Reference Designation
Device
Package
Description
Manufacturer
Mfg Part Number
33
1
T301
Choke
2020
10 μH, 5 A, 50 V,
190 Ω @ 100 MHz
3.3 V,
IDT72V283L7-5PF
74VHC541,
octal buffer/line
driver, three-state
DS90LV048A
Murata
DLW5BSN191SQ2L
341
2
U101, U201
IC
IC
TQFP80
SOIC20
IDT
IDT72V283L7-5PF
74VHC541M
35
36
1
1
U102
U301
Fairchild
IC
SOIC16
National
DS90LV048A
Semiconductor
37
38
39
40
41
1
1
1
1
1
U302
U401
U402
U403
U501
IC
IC
IC
IC
IC
SOIC14
SO8M1
TSSOP20
SO8M1
SOT23L5
74VCX86
Fairchild
Motorola
74VCX86
MC100EPT22D
MC100EPT22D
MC100EP29DT
MC100EPT23D
ON Semiconductor MC100EP29DT
Motorola
Fairchild
MC100EPT23D
NC7SZ32M5
NC7SZ32M5,
NC7SZ32, tiny log
UHS 2-input or gate
42
1
U502
IC
TQFP128
CY7C68013
Cypress
CY7C68013-128AXC
or
CY7C68014A-128AXC
24LC00P
SN74LVC2G74DCTR
43
44
1
1
U503
U504
IC
IC
DIP8
24LC00P
Microchip
Texas Instruments
DCT_8PIN_06, SN74LVC2G74DCTR,
D-type flip-flop,
DCT_8PIN_0.65MM
5 mm
45
46
1
1
U505
U601
IC
IC
SOIC 14
74LVQ04SC, low
voltage hex inverter
74LCX574WM-ND,
74LCX574 octal D-type
flip-flop
Fairchild
Fairchild
74LVQ04SC
DIP20/SOL
74LCX574WM-ND
47
1
VR301
IC
SOT-223HS
Crystal
High accuracy,
ADP3339AKC-3.3, 3.3 V
Oscillator, 24 MHz
0.1” jumpers
Analog Devices
ADP3339AKC-3.3
48
49
1
6
Y501
Crystal
Connector 100 mil
jumper
Ecliptek
Samtec
EC-12-24.000M
SNT-100-BK-G-H
See schematic for placement
50
51
4
2
Insert from bottom side of
board
See schematic for placement
Standoff
Plastic mount 7/8” height, standoffs Richco
standoffs
CBSB-14-01A-RT
TSW-104-07-T-S
Connector Third-row
header key
These header inserts
for J104, Pin 81, and
Pin 120 are located
on the edges of the
top row
Samtec
1 Only U201 is populated for the single-channel version (HSC-ADC-EVALB-SC).
Rev. 0 | Page 24 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
ORDERING INFORMATION
ORDERING GUIDE
Model
Description
HSC-ADC-EVALB-SC
HSC-ADC-EVALB-DC
HSC-ADC-FPGA-4/-8
Single FIFO Version of USB Evaluation Kit
Dual FIFO Version of USB Evaluation Kit
Quad/Octal Serial LVDS to Dual Parallel CMOS Interface; supports all Quad/Octal ADCs in this family except
the AD9289 (not Included in Evaluation Kit)
HSC-ADC-FPGA-9289
AD922XFFA1
AD9283FFA1
AD9059FFA1
AD9051FFA1
LG-0204A1
Quad Serial LVDS to Dual Parallel CMOS Interface for the AD9289 Only (Not Included in Evaluation Kit)
Adapter for AD922x Family (Not Included in Evaluation Kit)
Adapter for the AD9283 and AD9057 (Not Included in Evaluation Kit)
Adapter for the AD9059 (Not Included in Evaluation Kit)
Adapter for the AD9051 (Not Included in Evaluation Kit)
Adapter for the AD10xxx and AD13xxx Families (Not Included in Evaluation Kit)
1 If an adapter is needed, send an email to highspeed.converters@analog.com.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 25 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
NOTES
Rev. 0 | Page 26 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
NOTES
Rev. 0 | Page 27 of 28
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
EB05870-0-2/06(0)
Rev. 0 | Page 28 of 28
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