AD8429BRZ-R7 [ADI]
1 nV/√Hz Low Noise Instrumentation Amplifier ±4 V to ±18 V dual supply; 1内华达州/ √Hz的低噪声仪表放大器± 4 V至± 18 V双电源供电
| 型号： | AD8429BRZ-R7 |
| 厂家： | 
ADI |
| 描述： | 1 nV/√Hz Low Noise Instrumentation Amplifier ±4 V to ±18 V dual supply |
| 文件： | 总20页 (文件大小：554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 nV/√Hz Low Noise
Instrumentation Amplifier
AD8429
FEATURES
PIN CONNECTION DIAGRAM
Low noise
1 nV/√Hz input noise
45 nV/√Hz output noise
AD8429
1
2
3
4
8
7
6
5
–IN
+V
S
R
R
V
OUT
G
G
REF
–V
High accuracy dc performance (AD8429BRZ)
90 dB CMRR minimum (G = 1)
50 μV maximum input offset voltage
0.02% maximum gain accuracy (G = 1)
Excellent ac specifications
80 dB CMRR to 5 kHz (G = 1)
15 MHz bandwidth (G = 1)
1.2 MHz bandwidth (G = 100)
22 V/μs slew rate
+IN
S
TOP VIEW
(Not to Scale)
Figure 1.
THD: −130 dBc (1 kHz, G = 1)
Versatile
4 V to 18 V dual supply
Gain set with a single resistor (G = 1 to 10,000)
Temperature range for specified performance
−40°C to +125°C
APPLICATIONS
Medical instrumentation
Precision data acquisition
Microphone preamplification
Vibration analysis
GENERAL DESCRIPTION
The AD8429 is an ultralow noise, instrumentation amplifier
designed for measuring extremely small signals over a wide
temperature range (−40°C to +125°C).
be useful to shift the output level when interfacing to a single
supply signal chain.
The AD8429 performance is specified over the extended industrial
The AD8429 excels at measuring tiny signals. It delivers ultralow
input noise performance of 1 nV/√Hz. The high CMRR of the
AD8429 prevents unwanted signals from corrupting the acqui-
sition. The CMRR increases as the gain increases, offering high
rejection when it is most needed. The high performance pin
configuration of the AD8429 allows it to reliably maintain high
CMRR at frequencies well beyond those of typical instrumentation
amplifiers.
temperature range of −40°C to +125°C. It is available in an 8-lead
plastic SOIC package.
1000
100
G = 1
10
The AD8429 reliably amplifies fast changing signals. Its current
feedback architecture provides high bandwidth at high gain, for
example, 1.2 MHz at G = 100. The design includes circuitry to im-
prove settling time after large input voltage transients. The AD8429
was designed for excellent distortion performance, allowing use in
demanding applications such as vibration analysis.
G = 10
G = 100
1
G = 1k
0.1
1
10
100
1k
10k
100k
Gain is set from 1 to 10,000 with a single resistor. A reference
pin allows the user to offset the output voltage. This feature can
FREQUENCY (Hz)
Figure 2. RTI Voltage Noise Spectral Density vs. Frequency
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
AD8429
TABLE OF CONTENTS
Features .............................................................................................. 1
Architecture ................................................................................ 15
Gain Selection............................................................................. 15
Reference Terminal .................................................................... 15
Input Voltage Range................................................................... 16
Layout .......................................................................................... 16
Input Bias Current Return Path ............................................... 17
Input Protection ......................................................................... 17
Radio Frequency Interference (RFI)........................................ 17
Calculating the Noise of the Input Stage................................. 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Pin Connection Diagram ................................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 15
REVISION HISTORY
4/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD8429
SPECIFICATIONS
VS = 15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.
Table 1.
A Grade
B Grade
Typ
Parameter
Test Conditions/Comments Min
Typ
Max
Min
Max
Unit
COMMON-MODE REJECTION
RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ
Source Imbalance
VCM
=
10 V
G = 1
80
90
dB
dB
dB
dB
G = 10
100
120
134
110
130
140
G = 100
G = 1000
CMRR at 5 kHz
G = 1
VCM
=
10 V
76
90
90
90
80
90
90
90
dB
dB
dB
dB
G = 10
G = 100
G = 1000
VOLTAGE NOISE, RTI
Spectral Density1: 1 kHz
Input Voltage Noise, eni
Output Voltage Noise, eno
Peak to Peak: 0.1 Hz to 10 Hz
G = 1
VIN+, VIN− = 0 V
1.0
45
1.0
45
nV/√Hz
nV/√Hz
2
2
μV p-p
nV p-p
G = 1000
100
100
CURRENT NOISE
Spectral Density: 1 kHz
Peak to Peak: 0.1 Hz to 10 Hz
VOLTAGE OFFSET2
Input Offset, VOSI
1.5
1.5
pA/√Hz
pA p-p
100
100
150
1
50
μV
Average TC
0.1
3
0.1
3
0.3
500
10
μV/°C
μV
Output Offset, VOSO
Average TC
Offset RTI vs. Supply (PSR)
G = 1
1000
10
μV/°C
VS = 5 V to 15 V
90
100
120
130
130
dB
dB
dB
dB
G = 10
G = 100
110
130
130
G = 1000
INPUT CURRENT
Input Bias Current
Average TC
300
100
150
30
nA
250
15
250
15
pA/°C
nA
Input Offset Current
Average TC
pA/°C
DYNAMIC RESPONSE
Small Signal Bandwidth: –3 dB
G = 1
15
4
15
4
MHz
MHz
MHz
MHz
G = 10
G = 100
G = 1000
1.2
0.15
1.2
0.15
Rev. 0 | Page 3 of 20
AD8429
A Grade
Typ
B Grade
Typ
Parameter
Settling Time 0.01%
G = 1
Test Conditions/Comments Min
Max
Min
Max
Unit
10 V step
0.75
0.65
0.85
5
0.75
0.65
0.85
5
μs
μs
μs
μs
G = 10
G = 100
G = 1000
Settling Time 0.001%
G = 1
10 V step
0.9
0.9
1.2
7
0.9
0.9
1.2
7
μs
μs
μs
μs
G = 10
G = 100
G = 1000
Slew Rate
G = 1 to 100
THD
22
22
V/μs
First five harmonics, f = 1 kHz,
RL = 2 kΩ, VOUT = 10 V p-p
G = 1
G = 10
−130
−116
−113
−111
−130
−116
−113
−111
dBc
dBc
dBc
dBc
G = 100
G = 1000
THD + N
f = 1 kHz, RL = 2 kΩ, VOUT
10 V p-p
=
G = 100
GAIN3
0.0005
0.0005
%
G = 1 + (6 kΩ/RG)
Gain Range
Gain Error
1
10000
1
10000
V/V
VOUT
= 10 V
G = 1
0.05
0.3
0.02
0.15
%
%
G > 1
Gain Nonlinearity
G = 1 to 1000
Gain vs. Temperature
G = 1
VOUT = −10 V to +10 V
RL = 10 kΩ
2
2
2
2
ppm
5
5
ppm/°C
ppm/°C
G > 1
−100
−100
INPUT
Impedance (Pin to Ground)4
1.5||3
1.5||3
GΩ||pF
V
Input Operating Voltage
Range5
VS = 4 V to 18 V
−VS + 2.8
+VS − 2.5
−VS + 2.8
+VS − 2.5
OUTPUT
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
REFERENCE INPUT
RIN
RL = 2 kΩ
−VS + 1.8
−VS + 1.9
−VS + 1.7
−VS + 1.8
+Vs − 1.2
+Vs − 1.3
+Vs − 1.1
+Vs − 1.2
−VS + 1.8
−VS + 1.9
−VS + 1.7
−VS + 1.8
+Vs − 1.2
+Vs − 1.3
+Vs − 1.1
+Vs − 1.2
V
V
RL = 10 kΩ
V
V
35
35
mA
10
70
10
70
kΩ
μA
V
IIN
VIN+, VIN− = 0 V
Voltage Range
Reference Gain to Output
Reference Gain Error
−VS
+VS
1
1
V/V
%
0.01
0.05
0.01
0.05
Rev. 0 | Page 4 of 20
AD8429
A Grade
Typ
B Grade
Typ
Parameter
Test Conditions/Comments Min
Max
Min
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current
4
18
7
4
18
7
V
6.7
6.7
mA
mA
T = 125°C
9
9
TEMPERATURE RANGE
For Specified Performance
−40
+125
−40
+125
°C
1 Total voltage noise = √(eni2 + (eno/G)2 + eRG2). See the Theory of Operation section for more information.
2 Total RTI VOS = (VOSI) + (VOSO/G).
3 These specifications do not include the tolerance of the external gain setting resistor, RG. For G > 1, add RG errors to the specifications given in this table.
4 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
5 Input voltage range of the AD8429 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage.
See the Input Voltage Range section for more details.
Rev. 0 | Page 5 of 20
AD8429
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
θJA is specified for a device in free air using a 4-layer JEDEC
printed circuit board (PCB).
Parameter
Rating
Supply Voltage
18 V
Indefinite
VS
Output Short-Circuit Current Duration
Maximum Voltage at –IN, +IN1
Differential Input Voltage1
Gain ≤ 4
Table 3.
Package
8-Lead SOIC
θJA
Unit
121
°C/W
VS
4 > Gain > 50
Gain ≥ 50
50 V/gain
1 V
ESD CAUTION
Maximum Voltage at REF
Storage Temperature Range
Specified Temperature Range
Maximum Junction Temperature
ESD
VS
−65°C to +150°C
−40°C to +125°C
140°C
Human Body Model
Charge Device Model
Machine Model
3.0 kV
1.5 kV
0.2 kV
1 For voltages beyond these limits, use input protection resistors. See the
Theory of Operation section for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 20
AD8429
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8429
1
2
3
4
8
7
6
5
–IN
+V
S
R
R
V
OUT
G
G
REF
–V
+IN
S
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
2, 3
4
5
6
−IN
RG
Negative Input Terminal.
Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (6 kΩ/RG).
Positive Input Terminal.
Negative Power Supply Terminal.
Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level shift the output.
+IN
−VS
REF
VOUT
+VS
7
8
Output Terminal.
Positive Power Supply Terminal.
Rev. 0 | Page 7 of 20
AD8429
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = 15, VREF = 0, RL = 10 kꢀ, unless otherwise noted.
15
160
140
120
100
80
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
V
= ±15V
S
G = 1
10
5
V
= ±12V
S
V
= ±5V
0
S
60
–5
–10
–15
40
20
0
1
10
100
1k
10k
100k
1M
–15
–10
–5
0
5
10
15
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 7. Positive PSRR vs. Frequency
Figure 4. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = 5 V, 12 V, 15 V (G = 1)
160
140
120
100
80
15
GAIN = 1000
V
= ±15V
S
G = 100
GAIN = 100
GAIN = 10
GAIN = 1
10
5
V
= ±12V
S
V
= ±5V
0
S
60
–5
–10
–15
40
20
0
1
10
100
1k
10k
100k
1M
–15
–10
–5
0
5
10
15
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 5. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = 5 V, 12 V, 15 V (G = 100)
Figure 8. Negative PSRR vs. Frequency
0
70
60
V
= ±15V
S
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
50
40
–12.28V
30
20
+12.60V
10
0
–10
–20
–30
–14 –12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
100
1k
10k
100k
1M
10M
100M
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 6. Input Bias Current vs. Common-Mode Voltage
Figure 9. Gain vs. Frequency
Rev. 0 | Page 8 of 20
AD8429
40
30
3.0
160
140
120
100
80
I
I
I
+
–
B
B
G = 1k
OS
G = 100
G = 10
2.5
2.0
1.5
1.0
0.5
0
20
G = 1
BANDWIDTH
LIMITED
10
60
0
40
–10
20
–20
0
1
10
100
1k
10k
100k
1M
–45 –30 –15
0
15 30 45 60 75 90 105 120 135
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 13. Input Bias Current and Input Offset Current vs. Temperature
Figure 10. CMRR vs. Frequency
40
140
120
100
80
GAIN = 1
G = 100
G = 1k
G = 10
30
20
10
G = 1
0
BANDWIDTH
LIMITED
–10
–20
–30
–40
60
40
20
–50
NORMALIZED AT 25°C
–60
0
–40 –25 –10
5
20
35
50
65
80
95 110 125
1
10
100
1k
10k
100k
1M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 14. CMRR vs. Temperature (G = 1), Normalized at 25°C
Figure 11. CMRR vs. Frequency, 1 kΩ Source Imbalance
12
10
8
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
6
4
2
0
0
100
200
300
400
500
600
700
–50
–30
–10
10
30
50
70
90
110
130
TEMPERATURE (°C)
WARM-UP TIME (s)
Figure 15. Supply Current vs. Temperature (G = 1)
Figure 12. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time
Rev. 0 | Page 9 of 20
AD8429
+V
50
40
S
+125°C
+85°C
+25°C
–40°C
–0.5
–1.0
–1.5
–2.0
–2.5
I
SHORT+
30
20
10
0
+2.5
+2.0
+1.5
+1.0
+0.5
–10
–20
–30
–40
–50
I
SHORT–
–V
S
4
6
8
10
12
14
16
18
–40 –25 –10
5
20
35
50
65
80
95 110 125
SUPPLY VOLTAGE (±V )
TEMPERATURE (°C)
S
Figure 16. Short-Circuit Current vs. Temperature (G = 1)
Figure 19. Input Voltage Limit vs. Supply Voltage
30
25
20
15
10
5
+V
S
–0.4
–0.8
–1.2
–SR
+SR
+2.0
+1.6
+1.2
+0.8
+0.4
+125°C
+85°C
+25°C
–40°C
0
–V
S
–40 –25 –10
5
20
35
50
65
80
95 110 125
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±V )
TEMPERATURE (°C)
S
Figure 17. Slew Rate vs. Temperature, VS = 15 V (G = 1)
Figure 20. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
+V
S
25
20
15
10
5
–0.4
–0.8
–1.2
–SR
+SR
+2.0
+1.6
+1.2
+125°C
+85°C
+25°C
–40°C
+0.8
+0.4
–V
S
0
4
6
8
10
12
14
16
18
–40 –25 –10
5
20
35
50
65
80
95 110 125
SUPPLY VOLTAGE (±V )
TEMPERATURE (°C)
S
Figure 21. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
Figure 18. Slew Rate vs. Temperature, VS = 5 V (G = 1)
Rev. 0 | Page 10 of 20
AD8429
15
10
5
10
8
V
= ±15V
S
GAIN = 1000
6
4
2
+125°C
+85°C
+25°C
–40°C
0
0
–2
–4
–6
–8
–10
–5
–10
–15
–10
–8
–6
–4
–2
0
2
4
6
8
10
100
1k
10k
100k
LOAD (Ω)
OUTPUT VOLTAGE (V)
Figure 25. Gain Nonlinearity (G = 1000), RL = 10 kΩ
Figure 22. Output Voltage Swing vs. Load Resistance
+V
1000
100
10
S
V
= ±15V
S
–0.4
–0.8
–1.2
–1.6
G = 1
+2.0
+1.6
+1.2
+0.8
+0.4
G = 10
G = 100
G = 1k
1
+125°C
+85°C
+25°C
–40°C
–V
S
10µ
0.1
1
10
100
1k
10k
100k
100µ
1m
10m
OUTPUT CURRENT (A)
FREQUENCY (Hz)
Figure 23. Output Voltage Swing vs. Output Current
Figure 26. RTI Voltage Noise Spectral Density vs. Frequency
10
8
GAIN = 1
GAIN = 1000, 100nV/DIV
6
4
2
GAIN = 1, 2μV/DIV
0
–2
–4
–6
–8
–10
1s/DIV
–10
–8
–6
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
Figure 24. Gain Nonlinearity (G = 1), RL = 10 kΩ
Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1, G = 1000)
Rev. 0 | Page 11 of 20
AD8429
16
15
14
13
12
11
10
9
5V/DIV
750ns TO 0.01%
872ns TO 0.001%
8
7
6
0.002%/DIV
5
4
3
2µs/DIV
2
1
1
TIME (µs)
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 28. Current Noise Spectral Density vs. Frequency
Figure 31. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step,
VS = 15 V
5V/DIV
640ns TO 0.01%
896ns TO 0.001%
0.002%/DIV
50pA/DIV
1s/DIV
2µs/DIV
TIME (µs)
Figure 29. 0.1 Hz to 10 Hz Current Noise
Figure 32. Large Signal Pulse Response and Settling Time (G = 10), 10 V Step,
VS = 15 V
30
25
20
15
10
5
G = 1
V
= ±15V
S
5V/DIV
840ns TO 0.01%
1152ns TO 0.001%
0.002%/DIV
V
= ±5V
S
2µs/DIV
0
100
1k
10k
100k
1M
10M
TIME (µs)
FREQUENCY (Hz)
Figure 30. Large Signal Frequency Response
Figure 33. Large Signal Pulse Response and Settling Time (G = 100),
10 V Step, VS = 15 V
Rev. 0 | Page 12 of 20
AD8429
G = 100
5V/DIV
5.04µs TO 0.01%
6.96µs TO 0.001%
0.002%/DIV
20mV/DIV
1µs/DIV
10µs/DIV
TIME (µs)
Figure 37. Small Signal Response (G = 100), RL = 10 kΩ, CL = 100 pF
Figure 34. Large Signal Pulse Response and Settling Time (G = 1000),
10 V Step, VS = 15 V
G = 1000
G = 1
20mV/DIV
10µs/DIV
50mV/DIV
1µs/DIV
Figure 35. Small Signal Response (G = 1), RL = 10 kΩ, CL = 100 pF
Figure 38. Small Signal Response (G = 1000), RL = 10 kΩ, CL = 100 pF
G = 10
G = 1
NO LOAD
C
C
= 100pF
= 147pF
L
L
20mV/DIV
1µs/DIV
50mV/DIV
1µs/DIV
Figure 39. Small Signal Response with Various Capacitive Loads (G = 1),
RL = Infinity
Figure 36. Small Signal Response (G = 10), RL = 10 kΩ, CL = 100 pF
Rev. 0 | Page 13 of 20
AD8429
1400
1200
1000
800
1
0.1
NO LOAD
2kꢀ LOAD
600ꢀ LOAD
G = 1000, SECOND HARMONIC
= 10V p-p
V
OUT
SETTLED TO 0.001%
0.01
SETTLED TO 0.01%
600
400
0.001
0.0001
200
0
2
4
6
8
10
12
14
16
18
20
10
100
1k
10k
100k
STEP SIZE (V)
FREQUENCY (Hz)
Figure 40. Settling Time vs. Step Size (G = 1)
Figure 43. Second Harmonic Distortion vs. Frequency (G = 1000)
1
1
0.1
NO LOAD
2kꢀ LOAD
600ꢀ LOAD
NO LOAD
2kꢀ LOAD
600ꢀ LOAD
G = 1, SECOND HARMONIC
= 10V p-p
G = 1000, THIRD HARMONIC
= 10V p-p
V
V
OUT
OUT
0.1
0.01
0.01
0.001
0.0001
0.001
0.0001
0.00001
10
10
100
1k
10k
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 41. Second Harmonic Distortion vs. Frequency (G = 1)
Figure 44. Third Harmonic Distortion vs. Frequency (G = 1000)
1
1
NO LOAD
2kꢀ LOAD
600ꢀ LOAD
G = 1, THIRD HARMONIC
= 10V p-p
V
R
= 10V p-p
OUT
≥ 2kꢀ
V
OUT
L
0.1
0.01
0.1
0.01
GAIN = 100
0.001
0.001
GAIN = 1000
GAIN = 10
GAIN = 1
0.0001
0.0001
0.00001
0.00001
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 42. Third Harmonic Distortion vs. Frequency (G = 1)
Figure 45. THD vs. Frequency
Rev. 0 | Page 14 of 20
AD8429
THEORY OF OPERATION
I
V
I
B
I
I
B
B
COMPENSATION
COMPENSATION
R3
5kꢀ
A1
A2
+V
–V
C1
C2
S
R4
5kꢀ
NODE 1
V
A3
OUT
NODE 2
+V
–V
R5
5kꢀ
S
+V
–V
+V
–V
S
S
R1
3kꢀ
R2
3kꢀ
R6
5kꢀ
S
+V
–V
+V
S
S
REF
Q1
Q2
–IN
+IN
R
G
S
S
S
RG–
RG+
–V
S
S
Figure 46. Simplified Schematic
ARCHITECTURE
Table 5. Gains Achieved Using 1% Resistors
The AD8429 is based on the classic 3-op-amp topology. This
topology has two stages: a preamplifier to provide differential
amplification followed by a difference amplifier that removes
the common-mode voltage and provides additional amplifica-
tion. Figure 46 shows a simplified schematic of the AD8429.
1% Standard Table Value of RG
Calculated Gain
6.04 kΩ
1.5 kΩ
665 Ω
316 Ω
121 Ω
60.4 Ω
30.1 Ω
12.1 Ω
6.04 Ω
3.01 Ω
1.993
5.000
10.02
19.99
50.59
100.3
200.3
496.9
994.4
1994
The first stage works as follows. To keep its two inputs matched,
Amplifier A1 must keep the collector of Q1 at a constant voltage.
It does this by forcing RG− to be a precise diode drop from –IN.
Similarly, A2 forces RG+ to be a constant diode drop from +IN.
Therefore, a replica of the differential input voltage is placed
across the gain setting resistor, RG. The current that flows through
this resistance must also flow through the R1 and R2 resistors,
creating a gained differential signal between the A2 and A1
outputs.
The AD8429 defaults to G = 1 when no gain resistor is used.
Add the tolerance and gain drift of the RG resistor to the
specifications of the AD8429 to determine the total gain accu-
racy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.
The second stage is a G = 1 difference amplifier, composed of
Amplifier A3 and the R3 through R6 resistors. This stage removes
the common-mode signal from the amplified differential signal.
RG Power Dissipation
The transfer function of the AD8429 is
The AD8429 duplicates the differential voltage across its inputs
onto the RG resistor. Choose an RG resistor size sufficient to
handle the expected power dissipation.
V
OUT = G × (VIN+ − VIN−) + VREF
where:
6 kΩ
REFERENCE TERMINAL
G =1+
RG
The output voltage of the AD8429 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal must be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level
shift the output, allowing the AD8429 to drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8429, which can be calculated by referring to Table 5 or by
using the following gain equation:
6 kΩ
RG
=
G −1
Rev. 0 | Page 15 of 20
AD8429
For best performance, maintain a source impedance to the REF
terminal that is well below 1 ꢀ. As shown in Figure 46, the
reference terminal, REF, is at one end of a 5 kΩ resistor.
Additional impedance at the REF terminal adds to this 5 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
can be calculated as follows:
source resistance in the input path (for example, for input
protection) close to the in-amp inputs, which minimizes their
interaction with parasitic capacitance from the PCB traces.
Parasitic capacitance at the gain setting pins can also affect CMRR
over frequency. If the board design has a component at the gain
setting pins (for example, a switch or jumper), choose a component
such that the parasitic capacitance is as small as possible.
2(5 kΩ + RREF)/(10 kΩ + RREF
)
Power Supplies and Grounding
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
Use a stable dc voltage to power the instrumentation amplifier.
Noise on the supply pins can adversely affect performance. See
the PSRR performance curves in Figure 9 and Figure 10 for more
information.
INCORRECT
CORRECT
Place a 0.1 μF capacitor as close as possible to each supply pin.
Because the length of the bypass capacitor leads is critical at
high frequency, surface-mount capacitors are recommended. A
parasitic inductance in the bypass ground trace works against
the low impedance created by the bypass capacitor. As shown in
Figure 49, a 10 μF capacitor can be used farther away from the
device. For larger value capacitors, intended to be effective at
lower frequencies, the current return path distance is less critical.
In most cases, this capacitor can be shared by other precision
integrated circuits.
AD8429
AD8429
REF
REF
V
V
+
OP1177
–
Figure 47. Driving the Reference Pin
INPUT VOLTAGE RANGE
+V
S
Figure 4 and Figure 5 show the allowable common-mode input
voltage ranges for various output voltages and supply voltages.
The 3-op-amp architecture of the AD8429 applies gain in the
first stage before removing common-mode voltage with the
difference amplifier stage. Internal nodes between the first and
second stages (Node 1 and Node 2 in Figure 46) experience a
combination of a gained signal, a common-mode signal, and a
diode drop. This combined signal can be limited by the voltage
supplies even when the individual input and output signals are
not limited.
0.1µF
10µF
+IN
–IN
V
OUT
R
G
AD8429
LOAD
REF
0.1µF
10µF
LAYOUT
–V
S
To ensure optimum performance of the AD8429 at the PCB
level, care must be taken in the design of the board layout. The
pins of the AD8429 are arranged in a logical manner to aid in
this task.
Figure 49. Supply Decoupling, REF, and Output Referred to Local Ground
A ground plane layer is helpful to reduce parasitic inductances.
This minimizes voltage drops with changes in current. The area
of the current path is directly proportional to the magnitude of
parasitic inductances and, therefore, the impedance of the path
at high frequency. Large changes in currents in an inductive
decoupling path or ground return create unwanted effects, due
to the coupling of such changes into the amplifier inputs.
1
8
7
6
5
+V
V
–IN
S
2
3
4
R
G
OUT
R
REF
G
+IN
–V
S
AD8429
TOP VIEW
(Not to Scale)
Because load currents flow from the supplies, the load should
be connected at the same physical location as the bypass capa-
citor grounds.
Figure 48. Pinout Diagram
Common-Mode Rejection Ratio over Frequency
Reference Pin
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To maintain high
CMRR over frequency, closely match the input source
impedance and capacitance of each path. Place additional
The output voltage of the AD8429 is developed with respect to
the potential on the reference terminal. Ensure that REF is tied
to the appropriate local ground.
Rev. 0 | Page 16 of 20
AD8429
Noise sensitive applications may require a lower protection resis-
tance. Low leakage diode clamps, such as the BAV199, can be used
at the inputs to shunt current away from the AD8429 inputs,
thereby allowing smaller protection resistor values. To ensure
current flows primarily through the external protection diodes,
place a small value resistor, such as a 33 Ω, between the diodes and
the AD8429.
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8429 must have a return path to
ground. When using a floating source without a current return
path, such as a thermocouple, create a current return path, as
shown in Figure 50.
INCORRECT
CORRECT
+V
+V
S
S
+V
S
+V
+V
S
S
R
+
IN+
–
R
PROTECT
I
33ꢀ
PROTECT
I
+
IN+
–
V
V
–V
+V
S
AD8429
AD8429
AD8429
AD8429
S
R
R
REF
REF
REF
REF
PROTECT
33ꢀ
PROTECT
+
IN–
–
+
IN–
–
–V
S
–V
S
V
V
–V
S
–V
–V
S
S
SIMPLE METHOD
LOW NOISE METHOD
TRANSFORMER
TRANSFORMER
Figure 51. Protection for Voltages Beyond the Rails
+V
+V
S
S
Large Differential Input Voltage at High Gain
If large differential voltages at high gain are expected, use an
external resistor in series with each input to limit current during
overload conditions. The limiting resistor at each input can be
computed by using the following equation:
AD8429
AD8429
REF
10Mꢀ
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VDIFF −1V
1
2
RPROTECT
≥
− RG
–V
S
–V
S
IMAX
THERMOCOUPLE
THERMOCOUPLE
Noise sensitive applications may require a lower protection resis-
tance. Low leakage diode clamps, such as the BAV199, can be used
across the inputs to shunt current away from the AD8429 inputs
and, therefore, allow smaller protection resistor values.
+V
+V
S
S
C
C
C
R
R
1
R
R
PROTECT
fHIGH-PASS
=
PROTECT
AD8429
2πRC
AD8429
I
I
C
+
+
REF
V
V
DIFF
–
DIFF
–
AD8429
AD8429
R
PROTECT
R
PROTECT
–V
–V
S
S
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
SIMPLE METHOD
LOW NOISE METHOD
Figure 50. Creating an Input Bias Current Return Path
Figure 52. Protection for Large Differential Voltages
INPUT PROTECTION
IMAX
Do not allow the inputs of the AD8429 to exceed the ratings
stated in the Absolute Maximum Ratings section of this data
sheet. If this cannot be done, protection circuitry can be added
in front of the AD8429 to limit the current into the inputs to a
The maximum current into the AD8429 inputs, IMAX, depends
on time and temperature. At room temperature, the device can
withstand a current of 10 mA for at least one day. This time is
cumulative over the life of the device.
maximum current, IMAX
.
RADIO FREQUENCY INTERFERENCE (RFI)
Input Voltages Beyond the Rails
RF rectification is often a problem when amplifiers are used in
applications that have strong RF signals. The disturbance can
appear as a small dc offset voltage. High frequency signals can
be filtered with a low-pass RC network placed at the input of
the instrumentation amplifier, as shown in Figure 53.
If voltages beyond the rails are expected, use an external resistor
in series with each input to limit current during overload condi-
tions. The limiting resistor at the input can be computed from
|VIN −VSUPPLY
|
RPROTECT
≥
IMAX
Rev. 0 | Page 17 of 20
AD8429
+V
S
at the amplifier input. To calculate the noise referred to the
amplifier output (RTO), simply multiply the RTI noise by the
gain of the instrumentation amplifier.
0.1µF
+IN
10µF
C
1nF
C
Source Resistance Noise
R
Any sensor connected to the AD8429 has some output resistance.
There may also be resistance placed in series with inputs for pro-
tection from either overvoltage or radio frequency interference.
This combined resistance is labeled R1 and R2 in Figure 54. Any
resistor, no matter how well made, has an intrinsic level of noise.
This noise is proportional to the square root of the resistor value.
At room temperature, the value is approximately equal to
4 nV/√Hz × √(resistor value in kΩ).
4.02kꢀ
V
C
D
10nF
OUT
R
G
AD8429
R
REF
–IN
4.02kꢀ
C
C
1nF
0.1µF
10µF
–V
S
Figure 53. RFI Suppression
For example, assuming that the combined sensor and protec-
tion resistance on the positive input is 4 kΩ, and on the negative
input is 1 kΩ, the total noise from the input resistance is
The filter limits the input signal bandwidth, according to the
following relationship:
2
2
1
4× 4
)
+
4× 1
)
= 64 +16 = 8.9 nV/√Hz
FilterFrequencyDIFF
FilterFrequencyCM
=
2πR(2CD +CC )
Voltage Noise of the Instrumentation Amplifier
1
=
2πRCC
The voltage noise of the instrumentation amplifier is calculated
using three parameters: the device input noise, output noise,
and the RG resistor noise. It is calculated as follows:
where CD ≥ 10 CC.
CD affects the difference signal, and CC affects the common-mode
signal. Choose values of R and CC that minimize RFI. A mismatch
between R × CC at the positive input and R × CC at the negative
input degrades the CMRR of the AD8429. By using a value of
CD that is one magnitude larger than CC, the effect of the
mismatch is reduced, and performance is improved.
Total Voltage Noise =
2
2
2
OutputNoise/G
)
+
InputNoise
)
+
(
Noise of RG Resistor
)
For example, for a gain of 100, the gain resistor is 60.4 Ω. There-
fore, the voltage noise of the in-amp is
Resistors add noise; therefore, the choice of resistor and capacitor
values depends on the desired tradeoff between noise, input
impedance at high frequencies, and RFI immunity. The resistors
used for the RFI filter can be the same as those used for input
protection.
2
2
(
45/100
)
+12 +
4× 0.0604
)
= 1.5 nV/√Hz
Current Noise of the Instrumentation Amplifier
Current noise is calculated by multiplying the source resistance
by the current noise.
CALCULATING THE NOISE OF THE INPUT STAGE
SENSOR
For example, if the R1 source resistance in Figure 54 is 4 kΩ,
and the R2 source resistance is 1 kΩ, the total effect from the
current noise is calculated as follows:
R
2
2
R1
G
AD8429
(
4×1.5
)
+
(
1×1.5
)
)
= 6.2 nV/√Hz
Total Noise Density Calculation
R2
To determine the total noise of the in-amp, referred to input,
combine the source resistance noise, voltage noise, and current
noise contribution by the sum of squares method.
Figure 54. Source Resistance from Sensor and Protection Resistors
The total noise of the amplifier front end depends on much
more than the 1 nV/√Hz specification of this data sheet. There
are three main contributors: the source resistance, the voltage
noise of the instrumentation amplifier, and the current noise of
the instrumentation amplifier.
For example, if the R1 source resistance in Figure 54 is 4 kΩ, the
R2 source resistance is 1 kΩ, and the gain of the in-amps is 100,
the total noise, referred to input, is
8.92 +1.52 + 6.22 = 11.0 nV/√Hz
In the following calculations, noise is referred to the input
(RTI). In other words, everything is calculated as if it appeared
Rev. 0 | Page 18 of 20
AD8429
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
AD8429ARZ
AD8429ARZ-R7
AD8429BRZ
AD8429BRZ-R7
8-Lead SOIC_N
8-Lead SOIC_N, 7”Tape and Reel
8-Lead SOIC_N
R-8
R-8
R-8
R-8
8-Lead SOIC_N, 7”Tape and Reel
1 Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
AD8429
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09730-0-4/11(0)
Rev. 0 | Page 20 of 20
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