AD842JRZ-16 [ADI]
Wideband, High Output Current, Fast Settling Op Amp;
| 型号： | AD842JRZ-16 |
| 厂家： | 
ADI |
| 描述： | Wideband, High Output Current, Fast Settling Op Amp 放大器 光电二极管 |
| 文件： | 总16页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wideband, High Output Current
Fast Settling Op Amp
Data Sheet
AD842
FEATURES
CONNECTION DIAGRAMS
NIC
1
2
3
4
5
6
7
NIC
14
13
12
AC performance
AD842
NIC
BALANCE
NIC
TOP VIEW
Gain bandwidth product: 80 MHz (gain = 2)
Fast settling: 100 ns to 0.01% for a 10 V step
Slew rate: 375 V/µs
Stable at gains of 2 or greater
Full power bandwidth: 6 MHz for 20 V p-p
DC performance
BALANCE
–INPUT
+INPUT
V–
11 V+
+
10 OUTPUT
9
8
NIC
NIC
(Not to Scale)
NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
Input offset voltage: 1.5 mV maximum
Input offset drift: 14 µV/°C
Figure 1. PDIP (N-14) and CERDIP (Q-14)
Input voltage noise: 9 nV/√Hz
Open-loop gain: 90 V/mV into a 499 Ω load
Output current: 100 mA minimum
Quiescent supply current: 14 mA maximum
NIC
BALANCE
–INPUT
NIC
1
2
3
4
5
6
7
8
16 NIC
AD842
TOP VIEW
15
BALANCE
(Not to Scale)
14 +V
S
13 NIC
+INPUT
NIC
12 OUTPUT
+
APPLICATIONS
11
NIC
–V
S
10 NIC
Line drivers
DAC and ADC buffers
NIC
9
NIC
Video and pulse amplifiers
MIL-STD-883B parts available, see military data sheet
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
Figure 2. SOIC_W (RW-16)
GENERAL DESCRIPTION
The AD842 is a member of the Analog Devices, Inc. family of
wide bandwidth operational amplifiers. This device is fabricated
using the Analog Device junction isolated complementary
bipolar (CB) process. This process permits a combination of dc
precision and wideband ac performance previously unobtain-
able in a monolithic op amp. In addition to its 80 MHz gain
bandwidth product, the AD842 offers extremely fast settling
characteristics, typically settling to within 0.01% of final value
in less than 100 ns for a 10 V step.
acquisition applications requiring 12-bit accuracy. The AD842
is also appropriate for other applications, such as high speed
DAC and ADC buffer amplifiers and other wide bandwidth
circuitry.
PRODUCT HIGHLIGHTS
1. The high slew rate and fast settling time of the AD842
make it ideal for DAC and ADC buffers amplifiers, line
drivers, and all types of video instrumentation circuitry.
2. The AD842 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth, performance
previously available only in hybrids.
3. Laser-wafer trimming reduces the input offset voltage of
1.5 mV maximum, thus eliminating the need for external
offset nulling in many applications.
The AD842 also offers a low quiescent current of 13 mA, a high
output current drive capability (100 mA minimum), a low input
voltage noise of 9 nV√Hz, and a low input offset voltage
(1.5 mV maximum).
The 375 V/µs slew rate of the AD842, along with its 80 MHz
gain bandwidth product, ensures excellent performance in
video and pulse amplifier applications. This amplifier is ideally
suited for use in high frequency signal conditioning circuits and
wide bandwidth active filters. The extremely rapid settling time
of the AD842 makes this amplifier the preferred choice for data
4. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where the
circuit gain is 2 or greater.
Rev. F
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©1988–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD842
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................5
Theory of Operation .........................................................................9
Offset Nulling ................................................................................9
Settling Time..................................................................................9
Grounding and Bypassing......................................................... 10
Capacitive Load Driving Ability............................................... 10
Using a Heat Sink ....................................................................... 10
Terminated Line Driver............................................................. 10
Overdrive Recovery ................................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics− 15 V Operation ............................ 3
Absolute Maximum Ratings............................................................ 4
Thermal Characteristics .............................................................. 4
ESD Caution.................................................................................. 4
Metalization Photograph............................................................. 4
REVISION HISTORY
2/14—Rev. E to Rev. F
Changes to Figure 18.........................................................................7
Changes to Figure 22 Caption, Figure 23 Caption, Figure 24,
and Figure 27......................................................................................8
Changes to Figure 28.........................................................................9
Changes to Using a Heat Sink Section and Figure 32................ 10
Changes to Figure 34...................................................................... 11
Updated Outline Dimensions....................................................... 12
Added Ordering Guide.................................................................. 13
Updated Format..................................................................Universal
Deleted 20-Terminal LCC and 12-Pin TO-8 ..................Universal
Changed NC Pin to NIC Pin Throughout .................................... 1
Changes to Features, General Description, Connection
Diagrams, and Product Highlights Sections................................. 1
Changes to Table 1............................................................................ 3
Changes to Table 2, Thermal Characteristics Section, Table 3,
and Figure 3....................................................................................... 4
Changes to Figure 11, Figure 13, Figure 14, and Figure 15 ........ 6
3/00—Rev. D to Rev. E
Rev. F | Page 2 of 16
Data Sheet
AD842
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS— 15 V OPERATION
TA = 25°C, unless otherwise specified. All minimum and maximum specifications are guaranteed. Specifications shown in boldface are
tested on all production units.
Table 1.
AD842JN/AD842JQ/AD842JR1
AD842KN/AD842KQ
AD842SQ
Typ
Test Conditions/
Comments
Parameter
INPUT OFFSET VOLTAGE2
Min
Typ
Max
Min
Typ
Max
1.0
Min
Max
1.5
3.5
Unit
mV
mV
µV/°C
µA
0.5
1.5
0.3
0.5
TMIN to TMAX
2.5/2.5/3
1.5
Offset Drift
14
14
14
INPUT BIAS CURRENT
4.2
8
3.5
5
4.2
8
TMIN to TMAX
10
0.4
0.5
6
0.2
0.3
12
0.4
0.6
µA
Input Offset Current
0.1
0.05
0.1
µA
TMIN to TMAX
µA
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Differential mode
100
2.0
100
2.0
100
2.0
kΩ
pF
INPUT VOLTAGE RANGE
Common Mode
10
86
10
90
10
86
V
Common-Mode Rejection
VCM
=
10 V
115
115
115
dB
TMIN to TMAX
f = 1 kHz
10 Hz to 10 MHz
80
86
80
dB
INPUT VOLTAGE NOISE
Wideband Noise
9
28
9
28
9
28
nV/√Hz
µV rms
OPEN-LOOP GAIN
VOUT = 10 V
RLOAD ≥ 499 Ω
TMIN to TMAX
40/40/30
20/20/15
90
50
25
90
40
20
90
V/mV
V/mV
OUTPUT CHARACTERISTICS
Voltage
Current
RLOAD ≥ 499 Ω
10
100
10
100
10
100
V
VOUT
=
10 V
mA
Ω
Open loop
5
5
5
FREQUENCY RESPONSE
Gain Bandwidth Product
VOUT = 90 mV,
80
6
80
6
80
6
MHz
MHz
A
VCL = 2
VOUT = 20 V p-p,
LOAD ≥ 499 Ω
Full Power Bandwidth3
4.7
4.7
4.7
R
Rise Time
AVCL = −2
AVCL = −2
AVCL = −2
10 V step
To 0.1%
10
20
375
10
20
375
10
20
375
ns
%
V/µs
Overshoot
Slew Rate
Settling Time4
300
300
300
80
80
80
ns
To 0.01%
f = 4.4 MHz
f = 4.4 MHz
100
0.015
0.035
100
0.015
0.035
100
0.015
0.035
ns
%
Degree
Differential Gain
Differential Phase
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
15
15
13
15
13
V
5
18
5
18
14
16
5
18
14
19
V
13/13/14
100
14/14/16
16/16/19.5
mA
mA
dB
TMIN to TMAX
VS = 5 V to
18 V
Power Supply Rejection
Ratio
105
100
86
90
86
86
80
TMIN to TMAX
80
dB
1 AD842JR specifications differ from those of the AD842JN and AD842JQ due to the thermal characteristics of the SOIC package.
2 Input offset voltage specifications are guaranteed after 5 minutes at TA = 25°C.
3 Full power bandwidth = slew rate/2 π V peak.
4 Refer to Figure 29 and Figure 30.
Rev. F | Page 3 of 16
AD842
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage
18 V
Internal Power Dissipation1
PDIP (N-14), SOIC_W (RW-16)
CERDIP (Q-14)
1.3 W
1.1 W
VS
Input Voltage
THERMAL CHARACTERISTICS
Differential Input Voltage
Operating Temperature Range
CERDIP (Q-14, AD842SQ Only)
PDIP (N-14), SOIC_W (RW-16),
CERDIP (Q-14, AD842JQ and
AD842KQ Only)
Storage Temperature Range
CERDIP (Q-14, All Models)
PDIP (N-14), SOIC_W (RW-16)
Junction Temperature
6 V
Table 3.
−55°C to +125°C
0°C to 70°C
Package
θJC
30
30
30
θJA
θSA
Unit
°C/W
°C/W
°C/W
14-Lead PDIP
14-Lead CERDIP
16-Lead SOIC_W
100
110
100
38
−65°C to +150°C
−65°C to +125°C
175°C
ESD CAUTION
Lead Temperature (Soldering 60 sec)
300°C
1 Maximum internal power dissipation is specified so that TJ does not exceed
150°C at an ambient temperature of 25°C.
METALIZATION PHOTOGRAPH
0.106 (2.68)
BALANCE
V+
BALANCE
–INPUT
OUTPUT
0.067
(1.69)
+INPUT
V–
Figure 3. Contact Factory for Latest Dimensions,
Dimensions Shown in Inches and (Millimeters)
Rev. F | Page 4 of 16
Data Sheet
AD842
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C and VS = 15 V, unless otherwise noted.
20
18
16
14
12
10
15
10
V
IN
5
0
0
5
10
SUPPLY VOLTAGE (±V)
15
20
0
5
10
15
20
SUPPLY VOLTAGE (±V)
Figure 4. Input Common-Mode Range vs. Supply Voltage
Figure 7. Quiescent Current vs. Supply Voltage
20
15
10
5
–5
–4
–3
–2
±V
OUT
0
0
5
10
SUPPLY VOLTAGE (±V)
15
20
–60 –40 –20
0
20
40
60
80 100 120 140
TEMPERATURE (°C)
Figure 5. Output Voltage Swing vs. Supply Voltage
Figure 8. Input Bias Current vs. Temperature
30
25
20
15
10
5
100
10
±15V SUPPLIES
1
0.1
0.01
0
10
100
1k
10k
10k
100k
1M
10M
100M
LOAD RESISTANCE (Ω)
FREQUENCY (Hz)
Figure 6. Output Voltage Swing vs. Load Resistance
Figure 9. Output Impedance vs. Frequency
Rev. F | Page 5 of 16
AD842
Data Sheet
18
17
16
15
14
13
12
11
10
120
100
80
60
40
20
0
100
80
60
40
20
0
499Ω LOAD
–60 –40 –20
0
20
40
60
80 100 120 140
100
1k
10k
100k
1M
10M
100M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 10. Quiescent Current vs. Temperature
Figure 13. Open-Loop Gain and Phase Margin vs. Frequency
300
275
250
225
200
175
150
125
100
110
105
100
95
+OUTPUT CURRENT
–OUTPUT CURRENT
499Ω LOAD
90
–60 –40 –20
0
20
40
60
80 100 120 140
0
5
10
SUPPLY VOLTAGE (±V)
15
20
TEMPERATURE (°C)
Figure 14. Open-Loop Gain vs. Supply Voltage
Figure 11. Short-Circuit Current Limit vs. Temperature
85
80
75
70
65
120
100
80
60
40
20
0
+V
S
–V
S
–60 –40 –20
0
20
40
60
80 100 120 140
100
1k
10k
100k
1M
10M
100M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 12. Gain Bandwidth Product vs. Temperature
Figure 15. Power Supply Rejection vs. Frequency
Rev. F | Page 6 of 16
Data Sheet
AD842
120
100
80
–80
–90
3V rms
= 1kΩ
V
V
T
= ±15V
S
R
L
= 1V p-p
CM
= 25°C
A
–100
–110
–120
–130
–140
SECOND HARMONIC
60
40
THIRD HARMONIC
10k
20
1k
10k
100k
1M
10M
100M
100M
110
100
1k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. Common-Mode Rejection vs. Frequency
Figure 19. Harmonic Distortion vs. Frequency
30
25
20
15
10
5
50
40
30
20
10
R
= 1kΩ
= 25°C
= ±15V
L
T
A
V
S
0
0
10
100
1k
10k
100k
1M
10M
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Large Signal Frequency Response
Figure 20. Input Voltage vs. Frequency
10
550
500
450
400
350
300
250
8
6
4
2
0
0.1%
0.1%
0.01%
0.01%
–2
–4
–6
–8
–10
–60 –40 –20
0
20
40
60
80 100 120 140
30
40
50
60
70
80
90
100
SETTLING TIME (ns)
TEMPERATURE (°C)
Figure 18. Output Swing vs. Settling Time
Figure 21. Slew Rate vs. Temperature
Rev. F | Page 7 of 16
AD842
Data Sheet
2V
2V
50ns
50ns
100%
90%
100%
90%
10%
0%
10%
0%
Figure 22. Inverting Large Signal Pulse Response (see Figure 24)
Figure 25. Noninverting Large Signal Pulse Response (see Figure 27)
50mV
50mV
50ns
50ns
100%
90%
100%
90%
10%
0%
10%
0%
Figure 23. Inverting Small Signal Pulse Response (see Figure 24)
Figure 26. Noninverting Small Signal Pulse Response (see Figure 27)
R
= 1kΩ
R
= 205Ω
R
= 205Ω
F
F
F
0.1µF
2.2µF
0.1µF
2.2µF
+V
+V
S
S
R
=
IN
499Ω
FUNCTION
GENERATOR
11
AD842
6
11
AD842
6
4
4
5
V
V
OUT
OUT
10
10
49.9Ω
V
100Ω
FUNCTION
GENERATOR
IN
5
499Ω
499Ω
332Ω
0.1µF
2.2µF
49.9Ω
0.1µF
2.2µF
–V
–V
S
S
Figure 27. Noninverting Amplifier Configuration (PDIP)
Figure 24. Inverting Amplifier Configuration (PDIP)
Rev. F | Page 8 of 16
Data Sheet
AD842
THEORY OF OPERATION
OFFSET NULLING
10V
10mV
20ns
100%
90%
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 28 can be used.
OUTPUT:
10V/DIV
SETTLING TIME
OUTPUT
ERROR:
0.02%/DIV
Figure 29 and Figure 31 show the settling performance of the
AD842 in the test circuit shown in Figure 30.
Settling time is the interval of time from the application of an
ideal step function input until the closed-loop amplifier output
enters and remains within a specified error band.
10%
0%
This definition encompasses the major components that
comprise settling time. They include the following:
Figure 29. 0.01% Settling Time
Figure 30 shows how measurement of the AD842 0.01% settling
in 100 ns is accomplished by amplifying the error signal from a
false summing junction with a very high speed proprietary
hybrid error amplifier specially designed to enable testing of
small settling errors. Under test, the device drives a 300 Ω load.
The input to the error amp is clamped to avoid possible
problems associated with the overdrive recovery of the
oscilloscope input amplifier. The error amp gains the error from
the false summing junction by 15, and it contains a gain vernier
to fine trim the gain.
•
•
•
Propagation delay through the amplifier.
Slewing time to approach the final output value.
Time of recovery from the overload associated with
slewing.
•
Linear settling to within the specified error band.
Expressed in these terms, the measurement of settling time
must be accurate to assure the user that the amplifier is worth
consideration for the application.
+V
S
10kΩ
0.1µF
2.2µF
Figure 31 shows the long-term stability of the settling
3
4
5
characteristics of the AD842 output after a 10 V step. There is
no evidence of settling tails after the initial transient recovery
time. The use of a junction isolated process, together with
careful layout, avoids these problems by minimizing the effects
of transistor isolation capacitance discharge and thermally
induced shifts in circuit operating points. These problems do
not occur even under high output current conditions.
13
11
V
OUT
10
V
AD842
IN
6
R
L
0.1µF
2.2µF
–V
S
Figure 28. Offset Nulling (PDIP)
ERROR
AMP
(×15)
TEK
7A13
TEK
7603
OSCILLOSCOPE
TEK
7A16
HP6263
DDD5109
FLAT-TOP
PULSE
499Ω
499Ω
1kΩ
1kΩ
GENERATOR
0.1µF
2.2µF
50Ω
+15V
11
4
5
FET PROBE
TEK P6201
10
AD842
499Ω
0.1µF
6
499Ω
2.2µF
–15V
Figure 30. Settling Time Test Circuit (PDIP)
Rev. F | Page 9 of 16
AD842
Data Sheet
the dynamic performance of the device, although instability
does not occur unless the load exceeds 100 pF.
GROUNDING AND BYPASSING
In designing practical circuits with the AD842, the user must
take some special precautions whenever high frequencies are
involved.
USING A HEAT SINK
The AD842 draws less quiescent power than most precision
high speed amplifiers and is specified for operation without a
heat sink. However, when driving low impedance loads, the
current to the load can be 10 times the quiescent current. This
creates a noticeable temperature rise. Use of a small heat sink
improves performance.
5mV
2µs
100%
90%
OUTPUT:
5V/DIV
OUTPUT
ERROR:
0.01%/DIV
TERMINATED LINE DRIVER
The AD842 is optimized for high speed line driver applications.
Figure 32 shows the AD842 driving a doubly terminated cable
in a gain-of-2 follower configuration. The AD842 maintains a
typical slew rate of 375 V/μs, which means it can drive a 10 V,
6.0 MHz signal, or a 3 V, 19.9 MHz signal.
10%
0%
The termination resistor, RT, minimizes reflections from the far
end of the cable when equal to the characteristic impedance of
the cable. A back-termination resistor (RBT, also equal to the
characteristic impedance of the cable) can be placed between
the AD842 output and the cable to damp any stray signals
caused by a mismatch between RT and the characteristic
impedance of the cable. This configuration results in a cleaner
signal. With this circuit, the voltage on the line equals VIN
because one half of VOUT is dropped across RBT.
Figure 31. AD842 Settling Demonstrating No Settling Tails
Circuits must be built with short interconnect leads. Use large
ground planes whenever possible to provide a low resistance,
low inductance circuit path; this also minimizes the effects of
high frequency coupling. Avoid sockets because the increased
interlead capacitance can degrade bandwidth.
Use feedback resistors of low enough value to ensure that the
time constant formed with the circuit capacitances does not
limit the amplifier performance. Resistor values of less than
5 kΩ are recommended. If a larger resistor must be used, a
small (<10 pF) feedback capacitor connected in parallel with
the feedback resistor, RF, can be used to compensate for these
stray capacitances and to optimize the dynamic performance of
the amplifier in the particular application.
The AD842 has a 100 mA minimum output current and,
therefore, can drive 5 V into a 50 Ω cable.
Choose the feedback resistors, R1 and R2, carefully. Large value
resistors are desirable to limit the amount of current drawn
from the amplifier output. Large resistors can cause amplifier
instability because the parallel resistance of R1||R2 combines
with the input capacitance (typically 2 pF to 5 pF) to create an
additional pole. The voltage noise of the AD842 is equivalent to
a 5 kΩ resistor; these large resistors can significantly increase
the system noise. Resistor values of 1 kΩ or 2 kΩ are
recommended.
Bypass power supply leads to ground as close as possible to the
amplifier pins. A 2.2 μF capacitor in parallel with a 0.1 μF
ceramic disk capacitor is recommended.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD842 is sensitive to
capacitive loading. The AD842 is designed to drive capacitive
loads of up to 20 pF without degradation of its rated
performance. Capacitive loads of greater than 20 pF decrease
If termination is not used, cables appear as capacitive loads and
can be decoupled from the AD842 by a resistor in series with
the output.
0.1µF
2.2µF
+V
S
50Ω OR 75Ω
CABLE
11
AD842
6
V
5
IN
R
BT
10
TERMINATION
RESISTOR FOR
INPUT SIGNAL
4
0.1µF
R
T
2.2µF
R1
R2
–V
S
R
= R = CABLE
BT
T
CHARACTERISTIC IMPEDANCE
Figure 32. Line Driver Configuration (PDIP)
Rev. F | Page 10 of 16
Data Sheet
AD842
0.1µF
2.2µF
OVERDRIVE RECOVERY
+V
S
Figure 33 shows the overdrive recovery capability of the AD842.
Typical recovery time is 80 ns from negative overdrive and
400 ns from positive overdrive.
11
AD842
6
4
5
PULSE
GENERATOR
V
OUT
10
1kΩ
1µs, ±1V
SQUARE WAVE
INPUT
50Ω
0.1µF
2.2µF
10V
1V
100ns
100%
90%
–V
S
OVERDRIVEN
OUTPUT:
10V/DIV
Figure 34. Overdrive Recovery Test Circuit (PDIP)
INPUT SQUARE
WAVE:
1V/DIV
10%
0%
Figure 33. Overdrive Recovery
Rev. F | Page 11 of 16
AD842
Data Sheet
OUTLINE DIMENSIONS
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
1
8
7
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 35. 14-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-14)
Dimensions Shown in Inches and (Millimeters)
0.098 (2.49) MAX
8
0.005 (0.13) MIN
14
0.310 (7.87)
0.220 (5.59)
1
7
PIN 1
0.100 (2.54) BSC
0.785 (19.94) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
15°
0°
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 36. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Dimensions Shown in Inches and (Millimeters)
Rev. F | Page 12 of 16
Data Sheet
AD842
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 37. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions Shown in Inches and (Millimeters)
ORDERING GUIDE
Model1
Temperature Range
0°C to 70°C
Package Description
Package Option
N-14
AD842JNZ
14-Lead Plastic Dual In-Line Package [PDIP]
AD842JQ
AD842KQ
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
14-Lead Ceramic Dual In-Line Package [CERDIP]
14-Lead Ceramic Dual In-Line Package [CERDIP]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
14-Lead Plastic Dual In-Line Package [PDIP]
Die
Q-14
Q-14
RW-16
RW-16
N-14
AD842JR-16
AD842JRZ-16
AD842KNZ
AD842SCHIPS
AD842SQ
0°C to 70°C
−55°C to +125°C
14-Lead Ceramic Dual In-Line Package [CERDIP]
Q-14
1 Z = RoHS Compliant Part.
Rev. F | Page 13 of 16
AD842
NOTES
Data Sheet
Rev. F | Page 14 of 16
Data Sheet
NOTES
AD842
Rev. F | Page 15 of 16
AD842
NOTES
Data Sheet
©1988–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09477-0-2/14(F)
Rev. F | Page 16 of 16
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