AD8401 [ADI]
8-Bit, 4-Channel Data Acquisition System; 8位， 4通道数据采集系统
| 型号： | AD8401 |
| 厂家： | 
ADI |
| 描述： | 8-Bit, 4-Channel Data Acquisition System |
| 文件： | 总12页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit, 4-Channel Data
Acquisition System
a
AD8401
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
2 s ADC w ith T/ H
4-Channel MUX
A0 A1
V
(+5.0V)
DD
AD899 Com patible
+5 Volt Operation
On-Chip Reference
4 s Voltage Output DAC
Fast Bus Access Tim e—75 ns
V
A
IN
M
U
X
V
V
B
C
D
8-BIT
DAC
IN
8-BIT ADC
V
OUT
T/H
IN
IN
V
1.25 REF
APPLICATIONS
Servo Controls
Digitally Controlled Calibration
Process Control Equipm ent
RS
DAC REG
ADC REG
INT
AD8401
CONTROL LOGIC
BUSY
ST
DGND
AG
AG
ADC
DATA I/O
(8 BITS)
RD CLK CS WR
DAC
GENERAL D ESCRIP TIO N
T he input multiplexer addressing is designed for direct interface
to the AD899 hard-disk drive, read-channel device with no extra
hardware or special software. Analog input range levels are like-
wise compatible with the AD899.
T he AD8401 is a complete data acquisition and control system
containing ADC, DAC, 4-channel MUX, and internal voltage
reference. Built using CBCMOS, this monolithic circuit offers
the user a complete system with very high package density and
reliability.
T he AD8401 is designed to operate from a single +5 volt sup-
ply, which will give an ADC input range of 0 V to 3.0 V, and
DAC output range of 0 V to 2.5 V.
T he converter is a successive approximation ADC with T /H,
and is capable of operating with conversion times as short as
2 µs. Analog input bandwidth is 200 kHz, and DAC output volt-
age settling time is less than 4 µs, making the AD8401 capable
of controlling servo loops with speed and precision.
T he AD8401 is offered in the SOIC-28 surface mount package,
and is guaranteed to operate over the extended industrial tem-
perature range of –40°C to +85°C.
T he 8-bit data interface provides both read and write operation
for parallel bus interfaces to microcontrollers and DSP proces-
sors. An external 5 MHz clock sets the 2 µs conversion rate.
Slower clocks reduce the conversion time and the internal power
dissipation. T he standard control lines: Reset, Busy, Interrupt,
Read and Write complete the handshaking signals for micro-
processor communication. A start trigger ST input allows pre-
cise sampling intervals in synchronous sampling applications.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD8401–SPECIFICATIONS
(@ V = +5.0 V ؎ 5%, AGDAC = AGADC = 0.0 V; fCLK = 5 MHz; –40؇C ≤ T ≤ +85؇C,
DD
A
ADC ELECTRICAL CHARACTERISTICS
unless otherwise noted)
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
ST AT IC PERFORMANCE
Resolution
N
8
Bits
T otal Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Offset Error
T UE
INL
DNL
VOSE
±3
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
–1
–1
–4
–6
–4
–6
+1
+1
+4
+6
+4
+6
1
TA = +25°C
T
A = Full T emp Range
TA = +25°C
A = Full T emp Range
Full-Scale Error
AE
T
∆Full-Scale/∆VDD
TA = +25°C
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
SNR
T HD
IMD
44
48
60
0.1
200
dB
dB
dB
dB
ns
T otal Harmonic Distortion
Intermodulation Distortion
Frequency Response
0 to 200 kHz
T rack/Hold Acquisition T ime
tAQ
ANALOG INPUT S (Applies to Inputs A, B. C, D)
Unipolar Input Range
Input Current
Input Capacitance
VIN
IIN
CIN
0
3
V
µA
pF
–500
+500
10
LOGIC INPUT S
Clock Input Current Low
Clock Input Current High
Input Leakage Current
ICKL
ICKH
IL
VIN = 0 V
VIN = VDD
CS, RD, RS, ST
1.6
4.0
mA
µA
µA
40
10
LOGIC OUT PUT S (Applies to Outputs DB0–DB7, INT, BUSY)
Logic Output Low Voltage
Logic Output High Voltage
Output Leakage Current
Output Capacitance
VOL
VOH
IOZ
IOL = 1.6 mA
IOH = 200 µA
CS = 1 (Except INT & BUSY)
CS = 1 (Except INT & BUSY)
0.4
V
V
µA
pF
10
10
COZ
CONVERSION T IME
tC
External Clock
2
µs
Specifications subject to change without notice.
Table I. Multiplexer Address Input D ecode
A1
A0
Input Selected
VIN
0
0
1
1
0
1
0
1
A
V
V
INB
INC
VIN
D
–2–
REV. 0
AD8401
DAC = AGADC = 0.0 V; R = 2 k⍀, C = 100 pF
to AG ; –40؇C ≤ T ≤ +85؇C, unless otherwise noted)
DAC A
DAC ELECTRICAL CHARACTERISTICS (@ V = +5.0 V ؎ 5%, AG
DD
L
L
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
ST AT IC PERFORMANCE
Resolution
N
8
Bits
T otal Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Offset Error
T UE
INL
DNL
VOSE
±2
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
–1
–1
–2
–2.5
–3
–4
–0.5
–0.2
+1
+1
+2
+2.5
+3
+4
+0.5
+0.2
TA = +25°C
TA = Full T emp Range
TA = +25°C
TA = Full T emp Range
TA = +25°C
Full-Scale Error
AE
∆Full-Scale/∆VDD
Load Regulation at Full-Scale
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
SNR
T HD
44
48
dB
dB
T otal Harmonic Distortion
ANALOG OUT PUT
Output Voltage Range
OVR
0
+2.5
0.8
V
LOGIC INPUT S (Applies to DB0–DB7, CS, WR, RD, RS)
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
VIL
VIH
IL
V
V
µA
pF
2.4
–10
10
10
CIL
AC CHARACT ERIST ICS
Voltage Output Settling T ime
Positive Full-Scale Change
Negative Full-Scale Change
DAC Glitch Impulse
tS
tPOS
tNEG
T o ±1/2 LSB of Final Value
10% to 90%
90% to 10%
2
1
2
15
1
4
2
4
µs
µs
µs
nV s
nV s
dB
Digital Feedthrough
VIN to VOUT Isolation
f = 50 kHz
No Load
60
POWER REQUIREMENT S
Positive Supply Current
IDD
13
mA
Specifications subject to change without notice.
REV. 0
–3–
AD8401
(@ V = +5.0 V ؎ 5%, AG = AG = 0.0 V; fCLK = 5 MHz; –40؇C ≤ T ≤ +85؇C,
DD
DAC
ADC
A
TIMING ELECTRICAL SPECIFICATIONS
unless otherwise noted)
P aram eters1, 2, 3
Sym bol
Condition
Min
Typ
Max
Units
DAC T IMING (See Figure 8 T iming Diagram)
WR Pulse Width
t1
t2
t3
t4
t5
50
0
0
60
0
ns
ns
ns
ns
ns
CS to WR Setup T ime
CS to WR Hold T ime
Data Setup T ime
Data Hold T ime
ADC T IMING (See Figures 6 and 7 T iming Diagrams)
ST Pulse Width
t6
t7
t8
t9
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ST to BUSY Delay
BUSY to INT Delay
BUSY to CS Delay
110
30
0
0
CS to RD Setup T ime
t10
t11
t12
t13
t13
t14
t15
t16
t17
t17
RD Pulse Width4
75
0
10
10
10
CS to RD Hold T ime
Data Access after RD
Data Access after RD
Bus Relinquish after RD
RD to INT Delay
RD to BUSY Delay
Data Valid after BUSY
Data Valid after BUSY
CL = 20 pF
CL = 100 pF
75
135
70
85
110
90
CL = 20 pF
CL = 100 pF
135
NOT ES
1All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2t13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.
3t14 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.
4t15 is determined by t13
.
+5V
+5V
3kΩ
3kΩ
DBN
DBN
3kΩ
DBN
DBN
CL
CL
10pF
10pF
3kΩ
DGND
DGND
DGND
DGND
b. VOL to High Z
b. High Z to VOL
a. VOH to High Z
a. High Z to VOH
Figure 2. Load Circuits for Bus Relinquish Tim e Test
Figure 1. Load Circuits for Data Access Tim e Test
ABSO LUTE MAXIMUM RATINGS*
Supply Voltage (VDD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V
Input Voltages . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Package Power Dissipation . . . . . . . . . . . . . . (T J max–TA)/θJA
T hermal Resistance θJA
28-Lead SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . 53°C/W
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Operating T emperature Range . . . . . . . . . . . . –40°C to +85°C
Junction T emperature Range (TJ max) . . . . –65°C to +150°C
Lead T emperature Range (Soldering, 60 sec) . . . . . . +300°C
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model*
AD8401AR
–40°C to +85°C 28-Lead SOIC SOL-28
AD8401Chips +25°C
Die
*T he AD8401 contains 1257 transistors.
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8401 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–4–
AD8401
P IN CO NFIGURATIO N
D ICE CH ARACTERISTICS
1
A0
1
2
28
27
26
25
24
23
22
21
20
V
DD
27
26
25
28
3
2
V
IN
A
AG
V
DAC
3
4
5
6
7
8
9
V
IN
V
IN
V
IN
B
C
D
OUT
NC
24
23
A1
RS
AG
ADC
DB7
CLK
INT
AD8401AR
Top View
(Not to Scale)
22
21
5
DB6
DB5
BUSY
ST
6
10
11
12
13
14
19
18
17
16
DB4
DB3
7
8
9
RD
20
DB2
CS
19
18
DGND
DB1
WR
DB0
15
10
11 12 13 14 15 16 17
Die Size 91 X 121 mil = 11,011 sq mil
NC = NO CONNECT
P IN D ESCRIP TIO NS
P in#
Nam e
D escription
Positive Supply. Nominal value +5 volts. T his pad requires 2 bonds for die assembly.
1
VDD
T he substrate is common with VDD
.
2
3
4
5
6
AGDAC
VOUT
Analog Ground for the DAC. T here is a separate analog ground for the ADC.
Voltage Output from the DAC.
NC
No Connect.
A1
Address Input that controls multiplexer. See T able I for address decode.
RESET (RS)
Active Low Digital Input that clears the DAC register to zero, setting the DAC to mini-
mum scale. It also asynchronously clears the INT line of the ADC.
7–12, 14, 15
DB7 to DB0
Digital I/O Lines. DB7 (7) is the Most Significant Bit (MSB), for both the ADC and
the DAC, and DB0 (15) is the Least Significant Bit (LSB).
13
16
17
18
DGND
WR
Digital Ground.
Rising Edge T riggered Write Input. Used to load data into the DAC register.
Chip Select. Active Low Input
CS
RD
Active Low Read Input. When this input is active, ADC data can be read from the
part. RD going low starts the ADC conversion.
19
ST
Falling Edge T riggered Start Input. Used for applications requiring precise sample tim-
ing. T he falling edge of ST starts the conversion and sets the BUSY low. T he ST is not
gated by CS.
20
21
BUSY
INT
ADC Active Low, Status Output. When the ADC is performing a conversion, the
BUSY output is low.
Active Low Output. T he Interrupt output notifies the system that the ADC has com-
pleted its conversion. INT goes high on the rising edge of CS or RD. It will also be
forced high when RESET is asserted.
22
CLK
External Clock Input Pin. Accepts a T T L or 5 V CMOS input logic levels.
Analog ADC Ground
23
AGADC
VINA, B, C, D
A0
27–24
28
Four Analog Inputs
Address input that controls multiplexer. See T able I for address decode.
REV. 0
–5–
AD8401
O P ERATIO N
Figure 4 shows the wave forms for a conversion cycle. T he track
and hold begins holding the input voltage VIN approximately
50 ns after the falling edge of the Start command. T he MSB de-
cision is made approximately 50 ns after the second falling edge
of the CLK. If tX is greater than 50 ns, then the falling edge of
the CLK will be seen as the first falling clock edge. If tX is less
than 50 ns, the first MSB conversion will not occur until one
clock cycle later. T he following bits will each be converted in a
similar manner 50 ns after each CLK edge until all eight bits
have been converted. After the end of conversion the contents of
the ADC SAR register are transferred to the output data latch,
the track and hold is returned to the track mode, INT goes low
and the SAR is reset.
T he AD8401 is a complete data acquisition and control system.
It contains the DAC, a four channel input multiplexer, a track/
hold, an ADC, as well as an internal bandgap reference. It inter-
faces to the microcontroller via an 8-bit digital I/O port.
D /A CO NVERTER SECTIO N
T he DAC is an 8-bit voltage mode DAC with an output that
swings from AGDAC to the 1.25 volt bandgap voltage. It uses an
R-2R ladder fed by PNP current sources which allow the output
to swing to ground so that the DAC operates in a unipolar mode.
AMP LIFIER SECTIO N
T he DAC’s output is buffered by an internal high speed op
amp. T he op amps output range is set at 0 V to 2.5 V. T he op
amp has a 500 ns typical settling time to 0.2% for positive
slewing signals. T here are differences in settling time for nega-
tive slewing signals. Signals going to zero volts will settle slightly
slower to ground than is seen in the positive direction.
CS , RD
OR ST
BUSY
100ns
TYP
50ns TYP
V
IN
50ns TYP
V
DD
CLK
t
x
LSB DECISION
DB0
MSB DECISION
DB7
20Ω
V
OUT
20Ω
Figure 4. Operating Waveform s Using the External Clock
n-CH
ANALO G INP UT
T he analog inputs of the AD8401 are fed into resistor voltage
divider networks with a typical value of 8.5 kΩ. T he amplifiers
driving these inputs must have an output resistance low enough
to drive these nodes without losing accuracy. T aps from the
voltage dividers are connected to the track and hold amplifier by
the multiplexer switches.
AG
DAC
Figure 3. Equivalent Am plifier Output Stage
Current sinking capability is also limited near zero volts in single
supply operation. Figure 3 provides an equivalent amplifier out-
put stage schematic.
INTERNAL REFERENCE
5kΩ
An on-chip bandgap is provided as a voltage reference to both
the DAC and the ADC. T his reference is internal to the
AD8401 and is not accessible to the user. It is laser trimmed for
both absolute accuracy and temperature coefficients. T he refer-
ence is internally buffered by a separate control amplifier for both
the DAC and ADC to improve isolation between the converters.
V
A
IN
3.57kΩ
MUX
T/H
V
D
IN
5kΩ
3.57kΩ
AGADC
D IGITAL I/O
T he 8-bit parallel data I/O port on the AD8401 provides access
to both the DAC and the ADC. T his port is T T L/CMOS com-
patible with three-state outputs that are ESD protected.
Figure 5. Equivalent Analog Input Circuit
TRACK-AND -H O LD AMP LIFIER
T he data format is binary. T his data coding applies to both the
DAC and the ADC. See the applications information section.
Following the resistive divider at the input of the AD8401 is a
track-and-hold amplifier that captures input signals accurately
up to the 200 kHz Nyquist frequency of the ADC. T o attain this
performance the T /H amplifier must have a much greater band-
width than the signal of interest. Because of this the user must
be careful to band limit the input signal to avoid aliasing high
frequency components and noise into the passband.
AD C SECTIO N
A fast successive approximation ADC is used to attain a conver-
sion time of 2 microseconds. Start of conversion is initiated by
CS and RD. Following a Start command the BUSY signal will
become active and another Start command should not be given
until the conversion is complete.
T he track-and-hold amplifier is internally controlled by the Start
command and is not directly available to the user. After the
Start command signal the track-and-hold is placed into the hold
mode; it returns to the track mode after the conversion is
complete.
T he RESET (RS) input does not affect A/D conversion, but the
INT (Interrupt or conversion complete) which normally goes
active low at the end of a conversion will be forced high by
RESET asynchronously.
REV. 0
–6–
AD8401
CLO CK
t9
T he AD8401 uses an external clock that is T T L or 5 V CMOS
compatible. T he external clock speed is 5 MHz and the duty
cycle may vary from 30% to 70%. T he external clock can be
continuously operated between conversions.
CS
RD
t10
t12
t11
t16
D IGITAL INTERFACE: AD C TIMING AND CO NTRO L
T wo basic ADC operating modes are available with the
AD8401. T he first mode uses the Start (ST) pin to trigger a
synchronized A/D conversion. As soon as the ST pin is asserted,
the T /H switches from tracking to the hold mode capturing the
present analog input-voltage sample. With the T /H holding the
analog sample the successive-approximation analog-to-digital
conversion is completed on that sample value. At the end of
conversion the T /H returns to the tracking mode. T his mode of
conversion is ideal for digital signal processing applications
where precise interval sampling is necessary to minimize errors
due to sampling uncertainty or jitter. A precise clock source can
be used to drive the ST input.
BUSY
t15
t8
INT
t13
t17
t14
DATA
OLD DATA
NEW DATA
HIGH Z
Figure 7. Mode 2, ADC Interface Tim ing
Mode 2 Inter face
T his interface mode can be used with microprocessors that can
be put into a WAIT state for at least 2 microseconds. T he ST
pin must be tied to logic high for proper operation. T he micro-
processor begins a conversion by executing a READ instruction
that asserts the CS and RD pins at the AD8401’s decoded ad-
dress. T he AD8401 BUSY output then goes low, forcing the
microprocessor’s READY (or WAIT ) line into a WAIT state.
T he analog input signal is captured by the T /H on the falling
edge of RD. When the conversion is complete (8 clocks later),
the BUSY line returns high, and then the µP completes its
READ of the new data now on the digital output port of the
AD8401. Note that while conversion is in progress the ADC
places the results from the last conversion (Old Data) on the
data bus. T he Figure 7 timing diagram details the applicable
timing specification requirements.
T he second mode of conversion is started by the RD and CS in-
puts going low, after which the BUSY line puts the micropro-
cessor into a WAIT state until end of conversion. Mode 2 is
asserted by connecting the ST pin to logic high. T he major ad-
vantage of this interface is that a single Read Instruction will
start and complete a new analog-to-digital conversion without
the need for carefully tailored software delays that often are not
portable when software routines are taken to a different proces-
sor running at a different clock speed.
t6
ST
t7
D IGITAL INTERFACE: D AC TIMING AND CO NTRO L
T able II shows the truth table for DAC operation. T he internal
8-bit DAC register contents are loaded from the data bus when
both WR and CS are asserted. T he DAC register determines the
D/A converter analog-output voltage. T he WR input is a posi-
tive edge triggered input that loads the bus data into the DAC
register subject to the data setup and data hold timing require-
ments. When CS and WR are low, the DAC register contents
will not change with changing data bus values. Figure 8 provides
the detail timing diagram for write cycle operation.
tCONVERT
BUSY
t8
INT
t9
t15
CS
t10
t12
t11
RD
t14
t13
Table II. D AC Register Logic
DATA
HIGH Z
DATA VALID
CS
WR
RS
D AC Function
Figure 6. Mode 1, ADC Interface Tim ing
Mode 1 Inter face
H
L
L
ٙ
X
H
L
ٙ
L
H
H
H
H
L
No Effect
No Effect
DAC Register Updated
DAC Register Updated
DAC Register Loaded with all Zeros
As shown in Figure 6, the falling edge of the ST pulse initiates a
conversion and puts the T /H amplifier into the hold mode. T he
BUSY signal goes low during the whole A/D conversion time
and returns high signaling end of conversion. T he INT line can
be used to interrupt the microprocessor. When the microproces-
sor performs a READ to access the AD8401 data, the rising
edges of CS or RD will reset the INT output to high after the t15
timing specification. INT can also be used to externally trigger a
pulse that activates the CS and RD and places the new data into
a buffer or First In First Out FIFO memory. T he microproces-
sor can then load a series of readings from this buffer memory at
a convenient time. Care must be taken not to have the ST input
high when RD is brought low; otherwise, the AD8401 will not
operate properly. Also triggering the ST line a second time be-
fore conversion is complete will cause erroneous readings.
X
CS
t2
t3
t1
WR
t4
VALID DATA
t5
DATA
Figure 8. Write Cycle Tim ing
REV. 0
–7–
AD8401
An active low pulse, at any time, on the RESET pin asynchro-
nously forces all DAC register bits to zero. T he DAC output
voltage becomes zero volts and stays at that value until a new
data word is loaded into the DAC register with a new WR com-
mand. T he equivalent input logic for the DAC register loading
is shown in Figure 9.
TO DAC LADDER
CS
D0 D7
WR
DAC REGISTER
RESET
INPUT DATA
Figure 9. Equivalent DAC Register Control Logic
TYP ICAL P ERFO RMANCE CH ARACTERISTICS
1.0
120
SS = 300 UNITS
T
= +25°C
A
110
100
90
80
70
60
50
40
30
20
10
0
V
= +5V
DD
T
= +25°C
A
0.5
0
–0.5
–0.1
0
64
128
192
256
–4.5 –3.5 –2.5 –1.5 –0.5
0.5
1.5
2.5
3.5
4.5
FULL SCALE ERROR – LSB
DIGITAL INPUT CODE – DECIMAL
Figure 12. ADC Full-Scale Error Histogram
Figure 10. ADC Linearity Error vs. Digital Code
1.0
2.5
2.0
V
= +5V
DD
V
= +5V
DD
T
= +25°C
A
1.5
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–0.5
–2.0
–2.5
–0.1
–3.0
0
64
128
192
256
–50
–25
0
25
50
75
100
DIGITAL INPUT CODE – DECIMAL
TEMPERATURE – °C
Figure 11. DAC Linearity Error vs. Digital Code
Figure 13. ADC Full-Scale Error vs. Tem perature
REV. 0
–8–
AD8401
240
220
200
180
160
140
120
100
80
TA = +25°C
V
= +5V
DD
2.5
2.0
1.5
1.0
SS = 300 UNITS
T
= +25°C
A
R
TO GND
L
60
R
TO V
DD
L
40
0.5
0
20
0
–4
–3
–2
–1
0
1
2
3
4
10
100
1k
LOAD RESISTANCE – Ω
10k
100k
FULL SCALE ERROR – LSB
Figure 14. DAC Full-Scale Error Histogram
Figure 17. DAC Output Swing vs. Load Resistance
3.0
2.5
V
= +5V
DD
3
2.0
1.5
5V
2
100
90
1.0
1
VOUT
x +3σ
0
0.5
0
5V
5V
0
WR
x
–0.5
–1.0
0
10
5V
0%
DATA
x – 3σ
–1.5
–2.0
0
1V
5V
1µS
TIME – 1µs/DIV
–2.5
–50
–25
0
25
50
75
100
Figure 18. DAC Output Slew Rate Positive Transition
TEMPERATURE – °C
Figure 15. DAC Full-Scale Error vs. Tem perature
4
5V
VDD = +5V
SS = 135 UNITS
3
3
2
100
V
90
OUT
2
1
0
1
x +3σ
0
5V
0
5V
0
WR
x
–1
10
0%
DATA
x – 3σ
0
–2
1V
5V
1µS
–3
–4
–5
TIME – 1µs/DIV
Figure 19. DAC Output Slew Rate Negative Transition
0
100
200
300
400
500
BURN-IN TIME @ 150°C – HOURS
Figure 16. DAC Full-Scale Out Change vs Tim e
Accelerated by Burn-In
REV. 0
–9–
AD8401
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
500mV
V
= +2.4V
IN
100
90
VDD = +5V
TA = +25°C
CL = 1000pF
V
= +5.25V
DD
10
0%
20µS
V
= +4.75V
DD
TIME – 20µs /DIV
Figure 20. DAC Output Swing with Capacitive Load
–50
–25
0
25
50
75
100
TEMPERATURE – °C
Figure 21. Supply Current vs. Tem perature
T
= +25°C
A
60
40
20
0
OUTPUT = FULL SCALE
V
= 5V ± 200mV
DD
1k
10k
100k
1M
FREQUENCY – Hz
Figure 22. Power Supply Rejection Ratio vs. Frequency
REV. 0
–10–
AD8401
AP P LICATIO NS INFO RMATIO N
T he software programming needs to format data as defined by
the transfer equations and Code T ables that follow.
T he nominal output voltages listed in the Code T able are sub-
ject to the static performance specifications. T he INL, Zero-
Scale and Full-Scale errors describe the total specified variation
that will be encountered from part to part. One LSB of error for
the 2.5 V FS range is 9.766 millivolts (= 2.50/256).
D AC Tr ansfer Equation
Although separate AGNDs exist for both the DAC and ADC to
minimize crosstalk, writing data to the DAC while the ADC is
performing a conversion may result in an incorrect conversion
from the ADC due to signal interaction between the DAC and
ADC. T herefore, to ensure correct operation of the ADC, the
DAC register should not be updated while the ADC is converting.
D
256
255
256
VOUT = 2.500 ×
= 2.500 ×
for a 2.50 V full scale
where D is the decimal value 0 through 255 of the 8-bit data
word.
T he AD8401 is configured for an input range of +3.0 volts Full
Scale. T he nominal transfer characteristic for this range is plot-
ted in Figure 23. T he output coding is natural binary with one
LSB equal to 11.72 millivolts. Note that the first code transition
between 0 LSB and 1 LSB occurs at 5.8 mV, one half of the
11.72 mV LSB step size. T he last code transition occurs at Full
Scale minus 1.5 LSBs, which is a 2.982 V input.
Table III. D AC Unipolar Code
Nom inal
Analog
D AC Register Contents
General Transfer
Equation
D ecim al
Binary
O utput VO UT
T he AD8401 is easily interfaced to most microprocessors by us-
ing either address bits or address decode to select the appropri-
ate multiplexer channel. Figure 24 shows how easily the AD8401
interfaces to the AD899. No additional hardware is required.
255
2.500 ×
256
255
1111 1111
2.490 V
129
2.500 ×
256
129
128
127
1
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
1.260 V
1.250 V
1.240 V
0.010 V
0.000 V
OUTPUT
CODE
128
2.500 ×
256
FULL SCALE
TRANSITION
127
2.500 ×
256
11111111
11111110
11111101
1
2.500 ×
256
0
2.500 ×
256
0
1LSB = FS
256
00000011
00000010
FS – 1LSB
00000001
00000000
1
2
3
FS
VIN INPUT VOLTAGE – LSBs
Figure 23. ADC 0 V to +3 V Input Transfer Characteristic
REV. 0
–11–
AD8401
ADDRESS BUS
VDD (+5.0V)
A1
A0
A1 A0
1.25V REF
AD8401
VIN
VIN
VIN
VIN
A
A
B
C
D
B
C
D
T/H
8-BIT ADC
VOUT
8-BIT DAC
AD899
RESET
INT
DAC REG
CONTROL LOGIC
ADC REG
BUSY
DGND
DATA I/O AGDAC
(8 BITS)
AGADC
Figure 24. AD8401 Interface to the AD899 Read-Channel Hard Disk Drive Circuit
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-Lead Wide-Body SO
(SO L-28)
0.7125 (18.10)
0.6969 (17.70)
28
15
1
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
REV. 0
–12–
相关型号：
AD8402AN10
DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDIP14, PLASTIC, MS-001, DIP-14
ROCHESTER
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