AD8402AN1 [ADI]
1-/2-/4-Channel Digital Potentiometers; 单/双/四通道数字电位器
| 型号： | AD8402AN1 |
| 厂家： | 
ADI |
| 描述： | 1-/2-/4-Channel Digital Potentiometers |
| 文件： | 总20页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1-/2-/4-Channel
Digital Potentiometers
a
AD8400/AD8402/AD8403
FEATURES
FUNCTIONAL BLOCK DIAGRAM
256 Position
Replaces 1, 2 or 4 Potentiometers
1 k⍀, 10 k⍀, 50 k⍀, 100 k⍀
Power Shut Down—Less than 5 A
3-Wire SPI Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single-Supply Operation
Midscale Preset
RDAC1
8
A1
W1
B1
8-BIT
LATCH
AD8403
V
DD
CK
SHDN
RS
AGND1
DGND
1
2
3
4
DAC
SELECT
RDAC2
8
A2
8-BIT
LATCH
W2
B2
A1, A0
2
CK
RS
SHDN
AGND2
APPLICATIONS
RDAC3
8
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
A3
8
8
10-BIT
SERIAL
LATCH
8-BIT
LATCH
W3
B3
CK
SHDN
RS
AGND3
D
SDI
CLK
CS
CK
Q
RS
RDAC4
A4
8-BIT
LATCH
W4
B4
GENERAL DESCRIPTION
CK
SHDN
SHDN
RS
AGND4
The AD8400/AD8402/AD8403 provide a single, dual or quad
channel, 256 position digitally controlled variable resistor (VR)
device. These devices perform the same electronic adjustment
function as a potentiometer or variable resistor. The AD8400
contains a single variable resistor in the compact SO-8 package.
The AD8402 contains two independent variable resistors in
space saving SO-14 surface mount package. The AD8403 con-
tains four independent variable resistors in 24-lead PDIP, SOIC
and TSSOP packages. Each part contains a fixed resistor with a
wiper contact that taps the fixed resistor value at a point deter-
mined by a digital code loaded into the controlling serial input
register. The resistance between the wiper and either endpoint
of the fixed resistor varies linearly with respect to the digital
code transferred into the VR latch. Each variable resistor offers
a completely programmable value of resistance, between the A
terminal and the wiper or the B terminal and the wiper. The
fixed A to B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ or 100 kΩ
has a ±1% channel-to-channel matching tolerance with a nominal
temperature coefficient of 500 ppm/°C. A unique switching cir-
cuit minimizes the high glitch inherent in traditional switched
resistor designs avoiding any make-before-break or break-before-
make operation.
SDO
RS
The reset (RS) pin forces the wiper to the midscale position by
loading 80H into the VR latch. The SHDN pin forces the resis-
tor to an end-to-end open circuit condition on the A terminal
and shorts the wiper to the B terminal, achieving a microwatt
power shutdown state. When SHDN is returned to logic high,
the previous latch settings put the wiper in the same resistance
setting prior to shutdown. The digital interface is still active in
shutdown so that code changes can be made which will produce
new wiper positions when the device is taken out of shutdown.
The AD8400 is available in both the SO-8 surface mount and
the 8-lead plastic DIP package.
The AD8402 is available in both surface mount (SO-14) and
the 14-lead plastic DIP package, while the AD8403 is available
in a narrow body 24-lead plastic DIP and the 24-lead surface
mount package. The AD8402/AD8403 are also offered in the
1.1 mm thin TSSOP-14/TSSOP-24 package for PCMCIA ap-
plications. All parts are guaranteed to operate over the extended
industrial temperature range of –40°C to +85°C.
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an SPI
compatible serial-to-parallel shift register that is loaded from a
standard 3-wire serial-input digital interface. Ten data bits make
up the data word clocked into the serial input register. The data
word is decoded where the first two bits determine the address
of the VR latch to be loaded, the last eight bits are data. A serial
data output pin at the opposite end of the serial register allows
simple daisy-chaining in multiple VR applications without addi-
tional external decoding logic.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1997
AD8400/AD8402/AD8403–SPECIFICATIONS
10 k⍀ VERSION
ELECTRICAL CHARACTERISTICS otherwise noted)
(VDD = +3 V ؎ 10% or + 5 V ؎ 10%, VA = +VDD, VB = 0 V, –40؇C ≤ TA ≤ +85؇C unless
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
Resistor Nonlinearity2
Nominal Resistance3
Resistance Tempco
Wiper Resistance
Nominal Resistance Match
R-DNL
R-INL
R
∆RAB/∆T
RW
RWB, VA = NC
RWB, VA = NC
TA = +25°C, Model: AD840XYY10
VAB = VDD, Wiper = No Connect
IW = 1 V/R
–1
–2
8
±1/4
±1/2
10
500
50
+1
+2
12
LSB
LSB
kΩ
ppm/°C
Ω
100
1
∆R/RO
CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C
0.2
%
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
N
INL
8
Bits
Integral Nonlinearity4
Differential Nonlinearity4
–2
–1
–1
–1.5
±1/2
±1/4
±1/4
±1/2
15
+2
+1
+1
+1.5
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
DNL
DNL
DNL
∆VW/∆T
VWFSE
VWZSE
VDD = +5 V
VDD = +3 V
TA = +25°C
TA = –40°C, +85°C
V
DD = +3 V
Voltage Divider Tempco
Full-Scale Error
Zero-Scale Error
Code = 80H
Code = FFH
Code = 00H
–4
0
–2.8
+1.3
0
+2
RESISTOR TERMINALS
Voltage Range5
VA, B, W
CA, B
CW
IA_SD
RW_SD
0
VDD
V
Capacitance6 Ax, Bx
Capacitance6 Wx
f = 1 MHz, Measured to GND, Code = 80H
f = 1 MHz, Measured to GND, Code = 80H
VA = VDD, VB = 0 V, SHDN = 0
75
pF
pF
µA
Ω
120
0.01
100
Shutdown Current7
Shutdown Wiper Resistance
5
200
VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V
DIGITAL INPUTS & OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
VIH
VIL
VIH
VIL
VOH
VOL
IIL
VDD = +5 V
VDD = +5 V
VDD = +3 V
VDD = +3 V
RL = 1 kΩ to VDD
IOL = 1.6 mA, VDD = +5 V
VIN = 0 V or +5 V, VDD = +5 V
2.4
V
V
V
V
V
V
µA
pF
0.8
0.6
2.1
Output Logic High
Output Logic Low
Input Current
VDD–0.1
0.4
±1
Input Capacitance6
CIL
5
POWER SUPPLIES
Power Supply Range
VDD Range
IDD
IDD
PDISS
PSS
2.7
5.5
5
4
V
Supply Current (CMOS)
Supply Current (TTL)8
Power Dissipation (CMOS)9
Power Supply Sensitivity
VIH = VDD or VIL = 0 V
VIH = 2.4 V or 0.8 V, VDD = +5.5 V
VIH = VDD or VIL = 0 V, VDD = +5.5 V
0.01
0.9
µA
mA
µW
27.5
V
DD = +5 V ± 10%
0.0002 0.001 %/%
PSS
VDD = +3 V ± 10%
0.006 0.03
%/%
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
Total Harmonic Distortion
BW_10K
THDW
tS
eNWB
CT
R = 10 kΩ
600
0.003
2
9
–65
kHz
%
µs
nV/√Hz
dB
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ±1% Error Band
RWB = 5 kΩ, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
V
W Settling Time
Resistor Noise Voltage
Crosstalk11
NOTES FOR 10 kΩ VERSION
1 Typicals represent average readings at +25°C and VDD = +5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
IW = 50 µA for VDD = +3 V and IW = 400 µA for VDD = +5 V for the 10 kΩ versions.
3 VAB = VDD, Wiper (VW) = No Connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I DD versus logic voltage.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All Dynamic Characteristics use VDD = +5 V.
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
REV. B
–2–
SPECIFICATIONS
AD8400/AD8402/AD8403
50 k⍀ & 100 k⍀ VERSION
ELECTRICAL CHARACTERISTICS
(VDD = +3 V ؎ 10% or + 5 V ؎ 10%, VA = +VDD, VB = 0 V, –40؇C ≤ TA ≤ +85؇C unless
otherwise noted)
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
Resistor Nonlinearity2
Nominal Resistance3
R-DNL
R-INL
R
RWB, VA = NC
RWB, VA = NC
TA = +25°C, Model: AD840XYY50
TA = +25°C, Model: AD840XYY100
VAB = VDD, Wiper = No Connect
IW = 1 V/R
–1
–2
35
70
±1/4
±1/2
50
100
500
53
+1
+2
65
LSB
LSB
kΩ
kΩ
ppm/°C
Ω
R
130
Resistance Tempco
Wiper Resistance
Nominal Resistance Match
∆RAB/∆T
RW
100
1
∆R/RO
CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C
0.2
%
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
N
INL
8
Bits
Integral Nonlinearity4
Differential Nonlinearity4
–4
–1
–1
–1.5
±1
+4
+1
+1
+1.5
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
DNL
DNL
DNL
∆VW/∆T
VWFSE
VWZSE
VDD = +5 V
VDD = +3 V
±1/4
±1/4
±1/2
15
–0.25
+0.1
TA = +25°C
TA = –40°C, +85°C
VDD = +3 V
Voltage Divider Tempco
Full-Scale Error
Zero-Scale Error
Code = 80H
Code = FFH
Code = 00H
–1
0
0
+1
RESISTOR TERMINALS
Voltage Range5
VA, B, W
CA, B
CW
IA_SD
RW_SD
0
VDD
V
Capacitance6 Ax, Bx
Capacitance6 Wx
f = 1 MHz, Measured to GND, Code = 80H
f = 1 MHz, Measured to GND, Code = 80H
VA = VDD, VB = 0 V, SHDN = 0
15
80
0.01
100
pF
pF
µA
Ω
Shutdown Current7
Shutdown Wiper Resistance
5
200
VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V
DIGITAL INPUTS & OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
VIH
VIL
VIH
VIL
VOH
VOL
IIL
VDD = +5 V
VDD = +5 V
VDD = +3 V
VDD = +3 V
RL = 1 kΩ to VDD
IOL = 1.6 mA, VDD = +5 V
VIN = 0 V or +5 V, VDD = +5 V
2.4
V
V
V
V
V
V
µA
pF
0.8
0.6
2.1
Output Logic High
Output Logic Low
Input Current
VDD–0.1
0.4
±1
Input Capacitance6
CIL
5
POWER SUPPLIES
Power Supply Range
VDD Range
IDD
IDD
PDISS
PSS
2.7
5.5
5
4
V
Supply Current (CMOS)
Supply Current (TTL)8
Power Dissipation (CMOS)9
Power Supply Sensitivity
VIH = VDD or VIL = 0 V
VIH = 2.4 V or 0.8 V, VDD = +5.5 V
VIH = VDD or VIL = 0 V, VDD = +5.5 V
0.01
0.9
µA
mA
µW
27.5
V
DD = +5 V ± 10%
0.0002 0.001 %/%
PSS
VDD = +3 V ± 10%
0.006 0.03
%/%
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
BW_50K
BW_100K
THDW
tS_50K
tS_100K
R = 50 kΩ
R = 100 kΩ
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ±1% Error Band
VA = VDD, VB = 0 V, ±1% Error Band
RWB = 25 kΩ, f = 1 kHz, RS = 0
125
71
0.003
9
18
20
kHz
kHz
%
µs
µs
nV/√Hz
nV/√Hz
dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
e
NWB_50K
eNWB_100K RWB = 50 kΩ, f = 1 kHz, RS = 0
CT VA = VDD, VB = 0 V
29
–65
Crosstalk11
NOTES FOR 50 kΩ and 100 kΩ VERSIONS
1 Typicals represent average readings at +25°C and VDD = +5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
IW = VDD/R for VDD = +3 V or +5 V for the 50 kΩ and 100 kΩ versions.
3 VAB = VDD, Wiper (VW) = No Connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I DD versus logic voltage.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All Dynamic Characteristics use VDD = +5 V.
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
REV. B
–3–
AD8400/AD8402/AD8403–SPECIFICATIONS
1 k⍀ VERSION
ELECTRICAL CHARACTERISTICS otherwise noted)
(VDD = +3 V ؎ 10% or + 5 V ؎ 10%, VA = +VDD, VB = 0 V, –40؇C ≤ TA ≤ +85؇C unless
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
Resistor Nonlinearity2
Nominal Resistance3
Resistance Tempco
Wiper Resistance
Nominal Resistance Match
R-DNL
R-INL
R
∆RAB/∆T
RW
RWB, VA = NC
RWB, VA = NC
TA = +25°C, Model: AD840XYY1
VAB = VDD, Wiper = No Connect
IW = 1 V/RAB
–5
–4
0.8
–1
+3
+4
1.5
LSB
LSB
kΩ
ppm/°C
Ω
±1.5
1.2
700
53
100
2
∆R/RO
CH 1 to 2, VAB = VDD, TA = +25°C
0.75
%
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
N
8
Bits
Integral Nonlinearity4
Differential Nonlinearity4
INL
DNL
DNL
–6
–4
–5
±2
–1.5
–2
25
–12
6
+6
+2
+5
LSB
LSB
LSB
ppm/°C
LSB
LSB
VDD = +5 V
VDD = +3 V, TA = +25°C
Code = 80H
Code = FFH
Code = 00H
Voltage Divider Temperature Coefficent ∆VW/∆T
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
–20
0
0
10
RESISTOR TERMINALS
Voltage Range5
VA, B, W
CA, B
CW
IDD_SD
RW_SD
0
VDD
V
Capacitance6 Ax, Bx
Capacitance6 Wx
f = 1 MHz, Measured to GND, Code = 80H
f = 1 MHz, Measured to GND, Code = 80H
VA = VDD, VB = 0 V, SHDN = 0
75
pF
pF
µA
Ω
120
0.01
50
Shutdown Supply Current7
Shutdown Wiper Resistance
5
100
VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V
DIGITAL INPUTS & OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
VIH
VIL
VIH
VIL
VOH
VOL
IIL
VDD = +5 V
VDD = +5 V
VDD = +3 V
VDD = +3 V
RL = 1 kΩ to VDD
IOL = 1.6 mA, VDD = +5 V
VIN = 0 V or +5 V, VDD = +5 V
2.4
V
V
V
V
V
V
µA
pF
0.8
0.6
2.1
Output Logic High
Output Logic Low
Input Current
VDD–0.1
0.4
±1
Input Capacitance6
CIL
5
POWER SUPPLIES
Power Supply Range
VDD Range
IDD
IDD
PDISS
PSS
2.7
5.5
5
4
V
Supply Current (CMOS)
Supply Current (TTL)8
Power Dissipation (CMOS)9
Power Supply Sensitivity
VIH = VDD or VIL = 0 V
0.01
0.9
µA
mA
µW
VIH = 2.4 V or 0.8 V, VDD = +5.5 V
VIH = VDD or VIL = 0 V, VDD = +5.5 V
∆VDD = +5 V ± 10%
27.5
0.0035 0.008 %/%
PSS
∆VDD = +3 V ± 10%
0.05
0.13
%/%
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
Total Harmonic Distortion
BW_1K
THDW
tS
eNWB
CT
R = 1 kΩ
5,000
0.015
0.5
3
–65
kHz
%
µs
nV/√Hz
dB
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ±1% Error Band
RWB = 500 Ω, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
V
W Settling Time
Resistor Noise Voltage
Crosstalk11
NOTES FOR 1 kΩ VERSION
1 Typicals represent average readings at +25°C and VDD = +5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See Figure 30 test circuit.
IW = 500 µA for VDD = +3 V and IW = 4 mA for VDD = +5 V for 1 kΩ version.
3 VAB = VDD, Wiper (VW) = No Connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL Specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I DD versus logic voltage.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All Dynamic Characteristics use VDD = +5 V.
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Specifications subject to change without notice.
REV. B
–4–
AD8400/AD8402/AD8403–SPECIFICATIONS
All VERSIONS
(VDD = +3 V ؎ 10% or + 5 V ؎ 10%, VA = +VDD, VB = 0 V, –40؇C ≤ TA ≤ +85؇C unless
otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
SWITCHING CHARACTERISTICS2, 3
Input Clock Pulse Width
Data Setup Time
tCH, tCL
tDS
tDH
Clock Level High or Low
10
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold Time
CLK to SDO Propagation Delay4
CS Setup Time
tPD
RL = 1 kΩ to +5 V, CL ≤ 20 pF
1
25
tCSS
tCSW
tRS
tCSH
tCS1
10
10
50
0
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
10
NOTES
1Typicals represent average readings at +25°C and VDD = +5 V.
2Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
3See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using VDD = +3 V or +5 V. To avoid false clocking a minimum input logic slew rate of 1 V/µs should be maintained.
4Propagation Delay depends on value of VDD, RL and CL–see applications text.
Specifications subject to change without notice.
tRS
1
1
0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDI
RS
0
1
tS
CLK
V
DD
0
V
±1%
OUT
V
/2
DAC REGISTER LOAD
DD
±1% ERROR BAND
1
0
CS
V
DD
Figure 1c. Reset Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
V
OUT
0V
(T = +25°C, unless otherwise noted)
Figure 1a. Timing Diagram
A
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
AX–BX, AX–WX, BX–WX . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ max) . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA
Thermal Resistance (θJA)
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +83°C/W
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +63°C/W
SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . +70°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . +120°C/W
TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . +180°C/W
TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . +143°C/W
1
0
SDI
(DATA IN)
Ax OR Dx
Ax OR Dx
tDS
tDH
1
0
SDO
(DATA OUT)
A'x OR D'x
tPD_MIN
A'x OR D'x
tPD_MAX
tCS1
tCH
1
0
1
0
CLK
tCL
tCSS
tCSH
tCSW
tS
CS
V
DD
±1 %
V
OUT
0V
±1 % ERROR BAND
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 1b. Detail Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8400/AD8402/AD8403 feature proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
AD8400/AD8402/AD8403
ORDERING GUIDE
Table I. Serial Data Word Format
#CHs/
k⍀
Temperature
Range
Package
Description Option*
Package
ADDR
B9
DATA
Model
B8
B7 B6 B5 B4 B3 B2 B1 B0
AD8400AN10
AD8400AR10
AD8402AN10
AD8402AR10
AD8402ARU10
AD8403AN10
AD8403AR10
AD8403ARU10
X1/10
X1/10
X2/10
X2/10
X2/10
X4/10
X4/10
X4/10
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PDIP-8
SO-8
PDIP-14
SO-14
TSSOP-14 RU-14
PDIP-24
SOIC-24
N-8
A1
A0
D7 D6 D5 D4 D3 D2 D1 D0
SO-8
N-14
SO-14
MSB
LSB MSB
LSB
29
28 27
20
N-24
SOL-24
PIN CONFIGURATIONS
TSSOP-24 RU-24
A1
8
AD8400AN50
AD8400AR50
AD8402AN50
AD8402AR50
AD8403AN50
AD8403AR50
X1/50
X1/50
X2/50
X2/50
X4/50
X4/50
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PDIP-8
SO-8
PDIP-14
SO-14
PDIP-24
SOIC-24
N-8
1
2
3
4
B1
SO-8
N-14
SO-14
N-24
SOL-24
AD8400
TOP VIEW
(Not to Scale)
7
6
5
GND
W1
V
CS
DD
SDI
CLK
AD8400AN100
AD8400AR100
AD8402AN100
AD8402AR100
AD8402ARU100 X2/100
AD8403AN100
AD8403AR100
X1/100
X1/100
X2/100
X2/100
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PDIP-8
SO-8
PDIP-14
SO-14
TSSOP-14 RU-14
PDIP-24
SOIC-24
N-8
B1
A1
W1
14
13
12
11
10
9
1
2
3
4
5
6
7
AGND
B2
SO-8
N-14
SO-14
A2
AD8402
TOP VIEW
(Not to Scale)
V
W2
DD
X4/100
X4/100
N-24
SOL-24
DGND
SHDN
CS
RS
CLK
SDI
AD8403ARU100 X4/100
TSSOP-24 RU-24
8
AD8400AN1
AD8400AR1
AD8402AN1
AD8402AR1
AD8403AN1
AD8403AR1
AD8403ARU1
X1/1
X1/1
X2/1
X2/1
X4/1
X4/1
X4/1
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PDIP-8
SO-8
PDIP-14
SO-14
PDIP-24
SOIC-24
TSSOP-24 RU-24
N-8
SO-8
N-14
SO-14
N-24
SOL-24
AGND2
B2
1
2
24
23
B1
A1
A2
3
22 W1
4
W2
AGND4
B4
21 AGND1
5
20
19
18
17
16
B3
AD8403
TOP VIEW
(Not to Scale)
6
A3
*N = Plastic DIP; SO = Small Outline; RU = Thin Shrink SO.
The AD8400, AD8402 and the AD8403 contain 720 transistors.
A4
7
W3
W4
8
AGND3
DGND
SHDN
9
V
DD
10
11
12
15 RS
14
CS
CLK
13 SDO
SDI
–6–
REV. B
AD8400/AD8402/AD8403
AD8400 PIN DESCRIPTIONS
Description
AD8403 PIN DESCRIPTIONS
Pin
Name
Pin
Name
Description
1
2
3
B1
Terminal B RDAC
Ground
1
2
AGND2 Analog Ground #2*
GND
CS
B2
A2
W2
Terminal B RDAC #2
Terminal A RDAC #2
Wiper RDAC #2, addr = 012
Chip Select Input, Active Low. When CS
returns high data in the serial input register is
loaded into the DAC register.
3
4
5
AGND4 Analog Ground #4*
4
5
6
SDI
CLK
VDD
Serial Data Input
6
B4
Terminal B RDAC #4
Terminal A RDAC #4
Wiper RDAC #4, addr = 112
Digital Ground*
Serial Clock Input, positive edge triggered
7
A4
Positive power supply, specified for operation
at both +3 V and +5 V.
8
W4
9
DGND
SHDN
7
8
W1
A1
Wiper RDAC, addr = 002
Terminal A RDAC
10
Active Low Input. Terminal A open circuit.
Shutdown controls variable resistors #1
through #4
11
CS
Chip Select Input, Active Low. When CS
returns high data in the serial input register
is decoded based on the address bits and
loaded into the target DAC register.
AD8402 PIN DESCRIPTIONS
Description
Pin Name
1
2
3
4
5
6
AGND
B2
Analog Ground*
12
13
SDI
Serial Data Input
Terminal B RDAC #2
Terminal A RDAC #2
Wiper RDAC #2, Addr = 012
Digital Ground*
SDO
Serial Data Output, Open Drain transistor
requires pull-up resistor
A2
14
15
CLK
Serial Clock Input, positive edge triggered
W2
RS
Active low reset to midscale; sets RDAC
registers to 80H
DGND
SHDN
Terminal A open circuit. Shutdown controls
Variable Resistors #1 and #2
16
VDD
Positive power supply, specified for
operation at both +3 V and +5 V
7
CS
Chip Select Input, Active Low. When CS
returns high data in the serial input register is
decoded based on the address bits and loaded
into the target DAC register.
17
18
19
20
21
22
23
24
AGND3 Analog Ground #3*
W3
A3
B3
Wiper RDAC #3, addr = 102
Terminal A RDAC #3
Terminal B RDAC #3
8
9
SDI
CLK
RS
Serial Data Input
Serial Clock Input, positive edge triggered
AGND1 Analog Ground #1*
10
Active low reset to midscale; sets RDAC
registers to 80H
W1
A1
B1
Wiper RDAC #1, addr = 002
Terminal A RDAC #1
Terminal B RDAC #1
11
VDD
Positive power supply, specified for operation
at both +3 V and +5 V
*All AGNDs must be connected to DGND.
12
13
14
W1
A1
B1
Wiper RDAC #1, addr = 002
Terminal A RDAC #1
Terminal B RDAC #1
*All AGNDs must be connected to DGND.
–7–
REV. B
AD8400/AD8402/AD8403–Typical Performance Characteristics
10
5
4
3
60
48
36
24
12
0
80
SS = 184 UNITS
V
= +3V OR +5V
H
DD
FF
V
= 4.5V
H
DD
= +25°C
T
8
A
40
H
20
H
6
CODE = 10
H
4
2
1
0
2
R
R
WA
05
T = +25°C
A
WB
H
V
= +5V
DD
0
40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 65.0
0
32
64
96 128 160 192 224 256
CODE – Decimal
0
1
2
I
3
4
5
6
7
WIPER RESISTANCE – Ω
CURRENT – mA
WA
Figure 2. Wiper to End Terminal
Resistance vs. Code
Figure 3. Resistance Linearity vs.
Conduction Current
Figure 4. 100 kΩ Wiper-Contact-
Resistance Histogram
1
60
10
SS = 1205 UNITS
V
= +5V
DD
V
= 4.5V
R
(END-TO-END)
DD
= +25°C
AB
T
A
48
36
24
12
0
8
6
4
2
0
0.5
0
T
= +85°C
= +25°C
A
T
= –40°C
R
(WIPER-TO-END)
A
WB
T
CODE = 80
A
H
–0.5
–1
0
32
64
96 128 160 192 224 256
DIGITAL INPUT CODE – Decimal
40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 65.0
–75 –50 –25
0
25
50
75 100 125
WIPER RESISTANCE – Ω
TEMPERATURE – °C
Figure 5. Resistance Step Position
Nonlinearity Error vs. Code
Figure 6. 10 kΩ Wiper-Contact-
Resistance Histogram
Figure 7. Nominal Resistance vs.
Temperature
1
70
60
V
= +5V
V
T
= +5V
SS = 184 UNITS
DD
DD
V
= 4.5V
60
50
40
30
20
10
0
= –40°C/+85°C
= 2.00V
DD
= +25°C
A
T
V
V
48
36
24
12
0
A
A
0.5
0
= 0V
B
T
= +25°C
A
T
= –40°C
A
–0.5
T
A
= +85°C
–1
–10
0
32
64
96 128 160 192 224 256
35 37 39 41 43 45 47 49 51 53 55
0
32
64
96 128 160 192 224 256
CODE – DECIMAL
DIGITAL INPUT CODE – Decimal
WIPER RESISTANCE – Ω
Figure 8. Potentiometer Divider
Nonlinearity Error vs. Code
Figure 9. 50 kΩ Wiper-Contact-
Resistance Histogram
Figure 10. ⌬VWB /⌬T Potentiometer
Mode Tempco
–8–
REV. B
AD8400/AD8402/AD8403
700
600
500
400
300
200
100
0
6
V
T
= +5V
CODE = FF
80
DD
0
–6
= –40°C/+85°C
= NO CONNECT
MEASURED
A
V
A
40
R
WB
–12
RW
20
(20mV/DIV)
–18
10
–24
08
04
02
–30
–36
–42
CS
(5V/DIV)
01
T
= +25°C
A
–48
–54
SEE TEST FIGURE 33
100 1k
FREQUENCY – Hz
–100
0
32
64
96 128 160 192 224 256
CODE – DECIMAL
10
10k
100k
1M
TIME 500ns/DIV
Figure 11. ⌬RWB /⌬T Rheostat Mode
Tempco
Figure 12. One Position Step Change
at Half-Scale (Code 7FH to 80H)
Figure 13. Gain vs. Frequency for
R = 10 kΩ
6
0.75
CODE = FF
H
CODE = 80
H
0
V
= +5V
DD
SS = 158 UNITS
0.5
0.25
0
–6
80
H
–12
AVG + 2 SIGMA
AVG
OUTPUT
40
H
–18
20
H
–24
10
H
–30
08
H
–0.25
–0.5
–0.75
–36
AVG – 2 SIGMA
04
H
–42
INPUT
02
H
–48
01
H
–54
0
100
200
300
400
500
600
TIME = 5µs/DIV
1k
10k
100k
1M
HOURS OF OPERATION AT 150°C
FREQUENCY – Hz
Figure 15. Large Signal Settling
Time
Figure 14. Long-Term Drift
Accelerated by Burn-In
Figure 16. 50 kΩ Gain vs. Fre-
quency vs. Code
6
10
CODE = FF
H
FILTER = 22kHz
0
–6
V
= +5V
80
40
20
10
08
04
02
01
DD
= +25°C
H
T
A
1
0.1
H
H
H
H
H
H
H
–12
–18
–24
–30
–36
–42
–48
–54
VOUT
(50mV/DIV)
SEE TEST CIRCUIT FIGURE 32
SEE TEST CIRCUIT FIGURE 31
0.01
0.001
1k
10k
100k
1M
10
100
1k
10k
100k
TIME 200ns/DIV
FREQUENCY – Hz
FREQUENCY – Hz
Figure 18. Digital Feedthrough
vs. Time
Figure 17. Total Harmonic Distortion
Plus Noise vs. Frequency
Figure 19. 100 kΩ Gain vs. Fre-
quency vs. Code
–9–
REV. B
AD8400/AD8402/AD8403
10
1
80
60
40
SEE TEST CIRCUIT 33
V
T
= +5V DC ± 1V p-p AC
DD
= +25°C
T
A
= +25°C
CODE = 80
H
A
V
T
= +5V
DD
= +25°C
CODE = 80
H
A
C
V
= 10pF
L
= 4V, V = 0V
A
B
R = 10kΩ
V
DD
= +5V
R = 50kΩ
0.1
0.01
20
0
SEE TEST CIRCUIT
FIGURE 32
V
= +3V
DD
R = 100kΩ
0
1
2
3
4
5
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
INPUT LOGIC VOLTAGE – Volts
FREQUENCY – Hz
FREQUENCY – Hz
Figure 21. Supply Current vs. Logic
Input Voltage
Figure 22. Power Supply Rejection
vs. Frequency
Figure 20. Normalized Gain Flat-
ness vs. Frequency
160
1200
12
T
= +25°C
T
= +25°C
A
A
A – V = 5.5V
DD
140
120
100
80
6
0
f
= 700kHz, R = 10kΩ
–3dB
CODE = 55
1000
800
600
400
200
0
H
V
= +2.7V
DD
B – V = 3.3V
DD
CODE = 55
H
–6
f
= 71kHz, R = 100kΩ
C – V = 5.5V
DD
–3dB
–12
CODE = FF
H
–18
–24
–30
–36
–42
V
= +5.5V
DD
D – V = 3.3V
DD
60
f
= 125kHz, R = 50kΩ
–3dB
CODE = FF
H
B
A
40
V
V
= 100mV rms
= +5V
SEE TEST CIRCUIT
FIGURE 36
IN
C
DD
20
R
= 1MΩ
L
D
0
0
1
2
3
4
5
6
1k
10k
100k
FREQUENCY – Hz
1M
10M
1k
10k
100k
1M
V
DD
FREQUENCY – Hz
Figure 24. Supply Current vs.
Clock Frequency
Figure 25. AD8403 Incremental
Wiper ON Resistance vs. VDD
Figure 23. –3 dB Bandwidths
1
100
LOGIC INPUT
VOLTAGE = 0, V
V
= +5V
0
–10
–20
DD
DD
0.1
0.01
0
10
V
= +5.5V
DD
–45
–90
V
= +5V
DD
= +25°C
T
A
WIPER SET AT
HALF-SCALE 80
H
V
= +3.3V
DD
0.001
1
–55 –35 –15
100k 200k 400k
1M
2M
4M 6M 10M
–55 –35 –15
5
25 45 65 85 105 125
5
25 45 65 85 105 125
TEMPERATURE – °C
TEMPERATURE – °C
FREQUENCY – Hz
Figure 28. Supply Current vs.
Temperature
Figure 26. 1 kΩ Gain and Phase
vs. Frequency
Figure 27. Shutdown Current vs.
Temperature
–10–
REV. B
Parametric Test Circuits–AD8400/AD8402/AD8403
DUT
V+ = V
DD
DUT
A
B
1LSB = V+/256
A
W
+5V
OP279
W
V+
V
V
OUT
~
IN
B
V
MS
OFFSET
GND
2.5V DC
Figure 29. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
Figure 33. Inverting Programmable Gain Test Circuit
+5V
V
NO CONNECT
OUT
OP279
I
V
DUT
W
IN
W
~
A
W
A
B
OFFSET
GND
B
DUT
V
2.5V
MS
Figure 30. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 34. Noninverting Programmable Gain Test Circuit
I
+15V
A
MS
DUT
V+
R
≈ V
DD
I
=
1V/R
NOMINAL
W
W
V
~
IN
DUT
A
V
W
V
– [V
+ I (R II R )]
W1 W AW BW
W2
W
V
OP42
= ––––––––––––––––––––––––––
OUT
V+
W
I
B
OFFSET
GND
W
B
WHERE V = V
W1
WHEN I = 0
W
MS
WHEN I = 1/R
V
MS
2.5V
AND V
= V
MS
W2
W
–15V
Figure 35. Gain vs. Frequency Test Circuit
Figure 31. Wiper Resistance Test Circuit
V
A
0.1V
R
=
DUT
SW
I
SW
A
V
DD
V+ = V ± 10%
CODE = ØØ
DD
H
V+
W
~
W
∆V
MS
PSRR (dB) = 20LOG
(
–––––
)
∆V
B
B
V
DD
MS
I
0.1V
SW
∆V
%
MS
PSS (%/%) = –––––––
∆V
%
DD
0 toV
DD
Figure 36. Incremental ON Resistance Test Circuit
Figure 32. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
–11–
REV. B
AD8400/AD8402/AD8403
OPERATION
PROGRAMMING THE VARIABLE RESISTOR
The AD8400/AD8402/AD8403 provide a single, dual and quad
channel, 256 position digitally controlled variable resistor (VR)
device. Changing the programmed VR settings is accomplished
by clocking in a 10-bit serial data word into the SDI (Serial
Data Input) pin. The format of this data word is two address
bits, MSB first, followed by eight data bits, MSB first. Table I
provides the serial register data word format. The AD8400/
AD8402/AD8403 has the following address assignments for the
ADDR decode, which determines the location of VR latch re-
ceiving the serial register data in Bits B7 through B0:
Rheostat Operation
The nominal resistance of the VR (RDAC) between terminals A
and B are available with values of 1 kΩ, 10 kΩ, 50 kΩ and 100 kΩ.
The final digits of the part number determine the nominal resis-
tance value, e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resis-
tance (RAB) of the VR has 256 contact points accessed by the
wiper terminal, plus the B terminal contact. The 8-bit data word
in the RDAC latch is decoded to select one of the 256 possible
settings. The wiper’s first connection starts at the B terminal for
data 00H. This B terminal connection has a wiper contact resis-
tance of 50 Ω. The second connection (10 kΩ part) is the first
tap point located at 89 Ω [= RBA (nominal resistance)/256 + RW
= 39 Ω + 50 Ω] for data 01H. The third connection is the next
tap point representing 78 + 50 = 128 Ω for data 02H. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10011 Ω. The wiper does not di-
rectly connect to the B terminal. See Figure 37 for a simplified
diagram of the equivalent RDAC circuit.
VR# = A1 × 2 + A0 + 1
Equation 1
The single-channel AD8400 requires A1 = A0 = 0. The dual-
channel AD8402 requires A1 = 0. VR settings can be changed
one at a time in random sequence. The serial clock running at
10 MHz makes it possible to load all 4 VRs in under 4 µs (10 ×
4 × 100 ns) for the AD8403. The exact timing requirements are
shown in Figures 1a, 1b and 1c.
The AD8402/AD8403 resets to midscale by asserting the RS
pin, simplifying initial conditions at power up. Both parts have a
power shutdown SHDN pin that places the VR in a zero power
consumption state where terminals Ax are open circuited and
the wiper Wx is connected to Bx resulting in only leakage cur-
rents being consumed in the VR structure. In shutdown mode
the VR latch settings are maintained so that returning to opera-
tional mode from power shutdown, the VR settings return to
their previous resistance values. The digital interface is still ac-
tive in shutdown, except that SDO is deactivated. Code changes
in the registers can be made that will produce new wiper posi-
tions when the device is taken out of shutdown.
The AD8400 contains one RDAC, the AD8402 contains two
independent RDACs and the AD8403 contains four independent
RDACs. The general transfer equation that determines the digi-
tally programmed output resistance between Wx and Bx is:
R
WB (Dx) = (Dx)/256 × RBA + RW
where Dx is the data contained in the 8-bit RDAC# latch, and
BA is the nominal end-to-end resistance.
Equation 2
R
For example, when VB = 0 V and A terminal is open circuit, the
following output resistance values will be set for the following
RDAC latch codes (applies to 10 kΩ potentiometers):
D
(Dec)
RWB
(Ω)
Ax
Output State
R
S
SHDN
255
128
1
10011
5050
89
Full Scale
Midscale (RS = 0 Condition)
1 LSB
R
S
D7
D6
D5
D4
D3
D2
D1
D0
0
50
Zero-Scale (Wiper Contact Resistance)
R
S
Note in the zero-scale condition a finite wiper resistance of 50 Ω
is present. Care should be taken to limit the current flow be-
tween W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
Wx
RDAC
LATCH
&
Like the mechanical potentiometer the RDAC replaces, it is to-
tally symmetrical. The resistance between the wiper W and ter-
minal A also produces a digitally controlled resistance RWA
When these terminals are used the B terminal should be tied to
the wiper. Setting the resistance value for RWA starts at a maxi-
mum value of resistance and decreases as the data loaded in the
RDAC latch is increased in value. The general transfer equation
for this operation is:
DECODER
R
S
Bx
.
R
= R
/256
NOMINAL
S
Figure 37. AD8402/AD8403 Equivalent VR (RDAC) Circuit
R
WA (Dx) = (256–Dx)/256 × RBA + RW
Equation 3
–12–
REV. B
AD8400/AD8402/AD8403
suitable means. The Figure 38 block diagrams show more detail
of the internal digital circuitry. When CS is taken active low, the
clock loads data into the 10-bit serial register on each positive
clock edge (see Table II).
where Dx is the data contained in the 8-bit RDAC# latch, and
BA is the nominal end-to-end resistance. For example, when
VA = 0 V and B terminal is open circuit, the following output
resistance values will be set for the following RDAC latch codes
(applies to 10 kΩ potentiometers):
R
VDD
CS
D
(Dec)
RWA
(Ω)
A1
W1
B1
CLK
D7
D0
Output State
EN
R
DAC
LAT
#1
255
128
1
89
Full Scale
Midscale (RS = 0 Condition)
1 LSB
ADDR
DEC
A1
A0
5050
10011
10050
D7
0
Zero Scale
10-BIT
SER
REG
AD8400
The typical distribution of RBA from channel-to-channel matches
within ±1%. However, device-to-device matching is process lot
dependent having a ±20% variation. The change in RBA with
temperature has a positive 500 ppm/°C temperature coefficient.
SDI
DI
D0
8
GND
The wiper-to-end-terminal resistance temperature coefficient
has the best performance over the 10% to 100% of adjustment
range where the internal wiper contact switches do not contribute
any significant temperature related errors. The graph in Figure
11 shows the performance of RWB tempco vs. code, using the
trimmer with codes below 32 results in the larger temperature
coefficients plotted.
a.
V
CS
AD8402
DD
A1
W1
B1
CLK
D7
EN
R
DAC
LAT
#1
ADDR
DEC
A1
A0
D0
D7
D0
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
R
D7
A4
W4
B4
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting A terminal to +5 V and B terminal to
ground produces an output voltage at the wiper starting at zero
volts up to 1 LSB less than +5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256
position resolution of the potentiometer divider. The general
equation defining the output voltage with respect to ground for
any given input voltage applied to terminals AB is:
10-BIT
SER
REG
R
DAC
LAT
#2
SDI
DI
D0
8
R
SHDN
DGND
AGND
RS
b.
VW (Dx) = Dx/256 × VAB + VB
Equation 4
V
Operation of the digital potentiometer in the divider mode re-
sults in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors,
not the absolute value; therefore, the temperature drift improves
to 15 ppm/°C.
CS
DD
A1
W1
B1
CLK
D7
D0
EN
R
DAC
LAT
#1
ADDR
DEC
A1
A0
D7
SDO
DO
R
At the lower wiper position settings, the potentiometer divider
temperature coefficient increases due to the contributions of the
CMOS switch wiper resistance becoming an appreciable portion
of the total resistance from terminal B to the wiper. See Figure 10
for a plot of potentiometer tempco performance versus code
setting.
SER
REG
AD8403
A4
W4
B4
D7
D0
SDI
DI
D0
R
DIGITAL INTERFACING
DAC
LAT
#4
The AD8400/AD8402/AD8403 contains a standard SPI com-
patible three-wire serial input control interface. The three inputs
are clock (CLK), CS and serial data input (SDI). The positive-
edge sensitive CLK input requires clean transitions to avoid
clocking incorrect data into the serial input register. For best re-
sults use logic transitions faster than 1 V/µs. Standard logic
families work well. If mechanical switches are used for product
evaluation, they should be debounced by a flip-flop or other
8
R
SHDN
DGND
AGND
RS
c.
Figure 38. Block Diagrams
–13–
REV. B
AD8400/AD8402/AD8403
Table II. Input Logic Control Truth Table
AD8403
RDAC 1
RDAC 2
CS
ADDR
DECODE
CLK CS RS SHDN Register Activity
RDAC 4
L
P
L
L
H
H
H
H
No SR effect, enables SDO pin.
CLK
SDI
SERIAL
REGISTER
Shift One bit in from the SDI pin.
The tenth previously entered bit is
shifted out of the SDO pin.
X
P
H
H
Load SR data into RDAC latch
based on A1, A0 decode (Table III).
Figure 39. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of the
serial data word completing one DAC update. In the case of the
AD8403 four separate 10-bit data words must be clocked in to
change all four VR settings.
X
X
H
X
H
L
H
H
No Operation.
Sets all RDAC latches to midscale,
wiper centered, and SDO latch
cleared.
SHDN
X
X
H
H
P
H
L
Latches all RDAC latches to 80H.
CS
SDO
H
Open circuits all resistor
SERIAL
REGISTER
A–terminals, connects W to B,
turns off SDO output transistor.
SDI
D
Q
RS
CK
CLK
NOTE: P = positive edge, X = don’t care, SR = shift register.
RS
The serial data-output (SDO) pin contains an open drain n-
channel FET. This output requires a pull-up resistor in order to
transfer data to the next package’s SDI pin. The pull-up resistor
termination voltage may be larger than the VDD supply (but less
than max VDD of +8 V) of the AD8403 SDO output device,
e.g., the AD8403 could operate at VDD = 3.3 V and the pull-up
for interface to the next device could be set at +5 V. This allows
for daisy chaining several RDACs from a single processor serial
data line. The clock period needs to be increased when using a
pull-up resistor to the SDI pin of the following device in the
series. Capacitive loading at the daisy chain node SDO–SDI
between devices must be accounted for to successfully transfer
data. When daisy chaining is used, the CS should be kept low
until all the bits of every package are clocked into their respec-
tive serial registers insuring that the address bits and data bits
are in the proper decoding location. This would require 20 bits
of address and data complying to the word format provided in
Table I if two AD8403 four-channel RDACs are daisy chained.
Note, only the AD8403 has a SDO pin. During shutdown
SHDN the SDO output pin is forced to the off (logic high state)
to disable power dissipation in the pull up resistor. See Figure 40
for equivalent SDO output circuit schematic.
Figure 40. Detail SDO Output Schematic of the AD8403
All digital pins are protected with a series input resistor and par-
allel Zener ESD structure shown in Figure 41a. This structure
applies to digital pins CS, SDI, SDO, RS, SHDN, CLK. The
digital input ESD protection allows for mixed power supply
applications where +5 V CMOS logic can be used to drive an
AD8400/AD8402 or AD8403 operating from a +3 V power sup-
ply. The analog pins A, B, W are protected with a 20 Ω series
resistor and parallel Zener, see Figure 41b.
1kΩ
DIGITAL
LOGIC
PINS
Figure 41a. Equivalent ESD Protection Circuits
20Ω
A, B, W
The data setup and data hold times in the specification table de-
termine the data valid time requirements. The last 10 bits of the
data word entered into the serial register are held when CS re-
turns high. At the same time CS goes high it gates the address
decoder, which enables one of the two (AD8402) or four
(AD8403) positive edge triggered RDAC latches. See Figure 39
detail and Table III Address Decode Table.
Figure 41b. Equivalent ESD Protection Circuit (Analog
Pins)
RDAC
10kΩ
A
B
C
C
A
B
C
W
120pF
Table III. Address Decode Table
DW
256
DW
256
C
= 90.4pF · (1 –
) + 30pF
C
= 90.4pF · (
) + 30pF
B
A
A1
A0
Latch Decoded
W
0
0
1
1
0
1
0
1
RDAC#1
RDAC#2
RDAC#3 AD8403 Only
RDAC#4 AD8403 Only
Figure 42. RDAC Circuit Simulation Model for RDAC =
10 kΩ
–14–
REV. B
AD8400/AD8402/AD8403
The ac characteristics of the RDACs are dominated by the inter-
nal parasitic capacitances and the external capacitive loads. The
–3 dB bandwidth of the AD8403AN10 (10 kΩ resistor) mea-
sures 600 kHz at half scale as a potentiometer divider. Figure 23
provides the large signal BODE plot characteristics of the three
available resistor versions 10 kΩ, 50 kΩ, and 100 kΩ. The gain
flatness versus frequency graph, Figure 26, predicts filter appli-
cations performance. A parasitic simulation model has been de-
veloped, and is shown in Figure 42. Listing I provides a macro
model net list for the 10 kΩ RDAC:
Certain boundary conditions must be satisfied for proper
AD8400/AD8402/AD8403 operation. First, all analog signals
must remain within the 0 to VDD range used to operate the
single-supply AD8400/AD8402/AD8403 products. For standard
potentiometer divider applications, the wiper output can be
used directly. For low resistance loads, buffer the wiper with a
suitable rail-to-rail op amp such as the OP291 or the OP279.
Second, for ac signals and bipolar dc adjustment applications, a
virtual ground will generally be needed. Whatever method is
used to create the virtual ground, the result must provide the
necessary sink and source current for all connected loads, in-
cluding adequate bypass capacitance. Figure 33 shows one
channel of the AD8402 connected in an inverting program-
mable gain amplifier circuit. The virtual ground is set at +2.5 V
which allows the circuit output to span a ±2.5 volt range with
respect to virtual ground. The rail-to-rail amplifier capability is
necessary for the widest output swing. As the wiper is adjusted
from its midscale reset position (80H) toward the A terminal
(code FFH), the voltage gain of the circuit is increased in suc-
cessfully larger increments. Alternatively, as the wiper is ad-
justed toward the B terminal (code 00H), the signal becomes
attenuated. The plot in Figure 43 shows the wiper settings for a
100:1 range of voltage gain (V/V). Note the ±10 dB of pseudo-
logarithmic gain around 0 dB (1 V/V). This circuit is mainly
useful for gain adjustments in the range of 0.14 V/V to 4 V/V;
beyond this range the step sizes become very large and the resis-
tance of the driving circuit can become a significant term in the
gain equation.
Listing I. Macro Model Net List for RDAC
.PARAM DW=255, RDAC=10E3
*
.SUBCKT DPOT (A,W,)
*
CA
RAW
CW
RBW
CB
*
A
A
W
W
B
0
W
0
B
0
{DW/256*90.4E-12+30E-12}
{(1-DW/256)*RDAC+50}
120E-12
{DW/256*RDAC+50}
{(1-DW/256)*90.4E-12+30E-12}
.ENDS DPOT
The total harmonic distortion plus noise (THD+N) is measured
at 0.003% in an inverting op amp circuit using an offset ground
and a rail-to-rail OP279 amplifier, Figure 33. Thermal noise is
primarily Johnson noise, typically 9 nV/√Hz for the 10 kΩ ver-
sion at f = 1 kHz. For the 100 kΩ device, thermal noise becomes
29 nV/√Hz. Channel-to-channel crosstalk measures less than
–65 dB at f = 100 kHz. To achieve this isolation, the extra ground
pins provided on the package to segregate the individual RDACs
must be connected to circuit ground. AGND and DGND pins
should be at the same voltage potential. Any unused potentio-
meters in a package should be connected to ground. Power sup-
ply rejection is typically –35 dB at 10 kHz (care is needed to
minimize power supply ripple in high accuracy applications).
256
224
192
160
128
96
APPLICATIONS
64
The digital potentiometer (RDAC) allows many of the applica-
tions of trimming potentiometers to be replaced by a solid-state
solution offering compact size, freedom from vibration, shock
and open contact problems encountered in hostile environ-
ments. A major advantage of the digital potentiometer is its
programmability. Any settings can be saved for later recall in
system memory.
32
0
0.1
1.0
10
INVERTING GAIN – V/V
Figure 43. Inverting Programmable Gain Plot
The two major configurations of the RDAC include the
potentiometer divider (basic 3-terminal application) and the
rheostat (2-terminal configuration) connections shown in
Figures 29 and 30.
–15–
REV. B
AD8400/AD8402/AD8403
ACTIVE FILTER
40
20
–0.16
20.0000 k
One of the standard circuits used to generate a low-pass, high-
pass or bandpass filter is the state variable active filter. The digi-
tal potentiometer allows full programmability of the frequency,
gain and Q of the filter outputs. Figure 44 shows the filter cir-
cuit using a +2.5 V virtual ground, which allows a ±2.5 VP input
and output swing. RDAC2 and 3 set the LP, HP and BP cutoff
and center frequencies respectively. These variable resistors
should be programmed with the same data (as with ganged po-
tentiometers) to maintain the best circuit Q. Figure 45 shows
the measured filter response at the bandpass output as a func-
tion of the RDAC2 and RDAC3 settings which produce a range
of center frequencies from 2 kHz to 20 kHz. The filter gain re-
sponse at the bandpass output is shown in Figure 46. At a cen-
ter frequency of 2 kHz, the gain is adjusted over a –20 dB to
+20 dB range determined by RDAC1. Circuit Q is adjusted by
RDAC4. For more detailed reading on the state variable active
filter, see Analog Devices’ application note, AN-318.
0
–20
–40
–60
–80
200k
100k
20
100
1k
FREQUENCY – Hz
10k
Figure 45. Programmed Center Frequency Bandpass
Response
10k
40
HIGH-
–19.01
2.00000 k
PASS
RDAC4
B
10k
0.01µF
A3
20
0
0.01µF
A4
~
V
IN
A1
B
RDAC1
B
LOW-
PASS
A2
B
RDAC2
RDAC3
±
2.5V
–20
–40
–60
–80
BAND-
PASS
OP279 × 2
Figure 44. Programmable State Variable Active Filter
200k
100k
20
100
1k
FREQUENCY – Hz
10k
Figure 46. Programmed Amplitude Bandpass Response
–16–
REV. B
AD8400/AD8402/AD8403
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
8-Pin Plastic DIP (N-8)
8-Lead SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.430 (10.92)
0.348 (8.84)
8
5
4
8
1
5
4
0.280 (7.11)
0.240 (6.10)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
0.195 (4.95)
0.115 (2.93)
x 45°
0.210 (5.33)
MAX
0.0098 (0.25)
0.0040 (0.10)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
8°
0°
SEATING
PLANE
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
14-Pin Plastic DIP Package (N-14)
14-Pin Narrow Body SOIC Package (SO-14)
14
1
8
14
1
8
7
0.280 (7.11)
0.240 (6.10)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
7
PIN 1
0.2440 (6.20)
0.2284 (5.80)
0.325 (8.25)
0.300 (7.62)
0.795 (20.19)
0.725 (18.42)
0.060 (1.52)
0.015 (0.38)
0.3444 (8.75)
0.3367 (8.55)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
0.0196 (0.50)
0.0099 (0.25)
x 45
°
0.0688 (1.75)
0.0532 (1.35)
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
8
0
°
°
0.0098 (0.25)
0.0040 (0.10)
0.0500 (1.27)
0.0160 (0.41)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
14-Lead TSSOP
(RU-14)
0.201 (5.10)
0.193 (4.90)
14
8
7
1
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–17–
REV. B
AD8400/AD8402/AD8403
24-Pin Narrow Body Plastic DIP Package (N-24)
13
12
24
0.280 (7.11)
0.240 (6.10)
PIN 1
1
1.275 (32.30)
1.125 (28.60)
0.325 (8.25)
0.300 (7.62)
0.015
(0.38)
MIN
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.92)
0.015 (0.381)
0.008 (0.203)
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100 (2.54)
BSC
SEATING
PLANE
24-Pin SOIC Package (SOL-24)
24
13
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
PIN 1
0.3937 (10.00)
12
1
0.1043 (2.65)
0.6141 (15.60)
0.0926 (2.35)
0.5985 (15.20)
0.0291 (0.74)
0.0098 (0.25)
x 45
°
0.0500 (1.27)
0.0157 (0.40)
8
0
°
°
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
24-Lead Thin Surface Mount TSSOP Package (RU-24)
0.311 (7.90)
0.303 (7.70)
24
13
12
1
0.006 (0.15)
0.002 (0.05)
PIN 1
0.0433
(1.10)
MAX
8°
0°
0.028 (0.70)
0.020 (0.50)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–18–
REV. B
–19–
–20–
相关型号：
AD8402AN10
DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDIP14, PLASTIC, MS-001, DIP-14
ROCHESTER
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