AD8376_1 [ADI]
Ultralow Distortion IF Dual VGA; 超低失真IF双通道VGA
| 型号： | AD8376_1 |
| 厂家： | 
ADI |
| 描述： | Ultralow Distortion IF Dual VGA |
| 文件： | 总24页 (文件大小：921K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Distortion IF Dual VGA
AD8376
FEATURES
FUNCTIONAL BLOCK DIAGRAM
A4 A3 A2 A1 A0
VCCA
GNDA
Dual independent digitally controlled VGAs
Bandwidth of 700 MHz (−3 dB)
Gain range: −4 dB to +20 dB
CHANNEL A
GAIN
DECODER
AD8376
Step size: 1 dB 0.2 dB
OPA+
OPA+
Differential input and output
Noise figure: 8.7 dB @ maximum gain
Output IP3 of ~50 dBm at 200 MHz
Output P1dB of 20 dBm at 200 MHz
Dual parallel 5-bit control interface
Provides constant SFDR vs. gain
Power-down control
IPA+
POST-AMP
α
α
OPA–
OPA–
ENBA
IPA–
VCMA
ENBB
VCMB
IPB+
OPB+
OPB+
Single 5 V supply operation
32-lead, 5 mm x 5 mm LFCSP
POST-AMP
OPB–
OPB–
IPB–
APPLICATIONS
CHANNEL B
GAIN
Differential ADC drivers
DECODER
Main and diversity IF sampling receivers
Wideband multichannel receivers
Instrumentation
B4 B3 B2 B1 B0
VCCB
GNDB
Figure 1.
GENERAL DESCRIPTION
The AD8376 is a dual channel, digitally controlled, variable gain
wide bandwidth amplifier that provides precise gain control,
high IP3, and low noise figure. The excellent distortion perform-
ance and high signal bandwidth make the AD8376 an excellent
gain control device for a variety of receiver applications.
AD8376 consumes less than 5 mA and offers excellent input-to-
output isolation, lower than −50 dB at 200 MHz.
Fabricated on an Analog Devices, Inc., high speed SiGe process,
the AD8376 is supplied in a compact, thermally enhanced,
5 mm × 5mm 32-lead LFCSP package and operates over the
temperature range of −40°C to +85°C.
Using an advanced high speed SiGe process and incorporating
proprietary distortion cancellation techniques, the AD8376
achieves 50 dBm output IP3 at 200 MHz.
–40
–50
–60
65
60
55
The AD8376 provides a broad 24 dB gain range with 1 dB
resolution. The gain of each channel is adjusted through
dedicated 5-pin control interfaces and can be driven using
standard TTL levels. The open-collector outputs provide a
flexible interface, allowing the overall signal gain to be set by
the loading impedance. Thus, the signal voltage gain is directly
proportional to the load.
OIP3
–70
–80
–90
50
45
40
HD2
HD3
Each channel of the AD8376 can be individually powered on by
applying the appropriate logic level to the ENBA and ENBB
power enable pins. The quiescent current of the AD8376 is
typically 130 mA per channel. When powered down, the
–100
–110
35
30
40
60
80
100
120
140
160
180
200
FREQUENCY (MHz)
Figure 2. Harmonic Distortion and Output IP3 vs. Frequency
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
AD8376
TABLE OF CONTENTS
Features .............................................................................................. 1
Basic Structure............................................................................ 12
Applications..................................................................................... 13
Basic Connections...................................................................... 13
Single-Ended-to-Differential Conversion............................... 13
Broadband Operation................................................................ 15
ADC Interfacing......................................................................... 15
Layout Considerations............................................................... 18
Characterization Test Circuits.................................................. 18
Evaluation Board........................................................................ 19
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Circuit Description......................................................................... 12
REVISION HISTORY
10/10—Rev. 0 to Rev. A
Changes to Figure 3 and Table 4..................................................... 6
Changes to Figure 36...................................................................... 14
Added Exposed Pad Notation to Outline Dimensions ............. 23
8/07—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8376
SPECIFICATIONS
VS = 5 V, T = 25°C, RS = RL = 150 Ω at 140 MHz, 2 V p-p differential output, both channels enabled, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
VOUT < 2 V p-p (5.2 dBm)
700
5
MHz
V/ns
INPUT STAGE
Pin IPA+ and Pin IPA−, Pin IPB+ and Pin IPB−
For linear operation (AV = −4 dB)
Differential
Maximum Input Swing
Differential Input Resistance
Common-Mode Input Voltage
CMRR
8.5
V p-p
Ω
V
120
150
1.85
45.5
165
Gain code = 00000
dB
GAIN
Amplifier Transconductance
Maximum Voltage Gain
Minimum Voltage Gain
Gain Step Size
Gain code = 00000
Gain code = 00000
Gain code ≥ 11000
From gain code = 00000 to 11000
All gain codes, 20% fractional bandwidth for fC < 200 MHz
Gain code = 00000
For VIN = 100 mV p-p, gain code = 10100 to 00000
Pin OPA+ and Pin OPA−, Pin OPB+ and Pin OPB−
At P1dB, gain code = 00000
Differential
0.060
0.93
0.067
20
−4
0.98
0.18
8
0.074
1.02
S
dB
dB
dB
dB
mdB/°C
ns
Gain Flatness
Gain Temperature Sensitivity
Gain Step Response
OUTPUT STAGE
Output Voltage Swing
Output Impedance
Channel Isolation
5
13.1
16||0.8
73
V p-p
kΩ||pF
dB
Measured at differential output for differential input
applied to alternate channel (referred to output)
NOISE/HARMONIC PERFORMANCE
46 MHz
Gain code = 00000
Noise Figure
8.7
dB
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
70 MHz
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, 3 dBm per tone
−92
−94
50
dBc
dBc
dBm
dBm
21.3
Gain code = 00000
Noise Figure
8.7
dB
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
140 MHz
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, 3 dBm per tone
−89
−95
50
dBc
dBc
dBm
dBm
21.4
Gain code = 00000
Noise Figure
8.7
dB
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
200 MHz
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, 3 dBm per tone
−87
−97
51
dBc
dBc
dBm
dBm
21.6
Gain code = 00000
Noise Figure
8.7
dB
Second Harmonic
Third Harmonic
Output IP3
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, 3 dBm per tone
−82
−91
50
dBc
dBc
dBm
dBm
Output 1 dB Compression Point
20.9
Rev. A | Page 3 of 24
AD8376
Parameter
Conditions
Min
Typ
Max
Unit
POWER INTERFACE
Supply Voltage
4.5
5.0
5.5
V
VCC and Output Quiescent Current
with Both Channels Enabled
Thermal connection made to exposed paddle under device 245
250
255
mA
vs. Temperature
Power-Down Current, Both Channels ENBA and ENBB Low
vs. Temperature
−40°C ≤ TA ≤ +85°C
285
7
mA
mA
mA
5.4
−40°C ≤ TA ≤ +85°C
POWER-UP/GAIN CONTROL
VIH
VIL
Pin A0 to Pin A4, Pin B0 to Pin B4, Pin ENBA, and Pin ENBB
Minimum voltage for a logic high
Maximum voltage for a logic low
1.6
V
0.8
V
Logic Input Bias Current
900
nA
Table 2. Gain Code vs. Voltage Gain Look-Up Table
5-Bit Binary Gain Code
Voltage Gain (dB)
5-Bit Binary Gain Code
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
Voltage Gain (dB)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
+20
+19
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
+7
+6
+5
+4
+3
+2
+1
0
−1
−2
−3
−4
−4
01100
+8
>11000
Rev. A | Page 4 of 24
AD8376
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage, VPOS
5.5 V
ENBA, ENBB, A0 to A4, B0 to B4
Input Voltage, VIN+, VIN−
DC Common Mode
−0.6 V to (VPOS + −0.6 V)
−0.15 V to +4.15 V
VCMA, VCMB 0.25 V
6 mA
VCMA, VCMB
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
θJC (At Exposed Paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
1.6 W
34.6°C/W
3.6°C/W
140°C
−40°C to +85°C
−65°C to +150°C
ESD CAUTION
Rev. A | Page 5 of 24
AD8376
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A2
A3
A4
1
2
3
4
5
6
7
8
24 OPA+
23 OPA–
22 ENBA
21 GNDA
20 GNDB
19 ENBB
18 OPB–
17 OPB+
PIN 1
INDICATOR
AD8376
TOP VIEW
(Not to Scale)
VCMA
VCMB
B4
B3
B2
NOTES
1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GROUND.
SOLDER TO A LOW IMPEDANCE GROUND PLANE.
Figure 3. 32-Lead LFCSP
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
A2
MSB − 2 for the Gain Control Interface for Channel A.
2
A3
MSB − 1 for the Gain Control Interface for Channel A.
3
A4
MSB for the 5-Bit Gain Control Interface for Channel A.
4
5
6
VCMA
VCMB
B4
Channel A Input Common-Mode Voltage. Typically bypassed to ground through capacitor.
Channel B Input Common-Mode Voltage. Typically bypassed to ground through capacitor.
MSB for the 5-Bit Gain Control Interface for Channel B.
7
B3
MSB − 1 for the Gain Control Interface for Channel B.
8
B2
MSB − 2 for the Gain Control Interface for Channel B.
9
B1
LSB + 1 for the Gain Control Interface for Channel B.
10
B0
LSB for the Gain Control Interface for Channel B.
11
12
IPB+
IPB−
GNDB
VCCB
OPB+
OPB−
ENBB
GNDA
ENBA
OPA−
OPA+
VCCA
IPA−
IPA+
A0
Channel B Positive Input.
Channel B Negative Input.
Device Common (DC Ground) for Channel B.
13, 20
14
15, 17
16, 18
19
21, 28
22
23, 25
24, 26
27
Positive Supply Pin for Channel B. Should be bypassed to ground using suitable bypass capacitor.
Positive Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal.
Negative Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal.
Power Enable Pin for Channel B. Channel B is enabled with a logic high and disabled with a logic low.
Device Common (DC Ground) for Channel A.
Power Enable Pin for Channel A. Channel A is enabled with a logic high and disabled with a logic low.
Negative Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal.
Positive Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal.
Positive Supply Pins for Channel A. Should be bypassed to ground using suitable bypass capacitor.
Channel A Negative Input.
29
30
31
Channel A Positive Input.
LSB for the Gain Control Interface for Channel A.
32
A1
LSB + 1 for the Gain Control Interface for Channel A.
Exposed Pad
Internally connected to ground. Solder to a low impedance ground plane.
Rev. A | Page 6 of 24
AD8376
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RS = RL = 150 Ω, 2 V p-p output, maximum gain unless otherwise noted.
25
20
15
10
5
1.0
0.8
0.6
0.4
0.2
46MHz, +5V
70MHz, +5V
140MHz, +5V
0
–0.2
–0.4
–0.6
–0.8
0
–5
–10
–1.0
–4
11000
0
5
10
01010
15
00101
20
00000
–4
0
5
10
01010
15
00101
20
00000
10100
01111
11000
10100
01111
GAIN CODE
GAIN CODE
Figure 4. Gain vs. Gain Code at 46 MHz, 70 MHz, and 140 MHz
Figure 7. Gain Step Error, Frequency 140 MHz
25
20
15
10
5
25
20dB
19dB
18dB
17dB
16dB
15dB
14dB
13dB
12dB
11dB
10dB
9dB
INPUT MAX
RATING
BOUNDARY
20
15
200MHz
140MHz
70MHz
46MHz
8dB
7dB
6dB
10
5
5dB
4dB
0
3dB
2dB
1dB
0dB
–5
–1dB
–2dB
–3dB
–4dB
–10
10
0
100
1000
–4
1
6
11
16
21
FREQUENCY (MHz)
GAIN (dB)
Figure 5. Gain vs. Frequency Response
Figure 8. P1dB vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz
10
9
8
7
6
25
20
25°C
85°C
–40°C
5
4
3
2
15
+25°C
+85°C
–40°C
1
0
–1
–2
–3
10
–4
–5
–6
–7
–8
–9
–10
5
0
46
100
150
200
250
300
350
400
450
500
–4
11000
0
5
10
01010
15
00101
20
00000
10100
01111
FREQUENCY (MHz)
GAIN CODE
Figure 6. Gain Error over Temperature at 140 MHz
Figure 9. P1dB vs. Frequency at Maximum Gain, Three Temperatures
Rev. A | Page 7 of 24
AD8376
55
50
45
40
35
30
25
65
60
55
50
45
40
35
52
51
50
+25°C 20dB
–40°C 20dB
+85°C 20dB
+25°C 0dB
–40°C 0dB
+85°C 0dB
A
= +20dB
V
A
= +10dB
V
A
= 20dB
V
49
48
A
= 0dB
V
47
46
A
= 0dB
V
45
44
A
= –4dB
V
43
42
41
40
30
50
70
90
110
130
150
170
190
210
–3
–2
–1
0
1
2
3
4
5
FREQUENCY (MHz)
P
PER TONE (dBm)
OUT
Figure 13. Output Third-Order Intercept vs. Power,
Frequency 140 MHz, Three Temperatures
Figure 10. Output Third-Order Intercept at Four Gains,
Output Level at 3 dBm/Tone
–70
52
51
50
46MHz
70MHz
140MHz
200MHz
–75
–80
–85
–90
–95
49
48
A
= +20dB
V
47
46
A
= 0dB
A
= +10dB
V
V
45
44
–100
–105
–110
43
42
A
= –4dB
V
41
40
–4
1
6
11
16
–4
–3
–2
–1
0
1
2
3
4
5
6
GAIN (dB)
P
(dBm)
OUT
Figure 11. Output Third-Order Intercept vs. Power
at Four Gains, Frequency 140 MHz
Figure 14. Two-Tone Output IMD vs. Gain
at 46 MHz, 70 MHz, 140 MHz, and 200 MHz, Output Level at 3 dBm/Tone
70
65
60
55
50
45
40
35
30
–70
–75
–80
–85
+25°C
+85°C
–40°C
+25°C
–90
–95
–100
–40°C
+85°C
–105
–110
40
60
80
100
120
140
160
180
200
40
60
80
100
120
140
160
180
200
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Output Third-Order Intercept vs. Frequency,
Three Temperatures, Output Level at 3 dBm/Tone
Figure 15. Two-Tone Output IMD vs. Frequency,
Three Temperatures, Output Level at 3 dBm/Tone
Rev. A | Page 8 of 24
AD8376
–75
–65
–80
–85
–70
–75
–80
–85
–90
–95
–100
–105
HD2 –40°C
HD2 –4dB
HD2 0dB
HD2 +10dB
HD2 +20dB
–80
–85
–70
–75
–80
–85
–90
–95
–100
–105
HD2 +85°C
HD2 +25°C
–90
–95
–90
–95
–100
–105
–110
–115
–120
HD3 –4dB
HD3 0dB
HD3 +10dB
HD3 +20dB
HD3 –40°C
HD3 +85°C
HD3 +25°C
–100
–105
–110
–115
–110
5
40
60
80
100
120
140
160
180
200
–5
–4
–3
–2
–1
0
1
2
3
4
FREQUENCY (MHz)
P
(dBm)
OUT
Figure 19. Harmonic Distortion vs. Power, Frequency 140 MHz,
Three Temperatures
Figure 16. Harmonic Distortion vs. Frequency at Four Gain Codes,
VOUT = 2 V p-p
40
35
30
25
20
–80
–60
–65
–70
–75
HD2_+20dB
HD2_+10dB
HD2_0dB
–85
–90
HD2_–M4dB
–95
–80
–100
–105
–85
HD3_+20dB
HD3_+10dB
HD3_0dB
–90
–110
–115
–120
–125
–130
15
46MHz
70MHz
140MHz
200MHz
HD3_–4dB
–95
10
5
–100
–105
0
–110
–4 –2
0
2
4
6
8
10 12 14 16 18 20
–5
–4
–3
–2
–1
0
1
2
3
4
5
GAIN (dB)
P
(dBm)
OUT
Figure 17. Harmonic Distortion vs. Power at Four Gain Codes,
Frequency 140 MHz
Figure 20. NF vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz
–70
45
40
HD2 +25°C
HD3 +25°C
HD2 –40°C
–75
A
= –4dB
= 0dB
HD3 –40°C
HD2 +85°C
HD3 +85°C
V
35
30
25
20
15
–80
–85
–90
–95
A
V
A
= +10dB
= +20dB
V
V
–100
–105
–110
10
5
A
0
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
40
60
80
100
120
140
160
180
200
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Frequency, Three Temperatures,
VOUT = 2 V p-p
Figure 21. NF vs. Frequency
Rev. A | Page 9 of 24
AD8376
REF3 POSITION
–600mV/DIV
REF3 SCALE
500mV
0pF
10pF EACH SIDE
INPUT
2
R1
R3
1
CH1 500mV Ω CH2 500mV Ω M10.0ns 10.0GS/s IT 10.0ps/pt
A CH1 960mV
M2.5ns 20.0GS/s IT 10.0ps/pt
CH4 28.0mV
REF3 500mV 2.5ns
A
Figure 22. Gain Step Time Domain Response
Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB
REF1 POSITION
–1.08/DIV
REF1 SCALE
50mV
OUTPUT
INPUT
RISE (C2) 1.339ns
FALL(C2) 1.367ns
2
2
REF1
1
CH2 500mV
REF1 50.0mV
M2.5ns 20Gsps
IT 2.5ps/pt
A CH2
–590mV
CH1 500mV Ω CH2 500mV Ω M20.0ns 10.0GS/s IT 20.0ps/pt
A CH1 960mV
Figure 23. ENBL Time Domain Response
Figure 26. Large Signal Pulse Response
0
180
120
60
REF1 POSITION
–420mV/DIV
REF1 SCALE
2V
–5
0pF
–10
10pF EACH SIDE
INPUT
–15
–20
–25
0
R1
R3
R4
–60
–120
–180
1000
–30
10
M2.5ns 20.0GS/s IT 10.0ps/pt
A CH4 28.0mV
100
REF 1 2.0V 2.5ns
FREQUENCY (MHz)
Figure 27. S11 vs. Frequency
Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB
Rev. A | Page 10 of 24
AD8376
0
–20
–40
–10
–20
–30
–40
–50
–60
–70
–80
A
= –4dB
V
A
= 0dB
V
–60
–80
A
= +10dB
V
–100
–120
A
= +20dB
V
–90
0
100
200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
Figure 31. Channel Isolation (Output to Output) vs. Frequency
Figure 28. Reverse Isolation vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
60
50
40
30
20
10
0
10
100
1000
0
100
200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 32. Common-Mode Rejection Ratio vs. Frequency
Figure 29. Off-State Isolation vs. Frequency
1.00E–09
9.00E–10
8.00E–10
7.00E–10
6.00E–10
5.00E–10
4.00E–10
3.00E–10
2.00E–10
1.00E–10
0.00E+00
0dB, 5V, 25°C
+10dB, 5V, 25°C
+20dB, 5V, 25°C
–4dB, 5V, 25°C
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
Figure 30. Group Delay vs. Frequency at Gain
Rev. A | Page 11 of 24
AD8376
CIRCUIT DESCRIPTION
The dependency of the gain on the load is due to the open-
collector architecture of the output stage.
BASIC STRUCTURE
The AD8376 is a dual differential variable gain amplifier with
each amplifier consisting of a 150 ꢀ digitally controlled passive
attenuator followed by a highly linear transconductance
amplifier.
The dc current to the outputs of each amplifier is supplied
through two external chokes. The inductance of the chokes and
the resistance of the load determine the low frequency pole of
the amplifier. The parasitic capacitance of the chokes adds to
the output capacitance of the part. This total capacitance in
parallel with the load resistance sets the high frequency pole of
the device. Generally, the larger the inductance of the choke, the
higher its parasitic capacitance. Therefore, the value and type of
the choke should be chosen keeping this trade-off in mind.
1/2 AD8376
ATTENUATOR
MUX BUFFERS
IP+
OP+
gm CORE
AMP
VCM
OP–
IP–
For operation frequency of 15 MHz to 700 MHz driving a
150 ꢀ load, 1 μH chokes with SRF of 160 MHz or higher are
recommended (such as 0805LS-102XJBB from Coilcraftꢁ.
A0 TO A4
DIGITAL
SELECT
The supply current of each amplifier consists of about 50 mA
through the VCC pin and 80 mA through the two chokes
combined. The latter increases with temperature at about
2.5 mA per 10°C.
Figure 33. Simplified Schematic
Input System
The dc voltage level at the inputs of the AD8376 is set by an
internal voltage reference circuit to about 2 V. This reference is
accessible at VCMA and VCMB and can be used to source or
sink 100 μA. For cases where a common-mode signal is applied
to the inputs, such as in a single-ended application, an external
capacitor between VCMA/VCMB and ground is required. The
capacitor improves the linearity performance of the part in this
mode. This capacitor should be sized to provide a reactance of
10 ꢀ or less at the lowest frequency of operation. If the applied
common-mode signal is dc, its amplitude should be limited to
0.25 V from VCMA/VCMB (VCMA or VCMB 0.25 Vꢁ. Each
device can be powered down by pulling the ENBA or ENBB pin
down to below 0.8 V. In the powered down mode, the total
current reduces to 3 mA (typicalꢁ. The dc level at the inputs and
at VCMA/VCMB remains at about 2 V, regardless of the state of
the ENBA of ENBB pin.
Each amplifier has two output pins for each polarity, and they
are oriented in an alternating fashion. When designing the
board, care should be taken to minimize the parasitic capaci-
tance due to the routing that connects the corresponding
outputs together. A good practice is to avoid any ground or
power plane under this routing region and under the chokes to
minimize the parasitic capacitance.
Gain Control
Two independent 5-bit binary codes change each attenuator
setting in 1 dB steps such that the gain of each amplifier
changes from +20 dB (Code 0ꢁ to −4 dB (Code 24 and higherꢁ.
The noise figure of each amplifier is about 8 dB at maximum
gain setting, and it increases as the gain is reduced. The increase
in noise figure is equal to the reduction in gain. The linearity of
the part measured at the output is first-order independent of
the gain setting. From 0 dB to 20 dB gain, OIP3 is approximately
50 dBm into 150 ꢀ load at 140 MHz (3 dBm per toneꢁ. At gain
settings below 0 dB, it drops to approximately 45 dBm.
Output Amplifier
The gain is based on a 150 ꢀ differential load and varies as RL is
changed per the following equations:
Voltage Gain = 20 × (log(RL/150ꢁ + 1ꢁ
and
Power Gain = 10 × (log(RL/150ꢁ + 2ꢁ
Rev. A | Page 12 of 24
AD8376
APPLICATIONS
+5V
BASIC CONNECTIONS
VCM
0.1µF
Figure 36 shows the basic connections for operating the
AD8376. A voltage between 4.5 V and 5.5 V should be applied
to the supply pins. Each supply pin should be decoupled with at
least one low inductance, surface-mount ceramic capacitor of
0.1 μF placed as close as possible to the device.
1µH 1µH
150Ω
0.1µF
0.1µF
0.1µF
1/2
AD8376
50Ω
150Ω
0.1µF
AC
The outputs of the AD8376 are open collectors that need to be
pulled up to the positive supply with 1 ꢂH RF chokes. The differ-
ential outputs are biased to the positive supply and require ac-
coupling capacitors, preferably 0.1 ꢂF. Similarly, the input pins
are at bias voltages of about 2 V above ground and should be ac-
coupled as well. The ac-coupling capacitors and the RF chokes are
the principle limitations for operation at low frequencies.
37.5Ω
5
A0 TO A4
Figure 34. Single-Ended-to-Differential Conversion
Featuring ½ of the AD8376
–60
–65
–70
To enable each channel of the AD8376, the ENBA or ENBB pin
must be pulled high. Taking ENBA or ENBB low puts the
channels of the AD8376 in sleep mode, reducing current
consumption to approximately 5 mA per channel at ambient.
HD2
–75
–80
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
The AD8376 can be configured as a single-ended input to
differential output driver, as shown in Figure 34. A 150 ꢀ
resistor in parallel with the input impedance of input pin
provides an impedance matching of 50 ꢀ. The voltage gain and
the bandwidth of this configuration, using a 150 ꢀ load,
remains the same as when using a differential input.
–85
–90
HD3
–95
–100
0
50
100
150
200
FREQUENCY (MHz)
Using a single-ended input decreases the power gain by 3 dB
and limits distortion cancellation. Consequently, the second-
order distortion is degraded. The third-order distortion remains
low to 200 MHz, as shown in Figure 35.
Figure 35. Harmonic Distortion vs. Frequency of
Single-Ended-to-Differential Conversion
Rev. A | Page 13 of 24
AD8376
BALANCED
SOURCE
R
2
R
S
2
S
AC
+V
S
CHANNEL A PARALLEL
CONTROL INTERFACE
0.1µF
0.1µF
0.1µF
10µF
1µH
1µH
32
31
30
29
28
27
26
25
A1
A0
IPA+ IPA– GNDA VCCA OPA+ OPA–
0.1µF
OPA+ 24
1
A2
A3
A4
BALANCED
LOAD
R
L
OPA– 23
ENBA 22
GNDA 21
GNDB 20
2
3
4
5
6
7
8
0.1µF
0.1µF
0.1µF
VCMA
VCMB
B4
AD8376
+V
ENBB 19
OPB– 18
OPB+ 17
S
B3
0.1µF
B2
BALANCED
LOAD
R
L
B1
B0
10
IPB+ IPB– GNDB VCCB OPB+ OPB–
11 12 13 14 15 16
9
0.1µF
1µH
CHANNEL B PARALLEL
CONTROL INTERFACE
1µH
0.1µF
0.1µF
+V
S
0.1µF
10µF
R
2
R
S
2
S
AC
BALANCED
SOURCE
Figure 36. Basic Connections
Rev. A | Page 14 of 24
AD8376
For example, in the extreme case where the load is assumed to
be high impedance, RL = ∞, the equation for R1 reduces to R1 =
75 ꢀ. Using the equation for VR, the applied voltage should be
VR = 8 V. The measured single-tone low frequency harmonic
distortion for a 2 V p-p output using 75 ꢀ resistive pull-ups is
provided in Figure 38.
BROADBAND OPERATION
The AD8376 uses an open-collector output structure that
requires dc bias through an external bias network. Typically,
choke inductors are used to provide bias to the open-collector
outputs. Choke inductors work well at signal frequencies where
the impedance of the choke is substantially larger than the
target ac load impedance. In broadband applications, it may not
be possible to find large enough choke inductors that offer
enough reactance at the lowest frequency of interest while
offering a high enough self resonant frequency (SRFꢁ to support
the maximum bandwidth available from the device. The circuit
in Figure 37 can be used when frequency response below
10 MHz is desired. This circuit replaces the bias chokes with
bias resistors. The bias resistor has the disadvantage of a greater
IR drop, and requires a supply rail that is several volts above the
local 5 V supply used to power the device. Additionally, it is
necessary to account for the ac loading effect of the bias
resistors when designing the output interface. Whereas the gain
of the AD8376 is load dependent, RL in parallel with R1 + R2
should equal the optimum 150 ꢀ target load impedance to
provide the expected ac performance depicted in the data sheet.
Additionally, to ensure good output balance and even-order
distortion performance, it is essential that R1 = R2.
–80
–82
HD2
–84
–86
–88
HD3
–90
–92
–94
–96
0
5
10
15
20
FREQUENCY (MHz)
Figure 38. Harmonic Distortion vs. Frequency Using Resistive Pull-Ups
ADC INTERFACING
The AD8376 is a high output linearity variable gain amplifier
that is optimized for ADC interfacing. The output IP3 and noise
floor essentially remain constant vs. the 24 dB available gain
range. This is a valuable feature in a variable gain receiver where
it is desirable to maintain a constant instantaneous dynamic
range as the receiver gain is modified. The output noise density
is typically around 20 nV/√Hz, which is comparable to 14-/16-
bit sensitivity limits. The two-tone IP3 performance of the
AD8376 is typically around 50 dBm. This results in SFDR levels
of better than 86 dB when driving the AD9445 up to 140 MHz.
SET TO
5V
VR
5V
37.5Ω
R1
0.1µF
0.1µF
0.1µF
ETC1-1-13
1/2
50Ω
RL
AD8376
0.1µF
37.5Ω
R2
VR
5
A0 TO A4
Figure 37. Single-Ended Broadband Operation with Resistive Pull-Ups
There are several options available to the designer when using
the AD8376. The open-collector output provides the capability
of driving a variety of loads. Figure 39 shows a simplified wide-
band interface with the AD8376 driving a AD9445. The AD9445
is a 14-bit 125 MSPS analog-to-digital converter with a buffered
wideband input, which presents a 2 kꢀ||3 pF differential load
impedance and requires a 2 V p-p differential input swing to
reach full scale.
Using the formula for R1 (Equation 1ꢁ, the values of R1 = R2
that provide a total presented load impedance of 150 ꢀ can be
found. The required voltage applied to the bias resistors, VR,
can be found by using the VR formula (Equation 2ꢁ.
75 × RL
(1ꢁ
R1 =
RL − 150
and
VR = R1 × 40 × 10−3 + 5
(2ꢁ
B0 TO B4
5
5V
5V
L
1µH
(SERIES)
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
ETC1-1-13
33Ω
33Ω
VIN+
AD9445
14-BIT ADC
VIN–
14
1/2
AD8376
50Ω
37.5Ω
82Ω
0.1µF
L
1µH
(SERIES)
37.5Ω
82Ω
5
A0 TO A4
Figure 39. Wideband ADC Interfacing Example Featuring ½ of the AD8376 and the AD9445
Rev. A | Page 15 of 24
AD8376
For optimum performance, the AD8376 should be driven
differentially using an input balun or impedance transformer.
Figure 39 uses a wideband 1:1 transmission line balun followed
by two 37.5 ꢀ resistors in parallel with the 150 ꢀ input imped-
ance of the AD8376 to provide a 50 ꢀ differential terminated
input impedance. This provides a wideband match to a 50 ꢀ
source. The open-collector outputs of the AD8376 are biased
through the two 1 μH inductors and are ac-coupled to the two
82 ꢀ load resistors. The 82 ꢀ load resistors in parallel with the
series-terminated ADC impedance yields the target 150 ꢀ
differential load impedance, which is recommended to provide
the specified gain accuracy of the device. The load resistors are
ac-coupled from the AD9445 to avoid common-mode dc
loading. The 33 ꢀ series resistors help to improve the isolation
between the AD8376 and any switching currents present at the
analog-to-digital sample and hold input circuitry.
The addition of the series inductors L (seriesꢁ in Figure 39
extends the bandwidth of the system and provides response
flatness. Using 100 nH inductors as L (seriesꢁ, the wideband
system response of Figure 41 is obtained. The wideband
frequency response is an advantage in broadband applications
such as predistortion receiver designs and instrumentation
applications. However, by designing for a wide analog input
frequency range, the cascaded SNR performance is somewhat
degraded due to high frequency noise aliasing into the wanted
Nyquist zone.
0
–1
–2
–3
–4
1
–5
0
SNR = 64.93dBc
SFDR = 86.37dBc
–10
–6
FIRST POINT = –2.93dBFs
END POINT = –9.66dBFs
MID POINT = –2.33dBFs
MIN = –9.66dBFs
–20
–30
–40
NOISE FLOOR = –108.1dB
FUND = –1.053dBFs
SECOND = –86.18dBc
THIRD = –86.22dBc
–7
–8
MAX = –1.91dBFs
–50
–60
–9
–10
20
–70
–80
48
76
104 132 160 188 216 244 272 300
FREQUENCY (MHz)
2
3
–90
+
4
5
Figure 41. Measured Frequency Response of Wideband
ADC Interface Depicted in Figure 39
6
–100
–110
–120
An alternative narrow-band approach is presented in Figure 42.
By designing a narrow band-pass antialiasing filter between the
AD8376 and the target ADC, the output noise of the AD8376
outside of the intended Nyquist zone can be attenuated, helping
to preserve the available SNR of the ADC. In general, the SNR
improves several dB when including a reasonable order antialias-
ing filter. In this example, a low loss 1:3 input transformer is used
to match the AD8376’s 150 ꢀ balanced input to a 50 ꢀ unbal-
anced source, resulting in minimum insertion loss at the input.
–130
–140
–150
0
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
Figure 40. Measured Single-Tone Performance of the
Circuit in Figure 39 for a 100 MHz Input Signal
The circuit depicted in Figure 39 provides variable gain,
isolation, and source matching for the AD9445. Using this
circuit with the AD8376 in a gain of 20 dB (maximum gainꢁ, an
SFDR performance of 86 dBc is achieved at 100 MHz, as
indicated in Figure 40.
Rev. A | Page 16 of 24
AD8376
Figure 42 is optimized for driving some of Analog Devices
popular unbuffered ADCs, such as the AD9246, AD9640,
and AD6655. Table 5 includes antialiasing filter component
recommendations for popular IF sampling center frequencies.
Inductor L5 works in parallel with the on-chip ADC input
capacitance and a portion of the capacitance presented by C4 to
form a resonant tank circuit. The resonant tank helps to ensure
the ADC input looks like a real resistance at the target center
frequency. Additionally, the L5 inductor shorts the ADC inputs
at dc, which introduces a zero into the transfer function. In
addition, the ac coupling capacitors and the bias chokes introduce
additional zeros into the transfer function. The final overall
frequency response takes on a band-pass characteristic, helping
to reject noise outside of the intended Nyquist zone. Table 5
provides initial suggestions for prototyping purposes. Some
empirical optimization may be needed to help compensate for
actual PCB parasitics.
1µH
1nF
1nF
1nF
L1
L3
1:3
AD9246
AD9640
AD6655
1/2
AD8376
165Ω
50Ω
L5
C2
L1
C4
301Ω
CML
165Ω
L3
1nF
1µH
5
A0 TO A4
Figure 42. Narrow-Band IF Sampling Solution for Unbuffered ADC Applications
Table 5. Interface Filter Recommendations for Various IF Sampling Frequencies
Center Frequency
1 dB Bandwidth
L1
C2
L3
C4
L5
96 MHz
140 MHz
170 MHz
211 MHz
27 MHz
30 MHz
32 MHz
32 MHz
390 nH
330 nH
270 nH
220 nH
5.6 pF
3.3 pF
2.7 pF
2.2 pF
390 nH
330 nH
270 nH
220 nH
25 pF
20 pF
20 pF
18 pF
100 nH
56 nH
39 nH
27 nH
Rev. A | Page 17 of 24
AD8376
+9V
LAYOUT CONSIDERATIONS
Each amplifier has two output pins for each polarity, and they
are oriented in an alternating fashion. When designing the
board, care should be taken to minimize the parasitic capaci-
tance due to the routing that connects the corresponding
outputs together. A good practice is to avoid any ground or
power plane under this routing region and under the chokes to
minimize the parasitic capacitance.
96Ω
96Ω
25Ω
25Ω
0.1µF
0.1µF
0.1µF
0.1µF
330Ω
330Ω
TC3-1T
T1
1/2
50Ω
AD8376
50Ω
AC
5
A0 TO A4
Figure 44. Test Circuit for Time Domain Measurements
CHARACTERIZATION TEST CIRCUITS
Differential-to-Differential Characterization
The S-parameter characterization for the AD8376 was
performed using a dedicated differential input to differential
output characterization board. Figure 45 shows the layout of the
characterization board. The board was designed for optimum
impedance matching into a 75 ꢀ system. Because both the
input and output impedances of the AD8376 are 150 ꢀ differ-
entially, 75 ꢀ impedance runs were used to match 75 ꢀ network
analyzer port impedances. On-board 1 μH inductors were used
for output biasing, and the output board traces were designed
for minimum capacitance.
+5V
L1
L2
1µH
1µH
0.1µF
75Ω TRACES
0.1µF
0.1µF
0.1µF
75Ω
AC
75Ω
AC
1/2
AD8376
75Ω TRACES
75Ω
75Ω
5
A0 TO A4
Figure 43. Test Circuit for S-Parameters on Dedicated 75 Ω
Differential-to-Differential Board
Figure 45. Differential-to-Differential Characterization Board
Circuit Side Layout
+5V
L2
L1
1µH
1µH
C3
0.1µF
C1
0.1µF
R4
25Ω
R1
62Ω
ETC1-1-13
T2
TC3-1T
1/2
AD8376
PAD LOSS = 11dB
T1
50Ω
50Ω
R3
25Ω
R2
62Ω
AC
C2
0.1µF
C4
0.1µF
5
A0 TO A4
Figure 46. Test Circuit for Distortion, Gain, and Noise
Rev. A | Page 18 of 24
AD8376
The output pins of the AD8376 require supply biasing with
EVALUATION BOARD
1 ꢂH RF chokes. Both the input and output pins must be ac-
coupled. These pins are converted to single-ended with a pair of
baluns (Mini-Circuits® TC3-1T+ and M/A-COM ETC1-1-13ꢁ.
The baluns at the input, T1 and T2, are used to transform 50 Ω
source impedances to the desired 150 Ω reference levels. The
output baluns, T3 and T4, and the matching components are
configured to provide 150 ꢀ to 50 ꢀ impedance transformations
with insertion losses of about 11 dB.
Figure 47 shows the schematic of the AD8376 evaluation board.
The silkscreen and layout of the component and circuit sides
are shown in Figure 48 through Figure 51. The board is powered
by a single supply in the 4. 5 V to 5.5 V range. The power supply
is decoupled by 10 ꢂF and 0.1 ꢂF capacitors at each power supply
pin. Additional decoupling, in the form of a series resistor or
inductor at the supply pins, can also be added. Table 6 details
the various configuration options of the evaluation board.
Rev. A | Page 19 of 24
AD8376
Figure 47. AD8376 Evaluation Board Schematic
Rev. A | Page 20 of 24
AD8376
Table 6. Evaluation Board Configuration Options
Components
Function
Default Conditions
C13, C14, C20 to C22,
C64 to C67, R90, R91
Power Supply Decoupling. Nominal supply decoupling consists a
10 μF capacitor to ground followed by 0.1 μF capacitors to ground
positioned as close to the device as possible.
C20 = 10 μF (size 3528)
C13, C14 = 0.1 μF (size 0402)
C21, C22, C64 to C67 = 0.1 μF
(size 0603)
R90, R91 = 0 Ω (size 0603)
T1, T2, C1 to C4, C61, C62,
R1 to R4, R9 to R12,
R70 to R75
Input Interface. T1 and T2 are 3:1 impedance ratio baluns to
transform a 50 Ω single-ended input into a 150 Ω balanced
differential signal. R1 and R4 ground one side of the differential drive
interface for single-ended applications. R9 to R12 and R70 to R75 are
provided for generic placement of matching components. C1 to C4
are dc blocks.
T1, T2 = TC3-1+ (Mini-Circuits)
C1 to C4, C60, C61 = 0.1 μF (size 0402)
R1, R4, R9 to R12 = 0 Ω (size 0402)
R2, R3, R70 to R75 = open (size 0402)
T3, T4, C7 to C10,
L1 to L4, R15 to R32,
R62, R63, C62, C63
Output Interface. C7 to C10 are dc blocks. L1 to L4 provide dc biases
for the outputs. R19 to R28 are provided for generic placement of
matching components. The evaluation board is configured to
provide a 150 Ω to 50 Ω impedance transformation with an insertion
loss of about 11 dB. T3 and T4 are 1:1 impedance ratio baluns to
transform the balanced differential signals to single-ended signals.
R29 and R32 ground one side of the differential output interface for
single-ended applications.
C7 to C10 = 0.1 μF (size 0402)
L1 to L4 = 1 μH (size 0805)
T3, T4 = ETC1-1-13 (M/A-COM)
R19 to R22 = 61.9 Ω (size 0402)
R23, R25, R26, R28 = 30.9 Ω (size 0402)
R15 to R18 = 0 Ω (size 0603)
R29, R32 = 0 Ω (size 0402)
R24, R27, R30, R31, R62, R63 = open
(size 0402)
C62, C63 = 0.1 μF (size 0402)
PUA, PUB, R13, R14,
C5, C6
Enable Interface. The AD8376 is enabled by applying a logic high
voltage to the ENBA pin for Channel A or the ENBB pin for Channel B.
Channel A is enabled when the PUA switch is set in the up position,
connecting the ENBA pin to VPOS. Likewise, Channel B is enabled
when the PUB switch is set in the up position, connecting the ENBB
pin to VPOS. Both channels are disabled by setting the switches to
the down position, connecting the ENBA and ENBB pins to GND.
PUA, PUB = installed
R13, R14 = 0 Ω (size 0603)
C5, C6 = open (size 0603)
WA0 to WA4, WB0 to WB4
Parallel Interface Control. Used to hardwire A0 through A4 and B0
through B4 to the desired gain. The bank of switches WA0 to WA4 set
the binary gain code for Channel A. The bank of switches WB0 to
WB4 set the binary gain code for Channel B. WA0 and WB0 represent
the LSB for each of the respective channels.
WA0 to WA4, WB0 to WB4 = installed
C11, C12 = 0.1 μF (size 0402)
C11, C12
Voltage Reference. Input common-mode voltage ac-coupled to
ground by 0.1 μF capacitors, C11 and C12.
Rev. A | Page 21 of 24
AD8376
\
Figure 48. Component Side Silkscreen
Figure 50. Component Side Layout
Figure 51. Circuit Side Layout
Figure 49. Circuit Side Silkscreen
Rev. A | Page 22 of 24
AD8376
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
0.80 MAX
0.65 TYP
3.50 REF
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 52. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
CP-32-2
CP-32-2
AD8376ACPZ-WP
AD8376ACPZ-R7
AD8376-EVALZ
−40°C to +85°C
−40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] , Waffle Pack
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7”Tape and Reel
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. A | Page 23 of 24
AD8376
NOTES
©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06725-0-10/10(A)
Rev. A | Page 24 of 24
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