AD8380 [ADI]
Fast, High-Voltage Drive, 6-Channel Output DecDriver Decimating LCD Panel Driver; 快速，高电压驱动器， 6声道输出DecDriver抽取LCD面板驱动
| 型号： | AD8380 |
| 厂家： | 
ADI |
| 描述： | Fast, High-Voltage Drive, 6-Channel Output DecDriver Decimating LCD Panel Driver |
| 文件： | 总16页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fast, High-Voltage Drive, 6-Channel Output
™
a
DecDriver Decimating LCD Panel Driver
AD8380
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High-Voltage Drive to Within 1.3 V of Supply Rails
24 V Supply for Fast Output Voltage Drivers
High Update Rates: Fast 75 Ms/s 10-Bit Input Word Rate
Low Power Dissipation, 550 mW with Power-Down
Voltage Controlled Video Reference and Full-Scale
(Contrast) Output Levels
INV Bit Reverses Polarity of Video Signal
Nominal 3.3 V Logic and 15 V Analog Supplies
Flexible Logic
AD8380
10
10
10
10
10
10
10
2-STAGE
LATCH
DB [0:9]
VID0
VID1
VID2
DAC
DAC
DAC
2-STAGE
LATCH
CLK
STSQ/CS
XFR
CHANNEL
SELECTOR
2-STAGE
LATCH
E/O
Addressable or Sequential Channel Loading
STSQ/CS Allow Parallel AD8380 Operation for XGA
and Greater Resolution
Drives Capacitive Loads
26 ns Settling Time to 1% Up to 150 pF Load
Slew Rate 270 V/s
R/L
10
10
10
10
10
10
2-STAGE
LATCH
VID3
VID4
VID5
DAC
DAC
DAC
A[0:2]
3
2-STAGE
LATCH
STBY
BYP
BIAS
2-STAGE
LATCH
Available in 44-Lead MQFP
VREFHI
SCALING
CONTROL
APPLICATIONS
Poly Si LCD Panel Analog Column Driver
VREFLO
INV
VMID
PRODUCT DESCRIPTION
The AD8380 is fabricated on ADI’s XFCB26 fast bipolar 26 V
process, providing fast input logic, trimmed accuracy bipolar
DACs and fast settling, high voltage precision drive amplifiers
on the same chip.
The AD8380 provides a fast, 10-bit latched decimating digital
input that drives 6-channel high voltage drive outputs. The 10-
bit input word is sequentially muxed into six separate high speed,
bipolar DACs. Flexible digital input formats allow several
AD8380s to be used in parallel for higher resolution displays.
STSQ/CS, in conjunction with 3-bit addressable channel-loading
pins, allows loading of the digital words either sequentially or
randomly, and R/L control sets loading as either left to right, or
vice versa. 6-channel high voltage output drivers drive to within
1.3 V of the rails to rated settling time. The output signal can be
adjusted for dc signal reference, signal inversion or contrast for
maximum flexibility.
The AD8380 dissipates nominally 0.55 W of static power. STBY
pin reduces power to a minimum, with fast recovery.
The AD8380 is offered in a 44-lead 10 × 10 × 2.0 mm MQFP
package and operates over the commercial temperature range of
0°C to 85°C.
DecDriver is a trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
(@ 25؇C, AVCC = 15 V, DVCC = 3.3 V, TMIN = 0؇C, TMAX = 85؇C, unless
otherwise noted)
AD8380–SPECIFICATIONS
Model
Conditions
Min
Typ
Max
Unit
VIDEO DC PERFORMANCE1
TMIN to TMAX
VDE
VCME
Scale Factor Error
Offset Error
DAC Code = 450 to 800
DAC Code = 450 to 800
DAC Code = 0 to 1023
DAC Code = 0 to 1023
–7.5
–3.5
–0.25
–7
+1
+0.5
+7.5
+3.5
+0.25
+7
mV
mV
%
+1
mV
REFERENCE INPUTS
VMID Range2
6
7
7.5
V
VMID Bias Current
VFS Range
VREFHI
3
5
µA
V
V
VFS = 2 × (VREFHI–VREFLO)
1
6
VREFLO +0.5
VMID – 0.5
AVCC – 2.5
VREFHI – 2.5 VREFHI – 0.5
AVCC
VREFLO
V
VREFHI Input Resistance
VREFLO Bias Current
VREFHI Input Current3
to VREFLO
VFS = 5 V
3.3
0.2
750
kΩ
µA
µA
RESOLUTION
Coding
Binary
10
Bits
DIGITAL INPUT CHARACTERISTICS
Input Data Update Rate
Clock to Data Setup Times: t1
Clock to STSQ Setup Times: t3
Clock to XFR Setup Times: t5
Maximum CLK Rise and Fall Time, t7
Clock to A[0:2] Hold Times: t9
Clock to Data Hold Times: t2
Clock to STSQ Hold Times: t4
Clock to XFR Hold Times: t6
Clock to A[0:2] Setup Times: t8
CIN
75
Ms/s
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
µA
V
1
1
1
4
4
4
4
4
1
3
IIN
VIH
0.6
2.0
VIL
0.8
V
VTH
Threshold Voltage
1.4
V
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
AVCC – VOH, VOL – AVEE
50% of VIDx
1.1
15.5
1.3
17.5
V
ns
mA
CLK to VID Delay4
13.5
30
Output Current
VIDEO OUTPUT DYNAMIC PERFORMANCE
TMIN to TMAX, VO = 5 V Step,
CL = 150 pF, RS = 25 Ω
Data Switching Slew Rate
Invert Switching Slew Rate
Data Switching Settling Time to 1%5
Data Switching Settling Time to 0.25%
Invert Switching Settling Time to 1%5
Invert Switching Settling Time to 0.25%
CLK Feedthrough6
270
625
26
35
30
85
2
V/µs
V/µs
ns
ns
ns
32
65
40
100
5
ns
mV p-p
All-Hostile Crosstalk7
Amplitude
Glitch Duration
95
40
mV p-p
ns
POWER SUPPLY
Supply Rejection (VDE)
DVCC, Operating Range
DVCC, Quiescent Current
AVCC, Operating Range
Total AVCC Quiescent Current
STBY AVCC Current
+VS = 15 V 1 V
1
mV/V
V
mA
V
mA
mA
mA
3
9
5.5
35
24
44
5
22
33
0.5
0.1
STBY = H
STBY = H
STBY DVCC Current
5
OPERATING TEMPERATURE RANGE
0
85
°C
NOTES
1For definitions of VDE and VCME, see the Transfer Function section. Scale factor error is expressed as percentage of VFS.
2See Figure 1 for valid ranges of VMID.
3VREFHI Input Current = (VREFHI – VREFLO)/(VREFHI Input Resistance) = 2.5 V/3.3 kΩ.
4Delay time from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.
5For best settling time results, use minimum series output resistance, RS of 25 Ω.
6An output channel is selected, and glitch is monitored as CLK is driven. STSQ and XFR are set to logic low.
7Input data is loaded such that any five output channels change by VFS (i.e., 5 V), and the sixth unselected channel is monitored. Measurement is made for both states of INV.
Specifications subject to change without notice.
–2–
REV. B
AD8380
PIN FUNCTION DESCRIPTIONS
Description
Pin No.
Mnemonic
1
NC
No Connect.
2–11
12
DB[0:9]
E/O
Video Data Inputs. DB9 is the MSB.
Even/Odd data select, input latches are loaded at the falling edge of CLK if E/O is low or
rising edge if E/O is high.
13
R/L
Determines starting point of internally generated channel-loading sequence.
R/L Low (when address = 111) loads from Channel 0 up to Channel 5.
14
15, 16
INV
DVEE, DVCC
When high, analog video outputs are above the VMID setpoint. See Figure 3.
Digital Supplies. Nominally 3.3 V and 0 V, respectively.
17, 20, 22, 24,
26, 28, 30, 32,
34, 37, 38
AVCCxxx, AVEExxx Analog Supplies. Nominally 15 V and 0 V, respectively.
18
STBY
Stand By. When high, all digital and analog circuits are “debiased” and the power dissipation
drops to a minimum.
19
21
BYP
VMID
An external capacitor connected from here to VEE will help to ensure rapid DAC settling time.
Externally supplied voltage applied here sets the midpoint reference for the video output.
23, 25, 27, 29,
31, 33
VID5–VID0
Analog Video Outputs.
36, 35
VREFHI, VREFLO Voltage between these pins sets DAC full-scale range. An external reference must be applied
and should be common to all devices to ensure best tracking.
39–41
42
A[0:2]
STSQ/CS
3-bit channel address for addressable loading of the digital input latches.
STSQ to start internal sequencing or Chip Select to enable addressable channel addressing.
See functional description. Used in conjunction with A[0:2].
43
44
XFR
CLK
If XFR = HIGH at the rising edge of CLK, data is transferred to the DACs on the next falling
edge of CLK. See Figures 4, 6, 7, and 8.
Master Clock Input.
CHANNEL SELECTION FUNCTIONALITY
There are two channel selection modes, addressed channel
loading, (in which the user directly controls which DAC is
loaded), and internally sequenced loading (in which the user
controls the direction and clock phase in which the loading
proceeds).
MAXIMUM OUTPUT VOLTAGE
The maximum output signal swing is constrained by the output
voltage compliance of the DACs and the output dynamic range
of the output amplifiers. The minimum voltage allowed at the
outputs of the DACs is about 6 V. This constrains the minimum
value of VMID to be 6 V. The output amplifiers will swing and
settle cleanly, as described on the specification page, for output
voltages within 1.5 V from each supply voltage rail.
ADDRESSED CHANNEL LOADING:
When channel address (A0, A1, A2) = 000 through 101, the
video data is loaded into Channels 0 through 5. (STSQ/CS
functions as “Chip Selection” this case.)
For a given value of VMID, the voltage required to saturate the
video output voltages defines the maximum usable full-scale
voltage. For example, if VMID is less than AVCC/2, the maxi-
mum value of VFS is (VMID – 1.5 V). If VMID is greater than
AVCC/2, the maximum useful VFS is (AVCC – 1.5 – VMID).
Figure 1 graphically describes these limiting factors.
INTERNALLY SEQUENCED LOADING:
When channel address = 111 the video data is loaded in a
sequence determined internally. The sequencing is initiated by
a pulse applied to STSQ/CS input. The count proceeds from
0 to 5 if R/L is LOW or from 5 to 0 if R/L is HIGH.
6
DAC TRANSFER FUNCTION
VOUT = VMID + VFS × (1 – N/1023); if INV is HIGH,
4.5
VOUT = VMID – VFS × (1 – N/1023); if INV is LOW
where VFS = 2 × (VREFHI – VREFLO)
6
7.5
VMID – Volts
Figure 1. Valid Range for VMID with Respect to VFS
(AVCC = 15 V)
REV. B
–3–
AD8380
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage AVCC–AVEE . . . . . . . . . . . . . . . . . . . . . 26 V
The maximum power that can be safely dissipated by the
AD8380 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a junc-
tion temperature of 175°C for an extended period can result in
device failure.
Internal Power Dissipation2
Quad Flat Package (S) . . . . . . . . . . . . . . . . . . . . . . . 1.7 W
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Associated Text
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . 0°C to 85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
Output Short Circuit Limit
The AD8380’s internal short circuit limitation is not sufficient to
protect the device in the event of a direct short circuit between a
video output and a power supply voltage rail (VCC or VEE). Tem-
porary short circuits can reduce an output’s ability to source or
sink current and, therefore, impact the device’s ability to drive a
load. Short circuits of extended duration can cause metal lines to
fuse open, rendering the device nonfunctional.
44-Lead MQFP Package: θJA = 73°C/W (Still Air), where PD = (TJ – TA)/θJA
.
θ
JC = 22°C/W.
PIN CONFIGURATION
To prevent these problems, it is recommended that a series
resistor of 25 Ω or greater be placed as close as possible to the
AD8380’s video outputs. This will serve to substantially reduce
the magnitude of the fault currents and protect the outputs from
damage caused by intermittent short circuits. This may not be
enough to guarantee that the maximum junction temperature
(150°C) is not exceeded under all conditions. To ensure proper
operation, it is necessary to observe the maximum power derat-
ing curve in Figure 2 below.
44 43 42 41 40 39 38 37 36 35 34
1
2
33
32
31
30
29
28
27
26
25
24
23
NC
VID0
PIN 1
IDENTIFIER
DB0
DB1
AVCC0,1
VID1
3
4
DB2
AVEE1,2
VID2
5
DB3
3.0
AD8380
TOP VIEW
(Not to Scale)
6
DB4
AVCC2,3
VID3
T , MAX = 150؇C
J
7
DB5
8
DB6
AVEE3,4
VID4
2.5
2.0
1.5
1.0
0.5
9
DB7
10
11
DB8
AVCC4,5
VID5
(MSB) DB9
12 13 14 15 16 17 18 19 20 21 22
NC = NO CONNECT
0
10
20
30
40
50
60
70
80
90
AMBIENT TEMPERATURE – ؇C
Figure 2. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD8380JS
0°C to 85°C
44-Lead MQFP
S-44A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8380 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
Typical Performance Characteristics–AD8380
INV = H
VMID = 7V
VFS = 5V
CODE = 0
VMID = 7V
VFS = 5V
VMID + VFS
VMID
25⍀
25⍀
VIDX
C
VIDX
L
C
L
150pF
150pF
1.25V/DIV
1V/DIV
VMID – VFS
INV = L
VMID – VFS
20ns/DIV
20ns/DIV
TPC 1. Invert Switching 10 V Step Response (Rise) at CL
TPC 4. Data Switching Full-Scale Step Response (Fall) at
CL, INV = L
INV = H
VMID = 7V
VFS = 5V
VMID + VFS
1.25V/DIV
CODE = 0
VMID = 7V
VFS = 5V
VMID + VFS
25⍀
25⍀
VIDX
C
L
VIDX
C
L
150pF
150pF
1V/DIV
VMID
INV = L
VMID – VFS
20ns/DIV
20ns/DIV
TPC 2. Invert Switching 10 V Step Response (Fall) at CL
TPC 5. Data Switching Full-Scale Step Response (Rise) at
CL, INV = H
VMID = 7V
VFS = 5V
VMID = 7V
VFS = 5V
VMID + VFS
VMID
25⍀
VIDX
C
L
150pF
1V/DIV
VMID
1V/DIV
25⍀
VIDX
C
L
150pF
VMID – VFS
20ns/DIV
20ns/DIV
TPC 3. Data Switching Full-Scale Step Response (Rise) at
CL, INV = L
TPC 6. Data Switching Full-Scale Step Response (Fall) at
CL, INV = H
–5–
REV. B
AD8380
VMID = 7V
VFS = 5V
INV = H
25⍀
VMID = 7V
VFS = 5V
INV = H
VIDX
C
L
VMID+ VFS
150pF
VMID +VFS
VMID
25⍀
VIDX
C
L
150pF
VMID
VMID +VFS
t
= 0
t
= 0
VMID
10ns/DIV
10ns/DIV
TPC 10. Output Settling Time Response to 0.25% of Full
Scale (Falling Edge) at CL
TPC 7. Output Settling Time Response to 1% of Full
Scale (Rising Edge) at CL
7.5
5.5
3.5
VMID = 7V
VFS = 5V
INV = H
CODE 482
1.5
0
25⍀
VIDX
CODE 738
C
L
150pF
–1.5
–3.5
–5.5
–7.5
VMID +VFS
VMID
VMID
t = 0
10ns/DIV
0
10
20
30
40
50
60
70
80
90
TEMPERATURE – ؇C
TPC 8. Output Settling Time Response to 1% of Full
Scale (Falling Edge) at CL
TPC 11. Differential Error Voltage (VDE) vs. Temperature
3.5
2.5
VMID = 7V
VFS = 5V
INV = H
1.5
CODE 738
VMID + VFS
0.5
0
–0.5
CODE 482
25⍀
–1.5
–2.5
–3.5
VIDX
C
L
150pF
VMID +VFS
t = 0
VMID
0
10
20
30
40
50
60
70
80
90
10ns/DIV
TEMPERATURE – ؇C
TPC 12. Common-Mode Error Voltage (VCME) vs.
Temperature
TPC 9. Output Settling Time Response to 0.25% of Full
Scale (Rising Edge) at CL
–6–
REV. B
AD8380
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
128
256
384
512
CODE
640
768
896
1024
0
128
256
384
512
CODE
640
768
896
1024
TPC 13. Differential Nonlinearity (DNL) vs. Code, INV = H
TPC 16. Integral Nonlinearity (INL) vs. Code, INV = H
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
128
256
384
512
640
768
896
1024
1024
0
128
256
384
512
640
768
896
CODE
CODE
TPC 14. Differential Nonlinearity (DNL) vs. Code, INV = L
TPC 17. Integral Nonlinearity (INL) vs. Code, INV = L
7.5
5.0
3.5
2.5
2.5
0
0
–2.5
–3.5
–2.5
–5.0
–7.5
1024
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
CODE
640
768
896
CODE
TPC 15. Differential Error Voltage (VDE) vs. Code
TPC 18. Common-Mode Error Voltage (VCME) vs. Code
REV. B
–7–
AD8380
VFS = 5V
VMID = 7V
INV = L
R
C
= 25⍀
S
L
= 25⍀
VID0,1,2,3,4
OUTPUT @ CODE 0
1mV/DIV
= 150pF
2.5V/DIV
VID5
(QUIET)
20mV/DIV
CLK
2V/DIV
20ns/DIV
10ns/DIV
TPC 19. Clock Switching Transient (Feedthrough) at CL
TPC 21. All-Hostile Crosstalk at CL
60
40
VFS = 5V
VMID = 7V
INV = L
20
R
C
= 25⍀
S
L
5mV/DIV
2V/DIV
= 150pF
0
OUTPUT
@ CODE 1023
VOUTP (INV = L)
–20
–40
DATA
VOUTN (INV = H)
–60
20ns/DIV
–80
10k
100k
FREQUENCY – Hz
1M
5M
TPC 20. Data Switching Transient (Feedthrough) at CL
TPC 22. AVCC Power Supply Rejection vs. Frequency
–8–
REV. B
AD8380
THEORY OF OPERATION
The region over which the output voltage varies with input code
is defined by the status of the INV input. When INV is low, the
video output voltages rise from (VMID – VFS), (where VFS =
the full-scale output voltage), to VMID as the input code increases
from 0 to 1023. When INV is high, the output voltages drop
from (VMID + VFS) to VMID with increasing code (see
Figure 4).
The AD8380 is a system building block designed to directly drive
the columns of poly-silicon LCD panels of the type popular-
ized for use in data projectors. It comprises six channels of
precision 10-bit digital-to-analog converters loaded from a
single, high speed, 10-bit parallel input. Precision current
feedback amplifiers providing well-damped pulse responses
and rapid voltage settling into large capacitive loads buffer the
six outputs. Excellent linearity performance and laser trimming
of scale factors and output offsets at the wafer level ensure low
absolute output errors over all input codes. Tight channel-to-
channel matching in high channel count systems is guaranteed
by reliance on an externally-applied voltage reference.
For each value of input code there are then two possible values
for the output voltage, depending on the status of INV. When
INV is low the output is defined as VOUTP(N) where N refers
to the input code, and the P refers to the positive slope of the
voltage variation with code. When INV is high, the output is
defined as VOUTN(N).
To best correlate transfer function errors to image artifacts, the
overall accuracy of the AD8380 is defined by comparing the output
voltages, VOUTP(N) and VOUTN(N), to each other and to
their ideal values. Two parameters are defined, one dependent
on the difference between the signal amplitudes at a particular
code, and one dependent on their average value. These are VDE
and VCME. Their defining expressions are:
AD8380
10
10
10
10
10
10
10
2-STAGE
LATCH
DB [0:9]
VID0
VID1
VID2
DAC
DAC
DAC
2-STAGE
LATCH
CLK
STSQ/CS
XFR
CHANNEL
SELECTOR
2-STAGE
LATCH
VDE = [VOUTN(N) – VOUTP(N)]/2 – [(1 – N/1023) × VFS]
where
E/O
R/L
10
10
10
10
10
10
2-STAGE
LATCH
VID3
VID4
VID5
DAC
DAC
DAC
A[0:2]
3
N = input code, and VFS = 2 × (VREFHI – VREFLO)
VCME = [[VOUTN(N) +VOUTP(N)]/2 – VMID] × (1/2)
2-STAGE
LATCH
STBY
BYP
BIAS
where
2-STAGE
LATCH
VMID = midpoint reference voltage for the video outputs.
VREFHI
SCALING
CONTROL
Setting the Full-Scale Output
VREFLO
The full-scale output voltage (VFS), which defines the maxi-
mum output voltage excursion for a full code input transition, is
defined as twice the voltage difference between the VREFHI and
VREFLO inputs.
INV
VMID
Figure 3. Top Level Block Diagram
Transfer Function
Operating Modes, Control Logic and DAC Latches
The transfer function of the AD8380 is made up of two regions
of operation, in which the video output voltages are either above
or below an output reference voltage externally applied at the
VMID input.
Control logic included on the AD8380 chip facilitates channel
loading in ascending or descending order (for image mirroring),
data loading on rising or falling clock edges (for even/odd word
loading), and addressing and loading individual channels (for
system testing or debugging). The on-chip logic makes it easy to
build systems requiring more than six drive channels per color.
(VMID + VFS)
INV = H
DAC latches are of a two-stage master-slave design that guaran-
tees all channel outputs are updated simultaneously.
VOUTN
VMID
VOUTP
INV = L
(VMID – VFS)
0
1023
INPUT CODE
Figure 4. Definition of Output Transfer Function
REV. B
–9–
AD8380
SVGA System Operation
1 COLOR OF ‘EVEN/ODD’ XGA
DVCC
3
An SVGA system is characterized by the requirement of six
channels of panel drive for each displayed color. Such a system
would use a single AD8380 per color.
STSQ/CS
XFR
A[0:2]
STSQ_A
STSQ_B
XFR
AD8380
DEVICE “A”
E/O
R/L
INV
E/O_A
R/L
INV
PANEL
With E/O and all address bits A[0:2] set high, channel loading
commences on the first rising edge of CLK following a valid
assertion of the Start Sequence (STSQ) input. The second stage
latches, and therefore the video outputs, are updated on the
first falling edge of the clock following a valid Transfer (XFR)
signal. (See Figure 5 for signal timing details.)
6
VIDEO
OUT
CONTROLLER
DB[0:9]
CLK
E/O_B
CLKIN
DVCC
3
STSQ/CS
XFR
A[0:2]
IMAGE
AD8380
DEVICE “B”
PROCESSOR
E/O
R/L
INV
6
DB[0:9]
5
0
5
0
VIDEO
OUT
DB[0:9]
VIDEO
t1
t2
DB[0:9]
10
DCLK/2
t7
CLK
t7
2.0V
2.0V
0.8V
CLK
0.8V
STSQ/CS
Figure 6. Even/Odd: Outputs of Devices A and B are
Configured as Even and Odd Data Channels and Loading
Sequence Is Defined by Status of E/O and R/L Inputs
t3
t4
XFR
t5
t6
Figure 5. Sequenced SVGA Timing (A[0:2] = HIGH, E/O =
HIGH, See Table I)
10
11
0
9
10
11
DB[0:9]
0
t1
t2
Table I. Sequenced SVGA Data Byte to Channel Assignment
CLK
(EVEN
CHIP)
Channel Number
Data Byte Number
t4
t3
E/O = HIGH VID0
0
1
2
3
4
5
STSQ/CS
(EVEN
CHIP)
R/L = LOW
VID1
VID2
VID3
VID4
VID5
t1
t2
CLK
(ODD
CHIP)
t4
t3
STSQ/CS
(ODD
CHIP)
t5
t6
Load Sequence Switching (Right/Left Control)
To facilitate image mirroring, the order in which channels are
loaded can be easily switched. When the voltage on the right/left
control input (R/L) is low, the internal sequencer will load data
starting with Channel 0 and counting up to Channel 5. When
this voltage is high, channel loading will be in reverse order, from
Channel 5 down to Channel 0.
XFR
A0:A2 = HIGH
Figure 7. Sequenced Even/Odd XGA Timing, A[0:2] =
HIGH (See Table II)
XGA System Operation
Table II. Sequenced Even/Odd XGA Data Byte to
Channel Assignment
In an XGA system, twelve column drivers (two AD8380s) are
required for each color (refer to Figure 6). An “even/odd”
system, in which one AD8380 drives even numbered columns
and another drives odd numbered columns, can be easily imple-
mented as detailed in Figures 7 and 8. A clock at one-half the
pixel rate is applied to the CLK input. Even bytes are loaded on
the rising edge of the clock, while odd bytes are loaded on the
falling edge. Identifying whether a chip is to load on rising or falling
edges is done by setting the proper level on the E/O input.
Data Byte Number
Channel Number
R/L = LOW
R/L = HIGH
E/O = HIGH
VID0
0
2
4
6
8
10
10
8
6
4
2
VID1
VID2
VID3
VID4
VID5
0
E/O = LOW
VID0
VID1
VID2
VID3
VID4
VID5
1
3
5
7
9
11
11
9
7
5
3
1
–10–
REV. B
AD8380
DCLK
AD8380 INPUT DATA
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CLK (AD8380)
STSQ/CS (EVEN)
STSQ/CS (ODD)
XFR
12
24
0
14
2
16
4
18
6
20
8
AD8380 #1
22
10
EVEN CHANNEL
(E/O = HIGH)
(R/L = LOW)
12
0
14
16
18
20
22
2
4
6
8
10
13
1
15
3
17
5
19
7
21
9
AD8380 #2
23
13
15
17
19
21
23
11
1
ODD CHANNEL
(E/O = LOW)
(R/L = LOW)
3
5
7
9
11
Figure 8. Operation of Even/Odd XGA System
REV. B
–11–
AD8380
SXGA and Beyond
APPLICATION
Very high resolution display systems can be built using the E/O
XGA system as a model. By using four AD8380s, twenty-four
columns can be driven together for an SXGA display. Two would
be designated for even columns and two for odd. Four separate
STSQ signals would be used to coordinate data loading with a
single XFR to synchronize updating of output voltages.
The AD8380 is a mixed-signal, high speed, very accurate device
with multiple channels. In order to realize its specifications, it is
essential to use a properly designed circuit board.
Layout and Grounding
The analog and digital sections of the AD8380 are pinned
out on approximately opposite sides of the package. When
laying out a circuit board, please keep these sections separate
from each other to minimize crosstalk and noise coupling of
the digital input signals into the analog outputs.
Using a single external voltage source to drive the VREF inputs
on all drivers for a particular color and a single voltage source
for all their VMID inputs, will guarantee matching for all channels.
The exceptional accuracy of the AD8380’s transfer function will
ensure that high channel count systems can be built without fear of
image artifacts resulting from channel-to-channel matching errors.
All signal trace lengths should be made as short and direct as
possible to prevent signal degradation due to parasitic effects.
Please note that digital signals should not cross or be routed
near analog signals.
Direct Channel Loading
For debug or characterization purposes, it may be desirable to
load data directly into a single channel without requiring exercise
of the STSQ and XFR inputs. This can be done by applying
dc logic high levels to the STSQ and XFR inputs, and addressing
the desired channel through the A[0:2] inputs. Data will then
be loaded into the selected channel on each falling edge of the
CLK signal.
It is imperative to provide a solid ground plane under and
around the part. All of the ground pins of the part should be
directly connected to the ground plane with no extra signal
path length. For conventional operation, this includes the
pins DVEE, AVEEDAC, AVEEBIAS, AVEE0, AVEE1,2;
AVEE3,4; and AVEE5. The return currents for any of the sig-
nals for the part should be routed close to the ground pin for
that section to prevent stray signals from appearing on other
ground pins.
The maximum rate at which a channel can be updated will be
limited by the settling time of the output amplifiers.
Addressed Channel Loading
Power Supply Bypassing
The direct channel loading method can be extended. Channels
may be loaded in an arbitrary sequence through the use of an
active XFR signal with STSQ set to a high level. Use the A[0:2]
inputs to define the desired channel sequence. Data will be loaded
on the falling edge of CLK into the channel whose address was
valid on the preceding rising edge of CLK. All channel outputs
are then updated together by qualification of a valid XFR signal.
See Figure 9 for timing details.
The AD8380 has several power supply and reference voltages
that must be properly bypassed to the ground plane for opti-
mum performance. The bypass capacitor for each supply pin, as
well as VREFHI, VREFLO, and VMID, should be connected as
close as possible to the IC pins and directly to the ground plane.
A 0.1 µF capacitor, preferably a ceramic chip, should be used to
minimize lead length.
To provide low frequency, high current bypassing, larger value
tantalum capacitors should also be used. These should be con-
nected from the supply to ground, but it is not necessary to place
these close to the IC pins. Stray inductance will not greatly affect
their performance. The high current outputs should be bypassed
with these capacitors. It is recommended that two 22 µF tantalum
capacitors be placed from the AVCC supply to ground at either
end of the output side of the IC. AVCCBIAS and AVCCDAC
should each have a 10 µF tantalum bypass capacitor to ground.
See Figure 10.
DB[0:9]
5
0
1
5
0
t1
t2
CLK
t5
t6
XFR
t8
t9
VREFHI Reference Distribution
In a system that uses more than one AD8380 per color, it is
important that all of the AD8380 devices operate from equal
reference voltages to ensure that the video outputs are well
matched. VREFLO is not a concern due to its high input resis-
tance and very low bias current. Therefore, it is not likely that
there will be significant dc voltage drops in the circuit traces to that
supply. It is recommended to have good local supply bypassing
at each AD8380 from their respective VREFLOs to ground.
A[0:2]
IN THIS CASE, INPUT LATCHES ARE LOADED IN THE ORDER SELECTED
BY A[0:2], THEN DACs ARE UPDATED TOGETHER BY XFR.
Figure 9. Addressed Channel Timing (E/O = HIGH,
STSQ/CS = HIGH)
Standby Mode
A high level applied to the standby (STBY) input will turn off
most of the internal circuitry, dropping the quiescent power
dissipation to a few milliwatts. Since both digital and analog
circuits are debiased, all stored data will be lost. Upon returning
STBY to a low level, normal operation is restored.
The higher input current that flows in the VREFHI circuit
requires that this be laid out more carefully. VREFHI connects
internally to a 20 kΩ resistor for each of the six channels to provide
an input resistance of about 3.3 kΩ. Thus with a (VREFHI –
VREFLO) voltage of 2.5 V (to yield a VFS of 5.0 V), about
750 µA will flow into each VREFHI circuit.
–12–
REV. B
AD8380
In order to obtain the best matching, the traces to each of the
VREFHI pins of the AD8380s should be connected by an
approximately same length and same width circuit trace in a
“star” configuration. The source of the VREFHI voltage should
be at the center of the “star.” Therefore, the VREFHI currents
for two devices will not share a significant length of circuit trace,
and each trace will provide an approximately equal voltage drop.
For example, if a trace length is 5 in. long (13 cm.), then the
trace width for a 1 oz. copper foil should be wider than 0.025 in.
(0.7 mm) in order to keep the trace impedance below 100 mΩ.
Driving a Capacitive Load
A purely capacitive load can react with output impedance of the
AD8380 resulting in overshoot and ringing in its step response.
To minimize this effect, and optimize settling time, it is recom-
mended that a 25 Ω resistor be placed in series with each of the
driver’s outputs as shown in Figure 10.
In addition, if the VREFHI traces must be long, then the traces
should be widened to minimize differences in the voltage drops
due to differences in the VREFHI input currents of different
AD8380s. The dc resistance of these traces should be less than
100 mΩ. If the VREFHI input current is about 1 mA, then the
voltage drop will be about 100 µV.
10V
22F
10F
10F
22F
2.500V
15V
3.3V
7V
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
10F
0.1F
10F
DVCC
VREFHI
VREFLO AVCCDAC
AVCCBIAS
AVCC0,1
AVCC2,3
AVCC4,5
VMID
CLK
10
DB[0:9]
XFR
R
24.9⍀
(TYP FOR 6)
S
E/O
R/L
6
LOGIC
DAC
BIAS
DRIVERS
VID0 – VID5
STSQ/CS
3
A[0:2]
INV
STBY
AVEE1,2
AVEE3,4
DVEE
AVEEDAC
BYP AVEEBIAS
AVEE0
AVEE5
0.1F
Figure 10. Interface Drawing
REV. B
–13–
AD8380
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead MQFP
(S-44A)
0.530 (13.45)
0.510 (12.95)
SQ
0.096 (2.45)
MAX
0.398 (10.10)
0.390 (9.90)
SQ
0.041 (1.03)
0.029 (0.73)
44
34
1
33
SEATING
PLANE
0.315 (8.00)
REF
TOP VIEW
(PINS DOWN)
11
23
0.010 (0.25)
MAX
22
12
0.009 (0.23)
0.005 (0.13)
0.018 (0.45)
0.012 (0.30)
0.031 (0.80)
BSC
0.083 (2.10)
0.077 (1.95)
AD8380–Revision History
Location
Page
Data sheet changed from REV. A to REV B.
Single-Channel Block Diagram section and graphic removed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
–14–
REV. B
–15–
–16–
相关型号：
AD8381AST-REEL
Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver
ADI
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